1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
6 #include <linux/clk-provider.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
11 #include <linux/of_device.h>
12 #include <linux/regmap.h>
14 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
16 #include "clk-alpha-pll.h"
17 #include "clk-branch.h"
19 #include "clk-regmap.h"
26 P_CORE_BI_PLL_TEST_SE
,
36 static struct clk_alpha_pll gpll0
= {
38 .regs
= clk_alpha_pll_regs
[CLK_ALPHA_PLL_TYPE_FABIA
],
40 .enable_reg
= 0x52010,
41 .enable_mask
= BIT(0),
42 .hw
.init
= &(struct clk_init_data
){
44 .parent_data
= &(const struct clk_parent_data
){
49 .ops
= &clk_alpha_pll_fixed_fabia_ops
,
54 static const struct clk_div_table post_div_table_gpll0_out_even
[] = {
59 static struct clk_alpha_pll_postdiv gpll0_out_even
= {
62 .post_div_table
= post_div_table_gpll0_out_even
,
63 .num_post_div
= ARRAY_SIZE(post_div_table_gpll0_out_even
),
65 .regs
= clk_alpha_pll_regs
[CLK_ALPHA_PLL_TYPE_FABIA
],
66 .clkr
.hw
.init
= &(struct clk_init_data
){
67 .name
= "gpll0_out_even",
68 .parent_data
= &(const struct clk_parent_data
){
72 .ops
= &clk_alpha_pll_postdiv_fabia_ops
,
76 static struct clk_fixed_factor gcc_pll0_main_div_cdiv
= {
79 .hw
.init
= &(struct clk_init_data
){
80 .name
= "gcc_pll0_main_div_cdiv",
81 .parent_data
= &(const struct clk_parent_data
){
85 .ops
= &clk_fixed_factor_ops
,
89 static struct clk_alpha_pll gpll1
= {
91 .regs
= clk_alpha_pll_regs
[CLK_ALPHA_PLL_TYPE_FABIA
],
93 .enable_reg
= 0x52010,
94 .enable_mask
= BIT(1),
95 .hw
.init
= &(struct clk_init_data
){
97 .parent_data
= &(const struct clk_parent_data
){
102 .ops
= &clk_alpha_pll_fixed_fabia_ops
,
107 static struct clk_alpha_pll gpll4
= {
109 .regs
= clk_alpha_pll_regs
[CLK_ALPHA_PLL_TYPE_FABIA
],
111 .enable_reg
= 0x52010,
112 .enable_mask
= BIT(4),
113 .hw
.init
= &(struct clk_init_data
){
115 .parent_data
= &(const struct clk_parent_data
){
116 .fw_name
= "bi_tcxo",
120 .ops
= &clk_alpha_pll_fixed_fabia_ops
,
125 static struct clk_alpha_pll gpll6
= {
127 .regs
= clk_alpha_pll_regs
[CLK_ALPHA_PLL_TYPE_FABIA
],
129 .enable_reg
= 0x52010,
130 .enable_mask
= BIT(6),
131 .hw
.init
= &(struct clk_init_data
){
133 .parent_data
= &(const struct clk_parent_data
){
134 .fw_name
= "bi_tcxo",
138 .ops
= &clk_alpha_pll_fixed_fabia_ops
,
143 static struct clk_alpha_pll gpll7
= {
145 .regs
= clk_alpha_pll_regs
[CLK_ALPHA_PLL_TYPE_FABIA
],
147 .enable_reg
= 0x52010,
148 .enable_mask
= BIT(7),
149 .hw
.init
= &(struct clk_init_data
){
151 .parent_data
= &(const struct clk_parent_data
){
152 .fw_name
= "bi_tcxo",
156 .ops
= &clk_alpha_pll_fixed_fabia_ops
,
161 static const struct parent_map gcc_parent_map_0
[] = {
163 { P_GPLL0_OUT_MAIN
, 1 },
164 { P_GPLL0_OUT_EVEN
, 6 },
165 { P_CORE_BI_PLL_TEST_SE
, 7 },
168 static const struct clk_parent_data gcc_parent_data_0
[] = {
169 { .fw_name
= "bi_tcxo", .name
= "bi_tcxo" },
170 { .hw
= &gpll0
.clkr
.hw
},
171 { .hw
= &gpll0_out_even
.clkr
.hw
},
172 { .fw_name
= "core_bi_pll_test_se", .name
= "core_bi_pll_test_se" },
175 static const struct clk_parent_data gcc_parent_data_0_ao
[] = {
176 { .fw_name
= "bi_tcxo_ao", .name
= "bi_tcxo_ao" },
177 { .hw
= &gpll0
.clkr
.hw
},
178 { .hw
= &gpll0_out_even
.clkr
.hw
},
179 { .fw_name
= "core_bi_pll_test_se", .name
= "core_bi_pll_test_se" },
182 static const struct parent_map gcc_parent_map_1
[] = {
184 { P_GPLL0_OUT_MAIN
, 1 },
185 { P_GPLL6_OUT_MAIN
, 2 },
186 { P_GPLL0_OUT_EVEN
, 6 },
187 { P_CORE_BI_PLL_TEST_SE
, 7 },
190 static const struct clk_parent_data gcc_parent_data_1
[] = {
191 { .fw_name
= "bi_tcxo", .name
= "bi_tcxo" },
192 { .hw
= &gpll0
.clkr
.hw
},
193 { .hw
= &gpll6
.clkr
.hw
},
194 { .hw
= &gpll0_out_even
.clkr
.hw
},
195 { .fw_name
= "core_bi_pll_test_se", .name
= "core_bi_pll_test_se" },
198 static const struct parent_map gcc_parent_map_2
[] = {
200 { P_GPLL0_OUT_MAIN
, 1 },
201 { P_GPLL1_OUT_MAIN
, 4 },
202 { P_GPLL4_OUT_MAIN
, 5 },
203 { P_GPLL0_OUT_EVEN
, 6 },
204 { P_CORE_BI_PLL_TEST_SE
, 7 },
207 static const struct clk_parent_data gcc_parent_data_2
[] = {
208 { .fw_name
= "bi_tcxo", .name
= "bi_tcxo" },
209 { .hw
= &gpll0
.clkr
.hw
},
210 { .hw
= &gpll1
.clkr
.hw
},
211 { .hw
= &gpll4
.clkr
.hw
},
212 { .hw
= &gpll0_out_even
.clkr
.hw
},
213 { .fw_name
= "core_bi_pll_test_se", .name
= "core_bi_pll_test_se" },
216 static const struct parent_map gcc_parent_map_3
[] = {
218 { P_GPLL0_OUT_MAIN
, 1 },
219 { P_CORE_BI_PLL_TEST_SE
, 7 },
222 static const struct clk_parent_data gcc_parent_data_3
[] = {
223 { .fw_name
= "bi_tcxo", .name
= "bi_tcxo" },
224 { .hw
= &gpll0
.clkr
.hw
},
225 { .fw_name
= "core_bi_pll_test_se", .name
= "core_bi_pll_test_se" },
228 static const struct parent_map gcc_parent_map_4
[] = {
230 { P_GPLL0_OUT_MAIN
, 1 },
232 { P_GPLL0_OUT_EVEN
, 6 },
233 { P_CORE_BI_PLL_TEST_SE
, 7 },
236 static const struct clk_parent_data gcc_parent_data_4
[] = {
237 { .fw_name
= "bi_tcxo", .name
= "bi_tcxo" },
238 { .hw
= &gpll0
.clkr
.hw
},
239 { .fw_name
= "sleep_clk", .name
= "sleep_clk" },
240 { .hw
= &gpll0_out_even
.clkr
.hw
},
241 { .fw_name
= "core_bi_pll_test_se", .name
= "core_bi_pll_test_se" },
244 static const struct parent_map gcc_parent_map_5
[] = {
246 { P_GPLL0_OUT_MAIN
, 1 },
247 { P_GPLL7_OUT_MAIN
, 3 },
248 { P_GPLL0_OUT_EVEN
, 6 },
249 { P_CORE_BI_PLL_TEST_SE
, 7 },
252 static const struct clk_parent_data gcc_parent_data_5
[] = {
253 { .fw_name
= "bi_tcxo", .name
= "bi_tcxo" },
254 { .hw
= &gpll0
.clkr
.hw
},
255 { .hw
= &gpll7
.clkr
.hw
},
256 { .hw
= &gpll0_out_even
.clkr
.hw
},
257 { .fw_name
= "core_bi_pll_test_se", .name
= "core_bi_pll_test_se" },
260 static const struct parent_map gcc_parent_map_6
[] = {
262 { P_GPLL0_OUT_MAIN
, 1 },
264 { P_CORE_BI_PLL_TEST_SE
, 7 },
267 static const struct clk_parent_data gcc_parent_data_6
[] = {
268 { .fw_name
= "bi_tcxo", .name
= "bi_tcxo" },
269 { .hw
= &gpll0
.clkr
.hw
},
270 { .fw_name
= "sleep_clk", .name
= "sleep_clk" },
271 { .fw_name
= "core_bi_pll_test_se", .name
= "core_bi_pll_test_se" },
274 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src
[] = {
275 F(19200000, P_BI_TCXO
, 1, 0, 0),
279 static struct clk_rcg2 gcc_cpuss_ahb_clk_src
= {
283 .parent_map
= gcc_parent_map_0
,
284 .freq_tbl
= ftbl_gcc_cpuss_ahb_clk_src
,
285 .clkr
.hw
.init
= &(struct clk_init_data
){
286 .name
= "gcc_cpuss_ahb_clk_src",
287 .parent_data
= gcc_parent_data_0_ao
,
289 .flags
= CLK_SET_RATE_PARENT
,
290 .ops
= &clk_rcg2_ops
,
294 static const struct freq_tbl ftbl_gcc_gp1_clk_src
[] = {
295 F(19200000, P_BI_TCXO
, 1, 0, 0),
296 F(25000000, P_GPLL0_OUT_EVEN
, 12, 0, 0),
297 F(50000000, P_GPLL0_OUT_EVEN
, 6, 0, 0),
298 F(100000000, P_GPLL0_OUT_EVEN
, 3, 0, 0),
299 F(200000000, P_GPLL0_OUT_EVEN
, 1.5, 0, 0),
303 static struct clk_rcg2 gcc_gp1_clk_src
= {
307 .parent_map
= gcc_parent_map_4
,
308 .freq_tbl
= ftbl_gcc_gp1_clk_src
,
309 .clkr
.hw
.init
= &(struct clk_init_data
){
310 .name
= "gcc_gp1_clk_src",
311 .parent_data
= gcc_parent_data_4
,
313 .ops
= &clk_rcg2_ops
,
317 static struct clk_rcg2 gcc_gp2_clk_src
= {
321 .parent_map
= gcc_parent_map_4
,
322 .freq_tbl
= ftbl_gcc_gp1_clk_src
,
323 .clkr
.hw
.init
= &(struct clk_init_data
){
324 .name
= "gcc_gp2_clk_src",
325 .parent_data
= gcc_parent_data_4
,
327 .ops
= &clk_rcg2_ops
,
331 static struct clk_rcg2 gcc_gp3_clk_src
= {
335 .parent_map
= gcc_parent_map_4
,
336 .freq_tbl
= ftbl_gcc_gp1_clk_src
,
337 .clkr
.hw
.init
= &(struct clk_init_data
){
338 .name
= "gcc_gp3_clk_src",
339 .parent_data
= gcc_parent_data_4
,
341 .ops
= &clk_rcg2_ops
,
345 static const struct freq_tbl ftbl_gcc_pdm2_clk_src
[] = {
346 F(19200000, P_BI_TCXO
, 1, 0, 0),
347 F(60000000, P_GPLL0_OUT_EVEN
, 5, 0, 0),
351 static struct clk_rcg2 gcc_pdm2_clk_src
= {
355 .parent_map
= gcc_parent_map_0
,
356 .freq_tbl
= ftbl_gcc_pdm2_clk_src
,
357 .clkr
.hw
.init
= &(struct clk_init_data
){
358 .name
= "gcc_pdm2_clk_src",
359 .parent_data
= gcc_parent_data_0
,
361 .ops
= &clk_rcg2_ops
,
365 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src
[] = {
366 F(75000000, P_GPLL0_OUT_EVEN
, 4, 0, 0),
367 F(150000000, P_GPLL0_OUT_EVEN
, 2, 0, 0),
368 F(300000000, P_GPLL0_OUT_EVEN
, 1, 0, 0),
372 static struct clk_rcg2 gcc_qspi_core_clk_src
= {
376 .parent_map
= gcc_parent_map_2
,
377 .freq_tbl
= ftbl_gcc_qspi_core_clk_src
,
378 .clkr
.hw
.init
= &(struct clk_init_data
){
379 .name
= "gcc_qspi_core_clk_src",
380 .parent_data
= gcc_parent_data_2
,
382 .ops
= &clk_rcg2_ops
,
386 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src
[] = {
387 F(7372800, P_GPLL0_OUT_EVEN
, 1, 384, 15625),
388 F(14745600, P_GPLL0_OUT_EVEN
, 1, 768, 15625),
389 F(19200000, P_BI_TCXO
, 1, 0, 0),
390 F(29491200, P_GPLL0_OUT_EVEN
, 1, 1536, 15625),
391 F(32000000, P_GPLL0_OUT_EVEN
, 1, 8, 75),
392 F(48000000, P_GPLL0_OUT_EVEN
, 1, 4, 25),
393 F(51200000, P_GPLL6_OUT_MAIN
, 7.5, 0, 0),
394 F(64000000, P_GPLL0_OUT_EVEN
, 1, 16, 75),
395 F(75000000, P_GPLL0_OUT_EVEN
, 4, 0, 0),
396 F(80000000, P_GPLL0_OUT_EVEN
, 1, 4, 15),
397 F(96000000, P_GPLL0_OUT_EVEN
, 1, 8, 25),
398 F(100000000, P_GPLL0_OUT_EVEN
, 3, 0, 0),
399 F(102400000, P_GPLL0_OUT_EVEN
, 1, 128, 375),
400 F(112000000, P_GPLL0_OUT_EVEN
, 1, 28, 75),
401 F(117964800, P_GPLL0_OUT_EVEN
, 1, 6144, 15625),
402 F(120000000, P_GPLL0_OUT_EVEN
, 2.5, 0, 0),
403 F(128000000, P_GPLL6_OUT_MAIN
, 3, 0, 0),
407 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init
= {
408 .name
= "gcc_qupv3_wrap0_s0_clk_src",
409 .parent_data
= gcc_parent_data_1
,
410 .num_parents
= ARRAY_SIZE(gcc_parent_data_1
),
411 .ops
= &clk_rcg2_ops
,
414 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src
= {
418 .parent_map
= gcc_parent_map_1
,
419 .freq_tbl
= ftbl_gcc_qupv3_wrap0_s0_clk_src
,
420 .clkr
.hw
.init
= &gcc_qupv3_wrap0_s0_clk_src_init
,
423 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init
= {
424 .name
= "gcc_qupv3_wrap0_s1_clk_src",
425 .parent_data
= gcc_parent_data_1
,
426 .num_parents
= ARRAY_SIZE(gcc_parent_data_1
),
427 .ops
= &clk_rcg2_ops
,
430 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src
= {
434 .parent_map
= gcc_parent_map_1
,
435 .freq_tbl
= ftbl_gcc_qupv3_wrap0_s0_clk_src
,
436 .clkr
.hw
.init
= &gcc_qupv3_wrap0_s1_clk_src_init
,
439 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init
= {
440 .name
= "gcc_qupv3_wrap0_s2_clk_src",
441 .parent_data
= gcc_parent_data_1
,
442 .num_parents
= ARRAY_SIZE(gcc_parent_data_1
),
443 .ops
= &clk_rcg2_ops
,
446 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src
= {
450 .parent_map
= gcc_parent_map_1
,
451 .freq_tbl
= ftbl_gcc_qupv3_wrap0_s0_clk_src
,
452 .clkr
.hw
.init
= &gcc_qupv3_wrap0_s2_clk_src_init
,
455 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init
= {
456 .name
= "gcc_qupv3_wrap0_s3_clk_src",
457 .parent_data
= gcc_parent_data_1
,
458 .num_parents
= ARRAY_SIZE(gcc_parent_data_1
),
459 .ops
= &clk_rcg2_ops
,
462 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src
= {
466 .parent_map
= gcc_parent_map_1
,
467 .freq_tbl
= ftbl_gcc_qupv3_wrap0_s0_clk_src
,
468 .clkr
.hw
.init
= &gcc_qupv3_wrap0_s3_clk_src_init
,
471 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init
= {
472 .name
= "gcc_qupv3_wrap0_s4_clk_src",
473 .parent_data
= gcc_parent_data_1
,
474 .num_parents
= ARRAY_SIZE(gcc_parent_data_1
),
475 .ops
= &clk_rcg2_ops
,
478 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src
= {
482 .parent_map
= gcc_parent_map_1
,
483 .freq_tbl
= ftbl_gcc_qupv3_wrap0_s0_clk_src
,
484 .clkr
.hw
.init
= &gcc_qupv3_wrap0_s4_clk_src_init
,
487 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init
= {
488 .name
= "gcc_qupv3_wrap0_s5_clk_src",
489 .parent_data
= gcc_parent_data_1
,
490 .num_parents
= ARRAY_SIZE(gcc_parent_data_1
),
491 .ops
= &clk_rcg2_ops
,
494 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src
= {
498 .parent_map
= gcc_parent_map_1
,
499 .freq_tbl
= ftbl_gcc_qupv3_wrap0_s0_clk_src
,
500 .clkr
.hw
.init
= &gcc_qupv3_wrap0_s5_clk_src_init
,
503 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init
= {
504 .name
= "gcc_qupv3_wrap1_s0_clk_src",
505 .parent_data
= gcc_parent_data_1
,
506 .num_parents
= ARRAY_SIZE(gcc_parent_data_1
),
507 .ops
= &clk_rcg2_ops
,
510 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src
= {
514 .parent_map
= gcc_parent_map_1
,
515 .freq_tbl
= ftbl_gcc_qupv3_wrap0_s0_clk_src
,
516 .clkr
.hw
.init
= &gcc_qupv3_wrap1_s0_clk_src_init
,
519 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init
= {
520 .name
= "gcc_qupv3_wrap1_s1_clk_src",
521 .parent_data
= gcc_parent_data_1
,
522 .num_parents
= ARRAY_SIZE(gcc_parent_data_1
),
523 .ops
= &clk_rcg2_ops
,
526 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src
= {
530 .parent_map
= gcc_parent_map_1
,
531 .freq_tbl
= ftbl_gcc_qupv3_wrap0_s0_clk_src
,
532 .clkr
.hw
.init
= &gcc_qupv3_wrap1_s1_clk_src_init
,
535 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init
= {
536 .name
= "gcc_qupv3_wrap1_s2_clk_src",
537 .parent_data
= gcc_parent_data_1
,
538 .num_parents
= ARRAY_SIZE(gcc_parent_data_1
),
539 .ops
= &clk_rcg2_ops
,
542 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src
= {
546 .parent_map
= gcc_parent_map_1
,
547 .freq_tbl
= ftbl_gcc_qupv3_wrap0_s0_clk_src
,
548 .clkr
.hw
.init
= &gcc_qupv3_wrap1_s2_clk_src_init
,
551 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init
= {
552 .name
= "gcc_qupv3_wrap1_s3_clk_src",
553 .parent_data
= gcc_parent_data_1
,
554 .num_parents
= ARRAY_SIZE(gcc_parent_data_1
),
555 .ops
= &clk_rcg2_ops
,
558 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src
= {
562 .parent_map
= gcc_parent_map_1
,
563 .freq_tbl
= ftbl_gcc_qupv3_wrap0_s0_clk_src
,
564 .clkr
.hw
.init
= &gcc_qupv3_wrap1_s3_clk_src_init
,
567 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init
= {
568 .name
= "gcc_qupv3_wrap1_s4_clk_src",
569 .parent_data
= gcc_parent_data_1
,
570 .num_parents
= ARRAY_SIZE(gcc_parent_data_1
),
571 .ops
= &clk_rcg2_ops
,
574 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src
= {
578 .parent_map
= gcc_parent_map_1
,
579 .freq_tbl
= ftbl_gcc_qupv3_wrap0_s0_clk_src
,
580 .clkr
.hw
.init
= &gcc_qupv3_wrap1_s4_clk_src_init
,
583 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init
= {
584 .name
= "gcc_qupv3_wrap1_s5_clk_src",
585 .parent_data
= gcc_parent_data_1
,
586 .num_parents
= ARRAY_SIZE(gcc_parent_data_1
),
587 .ops
= &clk_rcg2_ops
,
590 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src
= {
594 .parent_map
= gcc_parent_map_1
,
595 .freq_tbl
= ftbl_gcc_qupv3_wrap0_s0_clk_src
,
596 .clkr
.hw
.init
= &gcc_qupv3_wrap1_s5_clk_src_init
,
600 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src
[] = {
601 F(144000, P_BI_TCXO
, 16, 3, 25),
602 F(400000, P_BI_TCXO
, 12, 1, 4),
603 F(19200000, P_BI_TCXO
, 1, 0, 0),
604 F(20000000, P_GPLL0_OUT_EVEN
, 5, 1, 3),
605 F(25000000, P_GPLL0_OUT_EVEN
, 6, 1, 2),
606 F(50000000, P_GPLL0_OUT_EVEN
, 6, 0, 0),
607 F(100000000, P_GPLL0_OUT_EVEN
, 3, 0, 0),
608 F(192000000, P_GPLL6_OUT_MAIN
, 2, 0, 0),
609 F(384000000, P_GPLL6_OUT_MAIN
, 1, 0, 0),
613 static struct clk_rcg2 gcc_sdcc1_apps_clk_src
= {
617 .parent_map
= gcc_parent_map_1
,
618 .freq_tbl
= ftbl_gcc_sdcc1_apps_clk_src
,
619 .clkr
.hw
.init
= &(struct clk_init_data
){
620 .name
= "gcc_sdcc1_apps_clk_src",
621 .parent_data
= gcc_parent_data_1
,
623 .ops
= &clk_rcg2_ops
,
627 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src
[] = {
628 F(100000000, P_GPLL0_OUT_EVEN
, 3, 0, 0),
629 F(150000000, P_GPLL0_OUT_EVEN
, 2, 0, 0),
630 F(200000000, P_GPLL0_OUT_MAIN
, 3, 0, 0),
631 F(300000000, P_GPLL0_OUT_EVEN
, 1, 0, 0),
635 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src
= {
639 .parent_map
= gcc_parent_map_0
,
640 .freq_tbl
= ftbl_gcc_sdcc1_ice_core_clk_src
,
641 .clkr
.hw
.init
= &(struct clk_init_data
){
642 .name
= "gcc_sdcc1_ice_core_clk_src",
643 .parent_data
= gcc_parent_data_0
,
645 .ops
= &clk_rcg2_ops
,
649 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src
[] = {
650 F(400000, P_BI_TCXO
, 12, 1, 4),
651 F(9600000, P_BI_TCXO
, 2, 0, 0),
652 F(19200000, P_BI_TCXO
, 1, 0, 0),
653 F(25000000, P_GPLL0_OUT_EVEN
, 12, 0, 0),
654 F(100000000, P_GPLL0_OUT_EVEN
, 3, 0, 0),
655 F(202000000, P_GPLL7_OUT_MAIN
, 4, 0, 0),
659 static struct clk_rcg2 gcc_sdcc2_apps_clk_src
= {
663 .parent_map
= gcc_parent_map_5
,
664 .freq_tbl
= ftbl_gcc_sdcc2_apps_clk_src
,
665 .clkr
.hw
.init
= &(struct clk_init_data
){
666 .name
= "gcc_sdcc2_apps_clk_src",
667 .parent_data
= gcc_parent_data_5
,
669 .ops
= &clk_rcg2_ops
,
673 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src
[] = {
674 F(25000000, P_GPLL0_OUT_EVEN
, 12, 0, 0),
675 F(50000000, P_GPLL0_OUT_EVEN
, 6, 0, 0),
676 F(100000000, P_GPLL0_OUT_EVEN
, 3, 0, 0),
677 F(200000000, P_GPLL0_OUT_MAIN
, 3, 0, 0),
678 F(240000000, P_GPLL0_OUT_MAIN
, 2.5, 0, 0),
682 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src
= {
686 .parent_map
= gcc_parent_map_0
,
687 .freq_tbl
= ftbl_gcc_ufs_phy_axi_clk_src
,
688 .clkr
.hw
.init
= &(struct clk_init_data
){
689 .name
= "gcc_ufs_phy_axi_clk_src",
690 .parent_data
= gcc_parent_data_0
,
692 .ops
= &clk_rcg2_ops
,
696 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src
[] = {
697 F(37500000, P_GPLL0_OUT_EVEN
, 8, 0, 0),
698 F(75000000, P_GPLL0_OUT_EVEN
, 4, 0, 0),
699 F(150000000, P_GPLL0_OUT_EVEN
, 2, 0, 0),
700 F(300000000, P_GPLL0_OUT_EVEN
, 1, 0, 0),
704 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src
= {
708 .parent_map
= gcc_parent_map_0
,
709 .freq_tbl
= ftbl_gcc_ufs_phy_ice_core_clk_src
,
710 .clkr
.hw
.init
= &(struct clk_init_data
){
711 .name
= "gcc_ufs_phy_ice_core_clk_src",
712 .parent_data
= gcc_parent_data_0
,
714 .ops
= &clk_rcg2_ops
,
718 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src
[] = {
719 F(9600000, P_BI_TCXO
, 2, 0, 0),
720 F(19200000, P_BI_TCXO
, 1, 0, 0),
724 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src
= {
728 .parent_map
= gcc_parent_map_3
,
729 .freq_tbl
= ftbl_gcc_ufs_phy_phy_aux_clk_src
,
730 .clkr
.hw
.init
= &(struct clk_init_data
){
731 .name
= "gcc_ufs_phy_phy_aux_clk_src",
732 .parent_data
= gcc_parent_data_3
,
734 .ops
= &clk_rcg2_ops
,
738 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src
[] = {
739 F(37500000, P_GPLL0_OUT_EVEN
, 8, 0, 0),
740 F(75000000, P_GPLL0_OUT_EVEN
, 4, 0, 0),
741 F(150000000, P_GPLL0_OUT_EVEN
, 2, 0, 0),
745 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src
= {
749 .parent_map
= gcc_parent_map_0
,
750 .freq_tbl
= ftbl_gcc_ufs_phy_unipro_core_clk_src
,
751 .clkr
.hw
.init
= &(struct clk_init_data
){
752 .name
= "gcc_ufs_phy_unipro_core_clk_src",
753 .parent_data
= gcc_parent_data_0
,
755 .ops
= &clk_rcg2_ops
,
759 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src
[] = {
760 F(66666667, P_GPLL0_OUT_EVEN
, 4.5, 0, 0),
761 F(133333333, P_GPLL0_OUT_MAIN
, 4.5, 0, 0),
762 F(200000000, P_GPLL0_OUT_MAIN
, 3, 0, 0),
763 F(240000000, P_GPLL0_OUT_MAIN
, 2.5, 0, 0),
767 static struct clk_rcg2 gcc_usb30_prim_master_clk_src
= {
771 .parent_map
= gcc_parent_map_0
,
772 .freq_tbl
= ftbl_gcc_usb30_prim_master_clk_src
,
773 .clkr
.hw
.init
= &(struct clk_init_data
){
774 .name
= "gcc_usb30_prim_master_clk_src",
775 .parent_data
= gcc_parent_data_0
,
777 .ops
= &clk_rcg2_ops
,
781 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src
[] = {
782 F(19200000, P_BI_TCXO
, 1, 0, 0),
783 F(20000000, P_GPLL0_OUT_EVEN
, 15, 0, 0),
787 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src
= {
791 .parent_map
= gcc_parent_map_0
,
792 .freq_tbl
= ftbl_gcc_usb30_prim_mock_utmi_clk_src
,
793 .clkr
.hw
.init
= &(struct clk_init_data
){
794 .name
= "gcc_usb30_prim_mock_utmi_clk_src",
795 .parent_data
= gcc_parent_data_0
,
797 .ops
= &clk_rcg2_ops
,
801 static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src
[] = {
802 F(19200000, P_BI_TCXO
, 1, 0, 0),
806 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src
= {
810 .parent_map
= gcc_parent_map_6
,
811 .freq_tbl
= ftbl_gcc_usb3_prim_phy_aux_clk_src
,
812 .clkr
.hw
.init
= &(struct clk_init_data
){
813 .name
= "gcc_usb3_prim_phy_aux_clk_src",
814 .parent_data
= gcc_parent_data_6
,
816 .ops
= &clk_rcg2_ops
,
820 static const struct freq_tbl ftbl_gcc_sec_ctrl_clk_src
[] = {
821 F(4800000, P_BI_TCXO
, 4, 0, 0),
822 F(19200000, P_BI_TCXO
, 1, 0, 0),
826 static struct clk_rcg2 gcc_sec_ctrl_clk_src
= {
830 .parent_map
= gcc_parent_map_3
,
831 .freq_tbl
= ftbl_gcc_sec_ctrl_clk_src
,
832 .clkr
.hw
.init
= &(struct clk_init_data
){
833 .name
= "gcc_sec_ctrl_clk_src",
834 .parent_data
= gcc_parent_data_3
,
835 .num_parents
= ARRAY_SIZE(gcc_parent_data_3
),
836 .ops
= &clk_rcg2_ops
,
840 static struct clk_branch gcc_aggre_ufs_phy_axi_clk
= {
842 .halt_check
= BRANCH_HALT_DELAY
,
846 .enable_reg
= 0x82024,
847 .enable_mask
= BIT(0),
848 .hw
.init
= &(struct clk_init_data
){
849 .name
= "gcc_aggre_ufs_phy_axi_clk",
850 .parent_data
= &(const struct clk_parent_data
){
851 .hw
= &gcc_ufs_phy_axi_clk_src
.clkr
.hw
,
854 .flags
= CLK_SET_RATE_PARENT
,
855 .ops
= &clk_branch2_ops
,
860 static struct clk_branch gcc_aggre_usb3_prim_axi_clk
= {
862 .halt_check
= BRANCH_HALT
,
864 .enable_reg
= 0x8201c,
865 .enable_mask
= BIT(0),
866 .hw
.init
= &(struct clk_init_data
){
867 .name
= "gcc_aggre_usb3_prim_axi_clk",
868 .parent_data
= &(const struct clk_parent_data
){
869 .hw
= &gcc_usb30_prim_master_clk_src
.clkr
.hw
,
872 .flags
= CLK_SET_RATE_PARENT
,
873 .ops
= &clk_branch2_ops
,
878 static struct clk_branch gcc_boot_rom_ahb_clk
= {
880 .halt_check
= BRANCH_HALT_VOTED
,
884 .enable_reg
= 0x52000,
885 .enable_mask
= BIT(10),
886 .hw
.init
= &(struct clk_init_data
){
887 .name
= "gcc_boot_rom_ahb_clk",
888 .ops
= &clk_branch2_ops
,
893 static struct clk_branch gcc_camera_ahb_clk
= {
895 .halt_check
= BRANCH_HALT
,
899 .enable_reg
= 0xb008,
900 .enable_mask
= BIT(0),
901 .hw
.init
= &(struct clk_init_data
){
902 .name
= "gcc_camera_ahb_clk",
903 .ops
= &clk_branch2_ops
,
908 static struct clk_branch gcc_camera_hf_axi_clk
= {
910 .halt_check
= BRANCH_HALT
,
912 .enable_reg
= 0xb020,
913 .enable_mask
= BIT(0),
914 .hw
.init
= &(struct clk_init_data
){
915 .name
= "gcc_camera_hf_axi_clk",
916 .ops
= &clk_branch2_ops
,
921 static struct clk_branch gcc_camera_throttle_hf_axi_clk
= {
923 .halt_check
= BRANCH_HALT
,
927 .enable_reg
= 0xb080,
928 .enable_mask
= BIT(0),
929 .hw
.init
= &(struct clk_init_data
){
930 .name
= "gcc_camera_throttle_hf_axi_clk",
931 .ops
= &clk_branch2_ops
,
936 static struct clk_branch gcc_camera_xo_clk
= {
938 .halt_check
= BRANCH_HALT
,
940 .enable_reg
= 0xb02c,
941 .enable_mask
= BIT(0),
942 .hw
.init
= &(struct clk_init_data
){
943 .name
= "gcc_camera_xo_clk",
944 .ops
= &clk_branch2_ops
,
949 static struct clk_branch gcc_ce1_ahb_clk
= {
951 .halt_check
= BRANCH_HALT_VOTED
,
955 .enable_reg
= 0x52000,
956 .enable_mask
= BIT(3),
957 .hw
.init
= &(struct clk_init_data
){
958 .name
= "gcc_ce1_ahb_clk",
959 .ops
= &clk_branch2_ops
,
964 static struct clk_branch gcc_ce1_axi_clk
= {
966 .halt_check
= BRANCH_HALT_VOTED
,
968 .enable_reg
= 0x52000,
969 .enable_mask
= BIT(4),
970 .hw
.init
= &(struct clk_init_data
){
971 .name
= "gcc_ce1_axi_clk",
972 .ops
= &clk_branch2_ops
,
977 static struct clk_branch gcc_ce1_clk
= {
979 .halt_check
= BRANCH_HALT_VOTED
,
981 .enable_reg
= 0x52000,
982 .enable_mask
= BIT(5),
983 .hw
.init
= &(struct clk_init_data
){
984 .name
= "gcc_ce1_clk",
985 .ops
= &clk_branch2_ops
,
990 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk
= {
992 .halt_check
= BRANCH_HALT
,
994 .enable_reg
= 0x502c,
995 .enable_mask
= BIT(0),
996 .hw
.init
= &(struct clk_init_data
){
997 .name
= "gcc_cfg_noc_usb3_prim_axi_clk",
998 .parent_data
= &(const struct clk_parent_data
){
999 .hw
= &gcc_usb30_prim_master_clk_src
.clkr
.hw
,
1002 .flags
= CLK_SET_RATE_PARENT
,
1003 .ops
= &clk_branch2_ops
,
1008 /* For CPUSS functionality the AHB clock needs to be left enabled */
1009 static struct clk_branch gcc_cpuss_ahb_clk
= {
1010 .halt_reg
= 0x48000,
1011 .halt_check
= BRANCH_HALT_VOTED
,
1013 .enable_reg
= 0x52000,
1014 .enable_mask
= BIT(21),
1015 .hw
.init
= &(struct clk_init_data
){
1016 .name
= "gcc_cpuss_ahb_clk",
1017 .parent_data
= &(const struct clk_parent_data
){
1018 .hw
= &gcc_cpuss_ahb_clk_src
.clkr
.hw
,
1021 .flags
= CLK_IS_CRITICAL
| CLK_SET_RATE_PARENT
,
1022 .ops
= &clk_branch2_ops
,
1027 static struct clk_branch gcc_cpuss_rbcpr_clk
= {
1028 .halt_reg
= 0x48008,
1029 .halt_check
= BRANCH_HALT
,
1031 .enable_reg
= 0x48008,
1032 .enable_mask
= BIT(0),
1033 .hw
.init
= &(struct clk_init_data
){
1034 .name
= "gcc_cpuss_rbcpr_clk",
1035 .ops
= &clk_branch2_ops
,
1040 static struct clk_branch gcc_ddrss_gpu_axi_clk
= {
1041 .halt_reg
= 0x4452c,
1042 .halt_check
= BRANCH_VOTED
,
1044 .enable_reg
= 0x4452c,
1045 .enable_mask
= BIT(0),
1046 .hw
.init
= &(struct clk_init_data
){
1047 .name
= "gcc_ddrss_gpu_axi_clk",
1048 .ops
= &clk_branch2_ops
,
1053 static struct clk_branch gcc_disp_gpll0_clk_src
= {
1054 .halt_check
= BRANCH_HALT_DELAY
,
1056 .enable_reg
= 0x52000,
1057 .enable_mask
= BIT(18),
1058 .hw
.init
= &(struct clk_init_data
){
1059 .name
= "gcc_disp_gpll0_clk_src",
1060 .parent_data
= &(const struct clk_parent_data
){
1061 .hw
= &gpll0
.clkr
.hw
,
1064 .ops
= &clk_branch2_ops
,
1069 static struct clk_branch gcc_disp_gpll0_div_clk_src
= {
1070 .halt_check
= BRANCH_HALT_DELAY
,
1072 .enable_reg
= 0x52000,
1073 .enable_mask
= BIT(19),
1074 .hw
.init
= &(struct clk_init_data
){
1075 .name
= "gcc_disp_gpll0_div_clk_src",
1076 .parent_data
= &(const struct clk_parent_data
){
1077 .hw
= &gcc_pll0_main_div_cdiv
.hw
,
1080 .ops
= &clk_branch2_ops
,
1085 static struct clk_branch gcc_disp_hf_axi_clk
= {
1087 .halt_check
= BRANCH_HALT
,
1089 .enable_reg
= 0xb024,
1090 .enable_mask
= BIT(0),
1091 .hw
.init
= &(struct clk_init_data
){
1092 .name
= "gcc_disp_hf_axi_clk",
1093 .ops
= &clk_branch2_ops
,
1098 static struct clk_branch gcc_disp_throttle_hf_axi_clk
= {
1100 .halt_check
= BRANCH_HALT
,
1104 .enable_reg
= 0xb084,
1105 .enable_mask
= BIT(0),
1106 .hw
.init
= &(struct clk_init_data
){
1107 .name
= "gcc_disp_throttle_hf_axi_clk",
1108 .ops
= &clk_branch2_ops
,
1113 static struct clk_branch gcc_disp_xo_clk
= {
1115 .halt_check
= BRANCH_HALT
,
1117 .enable_reg
= 0xb030,
1118 .enable_mask
= BIT(0),
1119 .hw
.init
= &(struct clk_init_data
){
1120 .name
= "gcc_disp_xo_clk",
1121 .ops
= &clk_branch2_ops
,
1126 static struct clk_branch gcc_gp1_clk
= {
1127 .halt_reg
= 0x64000,
1128 .halt_check
= BRANCH_HALT
,
1130 .enable_reg
= 0x64000,
1131 .enable_mask
= BIT(0),
1132 .hw
.init
= &(struct clk_init_data
){
1133 .name
= "gcc_gp1_clk",
1134 .parent_data
= &(const struct clk_parent_data
){
1135 .hw
= &gcc_gp1_clk_src
.clkr
.hw
,
1138 .flags
= CLK_SET_RATE_PARENT
,
1139 .ops
= &clk_branch2_ops
,
1144 static struct clk_branch gcc_gp2_clk
= {
1145 .halt_reg
= 0x65000,
1146 .halt_check
= BRANCH_HALT
,
1148 .enable_reg
= 0x65000,
1149 .enable_mask
= BIT(0),
1150 .hw
.init
= &(struct clk_init_data
){
1151 .name
= "gcc_gp2_clk",
1152 .parent_data
= &(const struct clk_parent_data
){
1153 .hw
= &gcc_gp2_clk_src
.clkr
.hw
,
1156 .flags
= CLK_SET_RATE_PARENT
,
1157 .ops
= &clk_branch2_ops
,
1162 static struct clk_branch gcc_gp3_clk
= {
1163 .halt_reg
= 0x66000,
1164 .halt_check
= BRANCH_HALT
,
1166 .enable_reg
= 0x66000,
1167 .enable_mask
= BIT(0),
1168 .hw
.init
= &(struct clk_init_data
){
1169 .name
= "gcc_gp3_clk",
1170 .parent_data
= &(const struct clk_parent_data
){
1171 .hw
= &gcc_gp3_clk_src
.clkr
.hw
,
1174 .flags
= CLK_SET_RATE_PARENT
,
1175 .ops
= &clk_branch2_ops
,
1180 static struct clk_branch gcc_gpu_gpll0_clk_src
= {
1181 .halt_check
= BRANCH_HALT_DELAY
,
1183 .enable_reg
= 0x52000,
1184 .enable_mask
= BIT(15),
1185 .hw
.init
= &(struct clk_init_data
){
1186 .name
= "gcc_gpu_gpll0_clk_src",
1187 .parent_data
= &(const struct clk_parent_data
){
1188 .hw
= &gpll0
.clkr
.hw
,
1191 .ops
= &clk_branch2_ops
,
1196 static struct clk_branch gcc_gpu_gpll0_div_clk_src
= {
1197 .halt_check
= BRANCH_HALT_DELAY
,
1199 .enable_reg
= 0x52000,
1200 .enable_mask
= BIT(16),
1201 .hw
.init
= &(struct clk_init_data
){
1202 .name
= "gcc_gpu_gpll0_div_clk_src",
1203 .parent_data
= &(const struct clk_parent_data
){
1204 .hw
= &gcc_pll0_main_div_cdiv
.hw
,
1207 .ops
= &clk_branch2_ops
,
1212 static struct clk_branch gcc_gpu_memnoc_gfx_clk
= {
1213 .halt_reg
= 0x7100c,
1214 .halt_check
= BRANCH_VOTED
,
1216 .enable_reg
= 0x7100c,
1217 .enable_mask
= BIT(0),
1218 .hw
.init
= &(struct clk_init_data
){
1219 .name
= "gcc_gpu_memnoc_gfx_clk",
1220 .ops
= &clk_branch2_ops
,
1225 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk
= {
1226 .halt_reg
= 0x71018,
1227 .halt_check
= BRANCH_HALT
,
1229 .enable_reg
= 0x71018,
1230 .enable_mask
= BIT(0),
1231 .hw
.init
= &(struct clk_init_data
){
1232 .name
= "gcc_gpu_snoc_dvm_gfx_clk",
1233 .ops
= &clk_branch2_ops
,
1238 static struct clk_branch gcc_npu_axi_clk
= {
1239 .halt_reg
= 0x4d008,
1240 .halt_check
= BRANCH_HALT
,
1242 .enable_reg
= 0x4d008,
1243 .enable_mask
= BIT(0),
1244 .hw
.init
= &(struct clk_init_data
){
1245 .name
= "gcc_npu_axi_clk",
1246 .ops
= &clk_branch2_ops
,
1251 static struct clk_branch gcc_npu_bwmon_axi_clk
= {
1252 .halt_reg
= 0x73008,
1253 .halt_check
= BRANCH_HALT
,
1255 .enable_reg
= 0x73008,
1256 .enable_mask
= BIT(0),
1257 .hw
.init
= &(struct clk_init_data
){
1258 .name
= "gcc_npu_bwmon_axi_clk",
1259 .ops
= &clk_branch2_ops
,
1264 static struct clk_branch gcc_npu_bwmon_dma_cfg_ahb_clk
= {
1265 .halt_reg
= 0x73018,
1266 .halt_check
= BRANCH_HALT
,
1268 .enable_reg
= 0x73018,
1269 .enable_mask
= BIT(0),
1270 .hw
.init
= &(struct clk_init_data
){
1271 .name
= "gcc_npu_bwmon_dma_cfg_ahb_clk",
1272 .ops
= &clk_branch2_ops
,
1277 static struct clk_branch gcc_npu_bwmon_dsp_cfg_ahb_clk
= {
1278 .halt_reg
= 0x7301c,
1279 .halt_check
= BRANCH_HALT
,
1281 .enable_reg
= 0x7301c,
1282 .enable_mask
= BIT(0),
1283 .hw
.init
= &(struct clk_init_data
){
1284 .name
= "gcc_npu_bwmon_dsp_cfg_ahb_clk",
1285 .ops
= &clk_branch2_ops
,
1290 static struct clk_branch gcc_npu_cfg_ahb_clk
= {
1291 .halt_reg
= 0x4d004,
1292 .halt_check
= BRANCH_HALT
,
1293 .hwcg_reg
= 0x4d004,
1296 .enable_reg
= 0x4d004,
1297 .enable_mask
= BIT(0),
1298 .hw
.init
= &(struct clk_init_data
){
1299 .name
= "gcc_npu_cfg_ahb_clk",
1300 .ops
= &clk_branch2_ops
,
1305 static struct clk_branch gcc_npu_dma_clk
= {
1306 .halt_reg
= 0x4d1a0,
1307 .halt_check
= BRANCH_HALT
,
1308 .hwcg_reg
= 0x4d1a0,
1311 .enable_reg
= 0x4d1a0,
1312 .enable_mask
= BIT(0),
1313 .hw
.init
= &(struct clk_init_data
){
1314 .name
= "gcc_npu_dma_clk",
1315 .ops
= &clk_branch2_ops
,
1320 static struct clk_branch gcc_npu_gpll0_clk_src
= {
1321 .halt_check
= BRANCH_HALT_DELAY
,
1323 .enable_reg
= 0x52000,
1324 .enable_mask
= BIT(25),
1325 .hw
.init
= &(struct clk_init_data
){
1326 .name
= "gcc_npu_gpll0_clk_src",
1327 .parent_data
= &(const struct clk_parent_data
){
1328 .hw
= &gpll0
.clkr
.hw
,
1331 .ops
= &clk_branch2_ops
,
1336 static struct clk_branch gcc_npu_gpll0_div_clk_src
= {
1337 .halt_check
= BRANCH_HALT_DELAY
,
1339 .enable_reg
= 0x52000,
1340 .enable_mask
= BIT(26),
1341 .hw
.init
= &(struct clk_init_data
){
1342 .name
= "gcc_npu_gpll0_div_clk_src",
1343 .parent_data
= &(const struct clk_parent_data
){
1344 .hw
= &gcc_pll0_main_div_cdiv
.hw
,
1347 .flags
= CLK_SET_RATE_PARENT
,
1348 .ops
= &clk_branch2_ops
,
1353 static struct clk_branch gcc_pdm2_clk
= {
1354 .halt_reg
= 0x3300c,
1355 .halt_check
= BRANCH_HALT
,
1357 .enable_reg
= 0x3300c,
1358 .enable_mask
= BIT(0),
1359 .hw
.init
= &(struct clk_init_data
){
1360 .name
= "gcc_pdm2_clk",
1361 .parent_data
= &(const struct clk_parent_data
){
1362 .hw
= &gcc_pdm2_clk_src
.clkr
.hw
,
1365 .flags
= CLK_SET_RATE_PARENT
,
1366 .ops
= &clk_branch2_ops
,
1371 static struct clk_branch gcc_pdm_ahb_clk
= {
1372 .halt_reg
= 0x33004,
1373 .halt_check
= BRANCH_HALT
,
1374 .hwcg_reg
= 0x33004,
1377 .enable_reg
= 0x33004,
1378 .enable_mask
= BIT(0),
1379 .hw
.init
= &(struct clk_init_data
){
1380 .name
= "gcc_pdm_ahb_clk",
1381 .ops
= &clk_branch2_ops
,
1386 static struct clk_branch gcc_pdm_xo4_clk
= {
1387 .halt_reg
= 0x33008,
1388 .halt_check
= BRANCH_HALT
,
1390 .enable_reg
= 0x33008,
1391 .enable_mask
= BIT(0),
1392 .hw
.init
= &(struct clk_init_data
){
1393 .name
= "gcc_pdm_xo4_clk",
1394 .ops
= &clk_branch2_ops
,
1399 static struct clk_branch gcc_prng_ahb_clk
= {
1400 .halt_reg
= 0x34004,
1401 .halt_check
= BRANCH_HALT_VOTED
,
1402 .hwcg_reg
= 0x34004,
1405 .enable_reg
= 0x52000,
1406 .enable_mask
= BIT(13),
1407 .hw
.init
= &(struct clk_init_data
){
1408 .name
= "gcc_prng_ahb_clk",
1409 .ops
= &clk_branch2_ops
,
1414 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk
= {
1415 .halt_reg
= 0x4b004,
1416 .halt_check
= BRANCH_HALT
,
1417 .hwcg_reg
= 0x4b004,
1420 .enable_reg
= 0x4b004,
1421 .enable_mask
= BIT(0),
1422 .hw
.init
= &(struct clk_init_data
){
1423 .name
= "gcc_qspi_cnoc_periph_ahb_clk",
1424 .ops
= &clk_branch2_ops
,
1429 static struct clk_branch gcc_qspi_core_clk
= {
1430 .halt_reg
= 0x4b008,
1431 .halt_check
= BRANCH_HALT
,
1433 .enable_reg
= 0x4b008,
1434 .enable_mask
= BIT(0),
1435 .hw
.init
= &(struct clk_init_data
){
1436 .name
= "gcc_qspi_core_clk",
1437 .parent_data
= &(const struct clk_parent_data
){
1438 .hw
= &gcc_qspi_core_clk_src
.clkr
.hw
,
1441 .flags
= CLK_SET_RATE_PARENT
,
1442 .ops
= &clk_branch2_ops
,
1447 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk
= {
1448 .halt_reg
= 0x17014,
1449 .halt_check
= BRANCH_HALT_VOTED
,
1451 .enable_reg
= 0x52008,
1452 .enable_mask
= BIT(9),
1453 .hw
.init
= &(struct clk_init_data
){
1454 .name
= "gcc_qupv3_wrap0_core_2x_clk",
1455 .ops
= &clk_branch2_ops
,
1460 static struct clk_branch gcc_qupv3_wrap0_core_clk
= {
1461 .halt_reg
= 0x1700c,
1462 .halt_check
= BRANCH_HALT_VOTED
,
1464 .enable_reg
= 0x52008,
1465 .enable_mask
= BIT(8),
1466 .hw
.init
= &(struct clk_init_data
){
1467 .name
= "gcc_qupv3_wrap0_core_clk",
1468 .ops
= &clk_branch2_ops
,
1473 static struct clk_branch gcc_qupv3_wrap0_s0_clk
= {
1474 .halt_reg
= 0x17030,
1475 .halt_check
= BRANCH_HALT_VOTED
,
1477 .enable_reg
= 0x52008,
1478 .enable_mask
= BIT(10),
1479 .hw
.init
= &(struct clk_init_data
){
1480 .name
= "gcc_qupv3_wrap0_s0_clk",
1481 .parent_data
= &(const struct clk_parent_data
){
1482 .hw
= &gcc_qupv3_wrap0_s0_clk_src
.clkr
.hw
,
1485 .flags
= CLK_SET_RATE_PARENT
,
1486 .ops
= &clk_branch2_ops
,
1491 static struct clk_branch gcc_qupv3_wrap0_s1_clk
= {
1492 .halt_reg
= 0x17160,
1493 .halt_check
= BRANCH_HALT_VOTED
,
1495 .enable_reg
= 0x52008,
1496 .enable_mask
= BIT(11),
1497 .hw
.init
= &(struct clk_init_data
){
1498 .name
= "gcc_qupv3_wrap0_s1_clk",
1499 .parent_data
= &(const struct clk_parent_data
){
1500 .hw
= &gcc_qupv3_wrap0_s1_clk_src
.clkr
.hw
,
1503 .flags
= CLK_SET_RATE_PARENT
,
1504 .ops
= &clk_branch2_ops
,
1509 static struct clk_branch gcc_qupv3_wrap0_s2_clk
= {
1510 .halt_reg
= 0x17290,
1511 .halt_check
= BRANCH_HALT_VOTED
,
1513 .enable_reg
= 0x52008,
1514 .enable_mask
= BIT(12),
1515 .hw
.init
= &(struct clk_init_data
){
1516 .name
= "gcc_qupv3_wrap0_s2_clk",
1517 .parent_data
= &(const struct clk_parent_data
){
1518 .hw
= &gcc_qupv3_wrap0_s2_clk_src
.clkr
.hw
,
1521 .flags
= CLK_SET_RATE_PARENT
,
1522 .ops
= &clk_branch2_ops
,
1527 static struct clk_branch gcc_qupv3_wrap0_s3_clk
= {
1528 .halt_reg
= 0x173c0,
1529 .halt_check
= BRANCH_HALT_VOTED
,
1531 .enable_reg
= 0x52008,
1532 .enable_mask
= BIT(13),
1533 .hw
.init
= &(struct clk_init_data
){
1534 .name
= "gcc_qupv3_wrap0_s3_clk",
1535 .parent_data
= &(const struct clk_parent_data
){
1536 .hw
= &gcc_qupv3_wrap0_s3_clk_src
.clkr
.hw
,
1539 .flags
= CLK_SET_RATE_PARENT
,
1540 .ops
= &clk_branch2_ops
,
1545 static struct clk_branch gcc_qupv3_wrap0_s4_clk
= {
1546 .halt_reg
= 0x174f0,
1547 .halt_check
= BRANCH_HALT_VOTED
,
1549 .enable_reg
= 0x52008,
1550 .enable_mask
= BIT(14),
1551 .hw
.init
= &(struct clk_init_data
){
1552 .name
= "gcc_qupv3_wrap0_s4_clk",
1553 .parent_data
= &(const struct clk_parent_data
){
1554 .hw
= &gcc_qupv3_wrap0_s4_clk_src
.clkr
.hw
,
1557 .flags
= CLK_SET_RATE_PARENT
,
1558 .ops
= &clk_branch2_ops
,
1563 static struct clk_branch gcc_qupv3_wrap0_s5_clk
= {
1564 .halt_reg
= 0x17620,
1565 .halt_check
= BRANCH_HALT_VOTED
,
1567 .enable_reg
= 0x52008,
1568 .enable_mask
= BIT(15),
1569 .hw
.init
= &(struct clk_init_data
){
1570 .name
= "gcc_qupv3_wrap0_s5_clk",
1571 .parent_data
= &(const struct clk_parent_data
){
1572 .hw
= &gcc_qupv3_wrap0_s5_clk_src
.clkr
.hw
,
1575 .flags
= CLK_SET_RATE_PARENT
,
1576 .ops
= &clk_branch2_ops
,
1581 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk
= {
1582 .halt_reg
= 0x18004,
1583 .halt_check
= BRANCH_HALT_VOTED
,
1585 .enable_reg
= 0x52008,
1586 .enable_mask
= BIT(18),
1587 .hw
.init
= &(struct clk_init_data
){
1588 .name
= "gcc_qupv3_wrap1_core_2x_clk",
1589 .ops
= &clk_branch2_ops
,
1594 static struct clk_branch gcc_qupv3_wrap1_core_clk
= {
1595 .halt_reg
= 0x18008,
1596 .halt_check
= BRANCH_HALT_VOTED
,
1598 .enable_reg
= 0x52008,
1599 .enable_mask
= BIT(19),
1600 .hw
.init
= &(struct clk_init_data
){
1601 .name
= "gcc_qupv3_wrap1_core_clk",
1602 .ops
= &clk_branch2_ops
,
1607 static struct clk_branch gcc_qupv3_wrap1_s0_clk
= {
1608 .halt_reg
= 0x18014,
1609 .halt_check
= BRANCH_HALT_VOTED
,
1611 .enable_reg
= 0x52008,
1612 .enable_mask
= BIT(22),
1613 .hw
.init
= &(struct clk_init_data
){
1614 .name
= "gcc_qupv3_wrap1_s0_clk",
1615 .parent_data
= &(const struct clk_parent_data
){
1616 .hw
= &gcc_qupv3_wrap1_s0_clk_src
.clkr
.hw
,
1619 .flags
= CLK_SET_RATE_PARENT
,
1620 .ops
= &clk_branch2_ops
,
1625 static struct clk_branch gcc_qupv3_wrap1_s1_clk
= {
1626 .halt_reg
= 0x18144,
1627 .halt_check
= BRANCH_HALT_VOTED
,
1629 .enable_reg
= 0x52008,
1630 .enable_mask
= BIT(23),
1631 .hw
.init
= &(struct clk_init_data
){
1632 .name
= "gcc_qupv3_wrap1_s1_clk",
1633 .parent_data
= &(const struct clk_parent_data
){
1634 .hw
= &gcc_qupv3_wrap1_s1_clk_src
.clkr
.hw
,
1637 .flags
= CLK_SET_RATE_PARENT
,
1638 .ops
= &clk_branch2_ops
,
1643 static struct clk_branch gcc_qupv3_wrap1_s2_clk
= {
1644 .halt_reg
= 0x18274,
1645 .halt_check
= BRANCH_HALT_VOTED
,
1647 .enable_reg
= 0x52008,
1648 .enable_mask
= BIT(24),
1649 .hw
.init
= &(struct clk_init_data
){
1650 .name
= "gcc_qupv3_wrap1_s2_clk",
1651 .parent_data
= &(const struct clk_parent_data
){
1652 .hw
= &gcc_qupv3_wrap1_s2_clk_src
.clkr
.hw
,
1655 .flags
= CLK_SET_RATE_PARENT
,
1656 .ops
= &clk_branch2_ops
,
1661 static struct clk_branch gcc_qupv3_wrap1_s3_clk
= {
1662 .halt_reg
= 0x183a4,
1663 .halt_check
= BRANCH_HALT_VOTED
,
1665 .enable_reg
= 0x52008,
1666 .enable_mask
= BIT(25),
1667 .hw
.init
= &(struct clk_init_data
){
1668 .name
= "gcc_qupv3_wrap1_s3_clk",
1669 .parent_data
= &(const struct clk_parent_data
){
1670 .hw
= &gcc_qupv3_wrap1_s3_clk_src
.clkr
.hw
,
1673 .flags
= CLK_SET_RATE_PARENT
,
1674 .ops
= &clk_branch2_ops
,
1679 static struct clk_branch gcc_qupv3_wrap1_s4_clk
= {
1680 .halt_reg
= 0x184d4,
1681 .halt_check
= BRANCH_HALT_VOTED
,
1683 .enable_reg
= 0x52008,
1684 .enable_mask
= BIT(26),
1685 .hw
.init
= &(struct clk_init_data
){
1686 .name
= "gcc_qupv3_wrap1_s4_clk",
1687 .parent_data
= &(const struct clk_parent_data
){
1688 .hw
= &gcc_qupv3_wrap1_s4_clk_src
.clkr
.hw
,
1691 .flags
= CLK_SET_RATE_PARENT
,
1692 .ops
= &clk_branch2_ops
,
1697 static struct clk_branch gcc_qupv3_wrap1_s5_clk
= {
1698 .halt_reg
= 0x18604,
1699 .halt_check
= BRANCH_HALT_VOTED
,
1701 .enable_reg
= 0x52008,
1702 .enable_mask
= BIT(27),
1703 .hw
.init
= &(struct clk_init_data
){
1704 .name
= "gcc_qupv3_wrap1_s5_clk",
1705 .parent_data
= &(const struct clk_parent_data
){
1706 .hw
= &gcc_qupv3_wrap1_s5_clk_src
.clkr
.hw
,
1709 .flags
= CLK_SET_RATE_PARENT
,
1710 .ops
= &clk_branch2_ops
,
1715 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk
= {
1716 .halt_reg
= 0x17004,
1717 .halt_check
= BRANCH_HALT_VOTED
,
1719 .enable_reg
= 0x52008,
1720 .enable_mask
= BIT(6),
1721 .hw
.init
= &(struct clk_init_data
){
1722 .name
= "gcc_qupv3_wrap_0_m_ahb_clk",
1723 .ops
= &clk_branch2_ops
,
1728 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk
= {
1729 .halt_reg
= 0x17008,
1730 .halt_check
= BRANCH_HALT_VOTED
,
1731 .hwcg_reg
= 0x17008,
1734 .enable_reg
= 0x52008,
1735 .enable_mask
= BIT(7),
1736 .hw
.init
= &(struct clk_init_data
){
1737 .name
= "gcc_qupv3_wrap_0_s_ahb_clk",
1738 .ops
= &clk_branch2_ops
,
1743 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk
= {
1744 .halt_reg
= 0x1800c,
1745 .halt_check
= BRANCH_HALT_VOTED
,
1747 .enable_reg
= 0x52008,
1748 .enable_mask
= BIT(20),
1749 .hw
.init
= &(struct clk_init_data
){
1750 .name
= "gcc_qupv3_wrap_1_m_ahb_clk",
1751 .ops
= &clk_branch2_ops
,
1756 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk
= {
1757 .halt_reg
= 0x18010,
1758 .halt_check
= BRANCH_HALT_VOTED
,
1759 .hwcg_reg
= 0x18010,
1762 .enable_reg
= 0x52008,
1763 .enable_mask
= BIT(21),
1764 .hw
.init
= &(struct clk_init_data
){
1765 .name
= "gcc_qupv3_wrap_1_s_ahb_clk",
1766 .ops
= &clk_branch2_ops
,
1771 static struct clk_branch gcc_sdcc1_ahb_clk
= {
1772 .halt_reg
= 0x12008,
1773 .halt_check
= BRANCH_HALT
,
1775 .enable_reg
= 0x12008,
1776 .enable_mask
= BIT(0),
1777 .hw
.init
= &(struct clk_init_data
){
1778 .name
= "gcc_sdcc1_ahb_clk",
1779 .ops
= &clk_branch2_ops
,
1784 static struct clk_branch gcc_sdcc1_apps_clk
= {
1785 .halt_reg
= 0x1200c,
1786 .halt_check
= BRANCH_HALT
,
1788 .enable_reg
= 0x1200c,
1789 .enable_mask
= BIT(0),
1790 .hw
.init
= &(struct clk_init_data
){
1791 .name
= "gcc_sdcc1_apps_clk",
1792 .parent_data
= &(const struct clk_parent_data
){
1793 .hw
= &gcc_sdcc1_apps_clk_src
.clkr
.hw
,
1796 .flags
= CLK_SET_RATE_PARENT
,
1797 .ops
= &clk_branch2_ops
,
1802 static struct clk_branch gcc_sdcc1_ice_core_clk
= {
1803 .halt_reg
= 0x12040,
1804 .halt_check
= BRANCH_HALT
,
1806 .enable_reg
= 0x12040,
1807 .enable_mask
= BIT(0),
1808 .hw
.init
= &(struct clk_init_data
){
1809 .name
= "gcc_sdcc1_ice_core_clk",
1810 .parent_data
= &(const struct clk_parent_data
){
1811 .hw
= &gcc_sdcc1_ice_core_clk_src
.clkr
.hw
,
1814 .flags
= CLK_SET_RATE_PARENT
,
1815 .ops
= &clk_branch2_ops
,
1820 static struct clk_branch gcc_sdcc2_ahb_clk
= {
1821 .halt_reg
= 0x14008,
1822 .halt_check
= BRANCH_HALT
,
1824 .enable_reg
= 0x14008,
1825 .enable_mask
= BIT(0),
1826 .hw
.init
= &(struct clk_init_data
){
1827 .name
= "gcc_sdcc2_ahb_clk",
1828 .ops
= &clk_branch2_ops
,
1833 static struct clk_branch gcc_sdcc2_apps_clk
= {
1834 .halt_reg
= 0x14004,
1835 .halt_check
= BRANCH_HALT
,
1837 .enable_reg
= 0x14004,
1838 .enable_mask
= BIT(0),
1839 .hw
.init
= &(struct clk_init_data
){
1840 .name
= "gcc_sdcc2_apps_clk",
1841 .parent_data
= &(const struct clk_parent_data
){
1842 .hw
= &gcc_sdcc2_apps_clk_src
.clkr
.hw
,
1845 .flags
= CLK_SET_RATE_PARENT
,
1846 .ops
= &clk_branch2_ops
,
1851 /* For CPUSS functionality the SYS NOC clock needs to be left enabled */
1852 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk
= {
1854 .halt_check
= BRANCH_HALT_VOTED
,
1856 .enable_reg
= 0x52000,
1857 .enable_mask
= BIT(0),
1858 .hw
.init
= &(struct clk_init_data
){
1859 .name
= "gcc_sys_noc_cpuss_ahb_clk",
1860 .parent_data
= &(const struct clk_parent_data
){
1861 .hw
= &gcc_cpuss_ahb_clk_src
.clkr
.hw
,
1864 .flags
= CLK_IS_CRITICAL
| CLK_SET_RATE_PARENT
,
1865 .ops
= &clk_branch2_ops
,
1870 static struct clk_branch gcc_ufs_mem_clkref_clk
= {
1871 .halt_reg
= 0x8c000,
1872 .halt_check
= BRANCH_HALT
,
1874 .enable_reg
= 0x8c000,
1875 .enable_mask
= BIT(0),
1876 .hw
.init
= &(struct clk_init_data
){
1877 .name
= "gcc_ufs_mem_clkref_clk",
1878 .ops
= &clk_branch2_ops
,
1883 static struct clk_branch gcc_ufs_phy_ahb_clk
= {
1884 .halt_reg
= 0x77014,
1885 .halt_check
= BRANCH_HALT
,
1886 .hwcg_reg
= 0x77014,
1889 .enable_reg
= 0x77014,
1890 .enable_mask
= BIT(0),
1891 .hw
.init
= &(struct clk_init_data
){
1892 .name
= "gcc_ufs_phy_ahb_clk",
1893 .ops
= &clk_branch2_ops
,
1898 static struct clk_branch gcc_ufs_phy_axi_clk
= {
1899 .halt_reg
= 0x77038,
1900 .halt_check
= BRANCH_HALT
,
1901 .hwcg_reg
= 0x77038,
1904 .enable_reg
= 0x77038,
1905 .enable_mask
= BIT(0),
1906 .hw
.init
= &(struct clk_init_data
){
1907 .name
= "gcc_ufs_phy_axi_clk",
1908 .parent_data
= &(const struct clk_parent_data
){
1909 .hw
= &gcc_ufs_phy_axi_clk_src
.clkr
.hw
,
1912 .flags
= CLK_SET_RATE_PARENT
,
1913 .ops
= &clk_branch2_ops
,
1918 static struct clk_branch gcc_ufs_phy_ice_core_clk
= {
1919 .halt_reg
= 0x77090,
1920 .halt_check
= BRANCH_HALT
,
1921 .hwcg_reg
= 0x77090,
1924 .enable_reg
= 0x77090,
1925 .enable_mask
= BIT(0),
1926 .hw
.init
= &(struct clk_init_data
){
1927 .name
= "gcc_ufs_phy_ice_core_clk",
1928 .parent_data
= &(const struct clk_parent_data
){
1929 .hw
= &gcc_ufs_phy_ice_core_clk_src
.clkr
.hw
,
1932 .flags
= CLK_SET_RATE_PARENT
,
1933 .ops
= &clk_branch2_ops
,
1938 static struct clk_branch gcc_ufs_phy_phy_aux_clk
= {
1939 .halt_reg
= 0x77094,
1940 .halt_check
= BRANCH_HALT
,
1941 .hwcg_reg
= 0x77094,
1944 .enable_reg
= 0x77094,
1945 .enable_mask
= BIT(0),
1946 .hw
.init
= &(struct clk_init_data
){
1947 .name
= "gcc_ufs_phy_phy_aux_clk",
1948 .parent_data
= &(const struct clk_parent_data
){
1949 .hw
= &gcc_ufs_phy_phy_aux_clk_src
.clkr
.hw
,
1952 .flags
= CLK_SET_RATE_PARENT
,
1953 .ops
= &clk_branch2_ops
,
1958 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk
= {
1959 .halt_reg
= 0x7701c,
1960 .halt_check
= BRANCH_HALT_SKIP
,
1962 .enable_reg
= 0x7701c,
1963 .enable_mask
= BIT(0),
1964 .hw
.init
= &(struct clk_init_data
){
1965 .name
= "gcc_ufs_phy_rx_symbol_0_clk",
1966 .ops
= &clk_branch2_ops
,
1971 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk
= {
1972 .halt_reg
= 0x77018,
1973 .halt_check
= BRANCH_HALT_SKIP
,
1975 .enable_reg
= 0x77018,
1976 .enable_mask
= BIT(0),
1977 .hw
.init
= &(struct clk_init_data
){
1978 .name
= "gcc_ufs_phy_tx_symbol_0_clk",
1979 .ops
= &clk_branch2_ops
,
1984 static struct clk_branch gcc_ufs_phy_unipro_core_clk
= {
1985 .halt_reg
= 0x7708c,
1986 .halt_check
= BRANCH_HALT
,
1987 .hwcg_reg
= 0x7708c,
1990 .enable_reg
= 0x7708c,
1991 .enable_mask
= BIT(0),
1992 .hw
.init
= &(struct clk_init_data
){
1993 .name
= "gcc_ufs_phy_unipro_core_clk",
1994 .parent_data
= &(const struct clk_parent_data
){
1995 .hw
= &gcc_ufs_phy_unipro_core_clk_src
.clkr
.hw
,
1998 .flags
= CLK_SET_RATE_PARENT
,
1999 .ops
= &clk_branch2_ops
,
2004 static struct clk_branch gcc_usb30_prim_master_clk
= {
2006 .halt_check
= BRANCH_HALT
,
2008 .enable_reg
= 0xf010,
2009 .enable_mask
= BIT(0),
2010 .hw
.init
= &(struct clk_init_data
){
2011 .name
= "gcc_usb30_prim_master_clk",
2012 .parent_data
= &(const struct clk_parent_data
){
2013 .hw
= &gcc_usb30_prim_master_clk_src
.clkr
.hw
,
2016 .flags
= CLK_SET_RATE_PARENT
,
2017 .ops
= &clk_branch2_ops
,
2022 static struct clk_branch gcc_usb30_prim_mock_utmi_clk
= {
2024 .halt_check
= BRANCH_HALT
,
2026 .enable_reg
= 0xf018,
2027 .enable_mask
= BIT(0),
2028 .hw
.init
= &(struct clk_init_data
){
2029 .name
= "gcc_usb30_prim_mock_utmi_clk",
2030 .parent_data
= &(const struct clk_parent_data
){
2032 &gcc_usb30_prim_mock_utmi_clk_src
.clkr
.hw
,
2035 .flags
= CLK_SET_RATE_PARENT
,
2036 .ops
= &clk_branch2_ops
,
2041 static struct clk_branch gcc_usb30_prim_sleep_clk
= {
2043 .halt_check
= BRANCH_HALT
,
2045 .enable_reg
= 0xf014,
2046 .enable_mask
= BIT(0),
2047 .hw
.init
= &(struct clk_init_data
){
2048 .name
= "gcc_usb30_prim_sleep_clk",
2049 .ops
= &clk_branch2_ops
,
2054 static struct clk_branch gcc_usb3_prim_clkref_clk
= {
2055 .halt_reg
= 0x8c010,
2056 .halt_check
= BRANCH_HALT
,
2058 .enable_reg
= 0x8c010,
2059 .enable_mask
= BIT(0),
2060 .hw
.init
= &(struct clk_init_data
){
2061 .name
= "gcc_usb3_prim_clkref_clk",
2062 .ops
= &clk_branch2_ops
,
2067 static struct clk_branch gcc_usb3_prim_phy_aux_clk
= {
2069 .halt_check
= BRANCH_HALT
,
2071 .enable_reg
= 0xf050,
2072 .enable_mask
= BIT(0),
2073 .hw
.init
= &(struct clk_init_data
){
2074 .name
= "gcc_usb3_prim_phy_aux_clk",
2075 .parent_data
= &(const struct clk_parent_data
){
2076 .hw
= &gcc_usb3_prim_phy_aux_clk_src
.clkr
.hw
,
2079 .flags
= CLK_SET_RATE_PARENT
,
2080 .ops
= &clk_branch2_ops
,
2085 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk
= {
2087 .halt_check
= BRANCH_HALT
,
2089 .enable_reg
= 0xf054,
2090 .enable_mask
= BIT(0),
2091 .hw
.init
= &(struct clk_init_data
){
2092 .name
= "gcc_usb3_prim_phy_com_aux_clk",
2093 .parent_data
= &(const struct clk_parent_data
){
2094 .hw
= &gcc_usb3_prim_phy_aux_clk_src
.clkr
.hw
,
2097 .flags
= CLK_SET_RATE_PARENT
,
2098 .ops
= &clk_branch2_ops
,
2103 static struct clk_branch gcc_usb3_prim_phy_pipe_clk
= {
2105 .halt_check
= BRANCH_HALT_SKIP
,
2107 .enable_reg
= 0xf058,
2108 .enable_mask
= BIT(0),
2109 .hw
.init
= &(struct clk_init_data
){
2110 .name
= "gcc_usb3_prim_phy_pipe_clk",
2111 .ops
= &clk_branch2_ops
,
2116 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk
= {
2117 .halt_reg
= 0x6a004,
2118 .halt_check
= BRANCH_HALT
,
2119 .hwcg_reg
= 0x6a004,
2122 .enable_reg
= 0x6a004,
2123 .enable_mask
= BIT(0),
2124 .hw
.init
= &(struct clk_init_data
){
2125 .name
= "gcc_usb_phy_cfg_ahb2phy_clk",
2126 .ops
= &clk_branch2_ops
,
2131 static struct clk_branch gcc_video_axi_clk
= {
2133 .halt_check
= BRANCH_HALT
,
2135 .enable_reg
= 0xb01c,
2136 .enable_mask
= BIT(0),
2137 .hw
.init
= &(struct clk_init_data
){
2138 .name
= "gcc_video_axi_clk",
2139 .ops
= &clk_branch2_ops
,
2144 static struct clk_branch gcc_video_gpll0_div_clk_src
= {
2145 .halt_check
= BRANCH_HALT_DELAY
,
2147 .enable_reg
= 0x52000,
2148 .enable_mask
= BIT(20),
2149 .hw
.init
= &(struct clk_init_data
){
2150 .name
= "gcc_video_gpll0_div_clk_src",
2151 .parent_data
= &(const struct clk_parent_data
){
2152 .hw
= &gcc_pll0_main_div_cdiv
.hw
,
2155 .flags
= CLK_SET_RATE_PARENT
,
2156 .ops
= &clk_branch2_ops
,
2161 static struct clk_branch gcc_video_throttle_axi_clk
= {
2163 .halt_check
= BRANCH_HALT
,
2167 .enable_reg
= 0xb07c,
2168 .enable_mask
= BIT(0),
2169 .hw
.init
= &(struct clk_init_data
){
2170 .name
= "gcc_video_throttle_axi_clk",
2171 .ops
= &clk_branch2_ops
,
2176 static struct clk_branch gcc_video_xo_clk
= {
2178 .halt_check
= BRANCH_HALT
,
2180 .enable_reg
= 0xb028,
2181 .enable_mask
= BIT(0),
2182 .hw
.init
= &(struct clk_init_data
){
2183 .name
= "gcc_video_xo_clk",
2184 .ops
= &clk_branch2_ops
,
2189 static struct clk_branch gcc_mss_cfg_ahb_clk
= {
2190 .halt_reg
= 0x8a000,
2191 .halt_check
= BRANCH_HALT
,
2193 .enable_reg
= 0x8a000,
2194 .enable_mask
= BIT(0),
2195 .hw
.init
= &(struct clk_init_data
){
2196 .name
= "gcc_mss_cfg_ahb_clk",
2197 .ops
= &clk_branch2_ops
,
2202 static struct clk_branch gcc_mss_mfab_axis_clk
= {
2203 .halt_reg
= 0x8a004,
2204 .halt_check
= BRANCH_HALT_VOTED
,
2206 .enable_reg
= 0x8a004,
2207 .enable_mask
= BIT(0),
2208 .hw
.init
= &(struct clk_init_data
){
2209 .name
= "gcc_mss_mfab_axis_clk",
2210 .ops
= &clk_branch2_ops
,
2215 static struct clk_branch gcc_mss_nav_axi_clk
= {
2216 .halt_reg
= 0x8a00c,
2217 .halt_check
= BRANCH_HALT_VOTED
,
2219 .enable_reg
= 0x8a00c,
2220 .enable_mask
= BIT(0),
2221 .hw
.init
= &(struct clk_init_data
){
2222 .name
= "gcc_mss_nav_axi_clk",
2223 .ops
= &clk_branch2_ops
,
2228 static struct clk_branch gcc_mss_snoc_axi_clk
= {
2229 .halt_reg
= 0x8a150,
2230 .halt_check
= BRANCH_HALT
,
2232 .enable_reg
= 0x8a150,
2233 .enable_mask
= BIT(0),
2234 .hw
.init
= &(struct clk_init_data
){
2235 .name
= "gcc_mss_snoc_axi_clk",
2236 .ops
= &clk_branch2_ops
,
2241 static struct clk_branch gcc_mss_q6_memnoc_axi_clk
= {
2242 .halt_reg
= 0x8a154,
2243 .halt_check
= BRANCH_HALT
,
2245 .enable_reg
= 0x8a154,
2246 .enable_mask
= BIT(0),
2247 .hw
.init
= &(struct clk_init_data
){
2248 .name
= "gcc_mss_q6_memnoc_axi_clk",
2249 .ops
= &clk_branch2_ops
,
2254 static struct gdsc ufs_phy_gdsc
= {
2257 .name
= "ufs_phy_gdsc",
2259 .pwrsts
= PWRSTS_OFF_ON
,
2262 static struct gdsc usb30_prim_gdsc
= {
2265 .name
= "usb30_prim_gdsc",
2267 .pwrsts
= PWRSTS_OFF_ON
,
2270 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc
= {
2273 .name
= "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
2275 .pwrsts
= PWRSTS_OFF_ON
,
2279 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc
= {
2282 .name
= "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
2284 .pwrsts
= PWRSTS_OFF_ON
,
2288 static struct gdsc
*gcc_sc7180_gdscs
[] = {
2289 [UFS_PHY_GDSC
] = &ufs_phy_gdsc
,
2290 [USB30_PRIM_GDSC
] = &usb30_prim_gdsc
,
2291 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC
] =
2292 &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc
,
2293 [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC
] =
2294 &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc
,
2298 static struct clk_hw
*gcc_sc7180_hws
[] = {
2299 [GCC_GPLL0_MAIN_DIV_CDIV
] = &gcc_pll0_main_div_cdiv
.hw
,
2302 static struct clk_regmap
*gcc_sc7180_clocks
[] = {
2303 [GCC_AGGRE_UFS_PHY_AXI_CLK
] = &gcc_aggre_ufs_phy_axi_clk
.clkr
,
2304 [GCC_AGGRE_USB3_PRIM_AXI_CLK
] = &gcc_aggre_usb3_prim_axi_clk
.clkr
,
2305 [GCC_BOOT_ROM_AHB_CLK
] = &gcc_boot_rom_ahb_clk
.clkr
,
2306 [GCC_CAMERA_AHB_CLK
] = &gcc_camera_ahb_clk
.clkr
,
2307 [GCC_CAMERA_HF_AXI_CLK
] = &gcc_camera_hf_axi_clk
.clkr
,
2308 [GCC_CAMERA_THROTTLE_HF_AXI_CLK
] = &gcc_camera_throttle_hf_axi_clk
.clkr
,
2309 [GCC_CAMERA_XO_CLK
] = &gcc_camera_xo_clk
.clkr
,
2310 [GCC_CE1_AHB_CLK
] = &gcc_ce1_ahb_clk
.clkr
,
2311 [GCC_CE1_AXI_CLK
] = &gcc_ce1_axi_clk
.clkr
,
2312 [GCC_CE1_CLK
] = &gcc_ce1_clk
.clkr
,
2313 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK
] = &gcc_cfg_noc_usb3_prim_axi_clk
.clkr
,
2314 [GCC_CPUSS_AHB_CLK
] = &gcc_cpuss_ahb_clk
.clkr
,
2315 [GCC_CPUSS_AHB_CLK_SRC
] = &gcc_cpuss_ahb_clk_src
.clkr
,
2316 [GCC_CPUSS_RBCPR_CLK
] = &gcc_cpuss_rbcpr_clk
.clkr
,
2317 [GCC_DDRSS_GPU_AXI_CLK
] = &gcc_ddrss_gpu_axi_clk
.clkr
,
2318 [GCC_DISP_GPLL0_CLK_SRC
] = &gcc_disp_gpll0_clk_src
.clkr
,
2319 [GCC_DISP_GPLL0_DIV_CLK_SRC
] = &gcc_disp_gpll0_div_clk_src
.clkr
,
2320 [GCC_DISP_HF_AXI_CLK
] = &gcc_disp_hf_axi_clk
.clkr
,
2321 [GCC_DISP_THROTTLE_HF_AXI_CLK
] = &gcc_disp_throttle_hf_axi_clk
.clkr
,
2322 [GCC_DISP_XO_CLK
] = &gcc_disp_xo_clk
.clkr
,
2323 [GCC_GP1_CLK
] = &gcc_gp1_clk
.clkr
,
2324 [GCC_GP1_CLK_SRC
] = &gcc_gp1_clk_src
.clkr
,
2325 [GCC_GP2_CLK
] = &gcc_gp2_clk
.clkr
,
2326 [GCC_GP2_CLK_SRC
] = &gcc_gp2_clk_src
.clkr
,
2327 [GCC_GP3_CLK
] = &gcc_gp3_clk
.clkr
,
2328 [GCC_GP3_CLK_SRC
] = &gcc_gp3_clk_src
.clkr
,
2329 [GCC_GPU_GPLL0_CLK_SRC
] = &gcc_gpu_gpll0_clk_src
.clkr
,
2330 [GCC_GPU_GPLL0_DIV_CLK_SRC
] = &gcc_gpu_gpll0_div_clk_src
.clkr
,
2331 [GCC_GPU_MEMNOC_GFX_CLK
] = &gcc_gpu_memnoc_gfx_clk
.clkr
,
2332 [GCC_GPU_SNOC_DVM_GFX_CLK
] = &gcc_gpu_snoc_dvm_gfx_clk
.clkr
,
2333 [GCC_NPU_AXI_CLK
] = &gcc_npu_axi_clk
.clkr
,
2334 [GCC_NPU_BWMON_AXI_CLK
] = &gcc_npu_bwmon_axi_clk
.clkr
,
2335 [GCC_NPU_BWMON_DMA_CFG_AHB_CLK
] = &gcc_npu_bwmon_dma_cfg_ahb_clk
.clkr
,
2336 [GCC_NPU_BWMON_DSP_CFG_AHB_CLK
] = &gcc_npu_bwmon_dsp_cfg_ahb_clk
.clkr
,
2337 [GCC_NPU_CFG_AHB_CLK
] = &gcc_npu_cfg_ahb_clk
.clkr
,
2338 [GCC_NPU_DMA_CLK
] = &gcc_npu_dma_clk
.clkr
,
2339 [GCC_NPU_GPLL0_CLK_SRC
] = &gcc_npu_gpll0_clk_src
.clkr
,
2340 [GCC_NPU_GPLL0_DIV_CLK_SRC
] = &gcc_npu_gpll0_div_clk_src
.clkr
,
2341 [GCC_PDM2_CLK
] = &gcc_pdm2_clk
.clkr
,
2342 [GCC_PDM2_CLK_SRC
] = &gcc_pdm2_clk_src
.clkr
,
2343 [GCC_PDM_AHB_CLK
] = &gcc_pdm_ahb_clk
.clkr
,
2344 [GCC_PDM_XO4_CLK
] = &gcc_pdm_xo4_clk
.clkr
,
2345 [GCC_PRNG_AHB_CLK
] = &gcc_prng_ahb_clk
.clkr
,
2346 [GCC_QSPI_CNOC_PERIPH_AHB_CLK
] = &gcc_qspi_cnoc_periph_ahb_clk
.clkr
,
2347 [GCC_QSPI_CORE_CLK
] = &gcc_qspi_core_clk
.clkr
,
2348 [GCC_QSPI_CORE_CLK_SRC
] = &gcc_qspi_core_clk_src
.clkr
,
2349 [GCC_QUPV3_WRAP0_CORE_2X_CLK
] = &gcc_qupv3_wrap0_core_2x_clk
.clkr
,
2350 [GCC_QUPV3_WRAP0_CORE_CLK
] = &gcc_qupv3_wrap0_core_clk
.clkr
,
2351 [GCC_QUPV3_WRAP0_S0_CLK
] = &gcc_qupv3_wrap0_s0_clk
.clkr
,
2352 [GCC_QUPV3_WRAP0_S0_CLK_SRC
] = &gcc_qupv3_wrap0_s0_clk_src
.clkr
,
2353 [GCC_QUPV3_WRAP0_S1_CLK
] = &gcc_qupv3_wrap0_s1_clk
.clkr
,
2354 [GCC_QUPV3_WRAP0_S1_CLK_SRC
] = &gcc_qupv3_wrap0_s1_clk_src
.clkr
,
2355 [GCC_QUPV3_WRAP0_S2_CLK
] = &gcc_qupv3_wrap0_s2_clk
.clkr
,
2356 [GCC_QUPV3_WRAP0_S2_CLK_SRC
] = &gcc_qupv3_wrap0_s2_clk_src
.clkr
,
2357 [GCC_QUPV3_WRAP0_S3_CLK
] = &gcc_qupv3_wrap0_s3_clk
.clkr
,
2358 [GCC_QUPV3_WRAP0_S3_CLK_SRC
] = &gcc_qupv3_wrap0_s3_clk_src
.clkr
,
2359 [GCC_QUPV3_WRAP0_S4_CLK
] = &gcc_qupv3_wrap0_s4_clk
.clkr
,
2360 [GCC_QUPV3_WRAP0_S4_CLK_SRC
] = &gcc_qupv3_wrap0_s4_clk_src
.clkr
,
2361 [GCC_QUPV3_WRAP0_S5_CLK
] = &gcc_qupv3_wrap0_s5_clk
.clkr
,
2362 [GCC_QUPV3_WRAP0_S5_CLK_SRC
] = &gcc_qupv3_wrap0_s5_clk_src
.clkr
,
2363 [GCC_QUPV3_WRAP1_CORE_2X_CLK
] = &gcc_qupv3_wrap1_core_2x_clk
.clkr
,
2364 [GCC_QUPV3_WRAP1_CORE_CLK
] = &gcc_qupv3_wrap1_core_clk
.clkr
,
2365 [GCC_QUPV3_WRAP1_S0_CLK
] = &gcc_qupv3_wrap1_s0_clk
.clkr
,
2366 [GCC_QUPV3_WRAP1_S0_CLK_SRC
] = &gcc_qupv3_wrap1_s0_clk_src
.clkr
,
2367 [GCC_QUPV3_WRAP1_S1_CLK
] = &gcc_qupv3_wrap1_s1_clk
.clkr
,
2368 [GCC_QUPV3_WRAP1_S1_CLK_SRC
] = &gcc_qupv3_wrap1_s1_clk_src
.clkr
,
2369 [GCC_QUPV3_WRAP1_S2_CLK
] = &gcc_qupv3_wrap1_s2_clk
.clkr
,
2370 [GCC_QUPV3_WRAP1_S2_CLK_SRC
] = &gcc_qupv3_wrap1_s2_clk_src
.clkr
,
2371 [GCC_QUPV3_WRAP1_S3_CLK
] = &gcc_qupv3_wrap1_s3_clk
.clkr
,
2372 [GCC_QUPV3_WRAP1_S3_CLK_SRC
] = &gcc_qupv3_wrap1_s3_clk_src
.clkr
,
2373 [GCC_QUPV3_WRAP1_S4_CLK
] = &gcc_qupv3_wrap1_s4_clk
.clkr
,
2374 [GCC_QUPV3_WRAP1_S4_CLK_SRC
] = &gcc_qupv3_wrap1_s4_clk_src
.clkr
,
2375 [GCC_QUPV3_WRAP1_S5_CLK
] = &gcc_qupv3_wrap1_s5_clk
.clkr
,
2376 [GCC_QUPV3_WRAP1_S5_CLK_SRC
] = &gcc_qupv3_wrap1_s5_clk_src
.clkr
,
2377 [GCC_QUPV3_WRAP_0_M_AHB_CLK
] = &gcc_qupv3_wrap_0_m_ahb_clk
.clkr
,
2378 [GCC_QUPV3_WRAP_0_S_AHB_CLK
] = &gcc_qupv3_wrap_0_s_ahb_clk
.clkr
,
2379 [GCC_QUPV3_WRAP_1_M_AHB_CLK
] = &gcc_qupv3_wrap_1_m_ahb_clk
.clkr
,
2380 [GCC_QUPV3_WRAP_1_S_AHB_CLK
] = &gcc_qupv3_wrap_1_s_ahb_clk
.clkr
,
2381 [GCC_SDCC1_AHB_CLK
] = &gcc_sdcc1_ahb_clk
.clkr
,
2382 [GCC_SDCC1_APPS_CLK
] = &gcc_sdcc1_apps_clk
.clkr
,
2383 [GCC_SDCC1_APPS_CLK_SRC
] = &gcc_sdcc1_apps_clk_src
.clkr
,
2384 [GCC_SDCC1_ICE_CORE_CLK
] = &gcc_sdcc1_ice_core_clk
.clkr
,
2385 [GCC_SDCC1_ICE_CORE_CLK_SRC
] = &gcc_sdcc1_ice_core_clk_src
.clkr
,
2386 [GCC_SDCC2_AHB_CLK
] = &gcc_sdcc2_ahb_clk
.clkr
,
2387 [GCC_SDCC2_APPS_CLK
] = &gcc_sdcc2_apps_clk
.clkr
,
2388 [GCC_SDCC2_APPS_CLK_SRC
] = &gcc_sdcc2_apps_clk_src
.clkr
,
2389 [GCC_SYS_NOC_CPUSS_AHB_CLK
] = &gcc_sys_noc_cpuss_ahb_clk
.clkr
,
2390 [GCC_UFS_MEM_CLKREF_CLK
] = &gcc_ufs_mem_clkref_clk
.clkr
,
2391 [GCC_UFS_PHY_AHB_CLK
] = &gcc_ufs_phy_ahb_clk
.clkr
,
2392 [GCC_UFS_PHY_AXI_CLK
] = &gcc_ufs_phy_axi_clk
.clkr
,
2393 [GCC_UFS_PHY_AXI_CLK_SRC
] = &gcc_ufs_phy_axi_clk_src
.clkr
,
2394 [GCC_UFS_PHY_ICE_CORE_CLK
] = &gcc_ufs_phy_ice_core_clk
.clkr
,
2395 [GCC_UFS_PHY_ICE_CORE_CLK_SRC
] = &gcc_ufs_phy_ice_core_clk_src
.clkr
,
2396 [GCC_UFS_PHY_PHY_AUX_CLK
] = &gcc_ufs_phy_phy_aux_clk
.clkr
,
2397 [GCC_UFS_PHY_PHY_AUX_CLK_SRC
] = &gcc_ufs_phy_phy_aux_clk_src
.clkr
,
2398 [GCC_UFS_PHY_RX_SYMBOL_0_CLK
] = &gcc_ufs_phy_rx_symbol_0_clk
.clkr
,
2399 [GCC_UFS_PHY_TX_SYMBOL_0_CLK
] = &gcc_ufs_phy_tx_symbol_0_clk
.clkr
,
2400 [GCC_UFS_PHY_UNIPRO_CORE_CLK
] = &gcc_ufs_phy_unipro_core_clk
.clkr
,
2401 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC
] =
2402 &gcc_ufs_phy_unipro_core_clk_src
.clkr
,
2403 [GCC_USB30_PRIM_MASTER_CLK
] = &gcc_usb30_prim_master_clk
.clkr
,
2404 [GCC_USB30_PRIM_MASTER_CLK_SRC
] = &gcc_usb30_prim_master_clk_src
.clkr
,
2405 [GCC_USB30_PRIM_MOCK_UTMI_CLK
] = &gcc_usb30_prim_mock_utmi_clk
.clkr
,
2406 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC
] =
2407 &gcc_usb30_prim_mock_utmi_clk_src
.clkr
,
2408 [GCC_USB30_PRIM_SLEEP_CLK
] = &gcc_usb30_prim_sleep_clk
.clkr
,
2409 [GCC_USB3_PRIM_CLKREF_CLK
] = &gcc_usb3_prim_clkref_clk
.clkr
,
2410 [GCC_USB3_PRIM_PHY_AUX_CLK
] = &gcc_usb3_prim_phy_aux_clk
.clkr
,
2411 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC
] = &gcc_usb3_prim_phy_aux_clk_src
.clkr
,
2412 [GCC_USB3_PRIM_PHY_COM_AUX_CLK
] = &gcc_usb3_prim_phy_com_aux_clk
.clkr
,
2413 [GCC_USB3_PRIM_PHY_PIPE_CLK
] = &gcc_usb3_prim_phy_pipe_clk
.clkr
,
2414 [GCC_USB_PHY_CFG_AHB2PHY_CLK
] = &gcc_usb_phy_cfg_ahb2phy_clk
.clkr
,
2415 [GCC_VIDEO_AXI_CLK
] = &gcc_video_axi_clk
.clkr
,
2416 [GCC_VIDEO_GPLL0_DIV_CLK_SRC
] = &gcc_video_gpll0_div_clk_src
.clkr
,
2417 [GCC_VIDEO_THROTTLE_AXI_CLK
] = &gcc_video_throttle_axi_clk
.clkr
,
2418 [GCC_VIDEO_XO_CLK
] = &gcc_video_xo_clk
.clkr
,
2419 [GPLL0
] = &gpll0
.clkr
,
2420 [GPLL0_OUT_EVEN
] = &gpll0_out_even
.clkr
,
2421 [GPLL6
] = &gpll6
.clkr
,
2422 [GPLL7
] = &gpll7
.clkr
,
2423 [GPLL4
] = &gpll4
.clkr
,
2424 [GPLL1
] = &gpll1
.clkr
,
2425 [GCC_MSS_CFG_AHB_CLK
] = &gcc_mss_cfg_ahb_clk
.clkr
,
2426 [GCC_MSS_MFAB_AXIS_CLK
] = &gcc_mss_mfab_axis_clk
.clkr
,
2427 [GCC_MSS_NAV_AXI_CLK
] = &gcc_mss_nav_axi_clk
.clkr
,
2428 [GCC_MSS_Q6_MEMNOC_AXI_CLK
] = &gcc_mss_q6_memnoc_axi_clk
.clkr
,
2429 [GCC_MSS_SNOC_AXI_CLK
] = &gcc_mss_snoc_axi_clk
.clkr
,
2430 [GCC_SEC_CTRL_CLK_SRC
] = &gcc_sec_ctrl_clk_src
.clkr
,
2433 static const struct qcom_reset_map gcc_sc7180_resets
[] = {
2434 [GCC_QUSB2PHY_PRIM_BCR
] = { 0x26000 },
2435 [GCC_QUSB2PHY_SEC_BCR
] = { 0x26004 },
2436 [GCC_UFS_PHY_BCR
] = { 0x77000 },
2437 [GCC_USB30_PRIM_BCR
] = { 0xf000 },
2438 [GCC_USB3_PHY_PRIM_BCR
] = { 0x50000 },
2439 [GCC_USB3PHY_PHY_PRIM_BCR
] = { 0x50004 },
2440 [GCC_USB3_PHY_SEC_BCR
] = { 0x5000c },
2441 [GCC_USB3_DP_PHY_PRIM_BCR
] = { 0x50008 },
2442 [GCC_USB3PHY_PHY_SEC_BCR
] = { 0x50010 },
2443 [GCC_USB3_DP_PHY_SEC_BCR
] = { 0x50014 },
2444 [GCC_USB_PHY_CFG_AHB2PHY_BCR
] = { 0x6a000 },
2447 static struct clk_rcg_dfs_data gcc_dfs_clocks
[] = {
2448 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src
),
2449 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src
),
2450 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src
),
2451 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src
),
2452 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src
),
2453 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src
),
2454 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src
),
2455 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src
),
2456 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src
),
2457 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src
),
2458 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src
),
2459 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src
),
2462 static const struct regmap_config gcc_sc7180_regmap_config
= {
2466 .max_register
= 0x18208c,
2470 static const struct qcom_cc_desc gcc_sc7180_desc
= {
2471 .config
= &gcc_sc7180_regmap_config
,
2472 .clk_hws
= gcc_sc7180_hws
,
2473 .num_clk_hws
= ARRAY_SIZE(gcc_sc7180_hws
),
2474 .clks
= gcc_sc7180_clocks
,
2475 .num_clks
= ARRAY_SIZE(gcc_sc7180_clocks
),
2476 .resets
= gcc_sc7180_resets
,
2477 .num_resets
= ARRAY_SIZE(gcc_sc7180_resets
),
2478 .gdscs
= gcc_sc7180_gdscs
,
2479 .num_gdscs
= ARRAY_SIZE(gcc_sc7180_gdscs
),
2482 static const struct of_device_id gcc_sc7180_match_table
[] = {
2483 { .compatible
= "qcom,gcc-sc7180" },
2486 MODULE_DEVICE_TABLE(of
, gcc_sc7180_match_table
);
2488 static int gcc_sc7180_probe(struct platform_device
*pdev
)
2490 struct regmap
*regmap
;
2493 regmap
= qcom_cc_map(pdev
, &gcc_sc7180_desc
);
2495 return PTR_ERR(regmap
);
2498 * Disable the GPLL0 active input to MM blocks, NPU
2499 * and GPU via MISC registers.
2501 regmap_update_bits(regmap
, 0x09ffc, 0x3, 0x3);
2502 regmap_update_bits(regmap
, 0x4d110, 0x3, 0x3);
2503 regmap_update_bits(regmap
, 0x71028, 0x3, 0x3);
2506 * Keep the clocks always-ON
2507 * GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_DISP_AHB_CLK
2508 * GCC_GPU_CFG_AHB_CLK
2510 regmap_update_bits(regmap
, 0x48004, BIT(0), BIT(0));
2511 regmap_update_bits(regmap
, 0x0b004, BIT(0), BIT(0));
2512 regmap_update_bits(regmap
, 0x0b00c, BIT(0), BIT(0));
2513 regmap_update_bits(regmap
, 0x71004, BIT(0), BIT(0));
2515 ret
= qcom_cc_register_rcg_dfs(regmap
, gcc_dfs_clocks
,
2516 ARRAY_SIZE(gcc_dfs_clocks
));
2520 return qcom_cc_really_probe(pdev
, &gcc_sc7180_desc
, regmap
);
2523 static struct platform_driver gcc_sc7180_driver
= {
2524 .probe
= gcc_sc7180_probe
,
2526 .name
= "gcc-sc7180",
2527 .of_match_table
= gcc_sc7180_match_table
,
2531 static int __init
gcc_sc7180_init(void)
2533 return platform_driver_register(&gcc_sc7180_driver
);
2535 core_initcall(gcc_sc7180_init
);
2537 static void __exit
gcc_sc7180_exit(void)
2539 platform_driver_unregister(&gcc_sc7180_driver
);
2541 module_exit(gcc_sc7180_exit
);
2543 MODULE_DESCRIPTION("QTI GCC SC7180 Driver");
2544 MODULE_LICENSE("GPL v2");