drivers/clk/qcom/gdsc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/bitops.h>
   7 #include <linux/delay.h>
   8 #include <linux/err.h>
   9 #include <linux/export.h>
  10 #include <linux/jiffies.h>
  11 #include <linux/kernel.h>
  12 #include <linux/ktime.h>
  13 #include <linux/pm_domain.h>
  14 #include <linux/regmap.h>
  15 #include <linux/regulator/consumer.h>
  16 #include <linux/reset-controller.h>
  17 #include <linux/slab.h>
  18 #include "gdsc.h"
  19
  20 #define PWR_ON_MASK             BIT(31)
  21 #define EN_REST_WAIT_MASK       GENMASK_ULL(23, 20)
  22 #define EN_FEW_WAIT_MASK        GENMASK_ULL(19, 16)
  23 #define CLK_DIS_WAIT_MASK       GENMASK_ULL(15, 12)
  24 #define SW_OVERRIDE_MASK        BIT(2)
  25 #define HW_CONTROL_MASK         BIT(1)
  26 #define SW_COLLAPSE_MASK        BIT(0)
  27 #define GMEM_CLAMP_IO_MASK      BIT(0)
  28 #define GMEM_RESET_MASK         BIT(4)
  29
  30 /* CFG_GDSCR */
  31 #define GDSC_POWER_UP_COMPLETE          BIT(16)
  32 #define GDSC_POWER_DOWN_COMPLETE        BIT(15)
  33 #define GDSC_RETAIN_FF_ENABLE           BIT(11)
  34 #define CFG_GDSCR_OFFSET                0x4
  35
  36 /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
  37 #define EN_REST_WAIT_VAL        (0x2 << 20)
  38 #define EN_FEW_WAIT_VAL         (0x8 << 16)
  39 #define CLK_DIS_WAIT_VAL        (0x2 << 12)
  40
  41 #define RETAIN_MEM              BIT(14)
  42 #define RETAIN_PERIPH           BIT(13)
  43
  44 #define TIMEOUT_US              500
  45
  46 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
  47
  48 enum gdsc_status {
  49         GDSC_OFF,
  50         GDSC_ON
  51 };
  52
  53 /* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */
  54 static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status)
  55 {
  56         unsigned int reg;
  57         u32 val;
  58         int ret;
  59
  60         if (sc->flags & POLL_CFG_GDSCR)
  61                 reg = sc->gdscr + CFG_GDSCR_OFFSET;
  62         else if (sc->gds_hw_ctrl)
  63                 reg = sc->gds_hw_ctrl;
  64         else
  65                 reg = sc->gdscr;
  66
  67         ret = regmap_read(sc->regmap, reg, &val);
  68         if (ret)
  69                 return ret;
  70
  71         if (sc->flags & POLL_CFG_GDSCR) {
  72                 switch (status) {
  73                 case GDSC_ON:
  74                         return !!(val & GDSC_POWER_UP_COMPLETE);
  75                 case GDSC_OFF:
  76                         return !!(val & GDSC_POWER_DOWN_COMPLETE);
  77                 }
  78         }
  79
  80         switch (status) {
  81         case GDSC_ON:
  82                 return !!(val & PWR_ON_MASK);
  83         case GDSC_OFF:
  84                 return !(val & PWR_ON_MASK);
  85         }
  86
  87         return -EINVAL;
  88 }
  89
  90 static int gdsc_hwctrl(struct gdsc *sc, bool en)
  91 {
  92         u32 val = en ? HW_CONTROL_MASK : 0;
  93
  94         return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
  95 }
  96
  97 static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
  98 {
  99         ktime_t start;
 100
 101         start = ktime_get();
 102         do {
 103                 if (gdsc_check_status(sc, status))
 104                         return 0;
 105         } while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
 106
 107         if (gdsc_check_status(sc, status))
 108                 return 0;
 109
 110         return -ETIMEDOUT;
 111 }
 112
 113 static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status)
 114 {
 115         int ret;
 116         u32 val = (status == GDSC_ON) ? 0 : SW_COLLAPSE_MASK;
 117
 118         if (status == GDSC_ON && sc->rsupply) {
 119                 ret = regulator_enable(sc->rsupply);
 120                 if (ret < 0)
 121                         return ret;
 122         }
 123
 124         ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
 125         if (ret)
 126                 return ret;
 127
 128         /* If disabling votable gdscs, don't poll on status */
 129         if ((sc->flags & VOTABLE) && status == GDSC_OFF) {
 130                 /*
 131                  * Add a short delay here to ensure that an enable
 132                  * right after it was disabled does not put it in an
 133                  * unknown state
 134                  */
 135                 udelay(TIMEOUT_US);
 136                 return 0;
 137         }
 138
 139         if (sc->gds_hw_ctrl) {
 140                 /*
 141                  * The gds hw controller asserts/de-asserts the status bit soon
 142                  * after it receives a power on/off request from a master.
 143                  * The controller then takes around 8 xo cycles to start its
 144                  * internal state machine and update the status bit. During
 145                  * this time, the status bit does not reflect the true status
 146                  * of the core.
 147                  * Add a delay of 1 us between writing to the SW_COLLAPSE bit
 148                  * and polling the status bit.
 149                  */
 150                 udelay(1);
 151         }
 152
 153         ret = gdsc_poll_status(sc, status);
 154         WARN(ret, "%s status stuck at 'o%s'", sc->pd.name, status ? "ff" : "n");
 155
 156         if (!ret && status == GDSC_OFF && sc->rsupply) {
 157                 ret = regulator_disable(sc->rsupply);
 158                 if (ret < 0)
 159                         return ret;
 160         }
 161
 162         return ret;
 163 }
 164
 165 static inline int gdsc_deassert_reset(struct gdsc *sc)
 166 {
 167         int i;
 168
 169         for (i = 0; i < sc->reset_count; i++)
 170                 sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
 171         return 0;
 172 }
 173
 174 static inline int gdsc_assert_reset(struct gdsc *sc)
 175 {
 176         int i;
 177
 178         for (i = 0; i < sc->reset_count; i++)
 179                 sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
 180         return 0;
 181 }
 182
 183 static inline void gdsc_force_mem_on(struct gdsc *sc)
 184 {
 185         int i;
 186         u32 mask = RETAIN_MEM | RETAIN_PERIPH;
 187
 188         for (i = 0; i < sc->cxc_count; i++)
 189                 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
 190 }
 191
 192 static inline void gdsc_clear_mem_on(struct gdsc *sc)
 193 {
 194         int i;
 195         u32 mask = RETAIN_MEM | RETAIN_PERIPH;
 196
 197         for (i = 0; i < sc->cxc_count; i++)
 198                 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
 199 }
 200
 201 static inline void gdsc_deassert_clamp_io(struct gdsc *sc)
 202 {
 203         regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
 204                            GMEM_CLAMP_IO_MASK, 0);
 205 }
 206
 207 static inline void gdsc_assert_clamp_io(struct gdsc *sc)
 208 {
 209         regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
 210                            GMEM_CLAMP_IO_MASK, 1);
 211 }
 212
 213 static inline void gdsc_assert_reset_aon(struct gdsc *sc)
 214 {
 215         regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
 216                            GMEM_RESET_MASK, 1);
 217         udelay(1);
 218         regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
 219                            GMEM_RESET_MASK, 0);
 220 }
 221
 222 static void gdsc_retain_ff_on(struct gdsc *sc)
 223 {
 224         u32 mask = GDSC_RETAIN_FF_ENABLE;
 225
 226         regmap_update_bits(sc->regmap, sc->gdscr, mask, mask);
 227 }
 228
 229 static int gdsc_enable(struct generic_pm_domain *domain)
 230 {
 231         struct gdsc *sc = domain_to_gdsc(domain);
 232         int ret;
 233
 234         if (sc->pwrsts == PWRSTS_ON)
 235                 return gdsc_deassert_reset(sc);
 236
 237         if (sc->flags & SW_RESET) {
 238                 gdsc_assert_reset(sc);
 239                 udelay(1);
 240                 gdsc_deassert_reset(sc);
 241         }
 242
 243         if (sc->flags & CLAMP_IO) {
 244                 if (sc->flags & AON_RESET)
 245                         gdsc_assert_reset_aon(sc);
 246                 gdsc_deassert_clamp_io(sc);
 247         }
 248
 249         ret = gdsc_toggle_logic(sc, GDSC_ON);
 250         if (ret)
 251                 return ret;
 252
 253         if (sc->pwrsts & PWRSTS_OFF)
 254                 gdsc_force_mem_on(sc);
 255
 256         /*
 257          * If clocks to this power domain were already on, they will take an
 258          * additional 4 clock cycles to re-enable after the power domain is
 259          * enabled. Delay to account for this. A delay is also needed to ensure
 260          * clocks are not enabled within 400ns of enabling power to the
 261          * memories.
 262          */
 263         udelay(1);
 264
 265         /* Turn on HW trigger mode if supported */
 266         if (sc->flags & HW_CTRL) {
 267                 ret = gdsc_hwctrl(sc, true);
 268                 if (ret)
 269                         return ret;
 270                 /*
 271                  * Wait for the GDSC to go through a power down and
 272                  * up cycle.  In case a firmware ends up polling status
 273                  * bits for the gdsc, it might read an 'on' status before
 274                  * the GDSC can finish the power cycle.
 275                  * We wait 1us before returning to ensure the firmware
 276                  * can't immediately poll the status bits.
 277                  */
 278                 udelay(1);
 279         }
 280
 281         if (sc->flags & RETAIN_FF_ENABLE)
 282                 gdsc_retain_ff_on(sc);
 283
 284         return 0;
 285 }
 286
 287 static int gdsc_disable(struct generic_pm_domain *domain)
 288 {
 289         struct gdsc *sc = domain_to_gdsc(domain);
 290         int ret;
 291
 292         if (sc->pwrsts == PWRSTS_ON)
 293                 return gdsc_assert_reset(sc);
 294
 295         /* Turn off HW trigger mode if supported */
 296         if (sc->flags & HW_CTRL) {
 297                 ret = gdsc_hwctrl(sc, false);
 298                 if (ret < 0)
 299                         return ret;
 300                 /*
 301                  * Wait for the GDSC to go through a power down and
 302                  * up cycle.  In case we end up polling status
 303                  * bits for the gdsc before the power cycle is completed
 304                  * it might read an 'on' status wrongly.
 305                  */
 306                 udelay(1);
 307
 308                 ret = gdsc_poll_status(sc, GDSC_ON);
 309                 if (ret)
 310                         return ret;
 311         }
 312
 313         if (sc->pwrsts & PWRSTS_OFF)
 314                 gdsc_clear_mem_on(sc);
 315
 316         ret = gdsc_toggle_logic(sc, GDSC_OFF);
 317         if (ret)
 318                 return ret;
 319
 320         if (sc->flags & CLAMP_IO)
 321                 gdsc_assert_clamp_io(sc);
 322
 323         return 0;
 324 }
 325
 326 static int gdsc_init(struct gdsc *sc)
 327 {
 328         u32 mask, val;
 329         int on, ret;
 330
 331         /*
 332          * Disable HW trigger: collapse/restore occur based on registers writes.
 333          * Disable SW override: Use hardware state-machine for sequencing.
 334          * Configure wait time between states.
 335          */
 336         mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
 337                EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
 338         val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;
 339         ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
 340         if (ret)
 341                 return ret;
 342
 343         /* Force gdsc ON if only ON state is supported */
 344         if (sc->pwrsts == PWRSTS_ON) {
 345                 ret = gdsc_toggle_logic(sc, GDSC_ON);
 346                 if (ret)
 347                         return ret;
 348         }
 349
 350         on = gdsc_check_status(sc, GDSC_ON);
 351         if (on < 0)
 352                 return on;
 353
 354         /*
 355          * Votable GDSCs can be ON due to Vote from other masters.
 356          * If a Votable GDSC is ON, make sure we have a Vote.
 357          */
 358         if ((sc->flags & VOTABLE) && on)
 359                 gdsc_enable(&sc->pd);
 360
 361         /* If ALWAYS_ON GDSCs are not ON, turn them ON */
 362         if (sc->flags & ALWAYS_ON) {
 363                 if (!on)
 364                         gdsc_enable(&sc->pd);
 365                 on = true;
 366                 sc->pd.flags |= GENPD_FLAG_ALWAYS_ON;
 367         }
 368
 369         if (on || (sc->pwrsts & PWRSTS_RET))
 370                 gdsc_force_mem_on(sc);
 371         else
 372                 gdsc_clear_mem_on(sc);
 373
 374         if (!sc->pd.power_off)
 375                 sc->pd.power_off = gdsc_disable;
 376         if (!sc->pd.power_on)
 377                 sc->pd.power_on = gdsc_enable;
 378         pm_genpd_init(&sc->pd, NULL, !on);
 379
 380         return 0;
 381 }
 382
 383 int gdsc_register(struct gdsc_desc *desc,
 384                   struct reset_controller_dev *rcdev, struct regmap *regmap)
 385 {
 386         int i, ret;
 387         struct genpd_onecell_data *data;
 388         struct device *dev = desc->dev;
 389         struct gdsc **scs = desc->scs;
 390         size_t num = desc->num;
 391
 392         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 393         if (!data)
 394                 return -ENOMEM;
 395
 396         data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
 397                                      GFP_KERNEL);
 398         if (!data->domains)
 399                 return -ENOMEM;
 400
 401         for (i = 0; i < num; i++) {
 402                 if (!scs[i] || !scs[i]->supply)
 403                         continue;
 404
 405                 scs[i]->rsupply = devm_regulator_get(dev, scs[i]->supply);
 406                 if (IS_ERR(scs[i]->rsupply))
 407                         return PTR_ERR(scs[i]->rsupply);
 408         }
 409
 410         data->num_domains = num;
 411         for (i = 0; i < num; i++) {
 412                 if (!scs[i])
 413                         continue;
 414                 scs[i]->regmap = regmap;
 415                 scs[i]->rcdev = rcdev;
 416                 ret = gdsc_init(scs[i]);
 417                 if (ret)
 418                         return ret;
 419                 data->domains[i] = &scs[i]->pd;
 420         }
 421
 422         /* Add subdomains */
 423         for (i = 0; i < num; i++) {
 424                 if (!scs[i])
 425                         continue;
 426                 if (scs[i]->parent)
 427                         pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);
 428         }
 429
 430         return of_genpd_add_provider_onecell(dev->of_node, data);
 431 }
 432
 433 void gdsc_unregister(struct gdsc_desc *desc)
 434 {
 435         int i;
 436         struct device *dev = desc->dev;
 437         struct gdsc **scs = desc->scs;
 438         size_t num = desc->num;
 439
 440         /* Remove subdomains */
 441         for (i = 0; i < num; i++) {
 442                 if (!scs[i])
 443                         continue;
 444                 if (scs[i]->parent)
 445                         pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);
 446         }
 447         of_genpd_del_provider(dev->of_node);
 448 }
 449
 450 /*
 451  * On SDM845+ the GPU GX domain is *almost* entirely controlled by the GMU
 452  * running in the CX domain so the CPU doesn't need to know anything about the
 453  * GX domain EXCEPT....
 454  *
 455  * Hardware constraints dictate that the GX be powered down before the CX. If
 456  * the GMU crashes it could leave the GX on. In order to successfully bring back
 457  * the device the CPU needs to disable the GX headswitch. There being no sane
 458  * way to reach in and touch that register from deep inside the GPU driver we
 459  * need to set up the infrastructure to be able to ensure that the GPU can
 460  * ensure that the GX is off during this super special case. We do this by
 461  * defining a GX gdsc with a dummy enable function and a "default" disable
 462  * function.
 463  *
 464  * This allows us to attach with genpd_dev_pm_attach_by_name() in the GPU
 465  * driver. During power up, nothing will happen from the CPU (and the GMU will
 466  * power up normally but during power down this will ensure that the GX domain
 467  * is *really* off - this gives us a semi standard way of doing what we need.
 468  */
 469 int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain)
 470 {
 471         /* Do nothing but give genpd the impression that we were successful */
 472         return 0;
 473 }
 474 EXPORT_SYMBOL_GPL(gdsc_gx_do_nothing_enable);