drivers/clk/renesas/renesas-cpg-mssr.c

   1 /*
   2  * Renesas Clock Pulse Generator / Module Standby and Software Reset
   3  *
   4  * Copyright (C) 2015 Glider bvba
   5  *
   6  * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
   7  *
   8  * Copyright (C) 2013 Ideas On Board SPRL
   9  * Copyright (C) 2015 Renesas Electronics Corp.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; version 2 of the License.
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/clk-provider.h>
  18 #include <linux/clk/renesas.h>
  19 #include <linux/device.h>
  20 #include <linux/init.h>
  21 #include <linux/mod_devicetable.h>
  22 #include <linux/module.h>
  23 #include <linux/of_address.h>
  24 #include <linux/of_device.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_clock.h>
  27 #include <linux/pm_domain.h>
  28 #include <linux/slab.h>
  29
  30 #include <dt-bindings/clock/renesas-cpg-mssr.h>
  31
  32 #include "renesas-cpg-mssr.h"
  33 #include "clk-div6.h"
  34
  35 #ifdef DEBUG
  36 #define WARN_DEBUG(x)   WARN_ON(x)
  37 #else
  38 #define WARN_DEBUG(x)   do { } while (0)
  39 #endif
  40
  41
  42 /*
  43  * Module Standby and Software Reset register offets.
  44  *
  45  * If the registers exist, these are valid for SH-Mobile, R-Mobile,
  46  * R-Car Gen 2, and R-Car Gen 3.
  47  * These are NOT valid for R-Car Gen1 and RZ/A1!
  48  */
  49
  50 /*
  51  * Module Stop Status Register offsets
  52  */
  53
  54 static const u16 mstpsr[] = {
  55         0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
  56         0x9A0, 0x9A4, 0x9A8, 0x9AC,
  57 };
  58
  59 #define MSTPSR(i)       mstpsr[i]
  60
  61
  62 /*
  63  * System Module Stop Control Register offsets
  64  */
  65
  66 static const u16 smstpcr[] = {
  67         0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
  68         0x990, 0x994, 0x998, 0x99C,
  69 };
  70
  71 #define SMSTPCR(i)      smstpcr[i]
  72
  73
  74 /*
  75  * Software Reset Register offsets
  76  */
  77
  78 static const u16 srcr[] = {
  79         0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
  80         0x920, 0x924, 0x928, 0x92C,
  81 };
  82
  83 #define SRCR(i)         srcr[i]
  84
  85
  86 /* Realtime Module Stop Control Register offsets */
  87 #define RMSTPCR(i)      (smstpcr[i] - 0x20)
  88
  89 /* Modem Module Stop Control Register offsets (r8a73a4) */
  90 #define MMSTPCR(i)      (smstpcr[i] + 0x20)
  91
  92 /* Software Reset Clearing Register offsets */
  93 #define SRSTCLR(i)      (0x940 + (i) * 4)
  94
  95
  96 /**
  97  * Clock Pulse Generator / Module Standby and Software Reset Private Data
  98  *
  99  * @dev: CPG/MSSR device
 100  * @base: CPG/MSSR register block base address
 101  * @mstp_lock: protects writes to SMSTPCR
 102  * @clks: Array containing all Core and Module Clocks
 103  * @num_core_clks: Number of Core Clocks in clks[]
 104  * @num_mod_clks: Number of Module Clocks in clks[]
 105  * @last_dt_core_clk: ID of the last Core Clock exported to DT
 106  */
 107 struct cpg_mssr_priv {
 108         struct device *dev;
 109         void __iomem *base;
 110         spinlock_t mstp_lock;
 111
 112         struct clk **clks;
 113         unsigned int num_core_clks;
 114         unsigned int num_mod_clks;
 115         unsigned int last_dt_core_clk;
 116 };
 117
 118
 119 /**
 120  * struct mstp_clock - MSTP gating clock
 121  * @hw: handle between common and hardware-specific interfaces
 122  * @index: MSTP clock number
 123  * @priv: CPG/MSSR private data
 124  */
 125 struct mstp_clock {
 126         struct clk_hw hw;
 127         u32 index;
 128         struct cpg_mssr_priv *priv;
 129 };
 130
 131 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
 132
 133 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
 134 {
 135         struct mstp_clock *clock = to_mstp_clock(hw);
 136         struct cpg_mssr_priv *priv = clock->priv;
 137         unsigned int reg = clock->index / 32;
 138         unsigned int bit = clock->index % 32;
 139         struct device *dev = priv->dev;
 140         u32 bitmask = BIT(bit);
 141         unsigned long flags;
 142         unsigned int i;
 143         u32 value;
 144
 145         dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,
 146                 enable ? "ON" : "OFF");
 147         spin_lock_irqsave(&priv->mstp_lock, flags);
 148
 149         value = readl(priv->base + SMSTPCR(reg));
 150         if (enable)
 151                 value &= ~bitmask;
 152         else
 153                 value |= bitmask;
 154         writel(value, priv->base + SMSTPCR(reg));
 155
 156         spin_unlock_irqrestore(&priv->mstp_lock, flags);
 157
 158         if (!enable)
 159                 return 0;
 160
 161         for (i = 1000; i > 0; --i) {
 162                 if (!(readl(priv->base + MSTPSR(reg)) & bitmask))
 163                         break;
 164                 cpu_relax();
 165         }
 166
 167         if (!i) {
 168                 dev_err(dev, "Failed to enable SMSTP %p[%d]\n",
 169                         priv->base + SMSTPCR(reg), bit);
 170                 return -ETIMEDOUT;
 171         }
 172
 173         return 0;
 174 }
 175
 176 static int cpg_mstp_clock_enable(struct clk_hw *hw)
 177 {
 178         return cpg_mstp_clock_endisable(hw, true);
 179 }
 180
 181 static void cpg_mstp_clock_disable(struct clk_hw *hw)
 182 {
 183         cpg_mstp_clock_endisable(hw, false);
 184 }
 185
 186 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
 187 {
 188         struct mstp_clock *clock = to_mstp_clock(hw);
 189         struct cpg_mssr_priv *priv = clock->priv;
 190         u32 value;
 191
 192         value = readl(priv->base + MSTPSR(clock->index / 32));
 193
 194         return !(value & BIT(clock->index % 32));
 195 }
 196
 197 static const struct clk_ops cpg_mstp_clock_ops = {
 198         .enable = cpg_mstp_clock_enable,
 199         .disable = cpg_mstp_clock_disable,
 200         .is_enabled = cpg_mstp_clock_is_enabled,
 201 };
 202
 203 static
 204 struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
 205                                          void *data)
 206 {
 207         unsigned int clkidx = clkspec->args[1];
 208         struct cpg_mssr_priv *priv = data;
 209         struct device *dev = priv->dev;
 210         unsigned int idx;
 211         const char *type;
 212         struct clk *clk;
 213
 214         switch (clkspec->args[0]) {
 215         case CPG_CORE:
 216                 type = "core";
 217                 if (clkidx > priv->last_dt_core_clk) {
 218                         dev_err(dev, "Invalid %s clock index %u\n", type,
 219                                clkidx);
 220                         return ERR_PTR(-EINVAL);
 221                 }
 222                 clk = priv->clks[clkidx];
 223                 break;
 224
 225         case CPG_MOD:
 226                 type = "module";
 227                 idx = MOD_CLK_PACK(clkidx);
 228                 if (clkidx % 100 > 31 || idx >= priv->num_mod_clks) {
 229                         dev_err(dev, "Invalid %s clock index %u\n", type,
 230                                 clkidx);
 231                         return ERR_PTR(-EINVAL);
 232                 }
 233                 clk = priv->clks[priv->num_core_clks + idx];
 234                 break;
 235
 236         default:
 237                 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
 238                 return ERR_PTR(-EINVAL);
 239         }
 240
 241         if (IS_ERR(clk))
 242                 dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
 243                        PTR_ERR(clk));
 244         else
 245                 dev_dbg(dev, "clock (%u, %u) is %pC at %pCr Hz\n",
 246                         clkspec->args[0], clkspec->args[1], clk, clk);
 247         return clk;
 248 }
 249
 250 static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
 251                                               const struct cpg_mssr_info *info,
 252                                               struct cpg_mssr_priv *priv)
 253 {
 254         struct clk *clk = NULL, *parent;
 255         struct device *dev = priv->dev;
 256         unsigned int id = core->id, div = core->div;
 257         const char *parent_name;
 258
 259         WARN_DEBUG(id >= priv->num_core_clks);
 260         WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
 261
 262         switch (core->type) {
 263         case CLK_TYPE_IN:
 264                 clk = of_clk_get_by_name(priv->dev->of_node, core->name);
 265                 break;
 266
 267         case CLK_TYPE_FF:
 268         case CLK_TYPE_DIV6P1:
 269         case CLK_TYPE_DIV6_RO:
 270                 WARN_DEBUG(core->parent >= priv->num_core_clks);
 271                 parent = priv->clks[core->parent];
 272                 if (IS_ERR(parent)) {
 273                         clk = parent;
 274                         goto fail;
 275                 }
 276
 277                 parent_name = __clk_get_name(parent);
 278
 279                 if (core->type == CLK_TYPE_DIV6_RO)
 280                         /* Multiply with the DIV6 register value */
 281                         div *= (readl(priv->base + core->offset) & 0x3f) + 1;
 282
 283                 if (core->type == CLK_TYPE_DIV6P1) {
 284                         clk = cpg_div6_register(core->name, 1, &parent_name,
 285                                                 priv->base + core->offset);
 286                 } else {
 287                         clk = clk_register_fixed_factor(NULL, core->name,
 288                                                         parent_name, 0,
 289                                                         core->mult, div);
 290                 }
 291                 break;
 292
 293         default:
 294                 if (info->cpg_clk_register)
 295                         clk = info->cpg_clk_register(dev, core, info,
 296                                                      priv->clks, priv->base);
 297                 else
 298                         dev_err(dev, "%s has unsupported core clock type %u\n",
 299                                 core->name, core->type);
 300                 break;
 301         }
 302
 303         if (IS_ERR_OR_NULL(clk))
 304                 goto fail;
 305
 306         dev_dbg(dev, "Core clock %pC at %pCr Hz\n", clk, clk);
 307         priv->clks[id] = clk;
 308         return;
 309
 310 fail:
 311         dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",
 312                 core->name, PTR_ERR(clk));
 313 }
 314
 315 static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
 316                                              const struct cpg_mssr_info *info,
 317                                              struct cpg_mssr_priv *priv)
 318 {
 319         struct mstp_clock *clock = NULL;
 320         struct device *dev = priv->dev;
 321         unsigned int id = mod->id;
 322         struct clk_init_data init;
 323         struct clk *parent, *clk;
 324         const char *parent_name;
 325         unsigned int i;
 326
 327         WARN_DEBUG(id < priv->num_core_clks);
 328         WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
 329         WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
 330         WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
 331
 332         parent = priv->clks[mod->parent];
 333         if (IS_ERR(parent)) {
 334                 clk = parent;
 335                 goto fail;
 336         }
 337
 338         clock = kzalloc(sizeof(*clock), GFP_KERNEL);
 339         if (!clock) {
 340                 clk = ERR_PTR(-ENOMEM);
 341                 goto fail;
 342         }
 343
 344         init.name = mod->name;
 345         init.ops = &cpg_mstp_clock_ops;
 346         init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
 347         for (i = 0; i < info->num_crit_mod_clks; i++)
 348                 if (id == info->crit_mod_clks[i]) {
 349 #ifdef CLK_ENABLE_HAND_OFF
 350                         dev_dbg(dev, "MSTP %s setting CLK_ENABLE_HAND_OFF\n",
 351                                 mod->name);
 352                         init.flags |= CLK_ENABLE_HAND_OFF;
 353                         break;
 354 #else
 355                         dev_dbg(dev, "Ignoring MSTP %s to prevent disabling\n",
 356                                 mod->name);
 357                         kfree(clock);
 358                         return;
 359 #endif
 360                 }
 361
 362         parent_name = __clk_get_name(parent);
 363         init.parent_names = &parent_name;
 364         init.num_parents = 1;
 365
 366         clock->index = id - priv->num_core_clks;
 367         clock->priv = priv;
 368         clock->hw.init = &init;
 369
 370         clk = clk_register(NULL, &clock->hw);
 371         if (IS_ERR(clk))
 372                 goto fail;
 373
 374         dev_dbg(dev, "Module clock %pC at %pCr Hz\n", clk, clk);
 375         priv->clks[id] = clk;
 376         return;
 377
 378 fail:
 379         dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
 380                 mod->name, PTR_ERR(clk));
 381         kfree(clock);
 382 }
 383
 384 struct cpg_mssr_clk_domain {
 385         struct generic_pm_domain genpd;
 386         struct device_node *np;
 387         unsigned int num_core_pm_clks;
 388         unsigned int core_pm_clks[0];
 389 };
 390
 391 static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain;
 392
 393 static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec,
 394                                struct cpg_mssr_clk_domain *pd)
 395 {
 396         unsigned int i;
 397
 398         if (clkspec->np != pd->np || clkspec->args_count != 2)
 399                 return false;
 400
 401         switch (clkspec->args[0]) {
 402         case CPG_CORE:
 403                 for (i = 0; i < pd->num_core_pm_clks; i++)
 404                         if (clkspec->args[1] == pd->core_pm_clks[i])
 405                                 return true;
 406                 return false;
 407
 408         case CPG_MOD:
 409                 return true;
 410
 411         default:
 412                 return false;
 413         }
 414 }
 415
 416 int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev)
 417 {
 418         struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain;
 419         struct device_node *np = dev->of_node;
 420         struct of_phandle_args clkspec;
 421         struct clk *clk;
 422         int i = 0;
 423         int error;
 424
 425         if (!pd) {
 426                 dev_dbg(dev, "CPG/MSSR clock domain not yet available\n");
 427                 return -EPROBE_DEFER;
 428         }
 429
 430         while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
 431                                            &clkspec)) {
 432                 if (cpg_mssr_is_pm_clk(&clkspec, pd))
 433                         goto found;
 434
 435                 of_node_put(clkspec.np);
 436                 i++;
 437         }
 438
 439         return 0;
 440
 441 found:
 442         clk = of_clk_get_from_provider(&clkspec);
 443         of_node_put(clkspec.np);
 444
 445         if (IS_ERR(clk))
 446                 return PTR_ERR(clk);
 447
 448         error = pm_clk_create(dev);
 449         if (error) {
 450                 dev_err(dev, "pm_clk_create failed %d\n", error);
 451                 goto fail_put;
 452         }
 453
 454         error = pm_clk_add_clk(dev, clk);
 455         if (error) {
 456                 dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
 457                 goto fail_destroy;
 458         }
 459
 460         return 0;
 461
 462 fail_destroy:
 463         pm_clk_destroy(dev);
 464 fail_put:
 465         clk_put(clk);
 466         return error;
 467 }
 468
 469 void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev)
 470 {
 471         if (!list_empty(&dev->power.subsys_data->clock_list))
 472                 pm_clk_destroy(dev);
 473 }
 474
 475 static int __init cpg_mssr_add_clk_domain(struct device *dev,
 476                                           const unsigned int *core_pm_clks,
 477                                           unsigned int num_core_pm_clks)
 478 {
 479         struct device_node *np = dev->of_node;
 480         struct generic_pm_domain *genpd;
 481         struct cpg_mssr_clk_domain *pd;
 482         size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]);
 483
 484         pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL);
 485         if (!pd)
 486                 return -ENOMEM;
 487
 488         pd->np = np;
 489         pd->num_core_pm_clks = num_core_pm_clks;
 490         memcpy(pd->core_pm_clks, core_pm_clks, pm_size);
 491
 492         genpd = &pd->genpd;
 493         genpd->name = np->name;
 494         genpd->flags = GENPD_FLAG_PM_CLK;
 495         genpd->attach_dev = cpg_mssr_attach_dev;
 496         genpd->detach_dev = cpg_mssr_detach_dev;
 497         pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
 498         cpg_mssr_clk_domain = pd;
 499
 500         of_genpd_add_provider_simple(np, genpd);
 501         return 0;
 502 }
 503
 504 static const struct of_device_id cpg_mssr_match[] = {
 505 #ifdef CONFIG_ARCH_R8A7743
 506         {
 507                 .compatible = "renesas,r8a7743-cpg-mssr",
 508                 .data = &r8a7743_cpg_mssr_info,
 509         },
 510 #endif
 511 #ifdef CONFIG_ARCH_R8A7745
 512         {
 513                 .compatible = "renesas,r8a7745-cpg-mssr",
 514                 .data = &r8a7745_cpg_mssr_info,
 515         },
 516 #endif
 517 #ifdef CONFIG_ARCH_R8A7795
 518         {
 519                 .compatible = "renesas,r8a7795-cpg-mssr",
 520                 .data = &r8a7795_cpg_mssr_info,
 521         },
 522 #endif
 523 #ifdef CONFIG_ARCH_R8A7796
 524         {
 525                 .compatible = "renesas,r8a7796-cpg-mssr",
 526                 .data = &r8a7796_cpg_mssr_info,
 527         },
 528 #endif
 529         { /* sentinel */ }
 530 };
 531
 532 static void cpg_mssr_del_clk_provider(void *data)
 533 {
 534         of_clk_del_provider(data);
 535 }
 536
 537 static int __init cpg_mssr_probe(struct platform_device *pdev)
 538 {
 539         struct device *dev = &pdev->dev;
 540         struct device_node *np = dev->of_node;
 541         const struct cpg_mssr_info *info;
 542         struct cpg_mssr_priv *priv;
 543         unsigned int nclks, i;
 544         struct resource *res;
 545         struct clk **clks;
 546         int error;
 547
 548         info = of_match_node(cpg_mssr_match, np)->data;
 549         if (info->init) {
 550                 error = info->init(dev);
 551                 if (error)
 552                         return error;
 553         }
 554
 555         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 556         if (!priv)
 557                 return -ENOMEM;
 558
 559         priv->dev = dev;
 560         spin_lock_init(&priv->mstp_lock);
 561
 562         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 563         priv->base = devm_ioremap_resource(dev, res);
 564         if (IS_ERR(priv->base))
 565                 return PTR_ERR(priv->base);
 566
 567         nclks = info->num_total_core_clks + info->num_hw_mod_clks;
 568         clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
 569         if (!clks)
 570                 return -ENOMEM;
 571
 572         priv->clks = clks;
 573         priv->num_core_clks = info->num_total_core_clks;
 574         priv->num_mod_clks = info->num_hw_mod_clks;
 575         priv->last_dt_core_clk = info->last_dt_core_clk;
 576
 577         for (i = 0; i < nclks; i++)
 578                 clks[i] = ERR_PTR(-ENOENT);
 579
 580         for (i = 0; i < info->num_core_clks; i++)
 581                 cpg_mssr_register_core_clk(&info->core_clks[i], info, priv);
 582
 583         for (i = 0; i < info->num_mod_clks; i++)
 584                 cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv);
 585
 586         error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
 587         if (error)
 588                 return error;
 589
 590         error = devm_add_action_or_reset(dev,
 591                                          cpg_mssr_del_clk_provider,
 592                                          np);
 593         if (error)
 594                 return error;
 595
 596         error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks,
 597                                         info->num_core_pm_clks);
 598         if (error)
 599                 return error;
 600
 601         return 0;
 602 }
 603
 604 static struct platform_driver cpg_mssr_driver = {
 605         .driver         = {
 606                 .name   = "renesas-cpg-mssr",
 607                 .of_match_table = cpg_mssr_match,
 608         },
 609 };
 610
 611 static int __init cpg_mssr_init(void)
 612 {
 613         return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe);
 614 }
 615
 616 subsys_initcall(cpg_mssr_init);
 617
 618 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");
 619 MODULE_LICENSE("GPL v2");