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[mirror_ubuntu-zesty-kernel.git] / drivers / clk / rockchip / clk.h
1 /*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
6 * Author: Xing Zheng <zhengxing@rock-chips.com>
7 *
8 * based on
9 *
10 * samsung/clk.h
11 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
12 * Copyright (c) 2013 Linaro Ltd.
13 * Author: Thomas Abraham <thomas.ab@samsung.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 */
25
26 #ifndef CLK_ROCKCHIP_CLK_H
27 #define CLK_ROCKCHIP_CLK_H
28
29 #include <linux/io.h>
30
31 struct clk;
32
33 #define HIWORD_UPDATE(val, mask, shift) \
34 ((val) << (shift) | (mask) << ((shift) + 16))
35
36 /* register positions shared by RK2928, RK3066 and RK3188 */
37 #define RK2928_PLL_CON(x) ((x) * 0x4)
38 #define RK2928_MODE_CON 0x40
39 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
40 #define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0)
41 #define RK2928_GLB_SRST_FST 0x100
42 #define RK2928_GLB_SRST_SND 0x104
43 #define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
44 #define RK2928_MISC_CON 0x134
45
46 #define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
47 #define RK3288_MODE_CON 0x50
48 #define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
49 #define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160)
50 #define RK3288_GLB_SRST_FST 0x1b0
51 #define RK3288_GLB_SRST_SND 0x1b4
52 #define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8)
53 #define RK3288_MISC_CON 0x1e8
54 #define RK3288_SDMMC_CON0 0x200
55 #define RK3288_SDMMC_CON1 0x204
56 #define RK3288_SDIO0_CON0 0x208
57 #define RK3288_SDIO0_CON1 0x20c
58 #define RK3288_SDIO1_CON0 0x210
59 #define RK3288_SDIO1_CON1 0x214
60 #define RK3288_EMMC_CON0 0x218
61 #define RK3288_EMMC_CON1 0x21c
62
63 #define RK3368_PLL_CON(x) RK2928_PLL_CON(x)
64 #define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
65 #define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
66 #define RK3368_GLB_SRST_FST 0x280
67 #define RK3368_GLB_SRST_SND 0x284
68 #define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
69 #define RK3368_MISC_CON 0x380
70 #define RK3368_SDMMC_CON0 0x400
71 #define RK3368_SDMMC_CON1 0x404
72 #define RK3368_SDIO0_CON0 0x408
73 #define RK3368_SDIO0_CON1 0x40c
74 #define RK3368_SDIO1_CON0 0x410
75 #define RK3368_SDIO1_CON1 0x414
76 #define RK3368_EMMC_CON0 0x418
77 #define RK3368_EMMC_CON1 0x41c
78
79 enum rockchip_pll_type {
80 pll_rk3036,
81 pll_rk3066,
82 };
83
84 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
85 _postdiv2, _dsmpd, _frac) \
86 { \
87 .rate = _rate##U, \
88 .fbdiv = _fbdiv, \
89 .postdiv1 = _postdiv1, \
90 .refdiv = _refdiv, \
91 .postdiv2 = _postdiv2, \
92 .dsmpd = _dsmpd, \
93 .frac = _frac, \
94 }
95
96 #define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
97 { \
98 .rate = _rate##U, \
99 .nr = _nr, \
100 .nf = _nf, \
101 .no = _no, \
102 .nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \
103 }
104
105 #define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \
106 { \
107 .rate = _rate##U, \
108 .nr = _nr, \
109 .nf = _nf, \
110 .no = _no, \
111 .nb = _nb, \
112 }
113
114 struct rockchip_pll_rate_table {
115 unsigned long rate;
116 unsigned int nr;
117 unsigned int nf;
118 unsigned int no;
119 unsigned int nb;
120 /* for RK3036 */
121 unsigned int fbdiv;
122 unsigned int postdiv1;
123 unsigned int refdiv;
124 unsigned int postdiv2;
125 unsigned int dsmpd;
126 unsigned int frac;
127 };
128
129 /**
130 * struct rockchip_pll_clock: information about pll clock
131 * @id: platform specific id of the clock.
132 * @name: name of this pll clock.
133 * @parent_name: name of the parent clock.
134 * @flags: optional flags for basic clock.
135 * @con_offset: offset of the register for configuring the PLL.
136 * @mode_offset: offset of the register for configuring the PLL-mode.
137 * @mode_shift: offset inside the mode-register for the mode of this pll.
138 * @lock_shift: offset inside the lock register for the lock status.
139 * @type: Type of PLL to be registered.
140 * @pll_flags: hardware-specific flags
141 * @rate_table: Table of usable pll rates
142 *
143 * Flags:
144 * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
145 * rate_table parameters and ajust them if necessary.
146 */
147 struct rockchip_pll_clock {
148 unsigned int id;
149 const char *name;
150 const char *const *parent_names;
151 u8 num_parents;
152 unsigned long flags;
153 int con_offset;
154 int mode_offset;
155 int mode_shift;
156 int lock_shift;
157 enum rockchip_pll_type type;
158 u8 pll_flags;
159 struct rockchip_pll_rate_table *rate_table;
160 };
161
162 #define ROCKCHIP_PLL_SYNC_RATE BIT(0)
163
164 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
165 _lshift, _pflags, _rtable) \
166 { \
167 .id = _id, \
168 .type = _type, \
169 .name = _name, \
170 .parent_names = _pnames, \
171 .num_parents = ARRAY_SIZE(_pnames), \
172 .flags = CLK_GET_RATE_NOCACHE | _flags, \
173 .con_offset = _con, \
174 .mode_offset = _mode, \
175 .mode_shift = _mshift, \
176 .lock_shift = _lshift, \
177 .pll_flags = _pflags, \
178 .rate_table = _rtable, \
179 }
180
181 struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
182 const char *name, const char *const *parent_names,
183 u8 num_parents, void __iomem *base, int con_offset,
184 int grf_lock_offset, int lock_shift, int reg_mode,
185 int mode_shift, struct rockchip_pll_rate_table *rate_table,
186 u8 clk_pll_flags, spinlock_t *lock);
187
188 struct rockchip_cpuclk_clksel {
189 int reg;
190 u32 val;
191 };
192
193 #define ROCKCHIP_CPUCLK_NUM_DIVIDERS 2
194 struct rockchip_cpuclk_rate_table {
195 unsigned long prate;
196 struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
197 };
198
199 /**
200 * struct rockchip_cpuclk_reg_data: describes register offsets and masks of the cpuclock
201 * @core_reg: register offset of the core settings register
202 * @div_core_shift: core divider offset used to divide the pll value
203 * @div_core_mask: core divider mask
204 * @mux_core_shift: offset of the core multiplexer
205 */
206 struct rockchip_cpuclk_reg_data {
207 int core_reg;
208 u8 div_core_shift;
209 u32 div_core_mask;
210 int mux_core_reg;
211 u8 mux_core_shift;
212 };
213
214 struct clk *rockchip_clk_register_cpuclk(const char *name,
215 const char *const *parent_names, u8 num_parents,
216 const struct rockchip_cpuclk_reg_data *reg_data,
217 const struct rockchip_cpuclk_rate_table *rates,
218 int nrates, void __iomem *reg_base, spinlock_t *lock);
219
220 struct clk *rockchip_clk_register_mmc(const char *name,
221 const char *const *parent_names, u8 num_parents,
222 void __iomem *reg, int shift);
223
224 #define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0)
225
226 struct clk *rockchip_clk_register_inverter(const char *name,
227 const char *const *parent_names, u8 num_parents,
228 void __iomem *reg, int shift, int flags,
229 spinlock_t *lock);
230
231 #define PNAME(x) static const char *const x[] __initconst
232
233 enum rockchip_clk_branch_type {
234 branch_composite,
235 branch_mux,
236 branch_divider,
237 branch_fraction_divider,
238 branch_gate,
239 branch_mmc,
240 branch_inverter,
241 };
242
243 struct rockchip_clk_branch {
244 unsigned int id;
245 enum rockchip_clk_branch_type branch_type;
246 const char *name;
247 const char *const *parent_names;
248 u8 num_parents;
249 unsigned long flags;
250 int muxdiv_offset;
251 u8 mux_shift;
252 u8 mux_width;
253 u8 mux_flags;
254 u8 div_shift;
255 u8 div_width;
256 u8 div_flags;
257 struct clk_div_table *div_table;
258 int gate_offset;
259 u8 gate_shift;
260 u8 gate_flags;
261 };
262
263 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
264 df, go, gs, gf) \
265 { \
266 .id = _id, \
267 .branch_type = branch_composite, \
268 .name = cname, \
269 .parent_names = pnames, \
270 .num_parents = ARRAY_SIZE(pnames), \
271 .flags = f, \
272 .muxdiv_offset = mo, \
273 .mux_shift = ms, \
274 .mux_width = mw, \
275 .mux_flags = mf, \
276 .div_shift = ds, \
277 .div_width = dw, \
278 .div_flags = df, \
279 .gate_offset = go, \
280 .gate_shift = gs, \
281 .gate_flags = gf, \
282 }
283
284 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \
285 go, gs, gf) \
286 { \
287 .id = _id, \
288 .branch_type = branch_composite, \
289 .name = cname, \
290 .parent_names = (const char *[]){ pname }, \
291 .num_parents = 1, \
292 .flags = f, \
293 .muxdiv_offset = mo, \
294 .div_shift = ds, \
295 .div_width = dw, \
296 .div_flags = df, \
297 .gate_offset = go, \
298 .gate_shift = gs, \
299 .gate_flags = gf, \
300 }
301
302 #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
303 df, dt, go, gs, gf) \
304 { \
305 .id = _id, \
306 .branch_type = branch_composite, \
307 .name = cname, \
308 .parent_names = (const char *[]){ pname }, \
309 .num_parents = 1, \
310 .flags = f, \
311 .muxdiv_offset = mo, \
312 .div_shift = ds, \
313 .div_width = dw, \
314 .div_flags = df, \
315 .div_table = dt, \
316 .gate_offset = go, \
317 .gate_shift = gs, \
318 .gate_flags = gf, \
319 }
320
321 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \
322 go, gs, gf) \
323 { \
324 .id = _id, \
325 .branch_type = branch_composite, \
326 .name = cname, \
327 .parent_names = pnames, \
328 .num_parents = ARRAY_SIZE(pnames), \
329 .flags = f, \
330 .muxdiv_offset = mo, \
331 .mux_shift = ms, \
332 .mux_width = mw, \
333 .mux_flags = mf, \
334 .gate_offset = go, \
335 .gate_shift = gs, \
336 .gate_flags = gf, \
337 }
338
339 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
340 ds, dw, df) \
341 { \
342 .id = _id, \
343 .branch_type = branch_composite, \
344 .name = cname, \
345 .parent_names = pnames, \
346 .num_parents = ARRAY_SIZE(pnames), \
347 .flags = f, \
348 .muxdiv_offset = mo, \
349 .mux_shift = ms, \
350 .mux_width = mw, \
351 .mux_flags = mf, \
352 .div_shift = ds, \
353 .div_width = dw, \
354 .div_flags = df, \
355 .gate_offset = -1, \
356 }
357
358 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \
359 mw, mf, ds, dw, df, dt) \
360 { \
361 .id = _id, \
362 .branch_type = branch_composite, \
363 .name = cname, \
364 .parent_names = pnames, \
365 .num_parents = ARRAY_SIZE(pnames), \
366 .flags = f, \
367 .muxdiv_offset = mo, \
368 .mux_shift = ms, \
369 .mux_width = mw, \
370 .mux_flags = mf, \
371 .div_shift = ds, \
372 .div_width = dw, \
373 .div_flags = df, \
374 .div_table = dt, \
375 .gate_offset = -1, \
376 }
377
378 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
379 { \
380 .id = _id, \
381 .branch_type = branch_fraction_divider, \
382 .name = cname, \
383 .parent_names = (const char *[]){ pname }, \
384 .num_parents = 1, \
385 .flags = f, \
386 .muxdiv_offset = mo, \
387 .div_shift = 16, \
388 .div_width = 16, \
389 .div_flags = df, \
390 .gate_offset = go, \
391 .gate_shift = gs, \
392 .gate_flags = gf, \
393 }
394
395 #define MUX(_id, cname, pnames, f, o, s, w, mf) \
396 { \
397 .id = _id, \
398 .branch_type = branch_mux, \
399 .name = cname, \
400 .parent_names = pnames, \
401 .num_parents = ARRAY_SIZE(pnames), \
402 .flags = f, \
403 .muxdiv_offset = o, \
404 .mux_shift = s, \
405 .mux_width = w, \
406 .mux_flags = mf, \
407 .gate_offset = -1, \
408 }
409
410 #define DIV(_id, cname, pname, f, o, s, w, df) \
411 { \
412 .id = _id, \
413 .branch_type = branch_divider, \
414 .name = cname, \
415 .parent_names = (const char *[]){ pname }, \
416 .num_parents = 1, \
417 .flags = f, \
418 .muxdiv_offset = o, \
419 .div_shift = s, \
420 .div_width = w, \
421 .div_flags = df, \
422 .gate_offset = -1, \
423 }
424
425 #define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \
426 { \
427 .id = _id, \
428 .branch_type = branch_divider, \
429 .name = cname, \
430 .parent_names = (const char *[]){ pname }, \
431 .num_parents = 1, \
432 .flags = f, \
433 .muxdiv_offset = o, \
434 .div_shift = s, \
435 .div_width = w, \
436 .div_flags = df, \
437 .div_table = dt, \
438 }
439
440 #define GATE(_id, cname, pname, f, o, b, gf) \
441 { \
442 .id = _id, \
443 .branch_type = branch_gate, \
444 .name = cname, \
445 .parent_names = (const char *[]){ pname }, \
446 .num_parents = 1, \
447 .flags = f, \
448 .gate_offset = o, \
449 .gate_shift = b, \
450 .gate_flags = gf, \
451 }
452
453 #define MMC(_id, cname, pname, offset, shift) \
454 { \
455 .id = _id, \
456 .branch_type = branch_mmc, \
457 .name = cname, \
458 .parent_names = (const char *[]){ pname }, \
459 .num_parents = 1, \
460 .muxdiv_offset = offset, \
461 .div_shift = shift, \
462 }
463
464 #define INVERTER(_id, cname, pname, io, is, if) \
465 { \
466 .id = _id, \
467 .branch_type = branch_inverter, \
468 .name = cname, \
469 .parent_names = (const char *[]){ pname }, \
470 .num_parents = 1, \
471 .muxdiv_offset = io, \
472 .div_shift = is, \
473 .div_flags = if, \
474 }
475
476 void rockchip_clk_init(struct device_node *np, void __iomem *base,
477 unsigned long nr_clks);
478 struct regmap *rockchip_clk_get_grf(void);
479 void rockchip_clk_add_lookup(struct clk *clk, unsigned int id);
480 void rockchip_clk_register_branches(struct rockchip_clk_branch *clk_list,
481 unsigned int nr_clk);
482 void rockchip_clk_register_plls(struct rockchip_pll_clock *pll_list,
483 unsigned int nr_pll, int grf_lock_offset);
484 void rockchip_clk_register_armclk(unsigned int lookup_id, const char *name,
485 const char *const *parent_names, u8 num_parents,
486 const struct rockchip_cpuclk_reg_data *reg_data,
487 const struct rockchip_cpuclk_rate_table *rates,
488 int nrates);
489 void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
490 void rockchip_register_restart_notifier(unsigned int reg);
491
492 #define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
493
494 #ifdef CONFIG_RESET_CONTROLLER
495 void rockchip_register_softrst(struct device_node *np,
496 unsigned int num_regs,
497 void __iomem *base, u8 flags);
498 #else
499 static inline void rockchip_register_softrst(struct device_node *np,
500 unsigned int num_regs,
501 void __iomem *base, u8 flags)
502 {
503 }
504 #endif
505
506 #endif
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