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[mirror_ubuntu-artful-kernel.git] / drivers / clk / samsung / clk-exynos4.c
1 /*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 * Author: Thomas Abraham <thomas.ab@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Common Clock Framework support for all Exynos4 SoCs.
11 */
12
13 #include <dt-bindings/clock/exynos4.h>
14 #include <linux/clk.h>
15 #include <linux/clkdev.h>
16 #include <linux/clk-provider.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/syscore_ops.h>
20
21 #include "clk.h"
22
23 /* Exynos4 clock controller register offsets */
24 #define SRC_LEFTBUS 0x4200
25 #define DIV_LEFTBUS 0x4500
26 #define GATE_IP_LEFTBUS 0x4800
27 #define E4X12_GATE_IP_IMAGE 0x4930
28 #define CLKOUT_CMU_LEFTBUS 0x4a00
29 #define SRC_RIGHTBUS 0x8200
30 #define DIV_RIGHTBUS 0x8500
31 #define GATE_IP_RIGHTBUS 0x8800
32 #define E4X12_GATE_IP_PERIR 0x8960
33 #define CLKOUT_CMU_RIGHTBUS 0x8a00
34 #define EPLL_LOCK 0xc010
35 #define VPLL_LOCK 0xc020
36 #define EPLL_CON0 0xc110
37 #define EPLL_CON1 0xc114
38 #define EPLL_CON2 0xc118
39 #define VPLL_CON0 0xc120
40 #define VPLL_CON1 0xc124
41 #define VPLL_CON2 0xc128
42 #define SRC_TOP0 0xc210
43 #define SRC_TOP1 0xc214
44 #define SRC_CAM 0xc220
45 #define SRC_TV 0xc224
46 #define SRC_MFC 0xc228
47 #define SRC_G3D 0xc22c
48 #define E4210_SRC_IMAGE 0xc230
49 #define SRC_LCD0 0xc234
50 #define E4210_SRC_LCD1 0xc238
51 #define E4X12_SRC_ISP 0xc238
52 #define SRC_MAUDIO 0xc23c
53 #define SRC_FSYS 0xc240
54 #define SRC_PERIL0 0xc250
55 #define SRC_PERIL1 0xc254
56 #define E4X12_SRC_CAM1 0xc258
57 #define SRC_MASK_TOP 0xc310
58 #define SRC_MASK_CAM 0xc320
59 #define SRC_MASK_TV 0xc324
60 #define SRC_MASK_LCD0 0xc334
61 #define E4210_SRC_MASK_LCD1 0xc338
62 #define E4X12_SRC_MASK_ISP 0xc338
63 #define SRC_MASK_MAUDIO 0xc33c
64 #define SRC_MASK_FSYS 0xc340
65 #define SRC_MASK_PERIL0 0xc350
66 #define SRC_MASK_PERIL1 0xc354
67 #define DIV_TOP 0xc510
68 #define DIV_CAM 0xc520
69 #define DIV_TV 0xc524
70 #define DIV_MFC 0xc528
71 #define DIV_G3D 0xc52c
72 #define DIV_IMAGE 0xc530
73 #define DIV_LCD0 0xc534
74 #define E4210_DIV_LCD1 0xc538
75 #define E4X12_DIV_ISP 0xc538
76 #define DIV_MAUDIO 0xc53c
77 #define DIV_FSYS0 0xc540
78 #define DIV_FSYS1 0xc544
79 #define DIV_FSYS2 0xc548
80 #define DIV_FSYS3 0xc54c
81 #define DIV_PERIL0 0xc550
82 #define DIV_PERIL1 0xc554
83 #define DIV_PERIL2 0xc558
84 #define DIV_PERIL3 0xc55c
85 #define DIV_PERIL4 0xc560
86 #define DIV_PERIL5 0xc564
87 #define E4X12_DIV_CAM1 0xc568
88 #define GATE_SCLK_CAM 0xc820
89 #define GATE_IP_CAM 0xc920
90 #define GATE_IP_TV 0xc924
91 #define GATE_IP_MFC 0xc928
92 #define GATE_IP_G3D 0xc92c
93 #define E4210_GATE_IP_IMAGE 0xc930
94 #define GATE_IP_LCD0 0xc934
95 #define E4210_GATE_IP_LCD1 0xc938
96 #define E4X12_GATE_IP_ISP 0xc938
97 #define E4X12_GATE_IP_MAUDIO 0xc93c
98 #define GATE_IP_FSYS 0xc940
99 #define GATE_IP_GPS 0xc94c
100 #define GATE_IP_PERIL 0xc950
101 #define E4210_GATE_IP_PERIR 0xc960
102 #define GATE_BLOCK 0xc970
103 #define CLKOUT_CMU_TOP 0xca00
104 #define E4X12_MPLL_LOCK 0x10008
105 #define E4X12_MPLL_CON0 0x10108
106 #define SRC_DMC 0x10200
107 #define SRC_MASK_DMC 0x10300
108 #define DIV_DMC0 0x10500
109 #define DIV_DMC1 0x10504
110 #define GATE_IP_DMC 0x10900
111 #define CLKOUT_CMU_DMC 0x10a00
112 #define APLL_LOCK 0x14000
113 #define E4210_MPLL_LOCK 0x14008
114 #define APLL_CON0 0x14100
115 #define E4210_MPLL_CON0 0x14108
116 #define SRC_CPU 0x14200
117 #define DIV_CPU0 0x14500
118 #define DIV_CPU1 0x14504
119 #define GATE_SCLK_CPU 0x14800
120 #define GATE_IP_CPU 0x14900
121 #define CLKOUT_CMU_CPU 0x14a00
122 #define PWR_CTRL1 0x15020
123 #define E4X12_PWR_CTRL2 0x15024
124 #define E4X12_DIV_ISP0 0x18300
125 #define E4X12_DIV_ISP1 0x18304
126 #define E4X12_GATE_ISP0 0x18800
127 #define E4X12_GATE_ISP1 0x18804
128
129 /* Below definitions are used for PWR_CTRL settings */
130 #define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)
131 #define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16)
132 #define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
133 #define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
134 #define PWR_CTRL1_USE_CORE3_WFE (1 << 7)
135 #define PWR_CTRL1_USE_CORE2_WFE (1 << 6)
136 #define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
137 #define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
138 #define PWR_CTRL1_USE_CORE3_WFI (1 << 3)
139 #define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
140 #define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
141 #define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
142
143 /* the exynos4 soc type */
144 enum exynos4_soc {
145 EXYNOS4210,
146 EXYNOS4X12,
147 };
148
149 /* list of PLLs to be registered */
150 enum exynos4_plls {
151 apll, mpll, epll, vpll,
152 nr_plls /* number of PLLs */
153 };
154
155 static void __iomem *reg_base;
156 static enum exynos4_soc exynos4_soc;
157
158 /*
159 * Support for CMU save/restore across system suspends
160 */
161 #ifdef CONFIG_PM_SLEEP
162 static struct samsung_clk_reg_dump *exynos4_save_common;
163 static struct samsung_clk_reg_dump *exynos4_save_soc;
164 static struct samsung_clk_reg_dump *exynos4_save_pll;
165
166 /*
167 * list of controller registers to be saved and restored during a
168 * suspend/resume cycle.
169 */
170 static unsigned long exynos4210_clk_save[] __initdata = {
171 E4210_SRC_IMAGE,
172 E4210_SRC_LCD1,
173 E4210_SRC_MASK_LCD1,
174 E4210_DIV_LCD1,
175 E4210_GATE_IP_IMAGE,
176 E4210_GATE_IP_LCD1,
177 E4210_GATE_IP_PERIR,
178 E4210_MPLL_CON0,
179 PWR_CTRL1,
180 };
181
182 static unsigned long exynos4x12_clk_save[] __initdata = {
183 E4X12_GATE_IP_IMAGE,
184 E4X12_GATE_IP_PERIR,
185 E4X12_SRC_CAM1,
186 E4X12_DIV_ISP,
187 E4X12_DIV_CAM1,
188 E4X12_MPLL_CON0,
189 PWR_CTRL1,
190 E4X12_PWR_CTRL2,
191 };
192
193 static unsigned long exynos4_clk_pll_regs[] __initdata = {
194 EPLL_LOCK,
195 VPLL_LOCK,
196 EPLL_CON0,
197 EPLL_CON1,
198 EPLL_CON2,
199 VPLL_CON0,
200 VPLL_CON1,
201 VPLL_CON2,
202 };
203
204 static unsigned long exynos4_clk_regs[] __initdata = {
205 SRC_LEFTBUS,
206 DIV_LEFTBUS,
207 GATE_IP_LEFTBUS,
208 SRC_RIGHTBUS,
209 DIV_RIGHTBUS,
210 GATE_IP_RIGHTBUS,
211 SRC_TOP0,
212 SRC_TOP1,
213 SRC_CAM,
214 SRC_TV,
215 SRC_MFC,
216 SRC_G3D,
217 SRC_LCD0,
218 SRC_MAUDIO,
219 SRC_FSYS,
220 SRC_PERIL0,
221 SRC_PERIL1,
222 SRC_MASK_TOP,
223 SRC_MASK_CAM,
224 SRC_MASK_TV,
225 SRC_MASK_LCD0,
226 SRC_MASK_MAUDIO,
227 SRC_MASK_FSYS,
228 SRC_MASK_PERIL0,
229 SRC_MASK_PERIL1,
230 DIV_TOP,
231 DIV_CAM,
232 DIV_TV,
233 DIV_MFC,
234 DIV_G3D,
235 DIV_IMAGE,
236 DIV_LCD0,
237 DIV_MAUDIO,
238 DIV_FSYS0,
239 DIV_FSYS1,
240 DIV_FSYS2,
241 DIV_FSYS3,
242 DIV_PERIL0,
243 DIV_PERIL1,
244 DIV_PERIL2,
245 DIV_PERIL3,
246 DIV_PERIL4,
247 DIV_PERIL5,
248 GATE_SCLK_CAM,
249 GATE_IP_CAM,
250 GATE_IP_TV,
251 GATE_IP_MFC,
252 GATE_IP_G3D,
253 GATE_IP_LCD0,
254 GATE_IP_FSYS,
255 GATE_IP_GPS,
256 GATE_IP_PERIL,
257 GATE_BLOCK,
258 SRC_MASK_DMC,
259 SRC_DMC,
260 DIV_DMC0,
261 DIV_DMC1,
262 GATE_IP_DMC,
263 APLL_CON0,
264 SRC_CPU,
265 DIV_CPU0,
266 DIV_CPU1,
267 GATE_SCLK_CPU,
268 GATE_IP_CPU,
269 CLKOUT_CMU_LEFTBUS,
270 CLKOUT_CMU_RIGHTBUS,
271 CLKOUT_CMU_TOP,
272 CLKOUT_CMU_DMC,
273 CLKOUT_CMU_CPU,
274 };
275
276 static const struct samsung_clk_reg_dump src_mask_suspend[] = {
277 { .offset = SRC_MASK_TOP, .value = 0x00000001, },
278 { .offset = SRC_MASK_CAM, .value = 0x11111111, },
279 { .offset = SRC_MASK_TV, .value = 0x00000111, },
280 { .offset = SRC_MASK_LCD0, .value = 0x00001111, },
281 { .offset = SRC_MASK_MAUDIO, .value = 0x00000001, },
282 { .offset = SRC_MASK_FSYS, .value = 0x01011111, },
283 { .offset = SRC_MASK_PERIL0, .value = 0x01111111, },
284 { .offset = SRC_MASK_PERIL1, .value = 0x01110111, },
285 { .offset = SRC_MASK_DMC, .value = 0x00010000, },
286 };
287
288 static const struct samsung_clk_reg_dump src_mask_suspend_e4210[] = {
289 { .offset = E4210_SRC_MASK_LCD1, .value = 0x00001111, },
290 };
291
292 #define PLL_ENABLED (1 << 31)
293 #define PLL_LOCKED (1 << 29)
294
295 static void exynos4_clk_wait_for_pll(u32 reg)
296 {
297 u32 pll_con;
298
299 pll_con = readl(reg_base + reg);
300 if (!(pll_con & PLL_ENABLED))
301 return;
302
303 while (!(pll_con & PLL_LOCKED)) {
304 cpu_relax();
305 pll_con = readl(reg_base + reg);
306 }
307 }
308
309 static int exynos4_clk_suspend(void)
310 {
311 samsung_clk_save(reg_base, exynos4_save_common,
312 ARRAY_SIZE(exynos4_clk_regs));
313 samsung_clk_save(reg_base, exynos4_save_pll,
314 ARRAY_SIZE(exynos4_clk_pll_regs));
315
316 if (exynos4_soc == EXYNOS4210) {
317 samsung_clk_save(reg_base, exynos4_save_soc,
318 ARRAY_SIZE(exynos4210_clk_save));
319 samsung_clk_restore(reg_base, src_mask_suspend_e4210,
320 ARRAY_SIZE(src_mask_suspend_e4210));
321 } else {
322 samsung_clk_save(reg_base, exynos4_save_soc,
323 ARRAY_SIZE(exynos4x12_clk_save));
324 }
325
326 samsung_clk_restore(reg_base, src_mask_suspend,
327 ARRAY_SIZE(src_mask_suspend));
328
329 return 0;
330 }
331
332 static void exynos4_clk_resume(void)
333 {
334 samsung_clk_restore(reg_base, exynos4_save_pll,
335 ARRAY_SIZE(exynos4_clk_pll_regs));
336
337 exynos4_clk_wait_for_pll(EPLL_CON0);
338 exynos4_clk_wait_for_pll(VPLL_CON0);
339
340 samsung_clk_restore(reg_base, exynos4_save_common,
341 ARRAY_SIZE(exynos4_clk_regs));
342
343 if (exynos4_soc == EXYNOS4210)
344 samsung_clk_restore(reg_base, exynos4_save_soc,
345 ARRAY_SIZE(exynos4210_clk_save));
346 else
347 samsung_clk_restore(reg_base, exynos4_save_soc,
348 ARRAY_SIZE(exynos4x12_clk_save));
349 }
350
351 static struct syscore_ops exynos4_clk_syscore_ops = {
352 .suspend = exynos4_clk_suspend,
353 .resume = exynos4_clk_resume,
354 };
355
356 static void __init exynos4_clk_sleep_init(void)
357 {
358 exynos4_save_common = samsung_clk_alloc_reg_dump(exynos4_clk_regs,
359 ARRAY_SIZE(exynos4_clk_regs));
360 if (!exynos4_save_common)
361 goto err_warn;
362
363 if (exynos4_soc == EXYNOS4210)
364 exynos4_save_soc = samsung_clk_alloc_reg_dump(
365 exynos4210_clk_save,
366 ARRAY_SIZE(exynos4210_clk_save));
367 else
368 exynos4_save_soc = samsung_clk_alloc_reg_dump(
369 exynos4x12_clk_save,
370 ARRAY_SIZE(exynos4x12_clk_save));
371 if (!exynos4_save_soc)
372 goto err_common;
373
374 exynos4_save_pll = samsung_clk_alloc_reg_dump(exynos4_clk_pll_regs,
375 ARRAY_SIZE(exynos4_clk_pll_regs));
376 if (!exynos4_save_pll)
377 goto err_soc;
378
379 register_syscore_ops(&exynos4_clk_syscore_ops);
380 return;
381
382 err_soc:
383 kfree(exynos4_save_soc);
384 err_common:
385 kfree(exynos4_save_common);
386 err_warn:
387 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
388 __func__);
389 }
390 #else
391 static void __init exynos4_clk_sleep_init(void) {}
392 #endif
393
394 /* list of all parent clock list */
395 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
396 PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
397 PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
398 PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", };
399 PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
400 PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", };
401 PNAME(mout_mfc_p) = { "mout_mfc0", "mout_mfc1", };
402 PNAME(mout_g3d_p) = { "mout_g3d0", "mout_g3d1", };
403 PNAME(mout_g2d_p) = { "mout_g2d0", "mout_g2d1", };
404 PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", };
405 PNAME(mout_jpeg_p) = { "mout_jpeg0", "mout_jpeg1", };
406 PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
407 "spdif_extclk", };
408 PNAME(mout_onenand_p) = {"aclk133", "aclk160", };
409 PNAME(mout_onenand1_p) = {"mout_onenand", "sclk_vpll", };
410
411 /* Exynos 4210-specific parent groups */
412 PNAME(sclk_vpll_p4210) = { "mout_vpllsrc", "fout_vpll", };
413 PNAME(mout_core_p4210) = { "mout_apll", "sclk_mpll", };
414 PNAME(sclk_ampll_p4210) = { "sclk_mpll", "sclk_apll", };
415 PNAME(group1_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m",
416 "sclk_usbphy0", "none", "sclk_hdmiphy",
417 "sclk_mpll", "sclk_epll", "sclk_vpll", };
418 PNAME(mout_audio0_p4210) = { "cdclk0", "none", "sclk_hdmi24m",
419 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
420 "sclk_epll", "sclk_vpll" };
421 PNAME(mout_audio1_p4210) = { "cdclk1", "none", "sclk_hdmi24m",
422 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
423 "sclk_epll", "sclk_vpll", };
424 PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m",
425 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
426 "sclk_epll", "sclk_vpll", };
427 PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", };
428 PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", };
429 PNAME(mout_pwi_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
430 "sclk_usbphy1", "sclk_hdmiphy", "none",
431 "sclk_epll", "sclk_vpll" };
432 PNAME(clkout_left_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2",
433 "div_gdl", "div_gpl" };
434 PNAME(clkout_right_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2",
435 "div_gdr", "div_gpr" };
436 PNAME(clkout_top_p4210) = { "fout_epll", "fout_vpll", "sclk_hdmi24m",
437 "sclk_usbphy0", "sclk_usbphy1", "sclk_hdmiphy",
438 "cdclk0", "cdclk1", "cdclk2", "spdif_extclk",
439 "aclk160", "aclk133", "aclk200", "aclk100",
440 "sclk_mfc", "sclk_g3d", "sclk_g2d",
441 "cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l",
442 "s_rxbyteclkhs0_4l" };
443 PNAME(clkout_dmc_p4210) = { "div_dmcd", "div_dmcp", "div_acp_pclk", "div_dmc",
444 "div_dphy", "none", "div_pwi" };
445 PNAME(clkout_cpu_p4210) = { "fout_apll_div_2", "none", "fout_mpll_div_2",
446 "none", "arm_clk_div_2", "div_corem0",
447 "div_corem1", "div_corem0", "div_atb",
448 "div_periph", "div_pclk_dbg", "div_hpm" };
449
450 /* Exynos 4x12-specific parent groups */
451 PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", };
452 PNAME(mout_core_p4x12) = { "mout_apll", "mout_mpll_user_c", };
453 PNAME(mout_gdl_p4x12) = { "mout_mpll_user_l", "sclk_apll", };
454 PNAME(mout_gdr_p4x12) = { "mout_mpll_user_r", "sclk_apll", };
455 PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", };
456 PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
457 "none", "sclk_hdmiphy", "mout_mpll_user_t",
458 "sclk_epll", "sclk_vpll", };
459 PNAME(mout_audio0_p4x12) = { "cdclk0", "none", "sclk_hdmi24m",
460 "sclk_usbphy0", "xxti", "xusbxti",
461 "mout_mpll_user_t", "sclk_epll", "sclk_vpll" };
462 PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m",
463 "sclk_usbphy0", "xxti", "xusbxti",
464 "mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
465 PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m",
466 "sclk_usbphy0", "xxti", "xusbxti",
467 "mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
468 PNAME(aclk_p4412) = { "mout_mpll_user_t", "sclk_apll", };
469 PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", };
470 PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
471 PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
472 PNAME(mout_pwi_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
473 "none", "sclk_hdmiphy", "sclk_mpll",
474 "sclk_epll", "sclk_vpll" };
475 PNAME(clkout_left_p4x12) = { "sclk_mpll_user_l_div_2", "sclk_apll_div_2",
476 "div_gdl", "div_gpl" };
477 PNAME(clkout_right_p4x12) = { "sclk_mpll_user_r_div_2", "sclk_apll_div_2",
478 "div_gdr", "div_gpr" };
479 PNAME(clkout_top_p4x12) = { "fout_epll", "fout_vpll", "sclk_hdmi24m",
480 "sclk_usbphy0", "none", "sclk_hdmiphy",
481 "cdclk0", "cdclk1", "cdclk2", "spdif_extclk",
482 "aclk160", "aclk133", "aclk200", "aclk100",
483 "sclk_mfc", "sclk_g3d", "aclk400_mcuisp",
484 "cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l",
485 "s_rxbyteclkhs0_4l", "rx_half_byte_clk_csis0",
486 "rx_half_byte_clk_csis1", "div_jpeg",
487 "sclk_pwm_isp", "sclk_spi0_isp",
488 "sclk_spi1_isp", "sclk_uart_isp",
489 "sclk_mipihsi", "sclk_hdmi", "sclk_fimd0",
490 "sclk_pcm0" };
491 PNAME(clkout_dmc_p4x12) = { "div_dmcd", "div_dmcp", "aclk_acp", "div_acp_pclk",
492 "div_dmc", "div_dphy", "fout_mpll_div_2",
493 "div_pwi", "none", "div_c2c", "div_c2c_aclk" };
494 PNAME(clkout_cpu_p4x12) = { "fout_apll_div_2", "none", "none", "none",
495 "arm_clk_div_2", "div_corem0", "div_corem1",
496 "div_cores", "div_atb", "div_periph",
497 "div_pclk_dbg", "div_hpm" };
498
499 /* fixed rate clocks generated outside the soc */
500 static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
501 FRATE(CLK_XXTI, "xxti", NULL, CLK_IS_ROOT, 0),
502 FRATE(CLK_XUSBXTI, "xusbxti", NULL, CLK_IS_ROOT, 0),
503 };
504
505 /* fixed rate clocks generated inside the soc */
506 static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
507 FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
508 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", "hdmi", 0, 27000000),
509 FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
510 };
511
512 static struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
513 FRATE(0, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
514 };
515
516 static struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initdata = {
517 FFACTOR(0, "sclk_apll_div_2", "sclk_apll", 1, 2, 0),
518 FFACTOR(0, "fout_mpll_div_2", "fout_mpll", 1, 2, 0),
519 FFACTOR(0, "fout_apll_div_2", "fout_apll", 1, 2, 0),
520 FFACTOR(0, "arm_clk_div_2", "div_core2", 1, 2, 0),
521 };
522
523 static struct samsung_fixed_factor_clock exynos4210_fixed_factor_clks[] __initdata = {
524 FFACTOR(0, "sclk_mpll_div_2", "sclk_mpll", 1, 2, 0),
525 };
526
527 static struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initdata = {
528 FFACTOR(0, "sclk_mpll_user_l_div_2", "mout_mpll_user_l", 1, 2, 0),
529 FFACTOR(0, "sclk_mpll_user_r_div_2", "mout_mpll_user_r", 1, 2, 0),
530 FFACTOR(0, "sclk_mpll_user_t_div_2", "mout_mpll_user_t", 1, 2, 0),
531 FFACTOR(0, "sclk_mpll_user_c_div_2", "mout_mpll_user_c", 1, 2, 0),
532 };
533
534 /* list of mux clocks supported in all exynos4 soc's */
535 static struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
536 MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
537 CLK_SET_RATE_PARENT, 0, "mout_apll"),
538 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
539 MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
540 MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
541 MUX_F(CLK_MOUT_G3D1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1,
542 CLK_SET_RATE_PARENT, 0),
543 MUX_F(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1,
544 CLK_SET_RATE_PARENT, 0),
545 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
546 MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
547 MUX(CLK_SCLK_EPLL, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1),
548 MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
549
550 MUX(0, "mout_dmc_bus", sclk_ampll_p4210, SRC_DMC, 4, 1),
551 MUX(0, "mout_dphy", sclk_ampll_p4210, SRC_DMC, 8, 1),
552 };
553
554 /* list of mux clocks supported in exynos4210 soc */
555 static struct samsung_mux_clock exynos4210_mux_early[] __initdata = {
556 MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
557 };
558
559 static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
560 MUX(0, "mout_gdl", sclk_ampll_p4210, SRC_LEFTBUS, 0, 1),
561 MUX(0, "mout_clkout_leftbus", clkout_left_p4210,
562 CLKOUT_CMU_LEFTBUS, 0, 5),
563
564 MUX(0, "mout_gdr", sclk_ampll_p4210, SRC_RIGHTBUS, 0, 1),
565 MUX(0, "mout_clkout_rightbus", clkout_right_p4210,
566 CLKOUT_CMU_RIGHTBUS, 0, 5),
567
568 MUX(0, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
569 MUX(0, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
570 MUX(0, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
571 MUX(0, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1),
572 MUX(CLK_MOUT_MIXER, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1),
573 MUX(0, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
574 MUX(0, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1),
575 MUX(0, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1),
576 MUX(0, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
577 MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4),
578 MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
579 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
580 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
581 MUX(0, "mout_hpm", mout_core_p4210, SRC_CPU, 20, 1),
582 MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1),
583 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
584 MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
585 MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4),
586 MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4),
587 MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4),
588 MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4),
589 MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4),
590 MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4),
591 MUX(0, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1),
592 MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1,
593 CLK_SET_RATE_PARENT, 0),
594 MUX(0, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4),
595 MUX(0, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4),
596 MUX(0, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4),
597 MUX(0, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4),
598 MUX(0, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4),
599 MUX(0, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4),
600 MUX(0, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4),
601 MUX(0, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4),
602 MUX(0, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1),
603 MUX(0, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4),
604 MUX(0, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4),
605 MUX(0, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4),
606 MUX(0, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4),
607 MUX(0, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4),
608 MUX(0, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4),
609 MUX(0, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4),
610 MUX(0, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4),
611 MUX(0, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4),
612 MUX(0, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4),
613 MUX(0, "mout_clkout_top", clkout_top_p4210, CLKOUT_CMU_TOP, 0, 5),
614
615 MUX(0, "mout_pwi", mout_pwi_p4210, SRC_DMC, 16, 4),
616 MUX(0, "mout_clkout_dmc", clkout_dmc_p4210, CLKOUT_CMU_DMC, 0, 5),
617
618 MUX(0, "mout_clkout_cpu", clkout_cpu_p4210, CLKOUT_CMU_CPU, 0, 5),
619 };
620
621 /* list of mux clocks supported in exynos4x12 soc */
622 static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
623 MUX(0, "mout_mpll_user_l", mout_mpll_p, SRC_LEFTBUS, 4, 1),
624 MUX(0, "mout_gdl", mout_gdl_p4x12, SRC_LEFTBUS, 0, 1),
625 MUX(0, "mout_clkout_leftbus", clkout_left_p4x12,
626 CLKOUT_CMU_LEFTBUS, 0, 5),
627
628 MUX(0, "mout_mpll_user_r", mout_mpll_p, SRC_RIGHTBUS, 4, 1),
629 MUX(0, "mout_gdr", mout_gdr_p4x12, SRC_RIGHTBUS, 0, 1),
630 MUX(0, "mout_clkout_rightbus", clkout_right_p4x12,
631 CLKOUT_CMU_RIGHTBUS, 0, 5),
632
633 MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p4x12,
634 SRC_CPU, 24, 1),
635 MUX(0, "mout_clkout_cpu", clkout_cpu_p4x12, CLKOUT_CMU_CPU, 0, 5),
636
637 MUX(0, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
638 MUX(0, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
639 MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p4x12,
640 SRC_TOP1, 12, 1),
641 MUX(0, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12,
642 SRC_TOP1, 16, 1),
643 MUX(CLK_ACLK200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1),
644 MUX(CLK_ACLK400_MCUISP, "aclk400_mcuisp",
645 mout_user_aclk400_mcuisp_p4x12, SRC_TOP1, 24, 1),
646 MUX(0, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1),
647 MUX(0, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1),
648 MUX(0, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1),
649 MUX(0, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1),
650 MUX(0, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4),
651 MUX(0, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4),
652 MUX(0, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1),
653 MUX(0, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1),
654 MUX(0, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
655 MUX(0, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
656 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1),
657 MUX(CLK_SCLK_VPLL, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
658 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
659 MUX(0, "mout_hpm", mout_core_p4x12, SRC_CPU, 20, 1),
660 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
661 MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
662 MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
663 MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4),
664 MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4),
665 MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4),
666 MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4),
667 MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4),
668 MUX(0, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1),
669 MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1,
670 CLK_SET_RATE_PARENT, 0),
671 MUX(0, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4),
672 MUX(0, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4),
673 MUX(0, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4),
674 MUX(0, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4),
675 MUX(0, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4),
676 MUX(0, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4),
677 MUX(0, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4),
678 MUX(0, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4),
679 MUX(0, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1),
680 MUX(0, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4),
681 MUX(0, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4),
682 MUX(0, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4),
683 MUX(0, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4),
684 MUX(0, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4),
685 MUX(0, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4),
686 MUX(0, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4),
687 MUX(0, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4),
688 MUX(0, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4),
689 MUX(0, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4),
690 MUX(0, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4),
691 MUX(0, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
692 MUX(0, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
693 MUX(0, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
694 MUX(0, "mout_clkout_top", clkout_top_p4x12, CLKOUT_CMU_TOP, 0, 5),
695
696 MUX(0, "mout_c2c", sclk_ampll_p4210, SRC_DMC, 0, 1),
697 MUX(0, "mout_pwi", mout_pwi_p4x12, SRC_DMC, 16, 4),
698 MUX(0, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1),
699 MUX(0, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1),
700 MUX(0, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1),
701 MUX(0, "mout_clkout_dmc", clkout_dmc_p4x12, CLKOUT_CMU_DMC, 0, 5),
702 };
703
704 /* list of divider clocks supported in all exynos4 soc's */
705 static struct samsung_div_clock exynos4_div_clks[] __initdata = {
706 DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
707 DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
708 DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus",
709 CLKOUT_CMU_LEFTBUS, 8, 6),
710
711 DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),
712 DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
713 DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
714 CLKOUT_CMU_RIGHTBUS, 8, 6),
715
716 DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3),
717 DIV(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
718 DIV(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
719 DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
720 DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
721 DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
722 DIV(CLK_ARM_CLK, "div_core2", "div_core", DIV_CPU0, 28, 3),
723 DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
724 DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
725 DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
726
727 DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
728 DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
729 DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
730 DIV(0, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4),
731 DIV(0, "div_cam0", "mout_cam0", DIV_CAM, 16, 4),
732 DIV(0, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
733 DIV(0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
734 DIV(0, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
735 DIV(CLK_SCLK_MFC, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
736 DIV(CLK_SCLK_G3D, "sclk_g3d", "mout_g3d", DIV_G3D, 0, 4),
737 DIV(0, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
738 DIV(0, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
739 DIV(0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
740 DIV(CLK_SCLK_PCM0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8),
741 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
742 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
743 DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
744 DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
745 DIV(CLK_SCLK_PIXEL, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4),
746 DIV(CLK_ACLK100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4),
747 DIV(CLK_ACLK160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3),
748 DIV(CLK_ACLK133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3),
749 DIV(0, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3),
750 DIV(CLK_SCLK_SLIMBUS, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4),
751 DIV(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8),
752 DIV(CLK_SCLK_PCM2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8),
753 DIV(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
754 DIV(CLK_SCLK_I2S2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
755 DIV(0, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
756 DIV_F(0, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8,
757 CLK_SET_RATE_PARENT, 0),
758 DIV(0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
759 DIV(0, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
760 DIV(0, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
761 DIV(0, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
762 DIV(0, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4),
763 DIV(0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
764 DIV(0, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8),
765 DIV(0, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
766 DIV(0, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8),
767 DIV(0, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
768 DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
769 DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
770 DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
771 DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
772 DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
773 CLK_SET_RATE_PARENT, 0),
774 DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
775 CLK_SET_RATE_PARENT, 0),
776 DIV_F(0, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8,
777 CLK_SET_RATE_PARENT, 0),
778 DIV_F(0, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8,
779 CLK_SET_RATE_PARENT, 0),
780 DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
781 CLK_SET_RATE_PARENT, 0),
782 DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6),
783
784 DIV(CLK_DIV_ACP, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3),
785 DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3),
786 DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3),
787 DIV(CLK_DIV_DMC, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3),
788 DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3),
789 DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3),
790 DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4),
791 DIV(0, "div_clkout_dmc", "mout_clkout_dmc", CLKOUT_CMU_DMC, 8, 6),
792 };
793
794 /* list of divider clocks supported in exynos4210 soc */
795 static struct samsung_div_clock exynos4210_div_clks[] __initdata = {
796 DIV(CLK_ACLK200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
797 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4),
798 DIV(0, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
799 DIV(0, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
800 DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
801 DIV_F(0, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4,
802 CLK_SET_RATE_PARENT, 0),
803 };
804
805 /* list of divider clocks supported in exynos4x12 soc */
806 static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
807 DIV(0, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
808 DIV(0, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
809 DIV(0, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
810 DIV(0, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4),
811 DIV(0, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4),
812 DIV(CLK_DIV_ACLK200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3),
813 DIV(0, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3),
814 DIV(CLK_DIV_ACLK400_MCUISP, "div_aclk400_mcuisp", "mout_aclk400_mcuisp",
815 DIV_TOP, 24, 3),
816 DIV(0, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4),
817 DIV(0, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4),
818 DIV(0, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8),
819 DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
820 DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
821 DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
822 DIV_F(CLK_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3,
823 CLK_GET_RATE_NOCACHE, 0),
824 DIV_F(CLK_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3,
825 CLK_GET_RATE_NOCACHE, 0),
826 DIV(0, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
827 DIV_F(CLK_DIV_MCUISP0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1,
828 4, 3, CLK_GET_RATE_NOCACHE, 0),
829 DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1,
830 8, 3, CLK_GET_RATE_NOCACHE, 0),
831 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
832 DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
833 DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
834 };
835
836 /* list of gate clocks supported in all exynos4 soc's */
837 static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
838 /*
839 * After all Exynos4 based platforms are migrated to use device tree,
840 * the device name and clock alias names specified below for some
841 * of the clocks can be removed.
842 */
843 GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0),
844 GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0),
845 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
846 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0,
847 0),
848 GATE(CLK_JPEG, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
849 GATE(CLK_MIE0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
850 GATE(CLK_DSIM0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0),
851 GATE(CLK_FIMD1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0),
852 GATE(CLK_MIE1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0),
853 GATE(CLK_DSIM1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0),
854 GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0,
855 0),
856 GATE(CLK_TSI, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
857 GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
858 GATE(CLK_G3D, "g3d", "aclk200", GATE_IP_G3D, 0, 0, 0),
859 GATE(CLK_PPMUG3D, "ppmug3d", "aclk200", GATE_IP_G3D, 1, 0, 0),
860 GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
861 GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
862 GATE(CLK_NFCON, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
863 GATE(CLK_GPS, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0),
864 GATE(CLK_SMMU_GPS, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0),
865 GATE(CLK_PPMUGPS, "ppmugps", "aclk200", GATE_IP_GPS, 2, 0, 0),
866 GATE(CLK_SLIMBUS, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0),
867 GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4,
868 CLK_SET_RATE_PARENT, 0),
869 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5,
870 CLK_SET_RATE_PARENT, 0),
871 GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi_pre0",
872 SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0),
873 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0,
874 CLK_SET_RATE_PARENT, 0),
875 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0,
876 CLK_SET_RATE_PARENT, 0),
877 GATE(CLK_VP, "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
878 GATE(CLK_MIXER, "mixer", "aclk160", GATE_IP_TV, 1, 0, 0),
879 GATE(CLK_HDMI, "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0),
880 GATE(CLK_PWM, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0),
881 GATE(CLK_SDMMC4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0),
882 GATE(CLK_USB_HOST, "usb_host", "aclk133", GATE_IP_FSYS, 12, 0, 0),
883 GATE(CLK_SCLK_FIMC0, "sclk_fimc0", "div_fimc0", SRC_MASK_CAM, 0,
884 CLK_SET_RATE_PARENT, 0),
885 GATE(CLK_SCLK_FIMC1, "sclk_fimc1", "div_fimc1", SRC_MASK_CAM, 4,
886 CLK_SET_RATE_PARENT, 0),
887 GATE(CLK_SCLK_FIMC2, "sclk_fimc2", "div_fimc2", SRC_MASK_CAM, 8,
888 CLK_SET_RATE_PARENT, 0),
889 GATE(CLK_SCLK_FIMC3, "sclk_fimc3", "div_fimc3", SRC_MASK_CAM, 12,
890 CLK_SET_RATE_PARENT, 0),
891 GATE(CLK_SCLK_CSIS0, "sclk_csis0", "div_csis0", SRC_MASK_CAM, 24,
892 CLK_SET_RATE_PARENT, 0),
893 GATE(CLK_SCLK_CSIS1, "sclk_csis1", "div_csis1", SRC_MASK_CAM, 28,
894 CLK_SET_RATE_PARENT, 0),
895 GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0", SRC_MASK_LCD0, 0,
896 CLK_SET_RATE_PARENT, 0),
897 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0,
898 CLK_SET_RATE_PARENT, 0),
899 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4,
900 CLK_SET_RATE_PARENT, 0),
901 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8,
902 CLK_SET_RATE_PARENT, 0),
903 GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12,
904 CLK_SET_RATE_PARENT, 0),
905 GATE(CLK_SCLK_MMC4, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16,
906 CLK_SET_RATE_PARENT, 0),
907 GATE(CLK_SCLK_UART0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0,
908 CLK_SET_RATE_PARENT, 0),
909 GATE(CLK_SCLK_UART1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4,
910 CLK_SET_RATE_PARENT, 0),
911 GATE(CLK_SCLK_UART2, "uclk2", "div_uart2", SRC_MASK_PERIL0, 8,
912 CLK_SET_RATE_PARENT, 0),
913 GATE(CLK_SCLK_UART3, "uclk3", "div_uart3", SRC_MASK_PERIL0, 12,
914 CLK_SET_RATE_PARENT, 0),
915 GATE(CLK_SCLK_UART4, "uclk4", "div_uart4", SRC_MASK_PERIL0, 16,
916 CLK_SET_RATE_PARENT, 0),
917 GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4,
918 CLK_SET_RATE_PARENT, 0),
919 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0", SRC_MASK_PERIL1, 16,
920 CLK_SET_RATE_PARENT, 0),
921 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1", SRC_MASK_PERIL1, 20,
922 CLK_SET_RATE_PARENT, 0),
923 GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2", SRC_MASK_PERIL1, 24,
924 CLK_SET_RATE_PARENT, 0),
925 GATE(CLK_FIMC0, "fimc0", "aclk160", GATE_IP_CAM, 0,
926 0, 0),
927 GATE(CLK_FIMC1, "fimc1", "aclk160", GATE_IP_CAM, 1,
928 0, 0),
929 GATE(CLK_FIMC2, "fimc2", "aclk160", GATE_IP_CAM, 2,
930 0, 0),
931 GATE(CLK_FIMC3, "fimc3", "aclk160", GATE_IP_CAM, 3,
932 0, 0),
933 GATE(CLK_CSIS0, "csis0", "aclk160", GATE_IP_CAM, 4,
934 0, 0),
935 GATE(CLK_CSIS1, "csis1", "aclk160", GATE_IP_CAM, 5,
936 0, 0),
937 GATE(CLK_SMMU_FIMC0, "smmu_fimc0", "aclk160", GATE_IP_CAM, 7,
938 0, 0),
939 GATE(CLK_SMMU_FIMC1, "smmu_fimc1", "aclk160", GATE_IP_CAM, 8,
940 0, 0),
941 GATE(CLK_SMMU_FIMC2, "smmu_fimc2", "aclk160", GATE_IP_CAM, 9,
942 0, 0),
943 GATE(CLK_SMMU_FIMC3, "smmu_fimc3", "aclk160", GATE_IP_CAM, 10,
944 0, 0),
945 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11,
946 0, 0),
947 GATE(CLK_PPMUCAMIF, "ppmucamif", "aclk160", GATE_IP_CAM, 16, 0, 0),
948 GATE(CLK_PIXELASYNCM0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),
949 GATE(CLK_PIXELASYNCM1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0),
950 GATE(CLK_SMMU_TV, "smmu_tv", "aclk160", GATE_IP_TV, 4,
951 0, 0),
952 GATE(CLK_PPMUTV, "ppmutv", "aclk160", GATE_IP_TV, 5, 0, 0),
953 GATE(CLK_MFC, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0),
954 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1,
955 0, 0),
956 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2,
957 0, 0),
958 GATE(CLK_PPMUMFC_L, "ppmumfc_l", "aclk100", GATE_IP_MFC, 3, 0, 0),
959 GATE(CLK_PPMUMFC_R, "ppmumfc_r", "aclk100", GATE_IP_MFC, 4, 0, 0),
960 GATE(CLK_FIMD0, "fimd0", "aclk160", GATE_IP_LCD0, 0,
961 0, 0),
962 GATE(CLK_SMMU_FIMD0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4,
963 0, 0),
964 GATE(CLK_PPMULCD0, "ppmulcd0", "aclk160", GATE_IP_LCD0, 5, 0, 0),
965 GATE(CLK_PDMA0, "pdma0", "aclk133", GATE_IP_FSYS, 0,
966 0, 0),
967 GATE(CLK_PDMA1, "pdma1", "aclk133", GATE_IP_FSYS, 1,
968 0, 0),
969 GATE(CLK_SDMMC0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5,
970 0, 0),
971 GATE(CLK_SDMMC1, "sdmmc1", "aclk133", GATE_IP_FSYS, 6,
972 0, 0),
973 GATE(CLK_SDMMC2, "sdmmc2", "aclk133", GATE_IP_FSYS, 7,
974 0, 0),
975 GATE(CLK_SDMMC3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8,
976 0, 0),
977 GATE(CLK_PPMUFILE, "ppmufile", "aclk133", GATE_IP_FSYS, 17, 0, 0),
978 GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0,
979 0, 0),
980 GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1,
981 0, 0),
982 GATE(CLK_UART2, "uart2", "aclk100", GATE_IP_PERIL, 2,
983 0, 0),
984 GATE(CLK_UART3, "uart3", "aclk100", GATE_IP_PERIL, 3,
985 0, 0),
986 GATE(CLK_UART4, "uart4", "aclk100", GATE_IP_PERIL, 4,
987 0, 0),
988 GATE(CLK_I2C0, "i2c0", "aclk100", GATE_IP_PERIL, 6,
989 0, 0),
990 GATE(CLK_I2C1, "i2c1", "aclk100", GATE_IP_PERIL, 7,
991 0, 0),
992 GATE(CLK_I2C2, "i2c2", "aclk100", GATE_IP_PERIL, 8,
993 0, 0),
994 GATE(CLK_I2C3, "i2c3", "aclk100", GATE_IP_PERIL, 9,
995 0, 0),
996 GATE(CLK_I2C4, "i2c4", "aclk100", GATE_IP_PERIL, 10,
997 0, 0),
998 GATE(CLK_I2C5, "i2c5", "aclk100", GATE_IP_PERIL, 11,
999 0, 0),
1000 GATE(CLK_I2C6, "i2c6", "aclk100", GATE_IP_PERIL, 12,
1001 0, 0),
1002 GATE(CLK_I2C7, "i2c7", "aclk100", GATE_IP_PERIL, 13,
1003 0, 0),
1004 GATE(CLK_I2C_HDMI, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14,
1005 0, 0),
1006 GATE(CLK_SPI0, "spi0", "aclk100", GATE_IP_PERIL, 16,
1007 0, 0),
1008 GATE(CLK_SPI1, "spi1", "aclk100", GATE_IP_PERIL, 17,
1009 0, 0),
1010 GATE(CLK_SPI2, "spi2", "aclk100", GATE_IP_PERIL, 18,
1011 0, 0),
1012 GATE(CLK_I2S1, "i2s1", "aclk100", GATE_IP_PERIL, 20,
1013 0, 0),
1014 GATE(CLK_I2S2, "i2s2", "aclk100", GATE_IP_PERIL, 21,
1015 0, 0),
1016 GATE(CLK_PCM1, "pcm1", "aclk100", GATE_IP_PERIL, 22,
1017 0, 0),
1018 GATE(CLK_PCM2, "pcm2", "aclk100", GATE_IP_PERIL, 23,
1019 0, 0),
1020 GATE(CLK_SPDIF, "spdif", "aclk100", GATE_IP_PERIL, 26,
1021 0, 0),
1022 GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27,
1023 0, 0),
1024 GATE(CLK_PPMUDMC0, "ppmudmc0", "aclk133", GATE_IP_DMC, 8, 0, 0),
1025 GATE(CLK_PPMUDMC1, "ppmudmc1", "aclk133", GATE_IP_DMC, 9, 0, 0),
1026 GATE(CLK_PPMUCPU, "ppmucpu", "aclk133", GATE_IP_DMC, 10, 0, 0),
1027 GATE(CLK_PPMUACP, "ppmuacp", "aclk133", GATE_IP_DMC, 16, 0, 0),
1028
1029 GATE(CLK_OUT_LEFTBUS, "clkout_leftbus", "div_clkout_leftbus",
1030 CLKOUT_CMU_LEFTBUS, 16, CLK_SET_RATE_PARENT, 0),
1031 GATE(CLK_OUT_RIGHTBUS, "clkout_rightbus", "div_clkout_rightbus",
1032 CLKOUT_CMU_RIGHTBUS, 16, CLK_SET_RATE_PARENT, 0),
1033 GATE(CLK_OUT_TOP, "clkout_top", "div_clkout_top",
1034 CLKOUT_CMU_TOP, 16, CLK_SET_RATE_PARENT, 0),
1035 GATE(CLK_OUT_DMC, "clkout_dmc", "div_clkout_dmc",
1036 CLKOUT_CMU_DMC, 16, CLK_SET_RATE_PARENT, 0),
1037 GATE(CLK_OUT_CPU, "clkout_cpu", "div_clkout_cpu",
1038 CLKOUT_CMU_CPU, 16, CLK_SET_RATE_PARENT, 0),
1039 };
1040
1041 /* list of gate clocks supported in exynos4210 soc */
1042 static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
1043 GATE(CLK_TVENC, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
1044 GATE(CLK_G2D, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
1045 GATE(CLK_ROTATOR, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
1046 GATE(CLK_MDMA, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0),
1047 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0),
1048 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0,
1049 0),
1050 GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4210_GATE_IP_IMAGE, 9, 0,
1051 0),
1052 GATE(CLK_PPMULCD1, "ppmulcd1", "aclk160", E4210_GATE_IP_LCD1, 5, 0, 0),
1053 GATE(CLK_PCIE_PHY, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0),
1054 GATE(CLK_SATA_PHY, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0),
1055 GATE(CLK_SATA, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0),
1056 GATE(CLK_PCIE, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0),
1057 GATE(CLK_SMMU_PCIE, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
1058 GATE(CLK_MODEMIF, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
1059 GATE(CLK_CHIPID, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
1060 GATE(CLK_SYSREG, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0,
1061 CLK_IGNORE_UNUSED, 0),
1062 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0,
1063 0),
1064 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200",
1065 E4210_GATE_IP_IMAGE, 4, 0, 0),
1066 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi_pre1",
1067 E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
1068 GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
1069 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
1070 GATE(CLK_SCLK_MIXER, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
1071 GATE(CLK_SCLK_DAC, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
1072 GATE(CLK_TSADC, "tsadc", "aclk100", GATE_IP_PERIL, 15,
1073 0, 0),
1074 GATE(CLK_MCT, "mct", "aclk100", E4210_GATE_IP_PERIR, 13,
1075 0, 0),
1076 GATE(CLK_WDT, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14,
1077 0, 0),
1078 GATE(CLK_RTC, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15,
1079 0, 0),
1080 GATE(CLK_KEYIF, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16,
1081 0, 0),
1082 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0,
1083 CLK_SET_RATE_PARENT, 0),
1084 GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0,
1085 0),
1086 };
1087
1088 /* list of gate clocks supported in exynos4x12 soc */
1089 static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
1090 GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
1091 GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
1092 GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
1093 GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
1094 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0,
1095 0),
1096 GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4X12_GATE_IP_IMAGE, 9, 0,
1097 0),
1098 GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
1099 GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
1100 GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
1101 CLK_IGNORE_UNUSED, 0),
1102 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0,
1103 0),
1104 GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_mdnie0",
1105 SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),
1106 GATE(CLK_SCLK_MDNIE_PWM0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0",
1107 SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0),
1108 GATE(CLK_SCLK_MIPIHSI, "sclk_mipihsi", "div_mipihsi",
1109 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
1110 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200",
1111 E4X12_GATE_IP_IMAGE, 4, 0, 0),
1112 GATE(CLK_MCT, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13,
1113 0, 0),
1114 GATE(CLK_RTC, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15,
1115 0, 0),
1116 GATE(CLK_KEYIF, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0),
1117 GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk", "div_pwm_isp",
1118 E4X12_GATE_IP_ISP, 0, 0, 0),
1119 GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk", "div_spi0_isp_pre",
1120 E4X12_GATE_IP_ISP, 1, 0, 0),
1121 GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk", "div_spi1_isp_pre",
1122 E4X12_GATE_IP_ISP, 2, 0, 0),
1123 GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk", "div_uart_isp",
1124 E4X12_GATE_IP_ISP, 3, 0, 0),
1125 GATE(CLK_WDT, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0),
1126 GATE(CLK_PCM0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2,
1127 0, 0),
1128 GATE(CLK_I2S0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3,
1129 0, 0),
1130 GATE(CLK_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0,
1131 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1132 GATE(CLK_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1,
1133 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1134 GATE(CLK_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2,
1135 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1136 GATE(CLK_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3,
1137 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1138 GATE(CLK_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4,
1139 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1140 GATE(CLK_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5,
1141 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1142 GATE(CLK_GICISP, "gicisp", "aclk200", E4X12_GATE_ISP0, 7,
1143 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1144 GATE(CLK_SMMU_ISP, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8,
1145 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1146 GATE(CLK_SMMU_DRC, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9,
1147 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1148 GATE(CLK_SMMU_FD, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10,
1149 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1150 GATE(CLK_SMMU_LITE0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
1151 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1152 GATE(CLK_SMMU_LITE1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
1153 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1154 GATE(CLK_PPMUISPMX, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
1155 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1156 GATE(CLK_PPMUISPX, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
1157 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1158 GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
1159 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1160 GATE(CLK_MPWM_ISP, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
1161 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1162 GATE(CLK_I2C0_ISP, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
1163 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1164 GATE(CLK_I2C1_ISP, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
1165 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1166 GATE(CLK_MTCADC_ISP, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
1167 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1168 GATE(CLK_PWM_ISP, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28,
1169 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1170 GATE(CLK_WDT_ISP, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30,
1171 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1172 GATE(CLK_UART_ISP, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
1173 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1174 GATE(CLK_ASYNCAXIM, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
1175 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1176 GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
1177 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1178 GATE(CLK_SPI0_ISP, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
1179 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1180 GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
1181 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1182 GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
1183 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0),
1184 GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0,
1185 0),
1186 };
1187
1188 static struct samsung_clock_alias exynos4_aliases[] __initdata = {
1189 ALIAS(CLK_MOUT_CORE, NULL, "moutcore"),
1190 ALIAS(CLK_ARM_CLK, NULL, "armclk"),
1191 ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"),
1192 };
1193
1194 static struct samsung_clock_alias exynos4210_aliases[] __initdata = {
1195 ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"),
1196 };
1197
1198 static struct samsung_clock_alias exynos4x12_aliases[] __initdata = {
1199 ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"),
1200 };
1201
1202 /*
1203 * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
1204 * resides in chipid register space, outside of the clock controller memory
1205 * mapped space. So to determine the parent of fin_pll clock, the chipid
1206 * controller is first remapped and the value of XOM[0] bit is read to
1207 * determine the parent clock.
1208 */
1209 static unsigned long exynos4_get_xom(void)
1210 {
1211 unsigned long xom = 0;
1212 void __iomem *chipid_base;
1213 struct device_node *np;
1214
1215 np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");
1216 if (np) {
1217 chipid_base = of_iomap(np, 0);
1218
1219 if (chipid_base)
1220 xom = readl(chipid_base + 8);
1221
1222 iounmap(chipid_base);
1223 }
1224
1225 return xom;
1226 }
1227
1228 static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx)
1229 {
1230 struct samsung_fixed_rate_clock fclk;
1231 struct clk *clk;
1232 unsigned long finpll_f = 24000000;
1233 char *parent_name;
1234 unsigned int xom = exynos4_get_xom();
1235
1236 parent_name = xom & 1 ? "xusbxti" : "xxti";
1237 clk = clk_get(NULL, parent_name);
1238 if (IS_ERR(clk)) {
1239 pr_err("%s: failed to lookup parent clock %s, assuming "
1240 "fin_pll clock frequency is 24MHz\n", __func__,
1241 parent_name);
1242 } else {
1243 finpll_f = clk_get_rate(clk);
1244 }
1245
1246 fclk.id = CLK_FIN_PLL;
1247 fclk.name = "fin_pll";
1248 fclk.parent_name = NULL;
1249 fclk.flags = CLK_IS_ROOT;
1250 fclk.fixed_rate = finpll_f;
1251 samsung_clk_register_fixed_rate(ctx, &fclk, 1);
1252
1253 }
1254
1255 static const struct of_device_id ext_clk_match[] __initconst = {
1256 { .compatible = "samsung,clock-xxti", .data = (void *)0, },
1257 { .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
1258 {},
1259 };
1260
1261 /* PLLs PMS values */
1262 static struct samsung_pll_rate_table exynos4210_apll_rates[] __initdata = {
1263 PLL_45XX_RATE(1200000000, 150, 3, 1, 28),
1264 PLL_45XX_RATE(1000000000, 250, 6, 1, 28),
1265 PLL_45XX_RATE( 800000000, 200, 6, 1, 28),
1266 PLL_45XX_RATE( 666857142, 389, 14, 1, 13),
1267 PLL_45XX_RATE( 600000000, 100, 4, 1, 13),
1268 PLL_45XX_RATE( 533000000, 533, 24, 1, 5),
1269 PLL_45XX_RATE( 500000000, 250, 6, 2, 28),
1270 PLL_45XX_RATE( 400000000, 200, 6, 2, 28),
1271 PLL_45XX_RATE( 200000000, 200, 6, 3, 28),
1272 { /* sentinel */ }
1273 };
1274
1275 static struct samsung_pll_rate_table exynos4210_epll_rates[] __initdata = {
1276 PLL_4600_RATE(192000000, 48, 3, 1, 0, 0),
1277 PLL_4600_RATE(180633605, 45, 3, 1, 10381, 0),
1278 PLL_4600_RATE(180000000, 45, 3, 1, 0, 0),
1279 PLL_4600_RATE( 73727996, 73, 3, 3, 47710, 1),
1280 PLL_4600_RATE( 67737602, 90, 4, 3, 20762, 1),
1281 PLL_4600_RATE( 49151992, 49, 3, 3, 9961, 0),
1282 PLL_4600_RATE( 45158401, 45, 3, 3, 10381, 0),
1283 { /* sentinel */ }
1284 };
1285
1286 static struct samsung_pll_rate_table exynos4210_vpll_rates[] __initdata = {
1287 PLL_4650_RATE(360000000, 44, 3, 0, 1024, 0, 14, 0),
1288 PLL_4650_RATE(324000000, 53, 2, 1, 1024, 1, 1, 1),
1289 PLL_4650_RATE(259617187, 63, 3, 1, 1950, 0, 20, 1),
1290 PLL_4650_RATE(110000000, 53, 3, 2, 2048, 0, 17, 0),
1291 PLL_4650_RATE( 55360351, 53, 3, 3, 2417, 0, 17, 0),
1292 { /* sentinel */ }
1293 };
1294
1295 static struct samsung_pll_rate_table exynos4x12_apll_rates[] __initdata = {
1296 PLL_35XX_RATE(1500000000, 250, 4, 0),
1297 PLL_35XX_RATE(1400000000, 175, 3, 0),
1298 PLL_35XX_RATE(1300000000, 325, 6, 0),
1299 PLL_35XX_RATE(1200000000, 200, 4, 0),
1300 PLL_35XX_RATE(1100000000, 275, 6, 0),
1301 PLL_35XX_RATE(1000000000, 125, 3, 0),
1302 PLL_35XX_RATE( 900000000, 150, 4, 0),
1303 PLL_35XX_RATE( 800000000, 100, 3, 0),
1304 PLL_35XX_RATE( 700000000, 175, 3, 1),
1305 PLL_35XX_RATE( 600000000, 200, 4, 1),
1306 PLL_35XX_RATE( 500000000, 125, 3, 1),
1307 PLL_35XX_RATE( 400000000, 100, 3, 1),
1308 PLL_35XX_RATE( 300000000, 200, 4, 2),
1309 PLL_35XX_RATE( 200000000, 100, 3, 2),
1310 { /* sentinel */ }
1311 };
1312
1313 static struct samsung_pll_rate_table exynos4x12_epll_rates[] __initdata = {
1314 PLL_36XX_RATE(192000000, 48, 3, 1, 0),
1315 PLL_36XX_RATE(180633605, 45, 3, 1, 10381),
1316 PLL_36XX_RATE(180000000, 45, 3, 1, 0),
1317 PLL_36XX_RATE( 73727996, 73, 3, 3, 47710),
1318 PLL_36XX_RATE( 67737602, 90, 4, 3, 20762),
1319 PLL_36XX_RATE( 49151992, 49, 3, 3, 9961),
1320 PLL_36XX_RATE( 45158401, 45, 3, 3, 10381),
1321 { /* sentinel */ }
1322 };
1323
1324 static struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initdata = {
1325 PLL_36XX_RATE(533000000, 133, 3, 1, 16384),
1326 PLL_36XX_RATE(440000000, 110, 3, 1, 0),
1327 PLL_36XX_RATE(350000000, 175, 3, 2, 0),
1328 PLL_36XX_RATE(266000000, 133, 3, 2, 0),
1329 PLL_36XX_RATE(160000000, 160, 3, 3, 0),
1330 PLL_36XX_RATE(106031250, 53, 3, 2, 1024),
1331 PLL_36XX_RATE( 53015625, 53, 3, 3, 1024),
1332 { /* sentinel */ }
1333 };
1334
1335 static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = {
1336 [apll] = PLL_A(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll",
1337 APLL_LOCK, APLL_CON0, "fout_apll", NULL),
1338 [mpll] = PLL_A(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
1339 E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL),
1340 [epll] = PLL_A(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
1341 EPLL_LOCK, EPLL_CON0, "fout_epll", NULL),
1342 [vpll] = PLL_A(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
1343 VPLL_LOCK, VPLL_CON0, "fout_vpll", NULL),
1344 };
1345
1346 static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
1347 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
1348 APLL_LOCK, APLL_CON0, NULL),
1349 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
1350 E4X12_MPLL_LOCK, E4X12_MPLL_CON0, NULL),
1351 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
1352 EPLL_LOCK, EPLL_CON0, NULL),
1353 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
1354 VPLL_LOCK, VPLL_CON0, NULL),
1355 };
1356
1357 static void __init exynos4_core_down_clock(enum exynos4_soc soc)
1358 {
1359 unsigned int tmp;
1360
1361 /*
1362 * Enable arm clock down (in idle) and set arm divider
1363 * ratios in WFI/WFE state.
1364 */
1365 tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
1366 PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
1367 PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
1368 PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
1369 /* On Exynos4412 enable it also on core 2 and 3 */
1370 if (num_possible_cpus() == 4)
1371 tmp |= PWR_CTRL1_USE_CORE3_WFE | PWR_CTRL1_USE_CORE2_WFE |
1372 PWR_CTRL1_USE_CORE3_WFI | PWR_CTRL1_USE_CORE2_WFI;
1373 __raw_writel(tmp, reg_base + PWR_CTRL1);
1374
1375 /*
1376 * Disable the clock up feature on Exynos4x12, in case it was
1377 * enabled by bootloader.
1378 */
1379 if (exynos4_soc == EXYNOS4X12)
1380 __raw_writel(0x0, reg_base + E4X12_PWR_CTRL2);
1381 }
1382
1383 /* register exynos4 clocks */
1384 static void __init exynos4_clk_init(struct device_node *np,
1385 enum exynos4_soc soc)
1386 {
1387 struct samsung_clk_provider *ctx;
1388 exynos4_soc = soc;
1389
1390 reg_base = of_iomap(np, 0);
1391 if (!reg_base)
1392 panic("%s: failed to map registers\n", __func__);
1393
1394 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
1395 if (!ctx)
1396 panic("%s: unable to allocate context.\n", __func__);
1397
1398 samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,
1399 ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
1400 ext_clk_match);
1401
1402 exynos4_clk_register_finpll(ctx);
1403
1404 if (exynos4_soc == EXYNOS4210) {
1405 samsung_clk_register_mux(ctx, exynos4210_mux_early,
1406 ARRAY_SIZE(exynos4210_mux_early));
1407
1408 if (_get_rate("fin_pll") == 24000000) {
1409 exynos4210_plls[apll].rate_table =
1410 exynos4210_apll_rates;
1411 exynos4210_plls[epll].rate_table =
1412 exynos4210_epll_rates;
1413 }
1414
1415 if (_get_rate("mout_vpllsrc") == 24000000)
1416 exynos4210_plls[vpll].rate_table =
1417 exynos4210_vpll_rates;
1418
1419 samsung_clk_register_pll(ctx, exynos4210_plls,
1420 ARRAY_SIZE(exynos4210_plls), reg_base);
1421 } else {
1422 if (_get_rate("fin_pll") == 24000000) {
1423 exynos4x12_plls[apll].rate_table =
1424 exynos4x12_apll_rates;
1425 exynos4x12_plls[epll].rate_table =
1426 exynos4x12_epll_rates;
1427 exynos4x12_plls[vpll].rate_table =
1428 exynos4x12_vpll_rates;
1429 }
1430
1431 samsung_clk_register_pll(ctx, exynos4x12_plls,
1432 ARRAY_SIZE(exynos4x12_plls), reg_base);
1433 }
1434
1435 samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,
1436 ARRAY_SIZE(exynos4_fixed_rate_clks));
1437 samsung_clk_register_mux(ctx, exynos4_mux_clks,
1438 ARRAY_SIZE(exynos4_mux_clks));
1439 samsung_clk_register_div(ctx, exynos4_div_clks,
1440 ARRAY_SIZE(exynos4_div_clks));
1441 samsung_clk_register_gate(ctx, exynos4_gate_clks,
1442 ARRAY_SIZE(exynos4_gate_clks));
1443 samsung_clk_register_fixed_factor(ctx, exynos4_fixed_factor_clks,
1444 ARRAY_SIZE(exynos4_fixed_factor_clks));
1445
1446 if (exynos4_soc == EXYNOS4210) {
1447 samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,
1448 ARRAY_SIZE(exynos4210_fixed_rate_clks));
1449 samsung_clk_register_mux(ctx, exynos4210_mux_clks,
1450 ARRAY_SIZE(exynos4210_mux_clks));
1451 samsung_clk_register_div(ctx, exynos4210_div_clks,
1452 ARRAY_SIZE(exynos4210_div_clks));
1453 samsung_clk_register_gate(ctx, exynos4210_gate_clks,
1454 ARRAY_SIZE(exynos4210_gate_clks));
1455 samsung_clk_register_alias(ctx, exynos4210_aliases,
1456 ARRAY_SIZE(exynos4210_aliases));
1457 samsung_clk_register_fixed_factor(ctx,
1458 exynos4210_fixed_factor_clks,
1459 ARRAY_SIZE(exynos4210_fixed_factor_clks));
1460 } else {
1461 samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
1462 ARRAY_SIZE(exynos4x12_mux_clks));
1463 samsung_clk_register_div(ctx, exynos4x12_div_clks,
1464 ARRAY_SIZE(exynos4x12_div_clks));
1465 samsung_clk_register_gate(ctx, exynos4x12_gate_clks,
1466 ARRAY_SIZE(exynos4x12_gate_clks));
1467 samsung_clk_register_alias(ctx, exynos4x12_aliases,
1468 ARRAY_SIZE(exynos4x12_aliases));
1469 samsung_clk_register_fixed_factor(ctx,
1470 exynos4x12_fixed_factor_clks,
1471 ARRAY_SIZE(exynos4x12_fixed_factor_clks));
1472 }
1473
1474 samsung_clk_register_alias(ctx, exynos4_aliases,
1475 ARRAY_SIZE(exynos4_aliases));
1476
1477 exynos4_core_down_clock(soc);
1478 exynos4_clk_sleep_init();
1479
1480 samsung_clk_of_add_provider(np, ctx);
1481
1482 pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
1483 "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
1484 exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
1485 _get_rate("sclk_apll"), _get_rate("sclk_mpll"),
1486 _get_rate("sclk_epll"), _get_rate("sclk_vpll"),
1487 _get_rate("div_core2"));
1488 }
1489
1490
1491 static void __init exynos4210_clk_init(struct device_node *np)
1492 {
1493 exynos4_clk_init(np, EXYNOS4210);
1494 }
1495 CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init);
1496
1497 static void __init exynos4412_clk_init(struct device_node *np)
1498 {
1499 exynos4_clk_init(np, EXYNOS4X12);
1500 }
1501 CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init);
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