2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 * Author: Thomas Abraham <thomas.ab@samsung.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Common Clock Framework support for Exynos5250 SoC.
13 #include <dt-bindings/clock/exynos5250.h>
14 #include <linux/clk-provider.h>
16 #include <linux/of_address.h>
17 #include <linux/syscore_ops.h>
23 #define APLL_CON0 0x100
25 #define DIV_CPU0 0x500
26 #define PWR_CTRL1 0x1020
27 #define PWR_CTRL2 0x1024
28 #define MPLL_LOCK 0x4000
29 #define MPLL_CON0 0x4100
30 #define SRC_CORE1 0x4204
31 #define GATE_IP_ACP 0x8800
32 #define GATE_IP_ISP0 0xc800
33 #define GATE_IP_ISP1 0xc804
34 #define CPLL_LOCK 0x10020
35 #define EPLL_LOCK 0x10030
36 #define VPLL_LOCK 0x10040
37 #define GPLL_LOCK 0x10050
38 #define CPLL_CON0 0x10120
39 #define EPLL_CON0 0x10130
40 #define VPLL_CON0 0x10140
41 #define GPLL_CON0 0x10150
42 #define SRC_TOP0 0x10210
43 #define SRC_TOP1 0x10214
44 #define SRC_TOP2 0x10218
45 #define SRC_TOP3 0x1021c
46 #define SRC_GSCL 0x10220
47 #define SRC_DISP1_0 0x1022c
48 #define SRC_MAU 0x10240
49 #define SRC_FSYS 0x10244
50 #define SRC_GEN 0x10248
51 #define SRC_PERIC0 0x10250
52 #define SRC_PERIC1 0x10254
53 #define SRC_MASK_GSCL 0x10320
54 #define SRC_MASK_DISP1_0 0x1032c
55 #define SRC_MASK_MAU 0x10334
56 #define SRC_MASK_FSYS 0x10340
57 #define SRC_MASK_GEN 0x10344
58 #define SRC_MASK_PERIC0 0x10350
59 #define SRC_MASK_PERIC1 0x10354
60 #define DIV_TOP0 0x10510
61 #define DIV_TOP1 0x10514
62 #define DIV_GSCL 0x10520
63 #define DIV_DISP1_0 0x1052c
64 #define DIV_GEN 0x1053c
65 #define DIV_MAU 0x10544
66 #define DIV_FSYS0 0x10548
67 #define DIV_FSYS1 0x1054c
68 #define DIV_FSYS2 0x10550
69 #define DIV_PERIC0 0x10558
70 #define DIV_PERIC1 0x1055c
71 #define DIV_PERIC2 0x10560
72 #define DIV_PERIC3 0x10564
73 #define DIV_PERIC4 0x10568
74 #define DIV_PERIC5 0x1056c
75 #define GATE_IP_GSCL 0x10920
76 #define GATE_IP_DISP1 0x10928
77 #define GATE_IP_MFC 0x1092c
78 #define GATE_IP_G3D 0x10930
79 #define GATE_IP_GEN 0x10934
80 #define GATE_IP_FSYS 0x10944
81 #define GATE_IP_PERIC 0x10950
82 #define GATE_IP_PERIS 0x10960
83 #define BPLL_LOCK 0x20010
84 #define BPLL_CON0 0x20110
85 #define SRC_CDREX 0x20200
86 #define PLL_DIV2_SEL 0x20a24
88 /*Below definitions are used for PWR_CTRL settings*/
89 #define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28)
90 #define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16)
91 #define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
92 #define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
93 #define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
94 #define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
95 #define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
96 #define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
98 #define PWR_CTRL2_DIV2_UP_EN (1 << 25)
99 #define PWR_CTRL2_DIV1_UP_EN (1 << 24)
100 #define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16)
101 #define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8)
102 #define PWR_CTRL2_CORE2_UP_RATIO (1 << 4)
103 #define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
105 /* list of PLLs to be registered */
106 enum exynos5250_plls
{
107 apll
, mpll
, cpll
, epll
, vpll
, gpll
, bpll
,
108 nr_plls
/* number of PLLs */
111 static void __iomem
*reg_base
;
113 #ifdef CONFIG_PM_SLEEP
114 static struct samsung_clk_reg_dump
*exynos5250_save
;
117 * list of controller registers to be saved and restored during a
118 * suspend/resume cycle.
120 static unsigned long exynos5250_clk_regs
[] __initdata
= {
174 static int exynos5250_clk_suspend(void)
176 samsung_clk_save(reg_base
, exynos5250_save
,
177 ARRAY_SIZE(exynos5250_clk_regs
));
182 static void exynos5250_clk_resume(void)
184 samsung_clk_restore(reg_base
, exynos5250_save
,
185 ARRAY_SIZE(exynos5250_clk_regs
));
188 static struct syscore_ops exynos5250_clk_syscore_ops
= {
189 .suspend
= exynos5250_clk_suspend
,
190 .resume
= exynos5250_clk_resume
,
193 static void exynos5250_clk_sleep_init(void)
195 exynos5250_save
= samsung_clk_alloc_reg_dump(exynos5250_clk_regs
,
196 ARRAY_SIZE(exynos5250_clk_regs
));
197 if (!exynos5250_save
) {
198 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
203 register_syscore_ops(&exynos5250_clk_syscore_ops
);
206 static void exynos5250_clk_sleep_init(void) {}
209 /* list of all parent clock list */
210 PNAME(mout_apll_p
) = { "fin_pll", "fout_apll", };
211 PNAME(mout_cpu_p
) = { "mout_apll", "mout_mpll", };
212 PNAME(mout_mpll_fout_p
) = { "fout_mplldiv2", "fout_mpll" };
213 PNAME(mout_mpll_p
) = { "fin_pll", "mout_mpll_fout" };
214 PNAME(mout_bpll_fout_p
) = { "fout_bplldiv2", "fout_bpll" };
215 PNAME(mout_bpll_p
) = { "fin_pll", "mout_bpll_fout" };
216 PNAME(mout_vpllsrc_p
) = { "fin_pll", "sclk_hdmi27m" };
217 PNAME(mout_vpll_p
) = { "mout_vpllsrc", "fout_vpll" };
218 PNAME(mout_cpll_p
) = { "fin_pll", "fout_cpll" };
219 PNAME(mout_epll_p
) = { "fin_pll", "fout_epll" };
220 PNAME(mout_gpll_p
) = { "fin_pll", "fout_gpll" };
221 PNAME(mout_mpll_user_p
) = { "fin_pll", "mout_mpll" };
222 PNAME(mout_bpll_user_p
) = { "fin_pll", "mout_bpll" };
223 PNAME(mout_aclk166_p
) = { "mout_cpll", "mout_mpll_user" };
224 PNAME(mout_aclk200_p
) = { "mout_mpll_user", "mout_bpll_user" };
225 PNAME(mout_aclk400_p
) = { "mout_aclk400_g3d_mid", "mout_gpll" };
226 PNAME(mout_aclk200_sub_p
) = { "fin_pll", "div_aclk200" };
227 PNAME(mout_aclk266_sub_p
) = { "fin_pll", "div_aclk266" };
228 PNAME(mout_aclk333_sub_p
) = { "fin_pll", "div_aclk333" };
229 PNAME(mout_aclk400_isp_sub_p
) = { "fin_pll", "div_aclk400_isp" };
230 PNAME(mout_hdmi_p
) = { "div_hdmi_pixel", "sclk_hdmiphy" };
231 PNAME(mout_usb3_p
) = { "mout_mpll_user", "mout_cpll" };
232 PNAME(mout_group1_p
) = { "fin_pll", "fin_pll", "sclk_hdmi27m",
233 "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy",
234 "mout_mpll_user", "mout_epll", "mout_vpll",
235 "mout_cpll", "none", "none",
236 "none", "none", "none",
238 PNAME(mout_audio0_p
) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
239 "sclk_uhostphy", "fin_pll",
240 "mout_mpll_user", "mout_epll", "mout_vpll",
241 "mout_cpll", "none", "none",
242 "none", "none", "none",
244 PNAME(mout_audio1_p
) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
245 "sclk_uhostphy", "fin_pll",
246 "mout_mpll_user", "mout_epll", "mout_vpll",
247 "mout_cpll", "none", "none",
248 "none", "none", "none",
250 PNAME(mout_audio2_p
) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
251 "sclk_uhostphy", "fin_pll",
252 "mout_mpll_user", "mout_epll", "mout_vpll",
253 "mout_cpll", "none", "none",
254 "none", "none", "none",
256 PNAME(mout_spdif_p
) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
259 /* fixed rate clocks generated outside the soc */
260 static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks
[] __initdata
= {
261 FRATE(CLK_FIN_PLL
, "fin_pll", NULL
, CLK_IS_ROOT
, 0),
264 /* fixed rate clocks generated inside the soc */
265 static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks
[] __initdata
= {
266 FRATE(CLK_SCLK_HDMIPHY
, "sclk_hdmiphy", NULL
, CLK_IS_ROOT
, 24000000),
267 FRATE(0, "sclk_hdmi27m", NULL
, CLK_IS_ROOT
, 27000000),
268 FRATE(0, "sclk_dptxphy", NULL
, CLK_IS_ROOT
, 24000000),
269 FRATE(0, "sclk_uhostphy", NULL
, CLK_IS_ROOT
, 48000000),
272 static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks
[] __initdata
= {
273 FFACTOR(0, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
274 FFACTOR(0, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
277 static struct samsung_mux_clock exynos5250_pll_pmux_clks
[] __initdata
= {
278 MUX(0, "mout_vpllsrc", mout_vpllsrc_p
, SRC_TOP2
, 0, 1),
281 static struct samsung_mux_clock exynos5250_mux_clks
[] __initdata
= {
283 * NOTE: Following table is sorted by (clock domain, register address,
284 * bitfield shift) triplet in ascending order. When adding new entries,
285 * please make sure that the order is kept, to avoid merge conflicts
286 * and make further work with defined data easier.
292 MUX_FA(0, "mout_apll", mout_apll_p
, SRC_CPU
, 0, 1,
293 CLK_SET_RATE_PARENT
, 0, "mout_apll"),
294 MUX_A(0, "mout_cpu", mout_cpu_p
, SRC_CPU
, 16, 1, "mout_cpu"),
299 MUX_A(0, "mout_mpll", mout_mpll_p
, SRC_CORE1
, 8, 1, "mout_mpll"),
304 MUX(0, "mout_aclk166", mout_aclk166_p
, SRC_TOP0
, 8, 1),
305 MUX(0, "mout_aclk200", mout_aclk200_p
, SRC_TOP0
, 12, 1),
306 MUX(0, "mout_aclk333", mout_aclk166_p
, SRC_TOP0
, 16, 1),
307 MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p
, SRC_TOP0
, 20, 1),
309 MUX(0, "mout_aclk400_isp", mout_aclk200_p
, SRC_TOP1
, 24, 1),
310 MUX(0, "mout_aclk400_g3d", mout_aclk400_p
, SRC_TOP1
, 28, 1),
312 MUX(0, "mout_cpll", mout_cpll_p
, SRC_TOP2
, 8, 1),
313 MUX(0, "mout_epll", mout_epll_p
, SRC_TOP2
, 12, 1),
314 MUX(0, "mout_vpll", mout_vpll_p
, SRC_TOP2
, 16, 1),
315 MUX(0, "mout_mpll_user", mout_mpll_user_p
, SRC_TOP2
, 20, 1),
316 MUX(0, "mout_bpll_user", mout_bpll_user_p
, SRC_TOP2
, 24, 1),
317 MUX(CLK_MOUT_GPLL
, "mout_gpll", mout_gpll_p
, SRC_TOP2
, 28, 1),
319 MUX(0, "mout_aclk200_disp1_sub", mout_aclk200_sub_p
, SRC_TOP3
, 4, 1),
320 MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p
, SRC_TOP3
, 8, 1),
321 MUX(0, "mout_aclk_266_isp_sub", mout_aclk266_sub_p
, SRC_TOP3
, 16, 1),
322 MUX(0, "mout_aclk_400_isp_sub", mout_aclk400_isp_sub_p
,
324 MUX(0, "mout_aclk333_sub", mout_aclk333_sub_p
, SRC_TOP3
, 24, 1),
326 MUX(0, "mout_cam_bayer", mout_group1_p
, SRC_GSCL
, 12, 4),
327 MUX(0, "mout_cam0", mout_group1_p
, SRC_GSCL
, 16, 4),
328 MUX(0, "mout_cam1", mout_group1_p
, SRC_GSCL
, 20, 4),
329 MUX(0, "mout_gscl_wa", mout_group1_p
, SRC_GSCL
, 24, 4),
330 MUX(0, "mout_gscl_wb", mout_group1_p
, SRC_GSCL
, 28, 4),
332 MUX(0, "mout_fimd1", mout_group1_p
, SRC_DISP1_0
, 0, 4),
333 MUX(0, "mout_mipi1", mout_group1_p
, SRC_DISP1_0
, 12, 4),
334 MUX(0, "mout_dp", mout_group1_p
, SRC_DISP1_0
, 16, 4),
335 MUX(CLK_MOUT_HDMI
, "mout_hdmi", mout_hdmi_p
, SRC_DISP1_0
, 20, 1),
337 MUX(0, "mout_audio0", mout_audio0_p
, SRC_MAU
, 0, 4),
339 MUX(0, "mout_mmc0", mout_group1_p
, SRC_FSYS
, 0, 4),
340 MUX(0, "mout_mmc1", mout_group1_p
, SRC_FSYS
, 4, 4),
341 MUX(0, "mout_mmc2", mout_group1_p
, SRC_FSYS
, 8, 4),
342 MUX(0, "mout_mmc3", mout_group1_p
, SRC_FSYS
, 12, 4),
343 MUX(0, "mout_sata", mout_aclk200_p
, SRC_FSYS
, 24, 1),
344 MUX(0, "mout_usb3", mout_usb3_p
, SRC_FSYS
, 28, 1),
346 MUX(0, "mout_jpeg", mout_group1_p
, SRC_GEN
, 0, 4),
348 MUX(0, "mout_uart0", mout_group1_p
, SRC_PERIC0
, 0, 4),
349 MUX(0, "mout_uart1", mout_group1_p
, SRC_PERIC0
, 4, 4),
350 MUX(0, "mout_uart2", mout_group1_p
, SRC_PERIC0
, 8, 4),
351 MUX(0, "mout_uart3", mout_group1_p
, SRC_PERIC0
, 12, 4),
352 MUX(0, "mout_pwm", mout_group1_p
, SRC_PERIC0
, 24, 4),
354 MUX(0, "mout_audio1", mout_audio1_p
, SRC_PERIC1
, 0, 4),
355 MUX(0, "mout_audio2", mout_audio2_p
, SRC_PERIC1
, 4, 4),
356 MUX(0, "mout_spdif", mout_spdif_p
, SRC_PERIC1
, 8, 2),
357 MUX(0, "mout_spi0", mout_group1_p
, SRC_PERIC1
, 16, 4),
358 MUX(0, "mout_spi1", mout_group1_p
, SRC_PERIC1
, 20, 4),
359 MUX(0, "mout_spi2", mout_group1_p
, SRC_PERIC1
, 24, 4),
364 MUX(0, "mout_bpll", mout_bpll_p
, SRC_CDREX
, 0, 1),
366 MUX(0, "mout_mpll_fout", mout_mpll_fout_p
, PLL_DIV2_SEL
, 4, 1),
367 MUX(0, "mout_bpll_fout", mout_bpll_fout_p
, PLL_DIV2_SEL
, 0, 1),
370 static struct samsung_div_clock exynos5250_div_clks
[] __initdata
= {
372 * NOTE: Following table is sorted by (clock domain, register address,
373 * bitfield shift) triplet in ascending order. When adding new entries,
374 * please make sure that the order is kept, to avoid merge conflicts
375 * and make further work with defined data easier.
381 DIV(0, "div_arm", "mout_cpu", DIV_CPU0
, 0, 3),
382 DIV(0, "div_apll", "mout_apll", DIV_CPU0
, 24, 3),
383 DIV_A(0, "div_arm2", "div_arm", DIV_CPU0
, 28, 3, "armclk"),
388 DIV(0, "div_aclk66", "div_aclk66_pre", DIV_TOP0
, 0, 3),
389 DIV(0, "div_aclk166", "mout_aclk166", DIV_TOP0
, 8, 3),
390 DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0
, 12, 3),
391 DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0
, 16, 3),
392 DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0
, 20, 3),
393 DIV(0, "div_aclk400_g3d", "mout_aclk400_g3d", DIV_TOP0
,
396 DIV(0, "div_aclk400_isp", "mout_aclk400_isp", DIV_TOP1
, 20, 3),
397 DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1
, 24, 3),
399 DIV(0, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL
, 12, 4),
400 DIV(0, "div_cam0", "mout_cam0", DIV_GSCL
, 16, 4),
401 DIV(0, "div_cam1", "mout_cam1", DIV_GSCL
, 20, 4),
402 DIV(0, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL
, 24, 4),
403 DIV(0, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL
, 28, 4),
405 DIV(0, "div_fimd1", "mout_fimd1", DIV_DISP1_0
, 0, 4),
406 DIV(0, "div_mipi1", "mout_mipi1", DIV_DISP1_0
, 16, 4),
407 DIV_F(0, "div_mipi1_pre", "div_mipi1",
408 DIV_DISP1_0
, 20, 4, CLK_SET_RATE_PARENT
, 0),
409 DIV(0, "div_dp", "mout_dp", DIV_DISP1_0
, 24, 4),
410 DIV(CLK_SCLK_PIXEL
, "div_hdmi_pixel", "mout_vpll", DIV_DISP1_0
, 28, 4),
412 DIV(0, "div_jpeg", "mout_jpeg", DIV_GEN
, 4, 4),
414 DIV(0, "div_audio0", "mout_audio0", DIV_MAU
, 0, 4),
415 DIV(CLK_DIV_PCM0
, "div_pcm0", "sclk_audio0", DIV_MAU
, 4, 8),
417 DIV(0, "div_sata", "mout_sata", DIV_FSYS0
, 20, 4),
418 DIV(0, "div_usb3", "mout_usb3", DIV_FSYS0
, 24, 4),
420 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1
, 0, 4),
421 DIV_F(0, "div_mmc_pre0", "div_mmc0",
422 DIV_FSYS1
, 8, 8, CLK_SET_RATE_PARENT
, 0),
423 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1
, 16, 4),
424 DIV_F(0, "div_mmc_pre1", "div_mmc1",
425 DIV_FSYS1
, 24, 8, CLK_SET_RATE_PARENT
, 0),
427 DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2
, 0, 4),
428 DIV_F(0, "div_mmc_pre2", "div_mmc2",
429 DIV_FSYS2
, 8, 8, CLK_SET_RATE_PARENT
, 0),
430 DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2
, 16, 4),
431 DIV_F(0, "div_mmc_pre3", "div_mmc3",
432 DIV_FSYS2
, 24, 8, CLK_SET_RATE_PARENT
, 0),
434 DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0
, 0, 4),
435 DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0
, 4, 4),
436 DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0
, 8, 4),
437 DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0
, 12, 4),
439 DIV(0, "div_spi0", "mout_spi0", DIV_PERIC1
, 0, 4),
440 DIV_F(0, "div_spi_pre0", "div_spi0",
441 DIV_PERIC1
, 8, 8, CLK_SET_RATE_PARENT
, 0),
442 DIV(0, "div_spi1", "mout_spi1", DIV_PERIC1
, 16, 4),
443 DIV_F(0, "div_spi_pre1", "div_spi1",
444 DIV_PERIC1
, 24, 8, CLK_SET_RATE_PARENT
, 0),
446 DIV(0, "div_spi2", "mout_spi2", DIV_PERIC2
, 0, 4),
447 DIV_F(0, "div_spi_pre2", "div_spi2",
448 DIV_PERIC2
, 8, 8, CLK_SET_RATE_PARENT
, 0),
450 DIV(0, "div_pwm", "mout_pwm", DIV_PERIC3
, 0, 4),
452 DIV(0, "div_audio1", "mout_audio1", DIV_PERIC4
, 0, 4),
453 DIV(0, "div_pcm1", "sclk_audio1", DIV_PERIC4
, 4, 8),
454 DIV(0, "div_audio2", "mout_audio2", DIV_PERIC4
, 16, 4),
455 DIV(0, "div_pcm2", "sclk_audio2", DIV_PERIC4
, 20, 8),
457 DIV(CLK_DIV_I2S1
, "div_i2s1", "sclk_audio1", DIV_PERIC5
, 0, 6),
458 DIV(CLK_DIV_I2S2
, "div_i2s2", "sclk_audio2", DIV_PERIC5
, 8, 6),
461 static struct samsung_gate_clock exynos5250_gate_clks
[] __initdata
= {
463 * NOTE: Following table is sorted by (clock domain, register address,
464 * bitfield shift) triplet in ascending order. When adding new entries,
465 * please make sure that the order is kept, to avoid merge conflicts
466 * and make further work with defined data easier.
472 GATE(CLK_MDMA0
, "mdma0", "div_aclk266", GATE_IP_ACP
, 1, 0, 0),
473 GATE(CLK_SSS
, "sss", "div_aclk266", GATE_IP_ACP
, 2, 0, 0),
474 GATE(CLK_G2D
, "g2d", "div_aclk200", GATE_IP_ACP
, 3, 0, 0),
475 GATE(CLK_SMMU_MDMA0
, "smmu_mdma0", "div_aclk266", GATE_IP_ACP
, 5, 0, 0),
480 GATE(CLK_SCLK_CAM_BAYER
, "sclk_cam_bayer", "div_cam_bayer",
481 SRC_MASK_GSCL
, 12, CLK_SET_RATE_PARENT
, 0),
482 GATE(CLK_SCLK_CAM0
, "sclk_cam0", "div_cam0",
483 SRC_MASK_GSCL
, 16, CLK_SET_RATE_PARENT
, 0),
484 GATE(CLK_SCLK_CAM1
, "sclk_cam1", "div_cam1",
485 SRC_MASK_GSCL
, 20, CLK_SET_RATE_PARENT
, 0),
486 GATE(CLK_SCLK_GSCL_WA
, "sclk_gscl_wa", "div_gscl_wa",
487 SRC_MASK_GSCL
, 24, CLK_SET_RATE_PARENT
, 0),
488 GATE(CLK_SCLK_GSCL_WB
, "sclk_gscl_wb", "div_gscl_wb",
489 SRC_MASK_GSCL
, 28, CLK_SET_RATE_PARENT
, 0),
491 GATE(CLK_SCLK_FIMD1
, "sclk_fimd1", "div_fimd1",
492 SRC_MASK_DISP1_0
, 0, CLK_SET_RATE_PARENT
, 0),
493 GATE(CLK_SCLK_MIPI1
, "sclk_mipi1", "div_mipi1",
494 SRC_MASK_DISP1_0
, 12, CLK_SET_RATE_PARENT
, 0),
495 GATE(CLK_SCLK_DP
, "sclk_dp", "div_dp",
496 SRC_MASK_DISP1_0
, 16, CLK_SET_RATE_PARENT
, 0),
497 GATE(CLK_SCLK_HDMI
, "sclk_hdmi", "mout_hdmi",
498 SRC_MASK_DISP1_0
, 20, 0, 0),
500 GATE(CLK_SCLK_AUDIO0
, "sclk_audio0", "div_audio0",
501 SRC_MASK_MAU
, 0, CLK_SET_RATE_PARENT
, 0),
503 GATE(CLK_SCLK_MMC0
, "sclk_mmc0", "div_mmc_pre0",
504 SRC_MASK_FSYS
, 0, CLK_SET_RATE_PARENT
, 0),
505 GATE(CLK_SCLK_MMC1
, "sclk_mmc1", "div_mmc_pre1",
506 SRC_MASK_FSYS
, 4, CLK_SET_RATE_PARENT
, 0),
507 GATE(CLK_SCLK_MMC2
, "sclk_mmc2", "div_mmc_pre2",
508 SRC_MASK_FSYS
, 8, CLK_SET_RATE_PARENT
, 0),
509 GATE(CLK_SCLK_MMC3
, "sclk_mmc3", "div_mmc_pre3",
510 SRC_MASK_FSYS
, 12, CLK_SET_RATE_PARENT
, 0),
511 GATE(CLK_SCLK_SATA
, "sclk_sata", "div_sata",
512 SRC_MASK_FSYS
, 24, CLK_SET_RATE_PARENT
, 0),
513 GATE(CLK_SCLK_USB3
, "sclk_usb3", "div_usb3",
514 SRC_MASK_FSYS
, 28, CLK_SET_RATE_PARENT
, 0),
516 GATE(CLK_SCLK_JPEG
, "sclk_jpeg", "div_jpeg",
517 SRC_MASK_GEN
, 0, CLK_SET_RATE_PARENT
, 0),
519 GATE(CLK_SCLK_UART0
, "sclk_uart0", "div_uart0",
520 SRC_MASK_PERIC0
, 0, CLK_SET_RATE_PARENT
, 0),
521 GATE(CLK_SCLK_UART1
, "sclk_uart1", "div_uart1",
522 SRC_MASK_PERIC0
, 4, CLK_SET_RATE_PARENT
, 0),
523 GATE(CLK_SCLK_UART2
, "sclk_uart2", "div_uart2",
524 SRC_MASK_PERIC0
, 8, CLK_SET_RATE_PARENT
, 0),
525 GATE(CLK_SCLK_UART3
, "sclk_uart3", "div_uart3",
526 SRC_MASK_PERIC0
, 12, CLK_SET_RATE_PARENT
, 0),
527 GATE(CLK_SCLK_PWM
, "sclk_pwm", "div_pwm",
528 SRC_MASK_PERIC0
, 24, CLK_SET_RATE_PARENT
, 0),
530 GATE(CLK_SCLK_AUDIO1
, "sclk_audio1", "div_audio1",
531 SRC_MASK_PERIC1
, 0, CLK_SET_RATE_PARENT
, 0),
532 GATE(CLK_SCLK_AUDIO2
, "sclk_audio2", "div_audio2",
533 SRC_MASK_PERIC1
, 4, CLK_SET_RATE_PARENT
, 0),
534 GATE(CLK_SCLK_SPDIF
, "sclk_spdif", "mout_spdif",
535 SRC_MASK_PERIC1
, 4, 0, 0),
536 GATE(CLK_SCLK_SPI0
, "sclk_spi0", "div_spi_pre0",
537 SRC_MASK_PERIC1
, 16, CLK_SET_RATE_PARENT
, 0),
538 GATE(CLK_SCLK_SPI1
, "sclk_spi1", "div_spi_pre1",
539 SRC_MASK_PERIC1
, 20, CLK_SET_RATE_PARENT
, 0),
540 GATE(CLK_SCLK_SPI2
, "sclk_spi2", "div_spi_pre2",
541 SRC_MASK_PERIC1
, 24, CLK_SET_RATE_PARENT
, 0),
543 GATE(CLK_GSCL0
, "gscl0", "mout_aclk266_gscl_sub", GATE_IP_GSCL
, 0, 0,
545 GATE(CLK_GSCL1
, "gscl1", "mout_aclk266_gscl_sub", GATE_IP_GSCL
, 1, 0,
547 GATE(CLK_GSCL2
, "gscl2", "mout_aclk266_gscl_sub", GATE_IP_GSCL
, 2, 0,
549 GATE(CLK_GSCL3
, "gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL
, 3, 0,
551 GATE(CLK_GSCL_WA
, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL
, 5, 0, 0),
552 GATE(CLK_GSCL_WB
, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL
, 6, 0, 0),
553 GATE(CLK_SMMU_GSCL0
, "smmu_gscl0", "mout_aclk266_gscl_sub",
554 GATE_IP_GSCL
, 7, 0, 0),
555 GATE(CLK_SMMU_GSCL1
, "smmu_gscl1", "mout_aclk266_gscl_sub",
556 GATE_IP_GSCL
, 8, 0, 0),
557 GATE(CLK_SMMU_GSCL2
, "smmu_gscl2", "mout_aclk266_gscl_sub",
558 GATE_IP_GSCL
, 9, 0, 0),
559 GATE(CLK_SMMU_GSCL3
, "smmu_gscl3", "mout_aclk266_gscl_sub",
560 GATE_IP_GSCL
, 10, 0, 0),
562 GATE(CLK_FIMD1
, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1
, 0, 0,
564 GATE(CLK_MIE1
, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1
, 1, 0,
566 GATE(CLK_DSIM0
, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1
, 3, 0,
568 GATE(CLK_DP
, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1
, 4, 0, 0),
569 GATE(CLK_MIXER
, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1
, 5, 0,
571 GATE(CLK_HDMI
, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1
, 6, 0,
574 GATE(CLK_MFC
, "mfc", "mout_aclk333_sub", GATE_IP_MFC
, 0, 0, 0),
575 GATE(CLK_SMMU_MFCR
, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC
, 1, 0,
577 GATE(CLK_SMMU_MFCL
, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC
, 2, 0,
579 GATE(CLK_G3D
, "g3d", "div_aclk400_g3d", GATE_IP_G3D
, 0,
580 CLK_SET_RATE_PARENT
, 0),
581 GATE(CLK_ROTATOR
, "rotator", "div_aclk266", GATE_IP_GEN
, 1, 0, 0),
582 GATE(CLK_JPEG
, "jpeg", "div_aclk166", GATE_IP_GEN
, 2, 0, 0),
583 GATE(CLK_MDMA1
, "mdma1", "div_aclk266", GATE_IP_GEN
, 4, 0, 0),
584 GATE(CLK_SMMU_ROTATOR
, "smmu_rotator", "div_aclk266", GATE_IP_GEN
, 6, 0,
586 GATE(CLK_SMMU_JPEG
, "smmu_jpeg", "div_aclk166", GATE_IP_GEN
, 7, 0, 0),
587 GATE(CLK_SMMU_MDMA1
, "smmu_mdma1", "div_aclk266", GATE_IP_GEN
, 9, 0, 0),
589 GATE(CLK_PDMA0
, "pdma0", "div_aclk200", GATE_IP_FSYS
, 1, 0, 0),
590 GATE(CLK_PDMA1
, "pdma1", "div_aclk200", GATE_IP_FSYS
, 2, 0, 0),
591 GATE(CLK_SATA
, "sata", "div_aclk200", GATE_IP_FSYS
, 6, 0, 0),
592 GATE(CLK_USBOTG
, "usbotg", "div_aclk200", GATE_IP_FSYS
, 7, 0, 0),
593 GATE(CLK_MIPI_HSI
, "mipi_hsi", "div_aclk200", GATE_IP_FSYS
, 8, 0, 0),
594 GATE(CLK_SDMMC0
, "sdmmc0", "div_aclk200", GATE_IP_FSYS
, 12, 0, 0),
595 GATE(CLK_SDMMC1
, "sdmmc1", "div_aclk200", GATE_IP_FSYS
, 13, 0, 0),
596 GATE(CLK_SDMMC2
, "sdmmc2", "div_aclk200", GATE_IP_FSYS
, 14, 0, 0),
597 GATE(CLK_SDMMC3
, "sdmmc3", "div_aclk200", GATE_IP_FSYS
, 15, 0, 0),
598 GATE(CLK_SROMC
, "sromc", "div_aclk200", GATE_IP_FSYS
, 17, 0, 0),
599 GATE(CLK_USB2
, "usb2", "div_aclk200", GATE_IP_FSYS
, 18, 0, 0),
600 GATE(CLK_USB3
, "usb3", "div_aclk200", GATE_IP_FSYS
, 19, 0, 0),
601 GATE(CLK_SATA_PHYCTRL
, "sata_phyctrl", "div_aclk200",
602 GATE_IP_FSYS
, 24, 0, 0),
603 GATE(CLK_SATA_PHYI2C
, "sata_phyi2c", "div_aclk200", GATE_IP_FSYS
, 25, 0,
606 GATE(CLK_UART0
, "uart0", "div_aclk66", GATE_IP_PERIC
, 0, 0, 0),
607 GATE(CLK_UART1
, "uart1", "div_aclk66", GATE_IP_PERIC
, 1, 0, 0),
608 GATE(CLK_UART2
, "uart2", "div_aclk66", GATE_IP_PERIC
, 2, 0, 0),
609 GATE(CLK_UART3
, "uart3", "div_aclk66", GATE_IP_PERIC
, 3, 0, 0),
610 GATE(CLK_UART4
, "uart4", "div_aclk66", GATE_IP_PERIC
, 4, 0, 0),
611 GATE(CLK_I2C0
, "i2c0", "div_aclk66", GATE_IP_PERIC
, 6, 0, 0),
612 GATE(CLK_I2C1
, "i2c1", "div_aclk66", GATE_IP_PERIC
, 7, 0, 0),
613 GATE(CLK_I2C2
, "i2c2", "div_aclk66", GATE_IP_PERIC
, 8, 0, 0),
614 GATE(CLK_I2C3
, "i2c3", "div_aclk66", GATE_IP_PERIC
, 9, 0, 0),
615 GATE(CLK_I2C4
, "i2c4", "div_aclk66", GATE_IP_PERIC
, 10, 0, 0),
616 GATE(CLK_I2C5
, "i2c5", "div_aclk66", GATE_IP_PERIC
, 11, 0, 0),
617 GATE(CLK_I2C6
, "i2c6", "div_aclk66", GATE_IP_PERIC
, 12, 0, 0),
618 GATE(CLK_I2C7
, "i2c7", "div_aclk66", GATE_IP_PERIC
, 13, 0, 0),
619 GATE(CLK_I2C_HDMI
, "i2c_hdmi", "div_aclk66", GATE_IP_PERIC
, 14, 0, 0),
620 GATE(CLK_ADC
, "adc", "div_aclk66", GATE_IP_PERIC
, 15, 0, 0),
621 GATE(CLK_SPI0
, "spi0", "div_aclk66", GATE_IP_PERIC
, 16, 0, 0),
622 GATE(CLK_SPI1
, "spi1", "div_aclk66", GATE_IP_PERIC
, 17, 0, 0),
623 GATE(CLK_SPI2
, "spi2", "div_aclk66", GATE_IP_PERIC
, 18, 0, 0),
624 GATE(CLK_I2S1
, "i2s1", "div_aclk66", GATE_IP_PERIC
, 20, 0, 0),
625 GATE(CLK_I2S2
, "i2s2", "div_aclk66", GATE_IP_PERIC
, 21, 0, 0),
626 GATE(CLK_PCM1
, "pcm1", "div_aclk66", GATE_IP_PERIC
, 22, 0, 0),
627 GATE(CLK_PCM2
, "pcm2", "div_aclk66", GATE_IP_PERIC
, 23, 0, 0),
628 GATE(CLK_PWM
, "pwm", "div_aclk66", GATE_IP_PERIC
, 24, 0, 0),
629 GATE(CLK_SPDIF
, "spdif", "div_aclk66", GATE_IP_PERIC
, 26, 0, 0),
630 GATE(CLK_AC97
, "ac97", "div_aclk66", GATE_IP_PERIC
, 27, 0, 0),
631 GATE(CLK_HSI2C0
, "hsi2c0", "div_aclk66", GATE_IP_PERIC
, 28, 0, 0),
632 GATE(CLK_HSI2C1
, "hsi2c1", "div_aclk66", GATE_IP_PERIC
, 29, 0, 0),
633 GATE(CLK_HSI2C2
, "hsi2c2", "div_aclk66", GATE_IP_PERIC
, 30, 0, 0),
634 GATE(CLK_HSI2C3
, "hsi2c3", "div_aclk66", GATE_IP_PERIC
, 31, 0, 0),
636 GATE(CLK_CHIPID
, "chipid", "div_aclk66", GATE_IP_PERIS
, 0, 0, 0),
637 GATE(CLK_SYSREG
, "sysreg", "div_aclk66",
638 GATE_IP_PERIS
, 1, CLK_IGNORE_UNUSED
, 0),
639 GATE(CLK_PMU
, "pmu", "div_aclk66", GATE_IP_PERIS
, 2, CLK_IGNORE_UNUSED
,
641 GATE(CLK_CMU_TOP
, "cmu_top", "div_aclk66",
642 GATE_IP_PERIS
, 3, CLK_IGNORE_UNUSED
, 0),
643 GATE(CLK_CMU_CORE
, "cmu_core", "div_aclk66",
644 GATE_IP_PERIS
, 4, CLK_IGNORE_UNUSED
, 0),
645 GATE(CLK_CMU_MEM
, "cmu_mem", "div_aclk66",
646 GATE_IP_PERIS
, 5, CLK_IGNORE_UNUSED
, 0),
647 GATE(CLK_TZPC0
, "tzpc0", "div_aclk66", GATE_IP_PERIS
, 6, 0, 0),
648 GATE(CLK_TZPC1
, "tzpc1", "div_aclk66", GATE_IP_PERIS
, 7, 0, 0),
649 GATE(CLK_TZPC2
, "tzpc2", "div_aclk66", GATE_IP_PERIS
, 8, 0, 0),
650 GATE(CLK_TZPC3
, "tzpc3", "div_aclk66", GATE_IP_PERIS
, 9, 0, 0),
651 GATE(CLK_TZPC4
, "tzpc4", "div_aclk66", GATE_IP_PERIS
, 10, 0, 0),
652 GATE(CLK_TZPC5
, "tzpc5", "div_aclk66", GATE_IP_PERIS
, 11, 0, 0),
653 GATE(CLK_TZPC6
, "tzpc6", "div_aclk66", GATE_IP_PERIS
, 12, 0, 0),
654 GATE(CLK_TZPC7
, "tzpc7", "div_aclk66", GATE_IP_PERIS
, 13, 0, 0),
655 GATE(CLK_TZPC8
, "tzpc8", "div_aclk66", GATE_IP_PERIS
, 14, 0, 0),
656 GATE(CLK_TZPC9
, "tzpc9", "div_aclk66", GATE_IP_PERIS
, 15, 0, 0),
657 GATE(CLK_HDMI_CEC
, "hdmi_cec", "div_aclk66", GATE_IP_PERIS
, 16, 0, 0),
658 GATE(CLK_MCT
, "mct", "div_aclk66", GATE_IP_PERIS
, 18, 0, 0),
659 GATE(CLK_WDT
, "wdt", "div_aclk66", GATE_IP_PERIS
, 19, 0, 0),
660 GATE(CLK_RTC
, "rtc", "div_aclk66", GATE_IP_PERIS
, 20, 0, 0),
661 GATE(CLK_TMU
, "tmu", "div_aclk66", GATE_IP_PERIS
, 21, 0, 0),
662 GATE(CLK_SMMU_TV
, "smmu_tv", "mout_aclk200_disp1_sub",
663 GATE_IP_DISP1
, 9, 0, 0),
664 GATE(CLK_SMMU_FIMD1
, "smmu_fimd1", "mout_aclk200_disp1_sub",
665 GATE_IP_DISP1
, 8, 0, 0),
666 GATE(CLK_SMMU_2D
, "smmu_2d", "div_aclk200", GATE_IP_ACP
, 7, 0, 0),
667 GATE(CLK_SMMU_FIMC_ISP
, "smmu_fimc_isp", "mout_aclk_266_isp_sub",
668 GATE_IP_ISP0
, 8, 0, 0),
669 GATE(CLK_SMMU_FIMC_DRC
, "smmu_fimc_drc", "mout_aclk_266_isp_sub",
670 GATE_IP_ISP0
, 9, 0, 0),
671 GATE(CLK_SMMU_FIMC_FD
, "smmu_fimc_fd", "mout_aclk_266_isp_sub",
672 GATE_IP_ISP0
, 10, 0, 0),
673 GATE(CLK_SMMU_FIMC_SCC
, "smmu_fimc_scc", "mout_aclk_266_isp_sub",
674 GATE_IP_ISP0
, 11, 0, 0),
675 GATE(CLK_SMMU_FIMC_SCP
, "smmu_fimc_scp", "mout_aclk_266_isp_sub",
676 GATE_IP_ISP0
, 12, 0, 0),
677 GATE(CLK_SMMU_FIMC_MCU
, "smmu_fimc_mcu", "mout_aclk_400_isp_sub",
678 GATE_IP_ISP0
, 13, 0, 0),
679 GATE(CLK_SMMU_FIMC_ODC
, "smmu_fimc_odc", "mout_aclk_266_isp_sub",
680 GATE_IP_ISP1
, 4, 0, 0),
681 GATE(CLK_SMMU_FIMC_DIS0
, "smmu_fimc_dis0", "mout_aclk_266_isp_sub",
682 GATE_IP_ISP1
, 5, 0, 0),
683 GATE(CLK_SMMU_FIMC_DIS1
, "smmu_fimc_dis1", "mout_aclk_266_isp_sub",
684 GATE_IP_ISP1
, 6, 0, 0),
685 GATE(CLK_SMMU_FIMC_3DNR
, "smmu_fimc_3dnr", "mout_aclk_266_isp_sub",
686 GATE_IP_ISP1
, 7, 0, 0),
689 static struct samsung_pll_rate_table vpll_24mhz_tbl
[] __initdata
= {
690 /* sorted in descending order */
691 /* PLL_36XX_RATE(rate, m, p, s, k) */
692 PLL_36XX_RATE(266000000, 266, 3, 3, 0),
693 /* Not in UM, but need for eDP on snow */
694 PLL_36XX_RATE(70500000, 94, 2, 4, 0),
698 static struct samsung_pll_rate_table epll_24mhz_tbl
[] __initdata
= {
699 /* sorted in descending order */
700 /* PLL_36XX_RATE(rate, m, p, s, k) */
701 PLL_36XX_RATE(192000000, 64, 2, 2, 0),
702 PLL_36XX_RATE(180633600, 90, 3, 2, 20762),
703 PLL_36XX_RATE(180000000, 90, 3, 2, 0),
704 PLL_36XX_RATE(73728000, 98, 2, 4, 19923),
705 PLL_36XX_RATE(67737600, 90, 2, 4, 20762),
706 PLL_36XX_RATE(49152000, 98, 3, 4, 19923),
707 PLL_36XX_RATE(45158400, 90, 3, 4, 20762),
708 PLL_36XX_RATE(32768000, 131, 3, 5, 4719),
712 static struct samsung_pll_rate_table apll_24mhz_tbl
[] __initdata
= {
713 /* sorted in descending order */
714 /* PLL_35XX_RATE(rate, m, p, s) */
715 PLL_35XX_RATE(1700000000, 425, 6, 0),
716 PLL_35XX_RATE(1600000000, 200, 3, 0),
717 PLL_35XX_RATE(1500000000, 250, 4, 0),
718 PLL_35XX_RATE(1400000000, 175, 3, 0),
719 PLL_35XX_RATE(1300000000, 325, 6, 0),
720 PLL_35XX_RATE(1200000000, 200, 4, 0),
721 PLL_35XX_RATE(1100000000, 275, 6, 0),
722 PLL_35XX_RATE(1000000000, 125, 3, 0),
723 PLL_35XX_RATE(900000000, 150, 4, 0),
724 PLL_35XX_RATE(800000000, 100, 3, 0),
725 PLL_35XX_RATE(700000000, 175, 3, 1),
726 PLL_35XX_RATE(600000000, 200, 4, 1),
727 PLL_35XX_RATE(500000000, 125, 3, 1),
728 PLL_35XX_RATE(400000000, 100, 3, 1),
729 PLL_35XX_RATE(300000000, 200, 4, 2),
730 PLL_35XX_RATE(200000000, 100, 3, 2),
733 static struct samsung_pll_clock exynos5250_plls
[nr_plls
] __initdata
= {
734 [apll
] = PLL_A(pll_35xx
, CLK_FOUT_APLL
, "fout_apll", "fin_pll",
735 APLL_LOCK
, APLL_CON0
, "fout_apll", NULL
),
736 [mpll
] = PLL_A(pll_35xx
, CLK_FOUT_MPLL
, "fout_mpll", "fin_pll",
737 MPLL_LOCK
, MPLL_CON0
, "fout_mpll", NULL
),
738 [bpll
] = PLL(pll_35xx
, CLK_FOUT_BPLL
, "fout_bpll", "fin_pll", BPLL_LOCK
,
740 [gpll
] = PLL(pll_35xx
, CLK_FOUT_GPLL
, "fout_gpll", "fin_pll", GPLL_LOCK
,
742 [cpll
] = PLL(pll_35xx
, CLK_FOUT_CPLL
, "fout_cpll", "fin_pll", CPLL_LOCK
,
744 [epll
] = PLL(pll_36xx
, CLK_FOUT_EPLL
, "fout_epll", "fin_pll", EPLL_LOCK
,
746 [vpll
] = PLL(pll_36xx
, CLK_FOUT_VPLL
, "fout_vpll", "mout_vpllsrc",
747 VPLL_LOCK
, VPLL_CON0
, NULL
),
750 #define E5250_CPU_DIV0(apll, pclk_dbg, atb, periph, acp, cpud) \
751 ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
752 ((periph) << 12) | ((acp) << 8) | ((cpud) << 4)))
753 #define E5250_CPU_DIV1(hpm, copy) \
754 (((hpm) << 4) | (copy))
756 static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d
[] __initconst
= {
757 { 1700000, E5250_CPU_DIV0(5, 3, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
758 { 1600000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
759 { 1500000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
760 { 1400000, E5250_CPU_DIV0(4, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
761 { 1300000, E5250_CPU_DIV0(3, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
762 { 1200000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
763 { 1100000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
764 { 1000000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
765 { 900000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
766 { 800000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
767 { 700000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
768 { 600000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
769 { 500000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
770 { 400000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
771 { 300000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
772 { 200000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
776 static const struct of_device_id ext_clk_match
[] __initconst
= {
777 { .compatible
= "samsung,clock-xxti", .data
= (void *)0, },
781 /* register exynox5250 clocks */
782 static void __init
exynos5250_clk_init(struct device_node
*np
)
784 struct samsung_clk_provider
*ctx
;
788 reg_base
= of_iomap(np
, 0);
790 panic("%s: failed to map registers\n", __func__
);
792 panic("%s: unable to determine soc\n", __func__
);
795 ctx
= samsung_clk_init(np
, reg_base
, CLK_NR_CLKS
);
797 panic("%s: unable to allocate context.\n", __func__
);
798 samsung_clk_of_register_fixed_ext(ctx
, exynos5250_fixed_rate_ext_clks
,
799 ARRAY_SIZE(exynos5250_fixed_rate_ext_clks
),
801 samsung_clk_register_mux(ctx
, exynos5250_pll_pmux_clks
,
802 ARRAY_SIZE(exynos5250_pll_pmux_clks
));
804 if (_get_rate("fin_pll") == 24 * MHZ
) {
805 exynos5250_plls
[epll
].rate_table
= epll_24mhz_tbl
;
806 exynos5250_plls
[apll
].rate_table
= apll_24mhz_tbl
;
809 if (_get_rate("mout_vpllsrc") == 24 * MHZ
)
810 exynos5250_plls
[vpll
].rate_table
= vpll_24mhz_tbl
;
812 samsung_clk_register_pll(ctx
, exynos5250_plls
,
813 ARRAY_SIZE(exynos5250_plls
),
815 samsung_clk_register_fixed_rate(ctx
, exynos5250_fixed_rate_clks
,
816 ARRAY_SIZE(exynos5250_fixed_rate_clks
));
817 samsung_clk_register_fixed_factor(ctx
, exynos5250_fixed_factor_clks
,
818 ARRAY_SIZE(exynos5250_fixed_factor_clks
));
819 samsung_clk_register_mux(ctx
, exynos5250_mux_clks
,
820 ARRAY_SIZE(exynos5250_mux_clks
));
821 samsung_clk_register_div(ctx
, exynos5250_div_clks
,
822 ARRAY_SIZE(exynos5250_div_clks
));
823 samsung_clk_register_gate(ctx
, exynos5250_gate_clks
,
824 ARRAY_SIZE(exynos5250_gate_clks
));
825 exynos_register_cpu_clock(ctx
, CLK_ARM_CLK
, "armclk",
826 mout_cpu_p
[0], mout_cpu_p
[1], 0x200,
827 exynos5250_armclk_d
, ARRAY_SIZE(exynos5250_armclk_d
),
831 * Enable arm clock down (in idle) and set arm divider
832 * ratios in WFI/WFE state.
834 tmp
= (PWR_CTRL1_CORE2_DOWN_RATIO
| PWR_CTRL1_CORE1_DOWN_RATIO
|
835 PWR_CTRL1_DIV2_DOWN_EN
| PWR_CTRL1_DIV1_DOWN_EN
|
836 PWR_CTRL1_USE_CORE1_WFE
| PWR_CTRL1_USE_CORE0_WFE
|
837 PWR_CTRL1_USE_CORE1_WFI
| PWR_CTRL1_USE_CORE0_WFI
);
838 __raw_writel(tmp
, reg_base
+ PWR_CTRL1
);
841 * Enable arm clock up (on exiting idle). Set arm divider
842 * ratios when not in idle along with the standby duration
845 tmp
= (PWR_CTRL2_DIV2_UP_EN
| PWR_CTRL2_DIV1_UP_EN
|
846 PWR_CTRL2_DUR_STANDBY2_VAL
| PWR_CTRL2_DUR_STANDBY1_VAL
|
847 PWR_CTRL2_CORE2_UP_RATIO
| PWR_CTRL2_CORE1_UP_RATIO
);
848 __raw_writel(tmp
, reg_base
+ PWR_CTRL2
);
850 exynos5250_clk_sleep_init();
852 samsung_clk_of_add_provider(np
, ctx
);
854 pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
855 _get_rate("div_arm2"));
857 CLK_OF_DECLARE(exynos5250_clk
, "samsung,exynos5250-clock", exynos5250_clk_init
);