drivers/clk/samsung/clk-exynos5250.c

   1 /*
   2  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   3  * Copyright (c) 2013 Linaro Ltd.
   4  * Author: Thomas Abraham <thomas.ab@samsung.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Common Clock Framework support for Exynos5250 SoC.
  11 */
  12
  13 #include <linux/clk.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/clk-provider.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18
  19 #include "clk.h"
  20
  21 #define APLL_LOCK               0x0
  22 #define APLL_CON0               0x100
  23 #define SRC_CPU                 0x200
  24 #define DIV_CPU0                0x500
  25 #define MPLL_LOCK               0x4000
  26 #define MPLL_CON0               0x4100
  27 #define SRC_CORE1               0x4204
  28 #define GATE_IP_ACP             0x8800
  29 #define CPLL_LOCK               0x10020
  30 #define EPLL_LOCK               0x10030
  31 #define VPLL_LOCK               0x10040
  32 #define GPLL_LOCK               0x10050
  33 #define CPLL_CON0               0x10120
  34 #define EPLL_CON0               0x10130
  35 #define VPLL_CON0               0x10140
  36 #define GPLL_CON0               0x10150
  37 #define SRC_TOP0                0x10210
  38 #define SRC_TOP2                0x10218
  39 #define SRC_TOP3                0x1021c
  40 #define SRC_GSCL                0x10220
  41 #define SRC_DISP1_0             0x1022c
  42 #define SRC_MAU                 0x10240
  43 #define SRC_FSYS                0x10244
  44 #define SRC_GEN                 0x10248
  45 #define SRC_PERIC0              0x10250
  46 #define SRC_PERIC1              0x10254
  47 #define SRC_MASK_GSCL           0x10320
  48 #define SRC_MASK_DISP1_0        0x1032c
  49 #define SRC_MASK_MAU            0x10334
  50 #define SRC_MASK_FSYS           0x10340
  51 #define SRC_MASK_GEN            0x10344
  52 #define SRC_MASK_PERIC0         0x10350
  53 #define SRC_MASK_PERIC1         0x10354
  54 #define DIV_TOP0                0x10510
  55 #define DIV_TOP1                0x10514
  56 #define DIV_GSCL                0x10520
  57 #define DIV_DISP1_0             0x1052c
  58 #define DIV_GEN                 0x1053c
  59 #define DIV_MAU                 0x10544
  60 #define DIV_FSYS0               0x10548
  61 #define DIV_FSYS1               0x1054c
  62 #define DIV_FSYS2               0x10550
  63 #define DIV_PERIC0              0x10558
  64 #define DIV_PERIC1              0x1055c
  65 #define DIV_PERIC2              0x10560
  66 #define DIV_PERIC3              0x10564
  67 #define DIV_PERIC4              0x10568
  68 #define DIV_PERIC5              0x1056c
  69 #define GATE_IP_GSCL            0x10920
  70 #define GATE_IP_DISP1           0x10928
  71 #define GATE_IP_MFC             0x1092c
  72 #define GATE_IP_GEN             0x10934
  73 #define GATE_IP_FSYS            0x10944
  74 #define GATE_IP_PERIC           0x10950
  75 #define GATE_IP_PERIS           0x10960
  76 #define BPLL_LOCK               0x20010
  77 #define BPLL_CON0               0x20110
  78 #define SRC_CDREX               0x20200
  79 #define PLL_DIV2_SEL            0x20a24
  80
  81 /* list of PLLs to be registered */
  82 enum exynos5250_plls {
  83         apll, mpll, cpll, epll, vpll, gpll, bpll,
  84         nr_plls                 /* number of PLLs */
  85 };
  86
  87 /*
  88  * Let each supported clock get a unique id. This id is used to lookup the clock
  89  * for device tree based platforms. The clocks are categorized into three
  90  * sections: core, sclk gate and bus interface gate clocks.
  91  *
  92  * When adding a new clock to this list, it is advised to choose a clock
  93  * category and add it to the end of that category. That is because the the
  94  * device tree source file is referring to these ids and any change in the
  95  * sequence number of existing clocks will require corresponding change in the
  96  * device tree files. This limitation would go away when pre-processor support
  97  * for dtc would be available.
  98  */
  99 enum exynos5250_clks {
 100         none,
 101
 102         /* core clocks */
 103         fin_pll, fout_apll, fout_mpll, fout_bpll, fout_gpll, fout_cpll,
 104         fout_epll, fout_vpll,
 105
 106         /* gate for special clocks (sclk) */
 107         sclk_cam_bayer = 128, sclk_cam0, sclk_cam1, sclk_gscl_wa, sclk_gscl_wb,
 108         sclk_fimd1, sclk_mipi1, sclk_dp, sclk_hdmi, sclk_pixel, sclk_audio0,
 109         sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
 110         sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
 111         sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
 112         div_i2s1, div_i2s2, sclk_hdmiphy,
 113
 114         /* gate clocks */
 115         gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
 116         smmu_gscl1, smmu_gscl2, smmu_gscl3, mfc, smmu_mfcl, smmu_mfcr, rotator,
 117         jpeg, mdma1, smmu_rotator, smmu_jpeg, smmu_mdma1, pdma0, pdma1, sata,
 118         usbotg, mipi_hsi, sdmmc0, sdmmc1, sdmmc2, sdmmc3, sromc, usb2, usb3,
 119         sata_phyctrl, sata_phyi2c, uart0, uart1, uart2, uart3, uart4, i2c0,
 120         i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, adc, spi0, spi1,
 121         spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
 122         hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
 123         tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
 124         wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d, mdma0,
 125         smmu_mdma0,
 126
 127         /* mux clocks */
 128         mout_hdmi = 1024,
 129
 130         nr_clks,
 131 };
 132
 133 /*
 134  * list of controller registers to be saved and restored during a
 135  * suspend/resume cycle.
 136  */
 137 static unsigned long exynos5250_clk_regs[] __initdata = {
 138         SRC_CPU,
 139         DIV_CPU0,
 140         SRC_CORE1,
 141         SRC_TOP0,
 142         SRC_TOP2,
 143         SRC_TOP3,
 144         SRC_GSCL,
 145         SRC_DISP1_0,
 146         SRC_MAU,
 147         SRC_FSYS,
 148         SRC_GEN,
 149         SRC_PERIC0,
 150         SRC_PERIC1,
 151         SRC_MASK_GSCL,
 152         SRC_MASK_DISP1_0,
 153         SRC_MASK_MAU,
 154         SRC_MASK_FSYS,
 155         SRC_MASK_GEN,
 156         SRC_MASK_PERIC0,
 157         SRC_MASK_PERIC1,
 158         DIV_TOP0,
 159         DIV_TOP1,
 160         DIV_GSCL,
 161         DIV_DISP1_0,
 162         DIV_GEN,
 163         DIV_MAU,
 164         DIV_FSYS0,
 165         DIV_FSYS1,
 166         DIV_FSYS2,
 167         DIV_PERIC0,
 168         DIV_PERIC1,
 169         DIV_PERIC2,
 170         DIV_PERIC3,
 171         DIV_PERIC4,
 172         DIV_PERIC5,
 173         GATE_IP_GSCL,
 174         GATE_IP_MFC,
 175         GATE_IP_GEN,
 176         GATE_IP_FSYS,
 177         GATE_IP_PERIC,
 178         GATE_IP_PERIS,
 179         SRC_CDREX,
 180         PLL_DIV2_SEL,
 181         GATE_IP_DISP1,
 182         GATE_IP_ACP,
 183 };
 184
 185 /* list of all parent clock list */
 186 PNAME(mout_apll_p)      = { "fin_pll", "fout_apll", };
 187 PNAME(mout_cpu_p)       = { "mout_apll", "mout_mpll", };
 188 PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" };
 189 PNAME(mout_mpll_p)      = { "fin_pll", "mout_mpll_fout" };
 190 PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" };
 191 PNAME(mout_bpll_p)      = { "fin_pll", "mout_bpll_fout" };
 192 PNAME(mout_vpllsrc_p)   = { "fin_pll", "sclk_hdmi27m" };
 193 PNAME(mout_vpll_p)      = { "mout_vpllsrc", "fout_vpll" };
 194 PNAME(mout_cpll_p)      = { "fin_pll", "fout_cpll" };
 195 PNAME(mout_epll_p)      = { "fin_pll", "fout_epll" };
 196 PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" };
 197 PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" };
 198 PNAME(mout_aclk166_p)   = { "mout_cpll", "mout_mpll_user" };
 199 PNAME(mout_aclk200_p)   = { "mout_mpll_user", "mout_bpll_user" };
 200 PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" };
 201 PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" };
 202 PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" };
 203 PNAME(mout_hdmi_p)      = { "div_hdmi_pixel", "sclk_hdmiphy" };
 204 PNAME(mout_usb3_p)      = { "mout_mpll_user", "mout_cpll" };
 205 PNAME(mout_group1_p)    = { "fin_pll", "fin_pll", "sclk_hdmi27m",
 206                                 "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy",
 207                                 "mout_mpll_user", "mout_epll", "mout_vpll",
 208                                 "mout_cpll", "none", "none",
 209                                 "none", "none", "none",
 210                                 "none" };
 211 PNAME(mout_audio0_p)    = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
 212                                 "sclk_uhostphy", "fin_pll",
 213                                 "mout_mpll_user", "mout_epll", "mout_vpll",
 214                                 "mout_cpll", "none", "none",
 215                                 "none", "none", "none",
 216                                 "none" };
 217 PNAME(mout_audio1_p)    = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
 218                                 "sclk_uhostphy", "fin_pll",
 219                                 "mout_mpll_user", "mout_epll", "mout_vpll",
 220                                 "mout_cpll", "none", "none",
 221                                 "none", "none", "none",
 222                                 "none" };
 223 PNAME(mout_audio2_p)    = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
 224                                 "sclk_uhostphy", "fin_pll",
 225                                 "mout_mpll_user", "mout_epll", "mout_vpll",
 226                                 "mout_cpll", "none", "none",
 227                                 "none", "none", "none",
 228                                 "none" };
 229 PNAME(mout_spdif_p)     = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
 230                                 "spdif_extclk" };
 231
 232 /* fixed rate clocks generated outside the soc */
 233 static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
 234         FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0),
 235 };
 236
 237 /* fixed rate clocks generated inside the soc */
 238 static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = {
 239         FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
 240         FRATE(none, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000),
 241         FRATE(none, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000),
 242         FRATE(none, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000),
 243 };
 244
 245 static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {
 246         FFACTOR(none, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
 247         FFACTOR(none, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
 248 };
 249
 250 static struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = {
 251         MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
 252 };
 253
 254 static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
 255         /*
 256          * NOTE: Following table is sorted by (clock domain, register address,
 257          * bitfield shift) triplet in ascending order. When adding new entries,
 258          * please make sure that the order is kept, to avoid merge conflicts
 259          * and make further work with defined data easier.
 260          */
 261
 262         /*
 263          * CMU_CPU
 264          */
 265         MUX_FA(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
 266                                         CLK_SET_RATE_PARENT, 0, "mout_apll"),
 267         MUX_A(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
 268
 269         /*
 270          * CMU_CORE
 271          */
 272         MUX_A(none, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),
 273
 274         /*
 275          * CMU_TOP
 276          */
 277         MUX(none, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
 278         MUX(none, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
 279         MUX(none, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
 280
 281         MUX(none, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
 282         MUX(none, "mout_epll", mout_epll_p, SRC_TOP2, 12, 1),
 283         MUX(none, "mout_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
 284         MUX(none, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
 285         MUX(none, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
 286
 287         MUX(none, "mout_aclk200_disp1_sub", mout_aclk200_sub_p, SRC_TOP3, 4, 1),
 288         MUX(none, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1),
 289         MUX(none, "mout_aclk333_sub", mout_aclk333_sub_p, SRC_TOP3, 24, 1),
 290
 291         MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
 292         MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
 293         MUX(none, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
 294         MUX(none, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4),
 295         MUX(none, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4),
 296
 297         MUX(none, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
 298         MUX(none, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
 299         MUX(none, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
 300         MUX(mout_hdmi, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
 301
 302         MUX(none, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
 303
 304         MUX(none, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
 305         MUX(none, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
 306         MUX(none, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4),
 307         MUX(none, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4),
 308         MUX(none, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1),
 309         MUX(none, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1),
 310
 311         MUX(none, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4),
 312
 313         MUX(none, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4),
 314         MUX(none, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4),
 315         MUX(none, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4),
 316         MUX(none, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4),
 317         MUX(none, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4),
 318
 319         MUX(none, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4),
 320         MUX(none, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4),
 321         MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2),
 322         MUX(none, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4),
 323         MUX(none, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4),
 324         MUX(none, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
 325
 326         /*
 327          * CMU_CDREX
 328          */
 329         MUX(none, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
 330
 331         MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
 332         MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
 333 };
 334
 335 static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
 336         /*
 337          * NOTE: Following table is sorted by (clock domain, register address,
 338          * bitfield shift) triplet in ascending order. When adding new entries,
 339          * please make sure that the order is kept, to avoid merge conflicts
 340          * and make further work with defined data easier.
 341          */
 342
 343         /*
 344          * CMU_CPU
 345          */
 346         DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
 347         DIV(none, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
 348         DIV_A(none, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"),
 349
 350         /*
 351          * CMU_TOP
 352          */
 353         DIV(none, "div_aclk66", "div_aclk66_pre", DIV_TOP0, 0, 3),
 354         DIV(none, "div_aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
 355         DIV(none, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
 356         DIV(none, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3),
 357         DIV(none, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
 358
 359         DIV(none, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3),
 360
 361         DIV(none, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
 362         DIV(none, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
 363         DIV(none, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
 364         DIV(none, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4),
 365         DIV(none, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4),
 366
 367         DIV(none, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4),
 368         DIV(none, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4),
 369         DIV_F(none, "div_mipi1_pre", "div_mipi1",
 370                         DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
 371         DIV(none, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
 372         DIV(sclk_pixel, "div_hdmi_pixel", "mout_vpll", DIV_DISP1_0, 28, 4),
 373
 374         DIV(none, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
 375
 376         DIV(none, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
 377         DIV(none, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
 378
 379         DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
 380         DIV(none, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
 381
 382         DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
 383         DIV_F(none, "div_mmc_pre0", "div_mmc0",
 384                         DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
 385         DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
 386         DIV_F(none, "div_mmc_pre1", "div_mmc1",
 387                         DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
 388
 389         DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
 390         DIV_F(none, "div_mmc_pre2", "div_mmc2",
 391                         DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
 392         DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
 393         DIV_F(none, "div_mmc_pre3", "div_mmc3",
 394                         DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
 395
 396         DIV(none, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
 397         DIV(none, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
 398         DIV(none, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
 399         DIV(none, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
 400
 401         DIV(none, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4),
 402         DIV_F(none, "div_spi_pre0", "div_spi0",
 403                         DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
 404         DIV(none, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4),
 405         DIV_F(none, "div_spi_pre1", "div_spi1",
 406                         DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
 407
 408         DIV(none, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4),
 409         DIV_F(none, "div_spi_pre2", "div_spi2",
 410                         DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
 411
 412         DIV(none, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
 413
 414         DIV(none, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4),
 415         DIV(none, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
 416         DIV(none, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
 417         DIV(none, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
 418
 419         DIV(div_i2s1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
 420         DIV(div_i2s2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
 421 };
 422
 423 static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
 424         /*
 425          * NOTE: Following table is sorted by (clock domain, register address,
 426          * bitfield shift) triplet in ascending order. When adding new entries,
 427          * please make sure that the order is kept, to avoid merge conflicts
 428          * and make further work with defined data easier.
 429          */
 430
 431         /*
 432          * CMU_ACP
 433          */
 434         GATE(mdma0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0),
 435         GATE(g2d, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0),
 436         GATE(smmu_mdma0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0),
 437
 438         /*
 439          * CMU_TOP
 440          */
 441         GATE(sclk_cam_bayer, "sclk_cam_bayer", "div_cam_bayer",
 442                         SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
 443         GATE(sclk_cam0, "sclk_cam0", "div_cam0",
 444                         SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
 445         GATE(sclk_cam1, "sclk_cam1", "div_cam1",
 446                         SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
 447         GATE(sclk_gscl_wa, "sclk_gscl_wa", "div_gscl_wa",
 448                         SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
 449         GATE(sclk_gscl_wb, "sclk_gscl_wb", "div_gscl_wb",
 450                         SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
 451
 452         GATE(sclk_fimd1, "sclk_fimd1", "div_fimd1",
 453                         SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
 454         GATE(sclk_mipi1, "sclk_mipi1", "div_mipi1",
 455                         SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
 456         GATE(sclk_dp, "sclk_dp", "div_dp",
 457                         SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
 458         GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi",
 459                         SRC_MASK_DISP1_0, 20, 0, 0),
 460
 461         GATE(sclk_audio0, "sclk_audio0", "div_audio0",
 462                         SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
 463
 464         GATE(sclk_mmc0, "sclk_mmc0", "div_mmc_pre0",
 465                         SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
 466         GATE(sclk_mmc1, "sclk_mmc1", "div_mmc_pre1",
 467                         SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
 468         GATE(sclk_mmc2, "sclk_mmc2", "div_mmc_pre2",
 469                         SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
 470         GATE(sclk_mmc3, "sclk_mmc3", "div_mmc_pre3",
 471                         SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
 472         GATE(sclk_sata, "sclk_sata", "div_sata",
 473                         SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
 474         GATE(sclk_usb3, "sclk_usb3", "div_usb3",
 475                         SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
 476
 477         GATE(sclk_jpeg, "sclk_jpeg", "div_jpeg",
 478                         SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
 479
 480         GATE(sclk_uart0, "sclk_uart0", "div_uart0",
 481                         SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
 482         GATE(sclk_uart1, "sclk_uart1", "div_uart1",
 483                         SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
 484         GATE(sclk_uart2, "sclk_uart2", "div_uart2",
 485                         SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
 486         GATE(sclk_uart3, "sclk_uart3", "div_uart3",
 487                         SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
 488         GATE(sclk_pwm, "sclk_pwm", "div_pwm",
 489                         SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
 490
 491         GATE(sclk_audio1, "sclk_audio1", "div_audio1",
 492                         SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
 493         GATE(sclk_audio2, "sclk_audio2", "div_audio2",
 494                         SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
 495         GATE(sclk_spdif, "sclk_spdif", "mout_spdif",
 496                         SRC_MASK_PERIC1, 4, 0, 0),
 497         GATE(sclk_spi0, "sclk_spi0", "div_spi_pre0",
 498                         SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
 499         GATE(sclk_spi1, "sclk_spi1", "div_spi_pre1",
 500                         SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
 501         GATE(sclk_spi2, "sclk_spi2", "div_spi_pre2",
 502                         SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
 503
 504         GATE(gscl0, "gscl0", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 0, 0, 0),
 505         GATE(gscl1, "gscl1", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 1, 0, 0),
 506         GATE(gscl2, "gscl2", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 2, 0, 0),
 507         GATE(gscl3, "gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 3, 0, 0),
 508         GATE(gscl_wa, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0),
 509         GATE(gscl_wb, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
 510         GATE(smmu_gscl0, "smmu_gscl0", "mout_aclk266_gscl_sub",
 511                         GATE_IP_GSCL, 7, 0, 0),
 512         GATE(smmu_gscl1, "smmu_gscl1", "mout_aclk266_gscl_sub",
 513                         GATE_IP_GSCL, 8, 0, 0),
 514         GATE(smmu_gscl2, "smmu_gscl2", "mout_aclk266_gscl_sub",
 515                         GATE_IP_GSCL, 9, 0, 0),
 516         GATE(smmu_gscl3, "smmu_gscl3", "mout_aclk266_gscl_sub",
 517                         GATE_IP_GSCL, 10, 0, 0),
 518
 519         GATE(fimd1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0, 0),
 520         GATE(mie1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0, 0),
 521         GATE(dsim0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0, 0),
 522         GATE(dp, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0),
 523         GATE(mixer, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0, 0),
 524         GATE(hdmi, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0, 0),
 525
 526         GATE(mfc, "mfc", "mout_aclk333_sub", GATE_IP_MFC, 0, 0, 0),
 527         GATE(smmu_mfcr, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 1, 0, 0),
 528         GATE(smmu_mfcl, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0, 0),
 529
 530         GATE(rotator, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0),
 531         GATE(jpeg, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0),
 532         GATE(mdma1, "mdma1", "div_aclk266", GATE_IP_GEN, 4, 0, 0),
 533         GATE(smmu_rotator, "smmu_rotator", "div_aclk266", GATE_IP_GEN, 6, 0, 0),
 534         GATE(smmu_jpeg, "smmu_jpeg", "div_aclk166", GATE_IP_GEN, 7, 0, 0),
 535         GATE(smmu_mdma1, "smmu_mdma1", "div_aclk266", GATE_IP_GEN, 9, 0, 0),
 536
 537         GATE(pdma0, "pdma0", "div_aclk200", GATE_IP_FSYS, 1, 0, 0),
 538         GATE(pdma1, "pdma1", "div_aclk200", GATE_IP_FSYS, 2, 0, 0),
 539         GATE(sata, "sata", "div_aclk200", GATE_IP_FSYS, 6, 0, 0),
 540         GATE(usbotg, "usbotg", "div_aclk200", GATE_IP_FSYS, 7, 0, 0),
 541         GATE(mipi_hsi, "mipi_hsi", "div_aclk200", GATE_IP_FSYS, 8, 0, 0),
 542         GATE(sdmmc0, "sdmmc0", "div_aclk200", GATE_IP_FSYS, 12, 0, 0),
 543         GATE(sdmmc1, "sdmmc1", "div_aclk200", GATE_IP_FSYS, 13, 0, 0),
 544         GATE(sdmmc2, "sdmmc2", "div_aclk200", GATE_IP_FSYS, 14, 0, 0),
 545         GATE(sdmmc3, "sdmmc3", "div_aclk200", GATE_IP_FSYS, 15, 0, 0),
 546         GATE(sromc, "sromc", "div_aclk200", GATE_IP_FSYS, 17, 0, 0),
 547         GATE(usb2, "usb2", "div_aclk200", GATE_IP_FSYS, 18, 0, 0),
 548         GATE(usb3, "usb3", "div_aclk200", GATE_IP_FSYS, 19, 0, 0),
 549         GATE(sata_phyctrl, "sata_phyctrl", "div_aclk200",
 550                         GATE_IP_FSYS, 24, 0, 0),
 551         GATE(sata_phyi2c, "sata_phyi2c", "div_aclk200", GATE_IP_FSYS, 25, 0, 0),
 552
 553         GATE(uart0, "uart0", "div_aclk66", GATE_IP_PERIC, 0, 0, 0),
 554         GATE(uart1, "uart1", "div_aclk66", GATE_IP_PERIC, 1, 0, 0),
 555         GATE(uart2, "uart2", "div_aclk66", GATE_IP_PERIC, 2, 0, 0),
 556         GATE(uart3, "uart3", "div_aclk66", GATE_IP_PERIC, 3, 0, 0),
 557         GATE(uart4, "uart4", "div_aclk66", GATE_IP_PERIC, 4, 0, 0),
 558         GATE(i2c0, "i2c0", "div_aclk66", GATE_IP_PERIC, 6, 0, 0),
 559         GATE(i2c1, "i2c1", "div_aclk66", GATE_IP_PERIC, 7, 0, 0),
 560         GATE(i2c2, "i2c2", "div_aclk66", GATE_IP_PERIC, 8, 0, 0),
 561         GATE(i2c3, "i2c3", "div_aclk66", GATE_IP_PERIC, 9, 0, 0),
 562         GATE(i2c4, "i2c4", "div_aclk66", GATE_IP_PERIC, 10, 0, 0),
 563         GATE(i2c5, "i2c5", "div_aclk66", GATE_IP_PERIC, 11, 0, 0),
 564         GATE(i2c6, "i2c6", "div_aclk66", GATE_IP_PERIC, 12, 0, 0),
 565         GATE(i2c7, "i2c7", "div_aclk66", GATE_IP_PERIC, 13, 0, 0),
 566         GATE(i2c_hdmi, "i2c_hdmi", "div_aclk66", GATE_IP_PERIC, 14, 0, 0),
 567         GATE(adc, "adc", "div_aclk66", GATE_IP_PERIC, 15, 0, 0),
 568         GATE(spi0, "spi0", "div_aclk66", GATE_IP_PERIC, 16, 0, 0),
 569         GATE(spi1, "spi1", "div_aclk66", GATE_IP_PERIC, 17, 0, 0),
 570         GATE(spi2, "spi2", "div_aclk66", GATE_IP_PERIC, 18, 0, 0),
 571         GATE(i2s1, "i2s1", "div_aclk66", GATE_IP_PERIC, 20, 0, 0),
 572         GATE(i2s2, "i2s2", "div_aclk66", GATE_IP_PERIC, 21, 0, 0),
 573         GATE(pcm1, "pcm1", "div_aclk66", GATE_IP_PERIC, 22, 0, 0),
 574         GATE(pcm2, "pcm2", "div_aclk66", GATE_IP_PERIC, 23, 0, 0),
 575         GATE(pwm, "pwm", "div_aclk66", GATE_IP_PERIC, 24, 0, 0),
 576         GATE(spdif, "spdif", "div_aclk66", GATE_IP_PERIC, 26, 0, 0),
 577         GATE(ac97, "ac97", "div_aclk66", GATE_IP_PERIC, 27, 0, 0),
 578         GATE(hsi2c0, "hsi2c0", "div_aclk66", GATE_IP_PERIC, 28, 0, 0),
 579         GATE(hsi2c1, "hsi2c1", "div_aclk66", GATE_IP_PERIC, 29, 0, 0),
 580         GATE(hsi2c2, "hsi2c2", "div_aclk66", GATE_IP_PERIC, 30, 0, 0),
 581         GATE(hsi2c3, "hsi2c3", "div_aclk66", GATE_IP_PERIC, 31, 0, 0),
 582
 583         GATE(chipid, "chipid", "div_aclk66", GATE_IP_PERIS, 0, 0, 0),
 584         GATE(sysreg, "sysreg", "div_aclk66",
 585                         GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
 586         GATE(pmu, "pmu", "div_aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, 0),
 587         GATE(cmu_top, "cmu_top", "div_aclk66",
 588                         GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
 589         GATE(cmu_core, "cmu_core", "div_aclk66",
 590                         GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
 591         GATE(cmu_mem, "cmu_mem", "div_aclk66",
 592                         GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
 593         GATE(tzpc0, "tzpc0", "div_aclk66", GATE_IP_PERIS, 6, 0, 0),
 594         GATE(tzpc1, "tzpc1", "div_aclk66", GATE_IP_PERIS, 7, 0, 0),
 595         GATE(tzpc2, "tzpc2", "div_aclk66", GATE_IP_PERIS, 8, 0, 0),
 596         GATE(tzpc3, "tzpc3", "div_aclk66", GATE_IP_PERIS, 9, 0, 0),
 597         GATE(tzpc4, "tzpc4", "div_aclk66", GATE_IP_PERIS, 10, 0, 0),
 598         GATE(tzpc5, "tzpc5", "div_aclk66", GATE_IP_PERIS, 11, 0, 0),
 599         GATE(tzpc6, "tzpc6", "div_aclk66", GATE_IP_PERIS, 12, 0, 0),
 600         GATE(tzpc7, "tzpc7", "div_aclk66", GATE_IP_PERIS, 13, 0, 0),
 601         GATE(tzpc8, "tzpc8", "div_aclk66", GATE_IP_PERIS, 14, 0, 0),
 602         GATE(tzpc9, "tzpc9", "div_aclk66", GATE_IP_PERIS, 15, 0, 0),
 603         GATE(hdmi_cec, "hdmi_cec", "div_aclk66", GATE_IP_PERIS, 16, 0, 0),
 604         GATE(mct, "mct", "div_aclk66", GATE_IP_PERIS, 18, 0, 0),
 605         GATE(wdt, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0),
 606         GATE(rtc, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
 607         GATE(tmu, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
 608 };
 609
 610 static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = {
 611         /* sorted in descending order */
 612         /* PLL_36XX_RATE(rate, m, p, s, k) */
 613         PLL_36XX_RATE(266000000, 266, 3, 3, 0),
 614         /* Not in UM, but need for eDP on snow */
 615         PLL_36XX_RATE(70500000, 94, 2, 4, 0),
 616         { },
 617 };
 618
 619 static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = {
 620         /* sorted in descending order */
 621         /* PLL_36XX_RATE(rate, m, p, s, k) */
 622         PLL_36XX_RATE(192000000, 64, 2, 2, 0),
 623         PLL_36XX_RATE(180633600, 90, 3, 2, 20762),
 624         PLL_36XX_RATE(180000000, 90, 3, 2, 0),
 625         PLL_36XX_RATE(73728000, 98, 2, 4, 19923),
 626         PLL_36XX_RATE(67737600, 90, 2, 4, 20762),
 627         PLL_36XX_RATE(49152000, 98, 3, 4, 19923),
 628         PLL_36XX_RATE(45158400, 90, 3, 4, 20762),
 629         PLL_36XX_RATE(32768000, 131, 3, 5, 4719),
 630         { },
 631 };
 632
 633 static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
 634         [apll] = PLL_A(pll_35xx, fout_apll, "fout_apll", "fin_pll", APLL_LOCK,
 635                 APLL_CON0, "fout_apll", NULL),
 636         [mpll] = PLL_A(pll_35xx, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK,
 637                 MPLL_CON0, "fout_mpll", NULL),
 638         [bpll] = PLL(pll_35xx, fout_bpll, "fout_bpll", "fin_pll", BPLL_LOCK,
 639                 BPLL_CON0, NULL),
 640         [gpll] = PLL(pll_35xx, fout_gpll, "fout_gpll", "fin_pll", GPLL_LOCK,
 641                 GPLL_CON0, NULL),
 642         [cpll] = PLL(pll_35xx, fout_cpll, "fout_cpll", "fin_pll", CPLL_LOCK,
 643                 CPLL_CON0, NULL),
 644         [epll] = PLL(pll_36xx, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK,
 645                 EPLL_CON0, NULL),
 646         [vpll] = PLL(pll_36xx, fout_vpll, "fout_vpll", "mout_vpllsrc",
 647                 VPLL_LOCK, VPLL_CON0, NULL),
 648 };
 649
 650 static struct of_device_id ext_clk_match[] __initdata = {
 651         { .compatible = "samsung,clock-xxti", .data = (void *)0, },
 652         { },
 653 };
 654
 655 /* register exynox5250 clocks */
 656 static void __init exynos5250_clk_init(struct device_node *np)
 657 {
 658         void __iomem *reg_base;
 659
 660         if (np) {
 661                 reg_base = of_iomap(np, 0);
 662                 if (!reg_base)
 663                         panic("%s: failed to map registers\n", __func__);
 664         } else {
 665                 panic("%s: unable to determine soc\n", __func__);
 666         }
 667
 668         samsung_clk_init(np, reg_base, nr_clks,
 669                         exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs),
 670                         NULL, 0);
 671         samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks,
 672                         ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
 673                         ext_clk_match);
 674         samsung_clk_register_mux(exynos5250_pll_pmux_clks,
 675                                 ARRAY_SIZE(exynos5250_pll_pmux_clks));
 676
 677         if (_get_rate("fin_pll") == 24 * MHZ)
 678                 exynos5250_plls[epll].rate_table = epll_24mhz_tbl;
 679
 680         if (_get_rate("mout_vpllsrc") == 24 * MHZ)
 681                 exynos5250_plls[vpll].rate_table =  vpll_24mhz_tbl;
 682
 683         samsung_clk_register_pll(exynos5250_plls, ARRAY_SIZE(exynos5250_plls),
 684                                         reg_base);
 685         samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
 686                         ARRAY_SIZE(exynos5250_fixed_rate_clks));
 687         samsung_clk_register_fixed_factor(exynos5250_fixed_factor_clks,
 688                         ARRAY_SIZE(exynos5250_fixed_factor_clks));
 689         samsung_clk_register_mux(exynos5250_mux_clks,
 690                         ARRAY_SIZE(exynos5250_mux_clks));
 691         samsung_clk_register_div(exynos5250_div_clks,
 692                         ARRAY_SIZE(exynos5250_div_clks));
 693         samsung_clk_register_gate(exynos5250_gate_clks,
 694                         ARRAY_SIZE(exynos5250_gate_clks));
 695
 696         pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
 697                         _get_rate("div_arm2"));
 698 }
 699 CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);