2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Chanwoo Choi <cw00.choi@samsung.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * Common Clock Framework support for Exynos5443 SoC.
12 #include <linux/clk.h>
13 #include <linux/clkdev.h>
14 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/exynos5433.h>
23 * Register offset definitions for CMU_TOP
25 #define ISP_PLL_LOCK 0x0000
26 #define AUD_PLL_LOCK 0x0004
27 #define ISP_PLL_CON0 0x0100
28 #define ISP_PLL_CON1 0x0104
29 #define ISP_PLL_FREQ_DET 0x0108
30 #define AUD_PLL_CON0 0x0110
31 #define AUD_PLL_CON1 0x0114
32 #define AUD_PLL_CON2 0x0118
33 #define AUD_PLL_FREQ_DET 0x011c
34 #define MUX_SEL_TOP0 0x0200
35 #define MUX_SEL_TOP1 0x0204
36 #define MUX_SEL_TOP2 0x0208
37 #define MUX_SEL_TOP3 0x020c
38 #define MUX_SEL_TOP4 0x0210
39 #define MUX_SEL_TOP_MSCL 0x0220
40 #define MUX_SEL_TOP_CAM1 0x0224
41 #define MUX_SEL_TOP_DISP 0x0228
42 #define MUX_SEL_TOP_FSYS0 0x0230
43 #define MUX_SEL_TOP_FSYS1 0x0234
44 #define MUX_SEL_TOP_PERIC0 0x0238
45 #define MUX_SEL_TOP_PERIC1 0x023c
46 #define MUX_ENABLE_TOP0 0x0300
47 #define MUX_ENABLE_TOP1 0x0304
48 #define MUX_ENABLE_TOP2 0x0308
49 #define MUX_ENABLE_TOP3 0x030c
50 #define MUX_ENABLE_TOP4 0x0310
51 #define MUX_ENABLE_TOP_MSCL 0x0320
52 #define MUX_ENABLE_TOP_CAM1 0x0324
53 #define MUX_ENABLE_TOP_DISP 0x0328
54 #define MUX_ENABLE_TOP_FSYS0 0x0330
55 #define MUX_ENABLE_TOP_FSYS1 0x0334
56 #define MUX_ENABLE_TOP_PERIC0 0x0338
57 #define MUX_ENABLE_TOP_PERIC1 0x033c
58 #define MUX_STAT_TOP0 0x0400
59 #define MUX_STAT_TOP1 0x0404
60 #define MUX_STAT_TOP2 0x0408
61 #define MUX_STAT_TOP3 0x040c
62 #define MUX_STAT_TOP4 0x0410
63 #define MUX_STAT_TOP_MSCL 0x0420
64 #define MUX_STAT_TOP_CAM1 0x0424
65 #define MUX_STAT_TOP_FSYS0 0x0430
66 #define MUX_STAT_TOP_FSYS1 0x0434
67 #define MUX_STAT_TOP_PERIC0 0x0438
68 #define MUX_STAT_TOP_PERIC1 0x043c
69 #define DIV_TOP0 0x0600
70 #define DIV_TOP1 0x0604
71 #define DIV_TOP2 0x0608
72 #define DIV_TOP3 0x060c
73 #define DIV_TOP4 0x0610
74 #define DIV_TOP_MSCL 0x0618
75 #define DIV_TOP_CAM10 0x061c
76 #define DIV_TOP_CAM11 0x0620
77 #define DIV_TOP_FSYS0 0x062c
78 #define DIV_TOP_FSYS1 0x0630
79 #define DIV_TOP_FSYS2 0x0634
80 #define DIV_TOP_PERIC0 0x0638
81 #define DIV_TOP_PERIC1 0x063c
82 #define DIV_TOP_PERIC2 0x0640
83 #define DIV_TOP_PERIC3 0x0644
84 #define DIV_TOP_PERIC4 0x0648
85 #define DIV_TOP_PLL_FREQ_DET 0x064c
86 #define DIV_STAT_TOP0 0x0700
87 #define DIV_STAT_TOP1 0x0704
88 #define DIV_STAT_TOP2 0x0708
89 #define DIV_STAT_TOP3 0x070c
90 #define DIV_STAT_TOP4 0x0710
91 #define DIV_STAT_TOP_MSCL 0x0718
92 #define DIV_STAT_TOP_CAM10 0x071c
93 #define DIV_STAT_TOP_CAM11 0x0720
94 #define DIV_STAT_TOP_FSYS0 0x072c
95 #define DIV_STAT_TOP_FSYS1 0x0730
96 #define DIV_STAT_TOP_FSYS2 0x0734
97 #define DIV_STAT_TOP_PERIC0 0x0738
98 #define DIV_STAT_TOP_PERIC1 0x073c
99 #define DIV_STAT_TOP_PERIC2 0x0740
100 #define DIV_STAT_TOP_PERIC3 0x0744
101 #define DIV_STAT_TOP_PLL_FREQ_DET 0x074c
102 #define ENABLE_ACLK_TOP 0x0800
103 #define ENABLE_SCLK_TOP 0x0a00
104 #define ENABLE_SCLK_TOP_MSCL 0x0a04
105 #define ENABLE_SCLK_TOP_CAM1 0x0a08
106 #define ENABLE_SCLK_TOP_DISP 0x0a0c
107 #define ENABLE_SCLK_TOP_FSYS 0x0a10
108 #define ENABLE_SCLK_TOP_PERIC 0x0a14
109 #define ENABLE_IP_TOP 0x0b00
110 #define ENABLE_CMU_TOP 0x0c00
111 #define ENABLE_CMU_TOP_DIV_STAT 0x0c04
113 static unsigned long top_clk_regs
[] __initdata
= {
143 MUX_ENABLE_TOP_FSYS0
,
144 MUX_ENABLE_TOP_FSYS1
,
145 MUX_ENABLE_TOP_PERIC0
,
146 MUX_ENABLE_TOP_PERIC1
,
174 DIV_TOP_PLL_FREQ_DET
,
190 DIV_STAT_TOP_PLL_FREQ_DET
,
193 ENABLE_SCLK_TOP_MSCL
,
194 ENABLE_SCLK_TOP_CAM1
,
195 ENABLE_SCLK_TOP_DISP
,
196 ENABLE_SCLK_TOP_FSYS
,
197 ENABLE_SCLK_TOP_PERIC
,
200 ENABLE_CMU_TOP_DIV_STAT
,
203 /* list of all parent clock list */
204 PNAME(mout_aud_pll_p
) = { "oscclk", "fout_aud_pll", };
205 PNAME(mout_isp_pll_p
) = { "oscclk", "fout_isp_pll", };
206 PNAME(mout_aud_pll_user_p
) = { "oscclk", "mout_aud_pll", };
207 PNAME(mout_mphy_pll_user_p
) = { "oscclk", "sclk_mphy_pll", };
208 PNAME(mout_mfc_pll_user_p
) = { "oscclk", "sclk_mfc_pll", };
209 PNAME(mout_bus_pll_user_p
) = { "oscclk", "sclk_bus_pll", };
210 PNAME(mout_bus_pll_user_t_p
) = { "oscclk", "mout_bus_pll_user", };
211 PNAME(mout_mphy_pll_user_t_p
) = { "oscclk", "mout_mphy_pll_user", };
213 PNAME(mout_bus_mfc_pll_user_p
) = { "mout_bus_pll_user", "mout_mfc_pll_user",};
214 PNAME(mout_mfc_bus_pll_user_p
) = { "mout_mfc_pll_user", "mout_bus_pll_user",};
215 PNAME(mout_aclk_cam1_552_b_p
) = { "mout_aclk_cam1_552_a",
216 "mout_mfc_pll_user", };
217 PNAME(mout_aclk_cam1_552_a_p
) = { "mout_isp_pll", "mout_bus_pll_user", };
219 PNAME(mout_aclk_mfc_400_c_p
) = { "mout_aclk_mfc_400_b",
220 "mout_mphy_pll_user", };
221 PNAME(mout_aclk_mfc_400_b_p
) = { "mout_aclk_mfc_400_a",
222 "mout_bus_pll_user", };
223 PNAME(mout_aclk_mfc_400_a_p
) = { "mout_mfc_pll_user", "mout_isp_pll", };
225 PNAME(mout_bus_mphy_pll_user_p
) = { "mout_bus_pll_user",
226 "mout_mphy_pll_user", };
227 PNAME(mout_aclk_mscl_b_p
) = { "mout_aclk_mscl_400_a",
228 "mout_mphy_pll_user", };
229 PNAME(mout_aclk_g2d_400_b_p
) = { "mout_aclk_g2d_400_a",
230 "mout_mphy_pll_user", };
232 PNAME(mout_sclk_jpeg_c_p
) = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",};
233 PNAME(mout_sclk_jpeg_b_p
) = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", };
235 PNAME(mout_sclk_mmc2_b_p
) = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",};
236 PNAME(mout_sclk_mmc1_b_p
) = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",};
237 PNAME(mout_sclk_mmc0_d_p
) = { "mout_sclk_mmc0_c", "mout_isp_pll", };
238 PNAME(mout_sclk_mmc0_c_p
) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
239 PNAME(mout_sclk_mmc0_b_p
) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
241 PNAME(mout_sclk_spdif_p
) = { "sclk_audio0", "sclk_audio1",
242 "oscclk", "ioclk_spdif_extclk", };
243 PNAME(mout_sclk_audio1_p
) = { "ioclk_audiocdclk1", "oscclk",
244 "mout_aud_pll_user_t",};
245 PNAME(mout_sclk_audio0_p
) = { "ioclk_audiocdclk0", "oscclk",
246 "mout_aud_pll_user_t",};
248 PNAME(mout_sclk_hdmi_spdif_p
) = { "sclk_audio1", "ioclk_spdif_extclk", };
250 static struct samsung_fixed_factor_clock top_fixed_factor_clks
[] __initdata
= {
251 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
254 static struct samsung_fixed_rate_clock top_fixed_clks
[] __initdata
= {
255 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
256 FRATE(0, "ioclk_audiocdclk1", NULL
, CLK_IS_ROOT
, 100000000),
257 FRATE(0, "ioclk_audiocdclk0", NULL
, CLK_IS_ROOT
, 100000000),
258 /* Xi2s1SDI input clock for SPDIF */
259 FRATE(0, "ioclk_spdif_extclk", NULL
, CLK_IS_ROOT
, 100000000),
260 /* XspiCLK[4:0] input clock for SPI */
261 FRATE(0, "ioclk_spi4_clk_in", NULL
, CLK_IS_ROOT
, 50000000),
262 FRATE(0, "ioclk_spi3_clk_in", NULL
, CLK_IS_ROOT
, 50000000),
263 FRATE(0, "ioclk_spi2_clk_in", NULL
, CLK_IS_ROOT
, 50000000),
264 FRATE(0, "ioclk_spi1_clk_in", NULL
, CLK_IS_ROOT
, 50000000),
265 FRATE(0, "ioclk_spi0_clk_in", NULL
, CLK_IS_ROOT
, 50000000),
266 /* Xi2s1SCLK input clock for I2S1_BCLK */
267 FRATE(0, "ioclk_i2s1_bclk_in", NULL
, CLK_IS_ROOT
, 12288000),
270 static struct samsung_mux_clock top_mux_clks
[] __initdata
= {
272 MUX(CLK_MOUT_AUD_PLL
, "mout_aud_pll", mout_aud_pll_p
, MUX_SEL_TOP0
,
274 MUX(CLK_MOUT_ISP_PLL
, "mout_isp_pll", mout_isp_pll_p
, MUX_SEL_TOP0
,
278 MUX(CLK_MOUT_AUD_PLL_USER_T
, "mout_aud_pll_user_t",
279 mout_aud_pll_user_p
, MUX_SEL_TOP1
, 12, 1),
280 MUX(CLK_MOUT_MPHY_PLL_USER
, "mout_mphy_pll_user", mout_mphy_pll_user_p
,
282 MUX(CLK_MOUT_MFC_PLL_USER
, "mout_mfc_pll_user", mout_mfc_pll_user_p
,
284 MUX(CLK_MOUT_BUS_PLL_USER
, "mout_bus_pll_user", mout_bus_pll_user_p
,
288 MUX(CLK_MOUT_ACLK_HEVC_400
, "mout_aclk_hevc_400",
289 mout_bus_mfc_pll_user_p
, MUX_SEL_TOP2
, 28, 1),
290 MUX(CLK_MOUT_ACLK_CAM1_333
, "mout_aclk_cam1_333",
291 mout_mfc_bus_pll_user_p
, MUX_SEL_TOP2
, 16, 1),
292 MUX(CLK_MOUT_ACLK_CAM1_552_B
, "mout_aclk_cam1_552_b",
293 mout_aclk_cam1_552_b_p
, MUX_SEL_TOP2
, 12, 1),
294 MUX(CLK_MOUT_ACLK_CAM1_552_A
, "mout_aclk_cam1_552_a",
295 mout_aclk_cam1_552_a_p
, MUX_SEL_TOP2
, 8, 1),
296 MUX(CLK_MOUT_ACLK_ISP_DIS_400
, "mout_aclk_isp_dis_400",
297 mout_bus_mfc_pll_user_p
, MUX_SEL_TOP2
, 4, 1),
298 MUX(CLK_MOUT_ACLK_ISP_400
, "mout_aclk_isp_400",
299 mout_bus_mfc_pll_user_p
, MUX_SEL_TOP2
, 0, 1),
302 MUX(CLK_MOUT_ACLK_BUS0_400
, "mout_aclk_bus0_400",
303 mout_bus_mphy_pll_user_p
, MUX_SEL_TOP3
, 20, 1),
304 MUX(CLK_MOUT_ACLK_MSCL_400_B
, "mout_aclk_mscl_400_b",
305 mout_aclk_mscl_b_p
, MUX_SEL_TOP3
, 16, 1),
306 MUX(CLK_MOUT_ACLK_MSCL_400_A
, "mout_aclk_mscl_400_a",
307 mout_bus_mfc_pll_user_p
, MUX_SEL_TOP3
, 12, 1),
308 MUX(CLK_MOUT_ACLK_GSCL_333
, "mout_aclk_gscl_333",
309 mout_mfc_bus_pll_user_p
, MUX_SEL_TOP3
, 8, 1),
310 MUX(CLK_MOUT_ACLK_G2D_400_B
, "mout_aclk_g2d_400_b",
311 mout_aclk_g2d_400_b_p
, MUX_SEL_TOP3
, 4, 1),
312 MUX(CLK_MOUT_ACLK_G2D_400_A
, "mout_aclk_g2d_400_a",
313 mout_bus_mfc_pll_user_p
, MUX_SEL_TOP3
, 0, 1),
316 MUX(CLK_MOUT_ACLK_MFC_400_C
, "mout_aclk_mfc_400_c",
317 mout_aclk_mfc_400_c_p
, MUX_SEL_TOP4
, 8, 1),
318 MUX(CLK_MOUT_ACLK_MFC_400_B
, "mout_aclk_mfc_400_b",
319 mout_aclk_mfc_400_b_p
, MUX_SEL_TOP4
, 4, 1),
320 MUX(CLK_MOUT_ACLK_MFC_400_A
, "mout_aclk_mfc_400_a",
321 mout_aclk_mfc_400_a_p
, MUX_SEL_TOP4
, 0, 1),
323 /* MUX_SEL_TOP_MSCL */
324 MUX(CLK_MOUT_SCLK_JPEG_C
, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p
,
325 MUX_SEL_TOP_MSCL
, 8, 1),
326 MUX(CLK_MOUT_SCLK_JPEG_B
, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p
,
327 MUX_SEL_TOP_MSCL
, 4, 1),
328 MUX(CLK_MOUT_SCLK_JPEG_A
, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p
,
329 MUX_SEL_TOP_MSCL
, 0, 1),
331 /* MUX_SEL_TOP_CAM1 */
332 MUX(CLK_MOUT_SCLK_ISP_SENSOR2
, "mout_sclk_isp_sensor2",
333 mout_bus_pll_user_t_p
, MUX_SEL_TOP_CAM1
, 24, 1),
334 MUX(CLK_MOUT_SCLK_ISP_SENSOR1
, "mout_sclk_isp_sensor1",
335 mout_bus_pll_user_t_p
, MUX_SEL_TOP_CAM1
, 20, 1),
336 MUX(CLK_MOUT_SCLK_ISP_SENSOR0
, "mout_sclk_isp_sensor0",
337 mout_bus_pll_user_t_p
, MUX_SEL_TOP_CAM1
, 16, 1),
338 MUX(CLK_MOUT_SCLK_ISP_UART
, "mout_sclk_isp_uart",
339 mout_bus_pll_user_t_p
, MUX_SEL_TOP_CAM1
, 8, 1),
340 MUX(CLK_MOUT_SCLK_ISP_SPI1
, "mout_sclk_isp_spi1",
341 mout_bus_pll_user_t_p
, MUX_SEL_TOP_CAM1
, 4, 1),
342 MUX(CLK_MOUT_SCLK_ISP_SPI0
, "mout_sclk_isp_spi0",
343 mout_bus_pll_user_t_p
, MUX_SEL_TOP_CAM1
, 0, 1),
345 /* MUX_SEL_TOP_FSYS0 */
346 MUX(CLK_MOUT_SCLK_MMC2_B
, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p
,
347 MUX_SEL_TOP_FSYS0
, 28, 1),
348 MUX(CLK_MOUT_SCLK_MMC2_A
, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p
,
349 MUX_SEL_TOP_FSYS0
, 24, 1),
350 MUX(CLK_MOUT_SCLK_MMC1_B
, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p
,
351 MUX_SEL_TOP_FSYS0
, 20, 1),
352 MUX(CLK_MOUT_SCLK_MMC1_A
, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p
,
353 MUX_SEL_TOP_FSYS0
, 16, 1),
354 MUX(CLK_MOUT_SCLK_MMC0_D
, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p
,
355 MUX_SEL_TOP_FSYS0
, 12, 1),
356 MUX(CLK_MOUT_SCLK_MMC0_C
, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p
,
357 MUX_SEL_TOP_FSYS0
, 8, 1),
358 MUX(CLK_MOUT_SCLK_MMC0_B
, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p
,
359 MUX_SEL_TOP_FSYS0
, 4, 1),
360 MUX(CLK_MOUT_SCLK_MMC0_A
, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p
,
361 MUX_SEL_TOP_FSYS0
, 0, 1),
363 /* MUX_SEL_TOP_FSYS1 */
364 MUX(CLK_MOUT_SCLK_PCIE_100
, "mout_sclk_pcie_100", mout_bus_pll_user_t_p
,
365 MUX_SEL_TOP_FSYS1
, 12, 1),
366 MUX(CLK_MOUT_SCLK_UFSUNIPRO
, "mout_sclk_ufsunipro",
367 mout_mphy_pll_user_t_p
, MUX_SEL_TOP_FSYS1
, 8, 1),
368 MUX(CLK_MOUT_SCLK_USBHOST30
, "mout_sclk_usbhost30",
369 mout_bus_pll_user_t_p
, MUX_SEL_TOP_FSYS1
, 4, 1),
370 MUX(CLK_MOUT_SCLK_USBDRD30
, "mout_sclk_usbdrd30",
371 mout_bus_pll_user_t_p
, MUX_SEL_TOP_FSYS1
, 0, 1),
373 /* MUX_SEL_TOP_PERIC0 */
374 MUX(CLK_MOUT_SCLK_SPI4
, "mout_sclk_spi4", mout_bus_pll_user_t_p
,
375 MUX_SEL_TOP_PERIC0
, 28, 1),
376 MUX(CLK_MOUT_SCLK_SPI3
, "mout_sclk_spi3", mout_bus_pll_user_t_p
,
377 MUX_SEL_TOP_PERIC0
, 24, 1),
378 MUX(CLK_MOUT_SCLK_UART2
, "mout_sclk_uart2", mout_bus_pll_user_t_p
,
379 MUX_SEL_TOP_PERIC0
, 20, 1),
380 MUX(CLK_MOUT_SCLK_UART1
, "mout_sclk_uart1", mout_bus_pll_user_t_p
,
381 MUX_SEL_TOP_PERIC0
, 16, 1),
382 MUX(CLK_MOUT_SCLK_UART0
, "mout_sclk_uart0", mout_bus_pll_user_t_p
,
383 MUX_SEL_TOP_PERIC0
, 12, 1),
384 MUX(CLK_MOUT_SCLK_SPI2
, "mout_sclk_spi2", mout_bus_pll_user_t_p
,
385 MUX_SEL_TOP_PERIC0
, 8, 1),
386 MUX(CLK_MOUT_SCLK_SPI1
, "mout_sclk_spi1", mout_bus_pll_user_t_p
,
387 MUX_SEL_TOP_PERIC0
, 4, 1),
388 MUX(CLK_MOUT_SCLK_SPI0
, "mout_sclk_spi0", mout_bus_pll_user_t_p
,
389 MUX_SEL_TOP_PERIC0
, 0, 1),
391 /* MUX_SEL_TOP_PERIC1 */
392 MUX(CLK_MOUT_SCLK_SLIMBUS
, "mout_sclk_slimbus", mout_aud_pll_user_p
,
393 MUX_SEL_TOP_PERIC1
, 16, 1),
394 MUX(CLK_MOUT_SCLK_SPDIF
, "mout_sclk_spdif", mout_sclk_spdif_p
,
395 MUX_SEL_TOP_PERIC1
, 12, 2),
396 MUX(CLK_MOUT_SCLK_AUDIO1
, "mout_sclk_audio1", mout_sclk_audio1_p
,
397 MUX_SEL_TOP_PERIC1
, 4, 2),
398 MUX(CLK_MOUT_SCLK_AUDIO0
, "mout_sclk_audio0", mout_sclk_audio0_p
,
399 MUX_SEL_TOP_PERIC1
, 0, 2),
401 /* MUX_SEL_TOP_DISP */
402 MUX(CLK_MOUT_SCLK_HDMI_SPDIF
, "mout_sclk_hdmi_spdif",
403 mout_sclk_hdmi_spdif_p
, MUX_SEL_TOP_DISP
, 0, 1),
406 static struct samsung_div_clock top_div_clks
[] __initdata
= {
408 DIV(CLK_DIV_ACLK_CAM1_333
, "div_aclk_cam1_333", "mout_aclk_cam1_333",
410 DIV(CLK_DIV_ACLK_CAM1_400
, "div_aclk_cam1_400", "mout_bus_pll_user",
412 DIV(CLK_DIV_ACLK_CAM1_552
, "div_aclk_cam1_552", "mout_aclk_cam1_552_b",
414 DIV(CLK_DIV_ACLK_CAM0_333
, "div_aclk_cam0_333", "mout_mfc_pll_user",
416 DIV(CLK_DIV_ACLK_CAM0_400
, "div_aclk_cam0_400", "mout_bus_pll_user",
418 DIV(CLK_DIV_ACLK_CAM0_552
, "div_aclk_cam0_552", "mout_isp_pll",
420 DIV(CLK_DIV_ACLK_ISP_DIS_400
, "div_aclk_isp_dis_400",
421 "mout_aclk_isp_dis_400", DIV_TOP0
, 4, 4),
422 DIV(CLK_DIV_ACLK_ISP_400
, "div_aclk_isp_400",
423 "mout_aclk_isp_400", DIV_TOP0
, 0, 4),
426 DIV(CLK_DIV_ACLK_GSCL_111
, "div_aclk_gscl_111", "mout_aclk_gscl_333",
428 DIV(CLK_DIV_ACLK_GSCL_333
, "div_aclk_gscl_333", "mout_aclk_gscl_333",
430 DIV(CLK_DIV_ACLK_HEVC_400
, "div_aclk_hevc_400", "mout_aclk_hevc_400",
432 DIV(CLK_DIV_ACLK_MFC_400
, "div_aclk_mfc_400", "mout_aclk_mfc_400_c",
434 DIV(CLK_DIV_ACLK_G2D_266
, "div_aclk_g2d_266", "mout_bus_pll_user",
436 DIV(CLK_DIV_ACLK_G2D_400
, "div_aclk_g2d_400", "mout_aclk_g2d_400_b",
440 DIV(CLK_DIV_ACLK_MSCL_400
, "div_aclk_mscl_400", "mout_aclk_mscl_400_b",
442 DIV(CLK_DIV_ACLK_FSYS_200
, "div_aclk_fsys_200", "mout_bus_pll_user",
446 DIV(CLK_DIV_ACLK_IMEM_SSSX_266
, "div_aclk_imem_sssx_266",
447 "mout_bus_pll_user", DIV_TOP3
, 24, 3),
448 DIV(CLK_DIV_ACLK_IMEM_200
, "div_aclk_imem_200",
449 "mout_bus_pll_user", DIV_TOP3
, 20, 3),
450 DIV(CLK_DIV_ACLK_IMEM_266
, "div_aclk_imem_266",
451 "mout_bus_pll_user", DIV_TOP3
, 16, 3),
452 DIV(CLK_DIV_ACLK_PERIC_66_B
, "div_aclk_peric_66_b",
453 "div_aclk_peric_66_a", DIV_TOP3
, 12, 3),
454 DIV(CLK_DIV_ACLK_PERIC_66_A
, "div_aclk_peric_66_a",
455 "mout_bus_pll_user", DIV_TOP3
, 8, 3),
456 DIV(CLK_DIV_ACLK_PERIS_66_B
, "div_aclk_peris_66_b",
457 "div_aclk_peris_66_a", DIV_TOP3
, 4, 3),
458 DIV(CLK_DIV_ACLK_PERIS_66_A
, "div_aclk_peris_66_a",
459 "mout_bus_pll_user", DIV_TOP3
, 0, 3),
462 DIV(CLK_DIV_ACLK_G3D_400
, "div_aclk_g3d_400", "mout_bus_pll_user",
464 DIV(CLK_DIV_ACLK_BUS0_400
, "div_aclk_bus0_400", "mout_aclk_bus0_400",
466 DIV(CLK_DIV_ACLK_BUS1_400
, "div_aclk_bus1_400", "mout_bus_pll_user",
470 DIV(CLK_DIV_SCLK_JPEG
, "div_sclk_jpeg", "mout_sclk_jpeg_c",
474 DIV(CLK_DIV_SCLK_ISP_UART
, "div_sclk_isp_uart", "mout_sclk_isp_uart",
475 DIV_TOP_CAM10
, 24, 5),
476 DIV(CLK_DIV_SCLK_ISP_SPI1_B
, "div_sclk_isp_spi1_b",
477 "div_sclk_isp_spi1_a", DIV_TOP_CAM10
, 16, 8),
478 DIV(CLK_DIV_SCLK_ISP_SPI1_A
, "div_sclk_isp_spi1_a",
479 "mout_sclk_isp_spi1", DIV_TOP_CAM10
, 12, 4),
480 DIV(CLK_DIV_SCLK_ISP_SPI0_B
, "div_sclk_isp_spi0_b",
481 "div_sclk_isp_spi0_a", DIV_TOP_CAM10
, 4, 8),
482 DIV(CLK_DIV_SCLK_ISP_SPI0_A
, "div_sclk_isp_spi0_a",
483 "mout_sclk_isp_spi0", DIV_TOP_CAM10
, 0, 4),
486 DIV(CLK_DIV_SCLK_ISP_SENSOR2_B
, "div_sclk_isp_sensor2_b",
487 "div_sclk_isp_sensor2_a", DIV_TOP_CAM11
, 20, 4),
488 DIV(CLK_DIV_SCLK_ISP_SENSOR2_A
, "div_sclk_isp_sensor2_a",
489 "mout_sclk_isp_sensor2", DIV_TOP_CAM11
, 16, 4),
490 DIV(CLK_DIV_SCLK_ISP_SENSOR1_B
, "div_sclk_isp_sensor1_b",
491 "div_sclk_isp_sensor1_a", DIV_TOP_CAM11
, 12, 4),
492 DIV(CLK_DIV_SCLK_ISP_SENSOR1_A
, "div_sclk_isp_sensor1_a",
493 "mout_sclk_isp_sensor1", DIV_TOP_CAM11
, 8, 4),
494 DIV(CLK_DIV_SCLK_ISP_SENSOR0_B
, "div_sclk_isp_sensor0_b",
495 "div_sclk_isp_sensor0_a", DIV_TOP_CAM11
, 12, 4),
496 DIV(CLK_DIV_SCLK_ISP_SENSOR0_A
, "div_sclk_isp_sensor0_a",
497 "mout_sclk_isp_sensor0", DIV_TOP_CAM11
, 8, 4),
500 DIV(CLK_DIV_SCLK_MMC1_B
, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
501 DIV_TOP_FSYS0
, 16, 8),
502 DIV(CLK_DIV_SCLK_MMC1_A
, "div_sclk_mmc1_a", "mout_sclk_mmc1_b",
503 DIV_TOP_FSYS0
, 12, 4),
504 DIV_F(CLK_DIV_SCLK_MMC0_B
, "div_sclk_mmc0_b", "div_sclk_mmc0_a",
505 DIV_TOP_FSYS0
, 4, 8, CLK_SET_RATE_PARENT
, 0),
506 DIV_F(CLK_DIV_SCLK_MMC0_A
, "div_sclk_mmc0_a", "mout_sclk_mmc0_d",
507 DIV_TOP_FSYS0
, 0, 4, CLK_SET_RATE_PARENT
, 0),
510 DIV(CLK_DIV_SCLK_MMC2_B
, "div_sclk_mmc2_b", "div_sclk_mmc2_a",
511 DIV_TOP_FSYS1
, 4, 8),
512 DIV(CLK_DIV_SCLK_MMC2_A
, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
513 DIV_TOP_FSYS1
, 0, 4),
516 DIV(CLK_DIV_SCLK_PCIE_100
, "div_sclk_pcie_100", "mout_sclk_pcie_100",
517 DIV_TOP_FSYS2
, 12, 3),
518 DIV(CLK_DIV_SCLK_USBHOST30
, "div_sclk_usbhost30",
519 "mout_sclk_usbhost30", DIV_TOP_FSYS2
, 8, 4),
520 DIV(CLK_DIV_SCLK_UFSUNIPRO
, "div_sclk_ufsunipro",
521 "mout_sclk_ufsunipro", DIV_TOP_FSYS2
, 4, 4),
522 DIV(CLK_DIV_SCLK_USBDRD30
, "div_sclk_usbdrd30", "mout_sclk_usbdrd30",
523 DIV_TOP_FSYS2
, 0, 4),
526 DIV(CLK_DIV_SCLK_SPI1_B
, "div_sclk_spi1_b", "div_sclk_spi1_a",
527 DIV_TOP_PERIC0
, 16, 8),
528 DIV(CLK_DIV_SCLK_SPI1_A
, "div_sclk_spi1_a", "mout_sclk_spi1",
529 DIV_TOP_PERIC0
, 12, 4),
530 DIV(CLK_DIV_SCLK_SPI0_B
, "div_sclk_spi0_b", "div_sclk_spi0_a",
531 DIV_TOP_PERIC0
, 4, 8),
532 DIV(CLK_DIV_SCLK_SPI0_A
, "div_sclk_spi0_a", "mout_sclk_spi0",
533 DIV_TOP_PERIC0
, 0, 4),
536 DIV(CLK_DIV_SCLK_SPI2_B
, "div_sclk_spi2_b", "div_sclk_spi2_a",
537 DIV_TOP_PERIC1
, 4, 8),
538 DIV(CLK_DIV_SCLK_SPI2_A
, "div_sclk_spi2_a", "mout_sclk_spi2",
539 DIV_TOP_PERIC1
, 0, 4),
542 DIV(CLK_DIV_SCLK_UART2
, "div_sclk_uart2", "mout_sclk_uart2",
543 DIV_TOP_PERIC2
, 8, 4),
544 DIV(CLK_DIV_SCLK_UART1
, "div_sclk_uart1", "mout_sclk_uart0",
545 DIV_TOP_PERIC2
, 4, 4),
546 DIV(CLK_DIV_SCLK_UART0
, "div_sclk_uart0", "mout_sclk_uart1",
547 DIV_TOP_PERIC2
, 0, 4),
550 DIV(CLK_DIV_SCLK_I2S1
, "div_sclk_i2s1", "sclk_audio1",
551 DIV_TOP_PERIC3
, 16, 6),
552 DIV(CLK_DIV_SCLK_PCM1
, "div_sclk_pcm1", "sclk_audio1",
553 DIV_TOP_PERIC3
, 8, 8),
554 DIV(CLK_DIV_SCLK_AUDIO1
, "div_sclk_audio1", "mout_sclk_audio1",
555 DIV_TOP_PERIC3
, 4, 4),
556 DIV(CLK_DIV_SCLK_AUDIO0
, "div_sclk_audio0", "mout_sclk_audio0",
557 DIV_TOP_PERIC3
, 0, 4),
560 DIV(CLK_DIV_SCLK_SPI4_B
, "div_sclk_spi4_b", "div_sclk_spi4_a",
561 DIV_TOP_PERIC4
, 16, 8),
562 DIV(CLK_DIV_SCLK_SPI4_A
, "div_sclk_spi4_a", "mout_sclk_spi4",
563 DIV_TOP_PERIC4
, 12, 4),
564 DIV(CLK_DIV_SCLK_SPI3_B
, "div_sclk_spi3_b", "div_sclk_spi3_a",
565 DIV_TOP_PERIC4
, 4, 8),
566 DIV(CLK_DIV_SCLK_SPI3_A
, "div_sclk_spi3_a", "mout_sclk_spi3",
567 DIV_TOP_PERIC4
, 0, 4),
570 static struct samsung_gate_clock top_gate_clks
[] __initdata
= {
571 /* ENABLE_ACLK_TOP */
572 GATE(CLK_ACLK_G3D_400
, "aclk_g3d_400", "div_aclk_g3d_400",
573 ENABLE_ACLK_TOP
, 30, 0, 0),
574 GATE(CLK_ACLK_IMEM_SSX_266
, "aclk_imem_ssx_266",
575 "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP
,
576 29, CLK_IGNORE_UNUSED
, 0),
577 GATE(CLK_ACLK_BUS0_400
, "aclk_bus0_400", "div_aclk_bus0_400",
579 CLK_IGNORE_UNUSED
| CLK_SET_RATE_PARENT
, 0),
580 GATE(CLK_ACLK_BUS1_400
, "aclk_bus1_400", "div_aclk_bus1_400",
582 CLK_IGNORE_UNUSED
| CLK_SET_RATE_PARENT
, 0),
583 GATE(CLK_ACLK_IMEM_200
, "aclk_imem_200", "div_aclk_imem_266",
585 CLK_IGNORE_UNUSED
| CLK_SET_RATE_PARENT
, 0),
586 GATE(CLK_ACLK_IMEM_266
, "aclk_imem_266", "div_aclk_imem_200",
588 CLK_IGNORE_UNUSED
| CLK_SET_RATE_PARENT
, 0),
589 GATE(CLK_ACLK_PERIC_66
, "aclk_peric_66", "div_aclk_peric_66_b",
591 CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
, 0),
592 GATE(CLK_ACLK_PERIS_66
, "aclk_peris_66", "div_aclk_peris_66_b",
594 CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
, 0),
595 GATE(CLK_ACLK_MSCL_400
, "aclk_mscl_400", "div_aclk_mscl_400",
597 CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
, 0),
598 GATE(CLK_ACLK_FSYS_200
, "aclk_fsys_200", "div_aclk_fsys_200",
600 CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
, 0),
601 GATE(CLK_ACLK_GSCL_111
, "aclk_gscl_111", "div_aclk_gscl_111",
603 CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
, 0),
604 GATE(CLK_ACLK_GSCL_333
, "aclk_gscl_333", "div_aclk_gscl_333",
606 CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
, 0),
607 GATE(CLK_ACLK_CAM1_333
, "aclk_cam1_333", "div_aclk_cam1_333",
609 CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
, 0),
610 GATE(CLK_ACLK_CAM1_400
, "aclk_cam1_400", "div_aclk_cam1_400",
612 CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
, 0),
613 GATE(CLK_ACLK_CAM1_552
, "aclk_cam1_552", "div_aclk_cam1_552",
615 CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
, 0),
616 GATE(CLK_ACLK_CAM0_333
, "aclk_cam0_333", "div_aclk_cam0_333",
618 CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
, 0),
619 GATE(CLK_ACLK_CAM0_400
, "aclk_cam0_400", "div_aclk_cam0_400",
621 CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
, 0),
622 GATE(CLK_ACLK_CAM0_552
, "aclk_cam0_552", "div_aclk_cam0_552",
624 CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
, 0),
625 GATE(CLK_ACLK_ISP_DIS_400
, "aclk_isp_dis_400", "div_aclk_isp_dis_400",
627 CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
, 0),
628 GATE(CLK_ACLK_ISP_400
, "aclk_isp_400", "div_aclk_isp_400",
630 CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
, 0),
631 GATE(CLK_ACLK_HEVC_400
, "aclk_hevc_400", "div_aclk_hevc_400",
633 CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
, 0),
634 GATE(CLK_ACLK_MFC_400
, "aclk_mfc_400", "div_aclk_mfc_400",
636 CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
, 0),
637 GATE(CLK_ACLK_G2D_266
, "aclk_g2d_266", "div_aclk_g2d_266",
639 CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
, 0),
640 GATE(CLK_ACLK_G2D_400
, "aclk_g2d_400", "div_aclk_g2d_400",
642 CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
, 0),
644 /* ENABLE_SCLK_TOP_MSCL */
645 GATE(CLK_SCLK_JPEG_MSCL
, "sclk_jpeg_mscl", "div_sclk_jpeg",
646 ENABLE_SCLK_TOP_MSCL
, 0, 0, 0),
648 /* ENABLE_SCLK_TOP_CAM1 */
649 GATE(CLK_SCLK_ISP_SENSOR2
, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b",
650 ENABLE_SCLK_TOP_CAM1
, 7, 0, 0),
651 GATE(CLK_SCLK_ISP_SENSOR1
, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b",
652 ENABLE_SCLK_TOP_CAM1
, 6, 0, 0),
653 GATE(CLK_SCLK_ISP_SENSOR0
, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b",
654 ENABLE_SCLK_TOP_CAM1
, 5, 0, 0),
655 GATE(CLK_SCLK_ISP_MCTADC_CAM1
, "sclk_isp_mctadc_cam1", "oscclk",
656 ENABLE_SCLK_TOP_CAM1
, 4, 0, 0),
657 GATE(CLK_SCLK_ISP_UART_CAM1
, "sclk_isp_uart_cam1", "div_sclk_isp_uart",
658 ENABLE_SCLK_TOP_CAM1
, 2, 0, 0),
659 GATE(CLK_SCLK_ISP_SPI1_CAM1
, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b",
660 ENABLE_SCLK_TOP_CAM1
, 1, 0, 0),
661 GATE(CLK_SCLK_ISP_SPI0_CAM1
, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b",
662 ENABLE_SCLK_TOP_CAM1
, 0, 0, 0),
664 /* ENABLE_SCLK_TOP_DISP */
665 GATE(CLK_SCLK_HDMI_SPDIF_DISP
, "sclk_hdmi_spdif_disp",
666 "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP
, 0,
667 CLK_IGNORE_UNUSED
, 0),
669 /* ENABLE_SCLK_TOP_FSYS */
670 GATE(CLK_SCLK_PCIE_100_FSYS
, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
671 ENABLE_SCLK_TOP_FSYS
, 7, 0, 0),
672 GATE(CLK_SCLK_MMC2_FSYS
, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
673 ENABLE_SCLK_TOP_FSYS
, 6, CLK_SET_RATE_PARENT
, 0),
674 GATE(CLK_SCLK_MMC1_FSYS
, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
675 ENABLE_SCLK_TOP_FSYS
, 5, CLK_SET_RATE_PARENT
, 0),
676 GATE(CLK_SCLK_MMC0_FSYS
, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
677 ENABLE_SCLK_TOP_FSYS
, 4, CLK_SET_RATE_PARENT
, 0),
678 GATE(CLK_SCLK_UFSUNIPRO_FSYS
, "sclk_ufsunipro_fsys",
679 "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS
,
680 3, CLK_SET_RATE_PARENT
, 0),
681 GATE(CLK_SCLK_USBHOST30_FSYS
, "sclk_usbhost30_fsys",
682 "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS
,
683 1, CLK_SET_RATE_PARENT
, 0),
684 GATE(CLK_SCLK_USBDRD30_FSYS
, "sclk_usbdrd30_fsys",
685 "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS
,
686 0, CLK_SET_RATE_PARENT
, 0),
688 /* ENABLE_SCLK_TOP_PERIC */
689 GATE(CLK_SCLK_SPI4_PERIC
, "sclk_spi4_peric", "div_sclk_spi4_b",
690 ENABLE_SCLK_TOP_PERIC
, 12, CLK_SET_RATE_PARENT
, 0),
691 GATE(CLK_SCLK_SPI3_PERIC
, "sclk_spi3_peric", "div_sclk_spi3_b",
692 ENABLE_SCLK_TOP_PERIC
, 11, CLK_SET_RATE_PARENT
, 0),
693 GATE(CLK_SCLK_SPDIF_PERIC
, "sclk_spdif_peric", "mout_sclk_spdif",
694 ENABLE_SCLK_TOP_PERIC
, 9, CLK_SET_RATE_PARENT
, 0),
695 GATE(CLK_SCLK_I2S1_PERIC
, "sclk_i2s1_peric", "div_sclk_i2s1",
696 ENABLE_SCLK_TOP_PERIC
, 8, CLK_SET_RATE_PARENT
, 0),
697 GATE(CLK_SCLK_PCM1_PERIC
, "sclk_pcm1_peric", "div_sclk_pcm1",
698 ENABLE_SCLK_TOP_PERIC
, 7, CLK_SET_RATE_PARENT
, 0),
699 GATE(CLK_SCLK_UART2_PERIC
, "sclk_uart2_peric", "div_sclk_uart2",
700 ENABLE_SCLK_TOP_PERIC
, 5, CLK_SET_RATE_PARENT
, 0),
701 GATE(CLK_SCLK_UART1_PERIC
, "sclk_uart1_peric", "div_sclk_uart1",
702 ENABLE_SCLK_TOP_PERIC
, 4, CLK_SET_RATE_PARENT
, 0),
703 GATE(CLK_SCLK_UART0_PERIC
, "sclk_uart0_peric", "div_sclk_uart0",
704 ENABLE_SCLK_TOP_PERIC
, 3, CLK_SET_RATE_PARENT
, 0),
705 GATE(CLK_SCLK_SPI2_PERIC
, "sclk_spi2_peric", "div_sclk_spi2_b",
706 ENABLE_SCLK_TOP_PERIC
, 2, CLK_SET_RATE_PARENT
, 0),
707 GATE(CLK_SCLK_SPI1_PERIC
, "sclk_spi1_peric", "div_sclk_spi1_b",
708 ENABLE_SCLK_TOP_PERIC
, 1, CLK_SET_RATE_PARENT
, 0),
709 GATE(CLK_SCLK_SPI0_PERIC
, "sclk_spi0_peric", "div_sclk_spi0_b",
710 ENABLE_SCLK_TOP_PERIC
, 0, CLK_SET_RATE_PARENT
, 0),
712 /* MUX_ENABLE_TOP_PERIC1 */
713 GATE(CLK_SCLK_SLIMBUS
, "sclk_slimbus", "mout_sclk_slimbus",
714 MUX_ENABLE_TOP_PERIC1
, 16, 0, 0),
715 GATE(CLK_SCLK_AUDIO1
, "sclk_audio1", "div_sclk_audio1",
716 MUX_ENABLE_TOP_PERIC1
, 4, 0, 0),
717 GATE(CLK_SCLK_AUDIO0
, "sclk_audio0", "div_sclk_audio0",
718 MUX_ENABLE_TOP_PERIC1
, 0, 0, 0),
722 * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
723 * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
725 static struct samsung_pll_rate_table exynos5443_pll_rates
[] = {
726 PLL_35XX_RATE(2500000000U, 625, 6, 0),
727 PLL_35XX_RATE(2400000000U, 500, 5, 0),
728 PLL_35XX_RATE(2300000000U, 575, 6, 0),
729 PLL_35XX_RATE(2200000000U, 550, 6, 0),
730 PLL_35XX_RATE(2100000000U, 350, 4, 0),
731 PLL_35XX_RATE(2000000000U, 500, 6, 0),
732 PLL_35XX_RATE(1900000000U, 475, 6, 0),
733 PLL_35XX_RATE(1800000000U, 375, 5, 0),
734 PLL_35XX_RATE(1700000000U, 425, 6, 0),
735 PLL_35XX_RATE(1600000000U, 400, 6, 0),
736 PLL_35XX_RATE(1500000000U, 250, 4, 0),
737 PLL_35XX_RATE(1400000000U, 350, 6, 0),
738 PLL_35XX_RATE(1332000000U, 222, 4, 0),
739 PLL_35XX_RATE(1300000000U, 325, 6, 0),
740 PLL_35XX_RATE(1200000000U, 500, 5, 1),
741 PLL_35XX_RATE(1100000000U, 550, 6, 1),
742 PLL_35XX_RATE(1086000000U, 362, 4, 1),
743 PLL_35XX_RATE(1066000000U, 533, 6, 1),
744 PLL_35XX_RATE(1000000000U, 500, 6, 1),
745 PLL_35XX_RATE(933000000U, 311, 4, 1),
746 PLL_35XX_RATE(921000000U, 307, 4, 1),
747 PLL_35XX_RATE(900000000U, 375, 5, 1),
748 PLL_35XX_RATE(825000000U, 275, 4, 1),
749 PLL_35XX_RATE(800000000U, 400, 6, 1),
750 PLL_35XX_RATE(733000000U, 733, 12, 1),
751 PLL_35XX_RATE(700000000U, 175, 3, 1),
752 PLL_35XX_RATE(667000000U, 222, 4, 1),
753 PLL_35XX_RATE(633000000U, 211, 4, 1),
754 PLL_35XX_RATE(600000000U, 500, 5, 2),
755 PLL_35XX_RATE(552000000U, 460, 5, 2),
756 PLL_35XX_RATE(550000000U, 550, 6, 2),
757 PLL_35XX_RATE(543000000U, 362, 4, 2),
758 PLL_35XX_RATE(533000000U, 533, 6, 2),
759 PLL_35XX_RATE(500000000U, 500, 6, 2),
760 PLL_35XX_RATE(444000000U, 370, 5, 2),
761 PLL_35XX_RATE(420000000U, 350, 5, 2),
762 PLL_35XX_RATE(400000000U, 400, 6, 2),
763 PLL_35XX_RATE(350000000U, 350, 6, 2),
764 PLL_35XX_RATE(333000000U, 222, 4, 2),
765 PLL_35XX_RATE(300000000U, 500, 5, 3),
766 PLL_35XX_RATE(266000000U, 532, 6, 3),
767 PLL_35XX_RATE(200000000U, 400, 6, 3),
768 PLL_35XX_RATE(166000000U, 332, 6, 3),
769 PLL_35XX_RATE(160000000U, 320, 6, 3),
770 PLL_35XX_RATE(133000000U, 532, 6, 4),
771 PLL_35XX_RATE(100000000U, 400, 6, 4),
776 static struct samsung_pll_rate_table exynos5443_aud_pll_rates
[] = {
777 PLL_36XX_RATE(400000000U, 200, 3, 2, 0),
778 PLL_36XX_RATE(393216000U, 197, 3, 2, -25690),
779 PLL_36XX_RATE(384000000U, 128, 2, 2, 0),
780 PLL_36XX_RATE(368640000U, 246, 4, 2, -15729),
781 PLL_36XX_RATE(361507200U, 181, 3, 2, -16148),
782 PLL_36XX_RATE(338688000U, 113, 2, 2, -6816),
783 PLL_36XX_RATE(294912000U, 98, 1, 3, 19923),
784 PLL_36XX_RATE(288000000U, 96, 1, 3, 0),
785 PLL_36XX_RATE(252000000U, 84, 1, 3, 0),
789 static struct samsung_pll_clock top_pll_clks
[] __initdata
= {
790 PLL(pll_35xx
, CLK_FOUT_ISP_PLL
, "fout_isp_pll", "oscclk",
791 ISP_PLL_LOCK
, ISP_PLL_CON0
, exynos5443_pll_rates
),
792 PLL(pll_36xx
, CLK_FOUT_AUD_PLL
, "fout_aud_pll", "oscclk",
793 AUD_PLL_LOCK
, AUD_PLL_CON0
, exynos5443_aud_pll_rates
),
796 static struct samsung_cmu_info top_cmu_info __initdata
= {
797 .pll_clks
= top_pll_clks
,
798 .nr_pll_clks
= ARRAY_SIZE(top_pll_clks
),
799 .mux_clks
= top_mux_clks
,
800 .nr_mux_clks
= ARRAY_SIZE(top_mux_clks
),
801 .div_clks
= top_div_clks
,
802 .nr_div_clks
= ARRAY_SIZE(top_div_clks
),
803 .gate_clks
= top_gate_clks
,
804 .nr_gate_clks
= ARRAY_SIZE(top_gate_clks
),
805 .fixed_clks
= top_fixed_clks
,
806 .nr_fixed_clks
= ARRAY_SIZE(top_fixed_clks
),
807 .fixed_factor_clks
= top_fixed_factor_clks
,
808 .nr_fixed_factor_clks
= ARRAY_SIZE(top_fixed_factor_clks
),
809 .nr_clk_ids
= TOP_NR_CLK
,
810 .clk_regs
= top_clk_regs
,
811 .nr_clk_regs
= ARRAY_SIZE(top_clk_regs
),
814 static void __init
exynos5433_cmu_top_init(struct device_node
*np
)
816 samsung_cmu_register_one(np
, &top_cmu_info
);
818 CLK_OF_DECLARE(exynos5433_cmu_top
, "samsung,exynos5433-cmu-top",
819 exynos5433_cmu_top_init
);
822 * Register offset definitions for CMU_CPIF
824 #define MPHY_PLL_LOCK 0x0000
825 #define MPHY_PLL_CON0 0x0100
826 #define MPHY_PLL_CON1 0x0104
827 #define MPHY_PLL_FREQ_DET 0x010c
828 #define MUX_SEL_CPIF0 0x0200
829 #define DIV_CPIF 0x0600
830 #define ENABLE_SCLK_CPIF 0x0a00
832 static unsigned long cpif_clk_regs
[] __initdata
= {
842 /* list of all parent clock list */
843 PNAME(mout_mphy_pll_p
) = { "oscclk", "fout_mphy_pll", };
845 static struct samsung_pll_clock cpif_pll_clks
[] __initdata
= {
846 PLL(pll_35xx
, CLK_FOUT_MPHY_PLL
, "fout_mphy_pll", "oscclk",
847 MPHY_PLL_LOCK
, MPHY_PLL_CON0
, exynos5443_pll_rates
),
850 static struct samsung_mux_clock cpif_mux_clks
[] __initdata
= {
852 MUX(CLK_MOUT_MPHY_PLL
, "mout_mphy_pll", mout_mphy_pll_p
, MUX_SEL_CPIF0
,
856 static struct samsung_div_clock cpif_div_clks
[] __initdata
= {
858 DIV(CLK_DIV_SCLK_MPHY
, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF
,
862 static struct samsung_gate_clock cpif_gate_clks
[] __initdata
= {
863 /* ENABLE_SCLK_CPIF */
864 GATE(CLK_SCLK_MPHY_PLL
, "sclk_mphy_pll", "mout_mphy_pll",
865 ENABLE_SCLK_CPIF
, 9, 0, 0),
866 GATE(CLK_SCLK_UFS_MPHY
, "sclk_ufs_mphy", "div_sclk_mphy",
867 ENABLE_SCLK_CPIF
, 4, 0, 0),
870 static struct samsung_cmu_info cpif_cmu_info __initdata
= {
871 .pll_clks
= cpif_pll_clks
,
872 .nr_pll_clks
= ARRAY_SIZE(cpif_pll_clks
),
873 .mux_clks
= cpif_mux_clks
,
874 .nr_mux_clks
= ARRAY_SIZE(cpif_mux_clks
),
875 .div_clks
= cpif_div_clks
,
876 .nr_div_clks
= ARRAY_SIZE(cpif_div_clks
),
877 .gate_clks
= cpif_gate_clks
,
878 .nr_gate_clks
= ARRAY_SIZE(cpif_gate_clks
),
879 .nr_clk_ids
= CPIF_NR_CLK
,
880 .clk_regs
= cpif_clk_regs
,
881 .nr_clk_regs
= ARRAY_SIZE(cpif_clk_regs
),
884 static void __init
exynos5433_cmu_cpif_init(struct device_node
*np
)
886 samsung_cmu_register_one(np
, &cpif_cmu_info
);
888 CLK_OF_DECLARE(exynos5433_cmu_cpif
, "samsung,exynos5433-cmu-cpif",
889 exynos5433_cmu_cpif_init
);
892 * Register offset definitions for CMU_MIF
894 #define MEM0_PLL_LOCK 0x0000
895 #define MEM1_PLL_LOCK 0x0004
896 #define BUS_PLL_LOCK 0x0008
897 #define MFC_PLL_LOCK 0x000c
898 #define MEM0_PLL_CON0 0x0100
899 #define MEM0_PLL_CON1 0x0104
900 #define MEM0_PLL_FREQ_DET 0x010c
901 #define MEM1_PLL_CON0 0x0110
902 #define MEM1_PLL_CON1 0x0114
903 #define MEM1_PLL_FREQ_DET 0x011c
904 #define BUS_PLL_CON0 0x0120
905 #define BUS_PLL_CON1 0x0124
906 #define BUS_PLL_FREQ_DET 0x012c
907 #define MFC_PLL_CON0 0x0130
908 #define MFC_PLL_CON1 0x0134
909 #define MFC_PLL_FREQ_DET 0x013c
910 #define MUX_SEL_MIF0 0x0200
911 #define MUX_SEL_MIF1 0x0204
912 #define MUX_SEL_MIF2 0x0208
913 #define MUX_SEL_MIF3 0x020c
914 #define MUX_SEL_MIF4 0x0210
915 #define MUX_SEL_MIF5 0x0214
916 #define MUX_SEL_MIF6 0x0218
917 #define MUX_SEL_MIF7 0x021c
918 #define MUX_ENABLE_MIF0 0x0300
919 #define MUX_ENABLE_MIF1 0x0304
920 #define MUX_ENABLE_MIF2 0x0308
921 #define MUX_ENABLE_MIF3 0x030c
922 #define MUX_ENABLE_MIF4 0x0310
923 #define MUX_ENABLE_MIF5 0x0314
924 #define MUX_ENABLE_MIF6 0x0318
925 #define MUX_ENABLE_MIF7 0x031c
926 #define MUX_STAT_MIF0 0x0400
927 #define MUX_STAT_MIF1 0x0404
928 #define MUX_STAT_MIF2 0x0408
929 #define MUX_STAT_MIF3 0x040c
930 #define MUX_STAT_MIF4 0x0410
931 #define MUX_STAT_MIF5 0x0414
932 #define MUX_STAT_MIF6 0x0418
933 #define MUX_STAT_MIF7 0x041c
934 #define DIV_MIF1 0x0604
935 #define DIV_MIF2 0x0608
936 #define DIV_MIF3 0x060c
937 #define DIV_MIF4 0x0610
938 #define DIV_MIF5 0x0614
939 #define DIV_MIF_PLL_FREQ_DET 0x0618
940 #define DIV_STAT_MIF1 0x0704
941 #define DIV_STAT_MIF2 0x0708
942 #define DIV_STAT_MIF3 0x070c
943 #define DIV_STAT_MIF4 0x0710
944 #define DIV_STAT_MIF5 0x0714
945 #define DIV_STAT_MIF_PLL_FREQ_DET 0x0718
946 #define ENABLE_ACLK_MIF0 0x0800
947 #define ENABLE_ACLK_MIF1 0x0804
948 #define ENABLE_ACLK_MIF2 0x0808
949 #define ENABLE_ACLK_MIF3 0x080c
950 #define ENABLE_PCLK_MIF 0x0900
951 #define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904
952 #define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908
953 #define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c
954 #define ENABLE_PCLK_MIF_SECURE_RTC 0x0910
955 #define ENABLE_SCLK_MIF 0x0a00
956 #define ENABLE_IP_MIF0 0x0b00
957 #define ENABLE_IP_MIF1 0x0b04
958 #define ENABLE_IP_MIF2 0x0b08
959 #define ENABLE_IP_MIF3 0x0b0c
960 #define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10
961 #define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14
962 #define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18
963 #define ENABLE_IP_MIF_SECURE_RTC 0x0b1c
964 #define CLKOUT_CMU_MIF 0x0c00
965 #define CLKOUT_CMU_MIF_DIV_STAT 0x0c04
966 #define DREX_FREQ_CTRL0 0x1000
967 #define DREX_FREQ_CTRL1 0x1004
969 #define DDRPHY_LOCK_CTRL 0x100c
971 static unsigned long mif_clk_regs
[] __initdata
= {
1017 DIV_MIF_PLL_FREQ_DET
,
1023 DIV_STAT_MIF_PLL_FREQ_DET
,
1029 ENABLE_PCLK_MIF_SECURE_DREX0_TZ
,
1030 ENABLE_PCLK_MIF_SECURE_DREX1_TZ
,
1031 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT
,
1032 ENABLE_PCLK_MIF_SECURE_RTC
,
1038 ENABLE_IP_MIF_SECURE_DREX0_TZ
,
1039 ENABLE_IP_MIF_SECURE_DREX1_TZ
,
1040 ENABLE_IP_MIF_SECURE_MONOTONIC_CNT
,
1041 ENABLE_IP_MIF_SECURE_RTC
,
1043 CLKOUT_CMU_MIF_DIV_STAT
,
1050 static struct samsung_pll_clock mif_pll_clks
[] __initdata
= {
1051 PLL(pll_35xx
, CLK_FOUT_MEM0_PLL
, "fout_mem0_pll", "oscclk",
1052 MEM0_PLL_LOCK
, MEM0_PLL_CON0
, exynos5443_pll_rates
),
1053 PLL(pll_35xx
, CLK_FOUT_MEM1_PLL
, "fout_mem1_pll", "oscclk",
1054 MEM1_PLL_LOCK
, MEM1_PLL_CON0
, exynos5443_pll_rates
),
1055 PLL(pll_35xx
, CLK_FOUT_BUS_PLL
, "fout_bus_pll", "oscclk",
1056 BUS_PLL_LOCK
, BUS_PLL_CON0
, exynos5443_pll_rates
),
1057 PLL(pll_35xx
, CLK_FOUT_MFC_PLL
, "fout_mfc_pll", "oscclk",
1058 MFC_PLL_LOCK
, MFC_PLL_CON0
, exynos5443_pll_rates
),
1061 /* list of all parent clock list */
1062 PNAME(mout_mfc_pll_div2_p
) = { "mout_mfc_pll", "dout_mfc_pll", };
1063 PNAME(mout_bus_pll_div2_p
) = { "mout_bus_pll", "dout_bus_pll", };
1064 PNAME(mout_mem1_pll_div2_p
) = { "mout_mem1_pll", "dout_mem1_pll", };
1065 PNAME(mout_mem0_pll_div2_p
) = { "mout_mem0_pll", "dout_mem0_pll", };
1066 PNAME(mout_mfc_pll_p
) = { "oscclk", "fout_mfc_pll", };
1067 PNAME(mout_bus_pll_p
) = { "oscclk", "fout_bus_pll", };
1068 PNAME(mout_mem1_pll_p
) = { "oscclk", "fout_mem1_pll", };
1069 PNAME(mout_mem0_pll_p
) = { "oscclk", "fout_mem0_pll", };
1071 PNAME(mout_clk2x_phy_c_p
) = { "mout_mem0_pll_div2", "mout_clkm_phy_b", };
1072 PNAME(mout_clk2x_phy_b_p
) = { "mout_bus_pll_div2", "mout_clkm_phy_a", };
1073 PNAME(mout_clk2x_phy_a_p
) = { "mout_bus_pll_div2", "mout_mfc_pll_div2", };
1074 PNAME(mout_clkm_phy_b_p
) = { "mout_mem1_pll_div2", "mout_clkm_phy_a", };
1076 PNAME(mout_aclk_mifnm_200_p
) = { "mout_mem0_pll_div2", "div_mif_pre", };
1077 PNAME(mout_aclk_mifnm_400_p
) = { "mout_mem1_pll_div2", "mout_bus_pll_div2",};
1079 PNAME(mout_aclk_disp_333_b_p
) = { "mout_aclk_disp_333_a",
1080 "mout_bus_pll_div2", };
1081 PNAME(mout_aclk_disp_333_a_p
) = { "mout_mfc_pll_div2", "sclk_mphy_pll", };
1083 PNAME(mout_sclk_decon_vclk_c_p
) = { "mout_sclk_decon_vclk_b",
1085 PNAME(mout_sclk_decon_vclk_b_p
) = { "mout_sclk_decon_vclk_a",
1086 "mout_mfc_pll_div2", };
1087 PNAME(mout_sclk_decon_p
) = { "oscclk", "mout_bus_pll_div2", };
1088 PNAME(mout_sclk_decon_eclk_c_p
) = { "mout_sclk_decon_eclk_b",
1090 PNAME(mout_sclk_decon_eclk_b_p
) = { "mout_sclk_decon_eclk_a",
1091 "mout_mfc_pll_div2", };
1093 PNAME(mout_sclk_decon_tv_eclk_c_p
) = { "mout_sclk_decon_tv_eclk_b",
1095 PNAME(mout_sclk_decon_tv_eclk_b_p
) = { "mout_sclk_decon_tv_eclk_a",
1096 "mout_mfc_pll_div2", };
1097 PNAME(mout_sclk_dsd_c_p
) = { "mout_sclk_dsd_b", "mout_bus_pll_div2", };
1098 PNAME(mout_sclk_dsd_b_p
) = { "mout_sclk_dsd_a", "sclk_mphy_pll", };
1099 PNAME(mout_sclk_dsd_a_p
) = { "oscclk", "mout_mfc_pll_div2", };
1101 PNAME(mout_sclk_dsim0_c_p
) = { "mout_sclk_dsim0_b", "sclk_mphy_pll", };
1102 PNAME(mout_sclk_dsim0_b_p
) = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" };
1104 PNAME(mout_sclk_decon_tv_vclk_c_p
) = { "mout_sclk_decon_tv_vclk_b",
1106 PNAME(mout_sclk_decon_tv_vclk_b_p
) = { "mout_sclk_decon_tv_vclk_a",
1107 "mout_mfc_pll_div2", };
1108 PNAME(mout_sclk_dsim1_c_p
) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", };
1109 PNAME(mout_sclk_dsim1_b_p
) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",};
1111 static struct samsung_fixed_factor_clock mif_fixed_factor_clks
[] __initdata
= {
1112 /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
1113 FFACTOR(CLK_DOUT_MFC_PLL
, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
1114 FFACTOR(CLK_DOUT_BUS_PLL
, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
1115 FFACTOR(CLK_DOUT_MEM1_PLL
, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0),
1116 FFACTOR(CLK_DOUT_MEM0_PLL
, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
1119 static struct samsung_mux_clock mif_mux_clks
[] __initdata
= {
1121 MUX(CLK_MOUT_MFC_PLL_DIV2
, "mout_mfc_pll_div2", mout_mfc_pll_div2_p
,
1122 MUX_SEL_MIF0
, 28, 1),
1123 MUX(CLK_MOUT_BUS_PLL_DIV2
, "mout_bus_pll_div2", mout_bus_pll_div2_p
,
1124 MUX_SEL_MIF0
, 24, 1),
1125 MUX(CLK_MOUT_MEM1_PLL_DIV2
, "mout_mem1_pll_div2", mout_mem1_pll_div2_p
,
1126 MUX_SEL_MIF0
, 20, 1),
1127 MUX(CLK_MOUT_MEM0_PLL_DIV2
, "mout_mem0_pll_div2", mout_mem0_pll_div2_p
,
1128 MUX_SEL_MIF0
, 16, 1),
1129 MUX(CLK_MOUT_MFC_PLL
, "mout_mfc_pll", mout_mfc_pll_p
, MUX_SEL_MIF0
,
1131 MUX(CLK_MOUT_BUS_PLL
, "mout_bus_pll", mout_bus_pll_p
, MUX_SEL_MIF0
,
1133 MUX(CLK_MOUT_MEM1_PLL
, "mout_mem1_pll", mout_mem1_pll_p
, MUX_SEL_MIF0
,
1135 MUX(CLK_MOUT_MEM0_PLL
, "mout_mem0_pll", mout_mem0_pll_p
, MUX_SEL_MIF0
,
1139 MUX(CLK_MOUT_CLK2X_PHY_C
, "mout_clk2x_phy_c", mout_clk2x_phy_c_p
,
1140 MUX_SEL_MIF1
, 24, 1),
1141 MUX(CLK_MOUT_CLK2X_PHY_B
, "mout_clk2x_phy_b", mout_clk2x_phy_b_p
,
1142 MUX_SEL_MIF1
, 20, 1),
1143 MUX(CLK_MOUT_CLK2X_PHY_A
, "mout_clk2x_phy_a", mout_clk2x_phy_a_p
,
1144 MUX_SEL_MIF1
, 16, 1),
1145 MUX(CLK_MOUT_CLKM_PHY_C
, "mout_clkm_phy_c", mout_clk2x_phy_c_p
,
1146 MUX_SEL_MIF1
, 12, 1),
1147 MUX(CLK_MOUT_CLKM_PHY_B
, "mout_clkm_phy_b", mout_clkm_phy_b_p
,
1148 MUX_SEL_MIF1
, 8, 1),
1149 MUX(CLK_MOUT_CLKM_PHY_A
, "mout_clkm_phy_a", mout_clk2x_phy_a_p
,
1150 MUX_SEL_MIF1
, 4, 1),
1153 MUX(CLK_MOUT_ACLK_MIFNM_200
, "mout_aclk_mifnm_200",
1154 mout_aclk_mifnm_200_p
, MUX_SEL_MIF2
, 8, 1),
1155 MUX(CLK_MOUT_ACLK_MIFNM_400
, "mout_aclk_mifnm_400",
1156 mout_aclk_mifnm_400_p
, MUX_SEL_MIF2
, 0, 1),
1159 MUX(CLK_MOUT_ACLK_DISP_333_B
, "mout_aclk_disp_333_b",
1160 mout_aclk_disp_333_b_p
, MUX_SEL_MIF3
, 4, 1),
1161 MUX(CLK_MOUT_ACLK_DISP_333_A
, "mout_aclk_disp_333_a",
1162 mout_aclk_disp_333_a_p
, MUX_SEL_MIF3
, 0, 1),
1165 MUX(CLK_MOUT_SCLK_DECON_VCLK_C
, "mout_sclk_decon_vclk_c",
1166 mout_sclk_decon_vclk_c_p
, MUX_SEL_MIF4
, 24, 1),
1167 MUX(CLK_MOUT_SCLK_DECON_VCLK_B
, "mout_sclk_decon_vclk_b",
1168 mout_sclk_decon_vclk_b_p
, MUX_SEL_MIF4
, 20, 1),
1169 MUX(CLK_MOUT_SCLK_DECON_VCLK_A
, "mout_sclk_decon_vclk_a",
1170 mout_sclk_decon_p
, MUX_SEL_MIF4
, 16, 1),
1171 MUX(CLK_MOUT_SCLK_DECON_ECLK_C
, "mout_sclk_decon_eclk_c",
1172 mout_sclk_decon_eclk_c_p
, MUX_SEL_MIF4
, 8, 1),
1173 MUX(CLK_MOUT_SCLK_DECON_ECLK_B
, "mout_sclk_decon_eclk_b",
1174 mout_sclk_decon_eclk_b_p
, MUX_SEL_MIF4
, 4, 1),
1175 MUX(CLK_MOUT_SCLK_DECON_ECLK_A
, "mout_sclk_decon_eclk_a",
1176 mout_sclk_decon_p
, MUX_SEL_MIF4
, 0, 1),
1179 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C
, "mout_sclk_decon_tv_eclk_c",
1180 mout_sclk_decon_tv_eclk_c_p
, MUX_SEL_MIF5
, 24, 1),
1181 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B
, "mout_sclk_decon_tv_eclk_b",
1182 mout_sclk_decon_tv_eclk_b_p
, MUX_SEL_MIF5
, 20, 1),
1183 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A
, "mout_sclk_decon_tv_eclk_a",
1184 mout_sclk_decon_p
, MUX_SEL_MIF5
, 16, 1),
1185 MUX(CLK_MOUT_SCLK_DSD_C
, "mout_sclk_dsd_c", mout_sclk_dsd_c_p
,
1186 MUX_SEL_MIF5
, 8, 1),
1187 MUX(CLK_MOUT_SCLK_DSD_B
, "mout_sclk_dsd_b", mout_sclk_dsd_b_p
,
1188 MUX_SEL_MIF5
, 4, 1),
1189 MUX(CLK_MOUT_SCLK_DSD_A
, "mout_sclk_dsd_a", mout_sclk_dsd_a_p
,
1190 MUX_SEL_MIF5
, 0, 1),
1193 MUX(CLK_MOUT_SCLK_DSIM0_C
, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p
,
1194 MUX_SEL_MIF6
, 8, 1),
1195 MUX(CLK_MOUT_SCLK_DSIM0_B
, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p
,
1196 MUX_SEL_MIF6
, 4, 1),
1197 MUX(CLK_MOUT_SCLK_DSIM0_A
, "mout_sclk_dsim0_a", mout_sclk_decon_p
,
1198 MUX_SEL_MIF6
, 0, 1),
1201 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C
, "mout_sclk_decon_tv_vclk_c",
1202 mout_sclk_decon_tv_vclk_c_p
, MUX_SEL_MIF7
, 24, 1),
1203 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B
, "mout_sclk_decon_tv_vclk_b",
1204 mout_sclk_decon_tv_vclk_b_p
, MUX_SEL_MIF7
, 20, 1),
1205 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A
, "mout_sclk_decon_tv_vclk_a",
1206 mout_sclk_decon_p
, MUX_SEL_MIF7
, 16, 1),
1207 MUX(CLK_MOUT_SCLK_DSIM1_C
, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p
,
1208 MUX_SEL_MIF7
, 8, 1),
1209 MUX(CLK_MOUT_SCLK_DSIM1_B
, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p
,
1210 MUX_SEL_MIF7
, 4, 1),
1211 MUX(CLK_MOUT_SCLK_DSIM1_A
, "mout_sclk_dsim1_a", mout_sclk_decon_p
,
1212 MUX_SEL_MIF7
, 0, 1),
1215 static struct samsung_div_clock mif_div_clks
[] __initdata
= {
1217 DIV(CLK_DIV_SCLK_HPM_MIF
, "div_sclk_hpm_mif", "div_clk2x_phy",
1219 DIV(CLK_DIV_ACLK_DREX1
, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1
,
1221 DIV(CLK_DIV_ACLK_DREX0
, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1
,
1223 DIV(CLK_DIV_CLK2XPHY
, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1
,
1227 DIV(CLK_DIV_ACLK_MIF_266
, "div_aclk_mif_266", "mout_bus_pll_div2",
1229 DIV(CLK_DIV_ACLK_MIFND_133
, "div_aclk_mifnd_133", "div_mif_pre",
1231 DIV(CLK_DIV_ACLK_MIF_133
, "div_aclk_mif_133", "div_mif_pre",
1233 DIV(CLK_DIV_ACLK_MIFNM_200
, "div_aclk_mifnm_200",
1234 "mout_aclk_mifnm_200", DIV_MIF2
, 8, 3),
1235 DIV(CLK_DIV_ACLK_MIF_200
, "div_aclk_mif_200", "div_aclk_mif_400",
1237 DIV(CLK_DIV_ACLK_MIF_400
, "div_aclk_mif_400", "mout_aclk_mifnm_400",
1241 DIV(CLK_DIV_ACLK_BUS2_400
, "div_aclk_bus2_400", "div_mif_pre",
1243 DIV(CLK_DIV_ACLK_DISP_333
, "div_aclk_disp_333", "mout_aclk_disp_333_b",
1245 DIV(CLK_DIV_ACLK_CPIF_200
, "div_aclk_cpif_200", "mout_aclk_mifnm_200",
1249 DIV(CLK_DIV_SCLK_DSIM1
, "div_sclk_dsim1", "mout_sclk_dsim1_c",
1251 DIV(CLK_DIV_SCLK_DECON_TV_VCLK
, "div_sclk_decon_tv_vclk",
1252 "mout_sclk_decon_tv_vclk_c", DIV_MIF4
, 20, 4),
1253 DIV(CLK_DIV_SCLK_DSIM0
, "div_sclk_dsim0", "mout_sclk_dsim0_c",
1255 DIV(CLK_DIV_SCLK_DSD
, "div_sclk_dsd", "mout_sclk_dsd_c",
1257 DIV(CLK_DIV_SCLK_DECON_TV_ECLK
, "div_sclk_decon_tv_eclk",
1258 "mout_sclk_decon_tv_eclk_c", DIV_MIF4
, 8, 4),
1259 DIV(CLK_DIV_SCLK_DECON_VCLK
, "div_sclk_decon_vclk",
1260 "mout_sclk_decon_vclk_c", DIV_MIF4
, 4, 4),
1261 DIV(CLK_DIV_SCLK_DECON_ECLK
, "div_sclk_decon_eclk",
1262 "mout_sclk_decon_eclk_c", DIV_MIF4
, 0, 4),
1265 DIV(CLK_DIV_MIF_PRE
, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5
,
1269 static struct samsung_gate_clock mif_gate_clks
[] __initdata
= {
1270 /* ENABLE_ACLK_MIF0 */
1271 GATE(CLK_CLK2X_PHY1
, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0
,
1272 19, CLK_IGNORE_UNUSED
, 0),
1273 GATE(CLK_CLK2X_PHY0
, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0
,
1274 18, CLK_IGNORE_UNUSED
, 0),
1275 GATE(CLK_CLKM_PHY1
, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0
,
1276 17, CLK_IGNORE_UNUSED
, 0),
1277 GATE(CLK_CLKM_PHY0
, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0
,
1278 16, CLK_IGNORE_UNUSED
, 0),
1279 GATE(CLK_RCLK_DREX1
, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0
,
1280 15, CLK_IGNORE_UNUSED
, 0),
1281 GATE(CLK_RCLK_DREX0
, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0
,
1282 14, CLK_IGNORE_UNUSED
, 0),
1283 GATE(CLK_ACLK_DREX1_TZ
, "aclk_drex1_tz", "div_aclk_drex1",
1284 ENABLE_ACLK_MIF0
, 13, CLK_IGNORE_UNUSED
, 0),
1285 GATE(CLK_ACLK_DREX0_TZ
, "aclk_drex0_tz", "div_aclk_drex0",
1286 ENABLE_ACLK_MIF0
, 12, CLK_IGNORE_UNUSED
, 0),
1287 GATE(CLK_ACLK_DREX1_PEREV
, "aclk_drex1_perev", "div_aclk_drex1",
1288 ENABLE_ACLK_MIF0
, 11, CLK_IGNORE_UNUSED
, 0),
1289 GATE(CLK_ACLK_DREX0_PEREV
, "aclk_drex0_perev", "div_aclk_drex0",
1290 ENABLE_ACLK_MIF0
, 10, CLK_IGNORE_UNUSED
, 0),
1291 GATE(CLK_ACLK_DREX1_MEMIF
, "aclk_drex1_memif", "div_aclk_drex1",
1292 ENABLE_ACLK_MIF0
, 9, CLK_IGNORE_UNUSED
, 0),
1293 GATE(CLK_ACLK_DREX0_MEMIF
, "aclk_drex0_memif", "div_aclk_drex0",
1294 ENABLE_ACLK_MIF0
, 8, CLK_IGNORE_UNUSED
, 0),
1295 GATE(CLK_ACLK_DREX1_SCH
, "aclk_drex1_sch", "div_aclk_drex1",
1296 ENABLE_ACLK_MIF0
, 7, CLK_IGNORE_UNUSED
, 0),
1297 GATE(CLK_ACLK_DREX0_SCH
, "aclk_drex0_sch", "div_aclk_drex0",
1298 ENABLE_ACLK_MIF0
, 6, CLK_IGNORE_UNUSED
, 0),
1299 GATE(CLK_ACLK_DREX1_BUSIF
, "aclk_drex1_busif", "div_aclk_drex1",
1300 ENABLE_ACLK_MIF0
, 5, CLK_IGNORE_UNUSED
, 0),
1301 GATE(CLK_ACLK_DREX0_BUSIF
, "aclk_drex0_busif", "div_aclk_drex0",
1302 ENABLE_ACLK_MIF0
, 4, CLK_IGNORE_UNUSED
, 0),
1303 GATE(CLK_ACLK_DREX1_BUSIF_RD
, "aclk_drex1_busif_rd", "div_aclk_drex1",
1304 ENABLE_ACLK_MIF0
, 3, CLK_IGNORE_UNUSED
, 0),
1305 GATE(CLK_ACLK_DREX0_BUSIF_RD
, "aclk_drex0_busif_rd", "div_aclk_drex0",
1306 ENABLE_ACLK_MIF0
, 2, CLK_IGNORE_UNUSED
, 0),
1307 GATE(CLK_ACLK_DREX1
, "aclk_drex1", "div_aclk_drex1",
1308 ENABLE_ACLK_MIF0
, 2, CLK_IGNORE_UNUSED
, 0),
1309 GATE(CLK_ACLK_DREX0
, "aclk_drex0", "div_aclk_drex0",
1310 ENABLE_ACLK_MIF0
, 1, CLK_IGNORE_UNUSED
, 0),
1312 /* ENABLE_ACLK_MIF1 */
1313 GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM
, "aclk_asyncaxis_mif_imem",
1314 "div_aclk_mif_200", ENABLE_ACLK_MIF1
, 28,
1315 CLK_IGNORE_UNUSED
, 0),
1316 GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI
, "aclk_asyncaxis_noc_p_cci",
1317 "div_aclk_mif_200", ENABLE_ACLK_MIF1
,
1318 27, CLK_IGNORE_UNUSED
, 0),
1319 GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI
, "aclk_asyncaxim_noc_p_cci",
1320 "div_aclk_mif_133", ENABLE_ACLK_MIF1
,
1321 26, CLK_IGNORE_UNUSED
, 0),
1322 GATE(CLK_ACLK_ASYNCAXIS_CP1
, "aclk_asyncaxis_cp1",
1323 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1
,
1324 25, CLK_IGNORE_UNUSED
, 0),
1325 GATE(CLK_ACLK_ASYNCAXIM_CP1
, "aclk_asyncaxim_cp1",
1326 "div_aclk_drex1", ENABLE_ACLK_MIF1
,
1327 24, CLK_IGNORE_UNUSED
, 0),
1328 GATE(CLK_ACLK_ASYNCAXIS_CP0
, "aclk_asyncaxis_cp0",
1329 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1
,
1330 23, CLK_IGNORE_UNUSED
, 0),
1331 GATE(CLK_ACLK_ASYNCAXIM_CP0
, "aclk_asyncaxim_cp0",
1332 "div_aclk_drex0", ENABLE_ACLK_MIF1
,
1333 22, CLK_IGNORE_UNUSED
, 0),
1334 GATE(CLK_ACLK_ASYNCAXIS_DREX1_3
, "aclk_asyncaxis_drex1_3",
1335 "div_aclk_mif_133", ENABLE_ACLK_MIF1
,
1336 21, CLK_IGNORE_UNUSED
, 0),
1337 GATE(CLK_ACLK_ASYNCAXIM_DREX1_3
, "aclk_asyncaxim_drex1_3",
1338 "div_aclk_drex1", ENABLE_ACLK_MIF1
,
1339 20, CLK_IGNORE_UNUSED
, 0),
1340 GATE(CLK_ACLK_ASYNCAXIS_DREX1_1
, "aclk_asyncaxis_drex1_1",
1341 "div_aclk_mif_133", ENABLE_ACLK_MIF1
,
1342 19, CLK_IGNORE_UNUSED
, 0),
1343 GATE(CLK_ACLK_ASYNCAXIM_DREX1_1
, "aclk_asyncaxim_drex1_1",
1344 "div_aclk_drex1", ENABLE_ACLK_MIF1
,
1345 18, CLK_IGNORE_UNUSED
, 0),
1346 GATE(CLK_ACLK_ASYNCAXIS_DREX1_0
, "aclk_asyncaxis_drex1_0",
1347 "div_aclk_mif_133", ENABLE_ACLK_MIF1
,
1348 17, CLK_IGNORE_UNUSED
, 0),
1349 GATE(CLK_ACLK_ASYNCAXIM_DREX1_0
, "aclk_asyncaxim_drex1_0",
1350 "div_aclk_drex1", ENABLE_ACLK_MIF1
,
1351 16, CLK_IGNORE_UNUSED
, 0),
1352 GATE(CLK_ACLK_ASYNCAXIS_DREX0_3
, "aclk_asyncaxis_drex0_3",
1353 "div_aclk_mif_133", ENABLE_ACLK_MIF1
,
1354 15, CLK_IGNORE_UNUSED
, 0),
1355 GATE(CLK_ACLK_ASYNCAXIM_DREX0_3
, "aclk_asyncaxim_drex0_3",
1356 "div_aclk_drex0", ENABLE_ACLK_MIF1
,
1357 14, CLK_IGNORE_UNUSED
, 0),
1358 GATE(CLK_ACLK_ASYNCAXIS_DREX0_1
, "aclk_asyncaxis_drex0_1",
1359 "div_aclk_mif_133", ENABLE_ACLK_MIF1
,
1360 13, CLK_IGNORE_UNUSED
, 0),
1361 GATE(CLK_ACLK_ASYNCAXIM_DREX0_1
, "aclk_asyncaxim_drex0_1",
1362 "div_aclk_drex0", ENABLE_ACLK_MIF1
,
1363 12, CLK_IGNORE_UNUSED
, 0),
1364 GATE(CLK_ACLK_ASYNCAXIS_DREX0_0
, "aclk_asyncaxis_drex0_0",
1365 "div_aclk_mif_133", ENABLE_ACLK_MIF1
,
1366 11, CLK_IGNORE_UNUSED
, 0),
1367 GATE(CLK_ACLK_ASYNCAXIM_DREX0_0
, "aclk_asyncaxim_drex0_0",
1368 "div_aclk_drex0", ENABLE_ACLK_MIF1
,
1369 10, CLK_IGNORE_UNUSED
, 0),
1370 GATE(CLK_ACLK_AHB2APB_MIF2P
, "aclk_ahb2apb_mif2p", "div_aclk_mif_133",
1371 ENABLE_ACLK_MIF1
, 9, CLK_IGNORE_UNUSED
, 0),
1372 GATE(CLK_ACLK_AHB2APB_MIF1P
, "aclk_ahb2apb_mif1p", "div_aclk_mif_133",
1373 ENABLE_ACLK_MIF1
, 8, CLK_IGNORE_UNUSED
, 0),
1374 GATE(CLK_ACLK_AHB2APB_MIF0P
, "aclk_ahb2apb_mif0p", "div_aclk_mif_133",
1375 ENABLE_ACLK_MIF1
, 7, CLK_IGNORE_UNUSED
, 0),
1376 GATE(CLK_ACLK_IXIU_CCI
, "aclk_ixiu_cci", "div_aclk_mif_400",
1377 ENABLE_ACLK_MIF1
, 6, CLK_IGNORE_UNUSED
, 0),
1378 GATE(CLK_ACLK_XIU_MIFSFRX
, "aclk_xiu_mifsfrx", "div_aclk_mif_200",
1379 ENABLE_ACLK_MIF1
, 5, CLK_IGNORE_UNUSED
, 0),
1380 GATE(CLK_ACLK_MIFNP_133
, "aclk_mifnp_133", "div_aclk_mif_133",
1381 ENABLE_ACLK_MIF1
, 4, CLK_IGNORE_UNUSED
, 0),
1382 GATE(CLK_ACLK_MIFNM_200
, "aclk_mifnm_200", "div_aclk_mifnm_200",
1383 ENABLE_ACLK_MIF1
, 3, CLK_IGNORE_UNUSED
, 0),
1384 GATE(CLK_ACLK_MIFND_133
, "aclk_mifnd_133", "div_aclk_mifnd_133",
1385 ENABLE_ACLK_MIF1
, 2, CLK_IGNORE_UNUSED
, 0),
1386 GATE(CLK_ACLK_MIFND_400
, "aclk_mifnd_400", "div_aclk_mif_400",
1387 ENABLE_ACLK_MIF1
, 1, CLK_IGNORE_UNUSED
, 0),
1388 GATE(CLK_ACLK_CCI
, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1
,
1389 0, CLK_IGNORE_UNUSED
, 0),
1391 /* ENABLE_ACLK_MIF2 */
1392 GATE(CLK_ACLK_MIFND_266
, "aclk_mifnd_266", "div_aclk_mif_266",
1393 ENABLE_ACLK_MIF2
, 20, CLK_IGNORE_UNUSED
, 0),
1394 GATE(CLK_ACLK_PPMU_DREX1S3
, "aclk_ppmu_drex1s3", "div_aclk_drex1",
1395 ENABLE_ACLK_MIF2
, 17, CLK_IGNORE_UNUSED
, 0),
1396 GATE(CLK_ACLK_PPMU_DREX1S1
, "aclk_ppmu_drex1s1", "div_aclk_drex1",
1397 ENABLE_ACLK_MIF2
, 16, CLK_IGNORE_UNUSED
, 0),
1398 GATE(CLK_ACLK_PPMU_DREX1S0
, "aclk_ppmu_drex1s0", "div_aclk_drex1",
1399 ENABLE_ACLK_MIF2
, 15, CLK_IGNORE_UNUSED
, 0),
1400 GATE(CLK_ACLK_PPMU_DREX0S3
, "aclk_ppmu_drex0s3", "div_aclk_drex0",
1401 ENABLE_ACLK_MIF2
, 14, CLK_IGNORE_UNUSED
, 0),
1402 GATE(CLK_ACLK_PPMU_DREX0S1
, "aclk_ppmu_drex0s1", "div_aclk_drex0",
1403 ENABLE_ACLK_MIF2
, 13, CLK_IGNORE_UNUSED
, 0),
1404 GATE(CLK_ACLK_PPMU_DREX0S0
, "aclk_ppmu_drex0s0", "div_aclk_drex0",
1405 ENABLE_ACLK_MIF2
, 12, CLK_IGNORE_UNUSED
, 0),
1406 GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX
, "aclk_axids_cci_mifsfrx",
1407 "div_aclk_mif_200", ENABLE_ACLK_MIF2
, 7,
1408 CLK_IGNORE_UNUSED
, 0),
1409 GATE(CLK_ACLK_AXISYNCDNS_CCI
, "aclk_axisyncdns_cci",
1410 "div_aclk_mif_400", ENABLE_ACLK_MIF2
,
1411 5, CLK_IGNORE_UNUSED
, 0),
1412 GATE(CLK_ACLK_AXISYNCDN_CCI
, "aclk_axisyncdn_cci", "div_aclk_mif_400",
1413 ENABLE_ACLK_MIF2
, 4, CLK_IGNORE_UNUSED
, 0),
1414 GATE(CLK_ACLK_AXISYNCDN_NOC_D
, "aclk_axisyncdn_noc_d",
1415 "div_aclk_mif_200", ENABLE_ACLK_MIF2
,
1416 3, CLK_IGNORE_UNUSED
, 0),
1417 GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS
, "aclk_asyncapbs_mif_cssys",
1418 "div_aclk_mifnd_133", ENABLE_ACLK_MIF2
, 0, 0, 0),
1420 /* ENABLE_ACLK_MIF3 */
1421 GATE(CLK_ACLK_BUS2_400
, "aclk_bus2_400", "div_aclk_bus2_400",
1422 ENABLE_ACLK_MIF3
, 4,
1423 CLK_IGNORE_UNUSED
| CLK_SET_RATE_PARENT
, 0),
1424 GATE(CLK_ACLK_DISP_333
, "aclk_disp_333", "div_aclk_disp_333",
1425 ENABLE_ACLK_MIF3
, 1,
1426 CLK_IGNORE_UNUSED
| CLK_SET_RATE_PARENT
, 0),
1427 GATE(CLK_ACLK_CPIF_200
, "aclk_cpif_200", "div_aclk_cpif_200",
1428 ENABLE_ACLK_MIF3
, 0,
1429 CLK_IGNORE_UNUSED
| CLK_SET_RATE_PARENT
, 0),
1431 /* ENABLE_PCLK_MIF */
1432 GATE(CLK_PCLK_PPMU_DREX1S3
, "pclk_ppmu_drex1s3", "div_aclk_drex1",
1433 ENABLE_PCLK_MIF
, 29, CLK_IGNORE_UNUSED
, 0),
1434 GATE(CLK_PCLK_PPMU_DREX1S1
, "pclk_ppmu_drex1s1", "div_aclk_drex1",
1435 ENABLE_PCLK_MIF
, 28, CLK_IGNORE_UNUSED
, 0),
1436 GATE(CLK_PCLK_PPMU_DREX1S0
, "pclk_ppmu_drex1s0", "div_aclk_drex1",
1437 ENABLE_PCLK_MIF
, 27, CLK_IGNORE_UNUSED
, 0),
1438 GATE(CLK_PCLK_PPMU_DREX0S3
, "pclk_ppmu_drex0s3", "div_aclk_drex0",
1439 ENABLE_PCLK_MIF
, 26, CLK_IGNORE_UNUSED
, 0),
1440 GATE(CLK_PCLK_PPMU_DREX0S1
, "pclk_ppmu_drex0s1", "div_aclk_drex0",
1441 ENABLE_PCLK_MIF
, 25, CLK_IGNORE_UNUSED
, 0),
1442 GATE(CLK_PCLK_PPMU_DREX0S0
, "pclk_ppmu_drex0s0", "div_aclk_drex0",
1443 ENABLE_PCLK_MIF
, 24, CLK_IGNORE_UNUSED
, 0),
1444 GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI
, "pclk_asyncaxi_noc_p_cci",
1445 "div_aclk_mif_133", ENABLE_PCLK_MIF
, 21,
1446 CLK_IGNORE_UNUSED
, 0),
1447 GATE(CLK_PCLK_ASYNCAXI_CP1
, "pclk_asyncaxi_cp1", "div_aclk_mif_133",
1448 ENABLE_PCLK_MIF
, 19, 0, 0),
1449 GATE(CLK_PCLK_ASYNCAXI_CP0
, "pclk_asyncaxi_cp0", "div_aclk_mif_133",
1450 ENABLE_PCLK_MIF
, 18, 0, 0),
1451 GATE(CLK_PCLK_ASYNCAXI_DREX1_3
, "pclk_asyncaxi_drex1_3",
1452 "div_aclk_mif_133", ENABLE_PCLK_MIF
, 17, 0, 0),
1453 GATE(CLK_PCLK_ASYNCAXI_DREX1_1
, "pclk_asyncaxi_drex1_1",
1454 "div_aclk_mif_133", ENABLE_PCLK_MIF
, 16, 0, 0),
1455 GATE(CLK_PCLK_ASYNCAXI_DREX1_0
, "pclk_asyncaxi_drex1_0",
1456 "div_aclk_mif_133", ENABLE_PCLK_MIF
, 15, 0, 0),
1457 GATE(CLK_PCLK_ASYNCAXI_DREX0_3
, "pclk_asyncaxi_drex0_3",
1458 "div_aclk_mif_133", ENABLE_PCLK_MIF
, 14, 0, 0),
1459 GATE(CLK_PCLK_ASYNCAXI_DREX0_1
, "pclk_asyncaxi_drex0_1",
1460 "div_aclk_mif_133", ENABLE_PCLK_MIF
, 13, 0, 0),
1461 GATE(CLK_PCLK_ASYNCAXI_DREX0_0
, "pclk_asyncaxi_drex0_0",
1462 "div_aclk_mif_133", ENABLE_PCLK_MIF
, 12, 0, 0),
1463 GATE(CLK_PCLK_MIFSRVND_133
, "pclk_mifsrvnd_133", "div_aclk_mif_133",
1464 ENABLE_PCLK_MIF
, 11, 0, 0),
1465 GATE(CLK_PCLK_PMU_MIF
, "pclk_pmu_mif", "div_aclk_mif_133",
1466 ENABLE_PCLK_MIF
, 10, CLK_IGNORE_UNUSED
, 0),
1467 GATE(CLK_PCLK_SYSREG_MIF
, "pclk_sysreg_mif", "div_aclk_mif_133",
1468 ENABLE_PCLK_MIF
, 9, CLK_IGNORE_UNUSED
, 0),
1469 GATE(CLK_PCLK_GPIO_ALIVE
, "pclk_gpio_alive", "div_aclk_mif_133",
1470 ENABLE_PCLK_MIF
, 8, CLK_IGNORE_UNUSED
, 0),
1471 GATE(CLK_PCLK_ABB
, "pclk_abb", "div_aclk_mif_133",
1472 ENABLE_PCLK_MIF
, 7, 0, 0),
1473 GATE(CLK_PCLK_PMU_APBIF
, "pclk_pmu_apbif", "div_aclk_mif_133",
1474 ENABLE_PCLK_MIF
, 6, CLK_IGNORE_UNUSED
, 0),
1475 GATE(CLK_PCLK_DDR_PHY1
, "pclk_ddr_phy1", "div_aclk_mif_133",
1476 ENABLE_PCLK_MIF
, 5, 0, 0),
1477 GATE(CLK_PCLK_DREX1
, "pclk_drex1", "div_aclk_mif_133",
1478 ENABLE_PCLK_MIF
, 3, CLK_IGNORE_UNUSED
, 0),
1479 GATE(CLK_PCLK_DDR_PHY0
, "pclk_ddr_phy0", "div_aclk_mif_133",
1480 ENABLE_PCLK_MIF
, 2, 0, 0),
1481 GATE(CLK_PCLK_DREX0
, "pclk_drex0", "div_aclk_mif_133",
1482 ENABLE_PCLK_MIF
, 0, CLK_IGNORE_UNUSED
, 0),
1484 /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
1485 GATE(CLK_PCLK_DREX0_TZ
, "pclk_drex0_tz", "div_aclk_mif_133",
1486 ENABLE_PCLK_MIF_SECURE_DREX0_TZ
, 0, 0, 0),
1488 /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
1489 GATE(CLK_PCLK_DREX1_TZ
, "pclk_drex1_tz", "div_aclk_mif_133",
1490 ENABLE_PCLK_MIF_SECURE_DREX1_TZ
, 0, 0, 0),
1492 /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
1493 GATE(CLK_PCLK_MONOTONIC_CNT
, "pclk_monotonic_cnt", "div_aclk_mif_133",
1494 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT
, 0, 0, 0),
1496 /* ENABLE_PCLK_MIF_SECURE_RTC */
1497 GATE(CLK_PCLK_RTC
, "pclk_rtc", "div_aclk_mif_133",
1498 ENABLE_PCLK_MIF_SECURE_RTC
, 0, 0, 0),
1500 /* ENABLE_SCLK_MIF */
1501 GATE(CLK_SCLK_DSIM1_DISP
, "sclk_dsim1_disp", "div_sclk_dsim1",
1502 ENABLE_SCLK_MIF
, 15, CLK_IGNORE_UNUSED
, 0),
1503 GATE(CLK_SCLK_DECON_TV_VCLK_DISP
, "sclk_decon_tv_vclk_disp",
1504 "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF
,
1505 14, CLK_IGNORE_UNUSED
, 0),
1506 GATE(CLK_SCLK_DSIM0_DISP
, "sclk_dsim0_disp", "div_sclk_dsim0",
1507 ENABLE_SCLK_MIF
, 9, CLK_IGNORE_UNUSED
, 0),
1508 GATE(CLK_SCLK_DSD_DISP
, "sclk_dsd_disp", "div_sclk_dsd",
1509 ENABLE_SCLK_MIF
, 8, CLK_IGNORE_UNUSED
, 0),
1510 GATE(CLK_SCLK_DECON_TV_ECLK_DISP
, "sclk_decon_tv_eclk_disp",
1511 "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF
,
1512 7, CLK_IGNORE_UNUSED
, 0),
1513 GATE(CLK_SCLK_DECON_VCLK_DISP
, "sclk_decon_vclk_disp",
1514 "div_sclk_decon_vclk", ENABLE_SCLK_MIF
,
1515 6, CLK_IGNORE_UNUSED
, 0),
1516 GATE(CLK_SCLK_DECON_ECLK_DISP
, "sclk_decon_eclk_disp",
1517 "div_sclk_decon_eclk", ENABLE_SCLK_MIF
,
1518 5, CLK_IGNORE_UNUSED
, 0),
1519 GATE(CLK_SCLK_HPM_MIF
, "sclk_hpm_mif", "div_sclk_hpm_mif",
1521 CLK_IGNORE_UNUSED
| CLK_SET_RATE_PARENT
, 0),
1522 GATE(CLK_SCLK_MFC_PLL
, "sclk_mfc_pll", "mout_mfc_pll_div2",
1523 ENABLE_SCLK_MIF
, 3, CLK_IGNORE_UNUSED
, 0),
1524 GATE(CLK_SCLK_BUS_PLL
, "sclk_bus_pll", "mout_bus_pll_div2",
1525 ENABLE_SCLK_MIF
, 2, CLK_IGNORE_UNUSED
, 0),
1526 GATE(CLK_SCLK_BUS_PLL_APOLLO
, "sclk_bus_pll_apollo", "sclk_bus_pll",
1527 ENABLE_SCLK_MIF
, 1, CLK_IGNORE_UNUSED
, 0),
1528 GATE(CLK_SCLK_BUS_PLL_ATLAS
, "sclk_bus_pll_atlas", "sclk_bus_pll",
1529 ENABLE_SCLK_MIF
, 0, CLK_IGNORE_UNUSED
, 0),
1532 static struct samsung_cmu_info mif_cmu_info __initdata
= {
1533 .pll_clks
= mif_pll_clks
,
1534 .nr_pll_clks
= ARRAY_SIZE(mif_pll_clks
),
1535 .mux_clks
= mif_mux_clks
,
1536 .nr_mux_clks
= ARRAY_SIZE(mif_mux_clks
),
1537 .div_clks
= mif_div_clks
,
1538 .nr_div_clks
= ARRAY_SIZE(mif_div_clks
),
1539 .gate_clks
= mif_gate_clks
,
1540 .nr_gate_clks
= ARRAY_SIZE(mif_gate_clks
),
1541 .fixed_factor_clks
= mif_fixed_factor_clks
,
1542 .nr_fixed_factor_clks
= ARRAY_SIZE(mif_fixed_factor_clks
),
1543 .nr_clk_ids
= MIF_NR_CLK
,
1544 .clk_regs
= mif_clk_regs
,
1545 .nr_clk_regs
= ARRAY_SIZE(mif_clk_regs
),
1548 static void __init
exynos5433_cmu_mif_init(struct device_node
*np
)
1550 samsung_cmu_register_one(np
, &mif_cmu_info
);
1552 CLK_OF_DECLARE(exynos5433_cmu_mif
, "samsung,exynos5433-cmu-mif",
1553 exynos5433_cmu_mif_init
);
1556 * Register offset definitions for CMU_PERIC
1558 #define DIV_PERIC 0x0600
1559 #define DIV_STAT_PERIC 0x0700
1560 #define ENABLE_ACLK_PERIC 0x0800
1561 #define ENABLE_PCLK_PERIC0 0x0900
1562 #define ENABLE_PCLK_PERIC1 0x0904
1563 #define ENABLE_SCLK_PERIC 0x0A00
1564 #define ENABLE_IP_PERIC0 0x0B00
1565 #define ENABLE_IP_PERIC1 0x0B04
1566 #define ENABLE_IP_PERIC2 0x0B08
1568 static unsigned long peric_clk_regs
[] __initdata
= {
1580 static struct samsung_div_clock peric_div_clks
[] __initdata
= {
1582 DIV(CLK_DIV_SCLK_SCI
, "div_sclk_sci", "oscclk", DIV_PERIC
, 4, 4),
1583 DIV(CLK_DIV_SCLK_SC_IN
, "div_sclk_sc_in", "oscclk", DIV_PERIC
, 0, 4),
1586 static struct samsung_gate_clock peric_gate_clks
[] __initdata
= {
1587 /* ENABLE_ACLK_PERIC */
1588 GATE(CLK_ACLK_AHB2APB_PERIC2P
, "aclk_ahb2apb_peric2p", "aclk_peric_66",
1589 ENABLE_ACLK_PERIC
, 3, CLK_IGNORE_UNUSED
, 0),
1590 GATE(CLK_ACLK_AHB2APB_PERIC1P
, "aclk_ahb2apb_peric1p", "aclk_peric_66",
1591 ENABLE_ACLK_PERIC
, 2, CLK_IGNORE_UNUSED
, 0),
1592 GATE(CLK_ACLK_AHB2APB_PERIC0P
, "aclk_ahb2apb_peric0p", "aclk_peric_66",
1593 ENABLE_ACLK_PERIC
, 1, CLK_IGNORE_UNUSED
, 0),
1594 GATE(CLK_ACLK_PERICNP_66
, "aclk_pericnp_66", "aclk_peric_66",
1595 ENABLE_ACLK_PERIC
, 0, CLK_IGNORE_UNUSED
, 0),
1597 /* ENABLE_PCLK_PERIC0 */
1598 GATE(CLK_PCLK_SCI
, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0
,
1599 31, CLK_SET_RATE_PARENT
, 0),
1600 GATE(CLK_PCLK_GPIO_FINGER
, "pclk_gpio_finger", "aclk_peric_66",
1601 ENABLE_PCLK_PERIC0
, 30, CLK_IGNORE_UNUSED
, 0),
1602 GATE(CLK_PCLK_GPIO_ESE
, "pclk_gpio_ese", "aclk_peric_66",
1603 ENABLE_PCLK_PERIC0
, 29, CLK_IGNORE_UNUSED
, 0),
1604 GATE(CLK_PCLK_PWM
, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0
,
1605 28, CLK_SET_RATE_PARENT
, 0),
1606 GATE(CLK_PCLK_SPDIF
, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0
,
1607 26, CLK_SET_RATE_PARENT
, 0),
1608 GATE(CLK_PCLK_PCM1
, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0
,
1609 25, CLK_SET_RATE_PARENT
, 0),
1610 GATE(CLK_PCLK_I2S1
, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0
,
1611 24, CLK_SET_RATE_PARENT
, 0),
1612 GATE(CLK_PCLK_SPI2
, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0
,
1613 23, CLK_SET_RATE_PARENT
, 0),
1614 GATE(CLK_PCLK_SPI1
, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0
,
1615 22, CLK_SET_RATE_PARENT
, 0),
1616 GATE(CLK_PCLK_SPI0
, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0
,
1617 21, CLK_SET_RATE_PARENT
, 0),
1618 GATE(CLK_PCLK_ADCIF
, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0
,
1619 20, CLK_SET_RATE_PARENT
, 0),
1620 GATE(CLK_PCLK_GPIO_TOUCH
, "pclk_gpio_touch", "aclk_peric_66",
1621 ENABLE_PCLK_PERIC0
, 19, CLK_IGNORE_UNUSED
, 0),
1622 GATE(CLK_PCLK_GPIO_NFC
, "pclk_gpio_nfc", "aclk_peric_66",
1623 ENABLE_PCLK_PERIC0
, 18, CLK_IGNORE_UNUSED
, 0),
1624 GATE(CLK_PCLK_GPIO_PERIC
, "pclk_gpio_peric", "aclk_peric_66",
1625 ENABLE_PCLK_PERIC0
, 17, CLK_IGNORE_UNUSED
, 0),
1626 GATE(CLK_PCLK_PMU_PERIC
, "pclk_pmu_peric", "aclk_peric_66",
1627 ENABLE_PCLK_PERIC0
, 16, CLK_SET_RATE_PARENT
, 0),
1628 GATE(CLK_PCLK_SYSREG_PERIC
, "pclk_sysreg_peric", "aclk_peric_66",
1629 ENABLE_PCLK_PERIC0
, 15,
1630 CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
, 0),
1631 GATE(CLK_PCLK_UART2
, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0
,
1632 14, CLK_SET_RATE_PARENT
, 0),
1633 GATE(CLK_PCLK_UART1
, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0
,
1634 13, CLK_SET_RATE_PARENT
, 0),
1635 GATE(CLK_PCLK_UART0
, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0
,
1636 12, CLK_SET_RATE_PARENT
, 0),
1637 GATE(CLK_PCLK_HSI2C3
, "pclk_hsi2c3", "aclk_peric_66",
1638 ENABLE_PCLK_PERIC0
, 11, CLK_SET_RATE_PARENT
, 0),
1639 GATE(CLK_PCLK_HSI2C2
, "pclk_hsi2c2", "aclk_peric_66",
1640 ENABLE_PCLK_PERIC0
, 10, CLK_SET_RATE_PARENT
, 0),
1641 GATE(CLK_PCLK_HSI2C1
, "pclk_hsi2c1", "aclk_peric_66",
1642 ENABLE_PCLK_PERIC0
, 9, CLK_SET_RATE_PARENT
, 0),
1643 GATE(CLK_PCLK_HSI2C0
, "pclk_hsi2c0", "aclk_peric_66",
1644 ENABLE_PCLK_PERIC0
, 8, CLK_SET_RATE_PARENT
, 0),
1645 GATE(CLK_PCLK_I2C7
, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0
,
1646 7, CLK_SET_RATE_PARENT
, 0),
1647 GATE(CLK_PCLK_I2C6
, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0
,
1648 6, CLK_SET_RATE_PARENT
, 0),
1649 GATE(CLK_PCLK_I2C5
, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0
,
1650 5, CLK_SET_RATE_PARENT
, 0),
1651 GATE(CLK_PCLK_I2C4
, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0
,
1652 4, CLK_SET_RATE_PARENT
, 0),
1653 GATE(CLK_PCLK_I2C3
, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0
,
1654 3, CLK_SET_RATE_PARENT
, 0),
1655 GATE(CLK_PCLK_I2C2
, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0
,
1656 2, CLK_SET_RATE_PARENT
, 0),
1657 GATE(CLK_PCLK_I2C1
, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0
,
1658 1, CLK_SET_RATE_PARENT
, 0),
1659 GATE(CLK_PCLK_I2C0
, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0
,
1660 0, CLK_SET_RATE_PARENT
, 0),
1662 /* ENABLE_PCLK_PERIC1 */
1663 GATE(CLK_PCLK_SPI4
, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1
,
1664 9, CLK_SET_RATE_PARENT
, 0),
1665 GATE(CLK_PCLK_SPI3
, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1
,
1666 8, CLK_SET_RATE_PARENT
, 0),
1667 GATE(CLK_PCLK_HSI2C11
, "pclk_hsi2c11", "aclk_peric_66",
1668 ENABLE_PCLK_PERIC1
, 7, CLK_SET_RATE_PARENT
, 0),
1669 GATE(CLK_PCLK_HSI2C10
, "pclk_hsi2c10", "aclk_peric_66",
1670 ENABLE_PCLK_PERIC1
, 6, CLK_SET_RATE_PARENT
, 0),
1671 GATE(CLK_PCLK_HSI2C9
, "pclk_hsi2c9", "aclk_peric_66",
1672 ENABLE_PCLK_PERIC1
, 5, CLK_SET_RATE_PARENT
, 0),
1673 GATE(CLK_PCLK_HSI2C8
, "pclk_hsi2c8", "aclk_peric_66",
1674 ENABLE_PCLK_PERIC1
, 4, CLK_SET_RATE_PARENT
, 0),
1675 GATE(CLK_PCLK_HSI2C7
, "pclk_hsi2c7", "aclk_peric_66",
1676 ENABLE_PCLK_PERIC1
, 3, CLK_SET_RATE_PARENT
, 0),
1677 GATE(CLK_PCLK_HSI2C6
, "pclk_hsi2c6", "aclk_peric_66",
1678 ENABLE_PCLK_PERIC1
, 2, CLK_SET_RATE_PARENT
, 0),
1679 GATE(CLK_PCLK_HSI2C5
, "pclk_hsi2c5", "aclk_peric_66",
1680 ENABLE_PCLK_PERIC1
, 1, CLK_SET_RATE_PARENT
, 0),
1681 GATE(CLK_PCLK_HSI2C4
, "pclk_hsi2c4", "aclk_peric_66",
1682 ENABLE_PCLK_PERIC1
, 0, CLK_SET_RATE_PARENT
, 0),
1684 /* ENABLE_SCLK_PERIC */
1685 GATE(CLK_SCLK_IOCLK_SPI4
, "sclk_ioclk_spi4", "ioclk_spi4_clk_in",
1686 ENABLE_SCLK_PERIC
, 21, CLK_SET_RATE_PARENT
, 0),
1687 GATE(CLK_SCLK_IOCLK_SPI3
, "sclk_ioclk_spi3", "ioclk_spi3_clk_in",
1688 ENABLE_SCLK_PERIC
, 20, CLK_SET_RATE_PARENT
, 0),
1689 GATE(CLK_SCLK_SPI4
, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC
,
1690 19, CLK_SET_RATE_PARENT
, 0),
1691 GATE(CLK_SCLK_SPI3
, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC
,
1692 18, CLK_SET_RATE_PARENT
, 0),
1693 GATE(CLK_SCLK_SCI
, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC
,
1695 GATE(CLK_SCLK_SC_IN
, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC
,
1697 GATE(CLK_SCLK_PWM
, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC
, 15, 0, 0),
1698 GATE(CLK_SCLK_IOCLK_SPI2
, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
1699 ENABLE_SCLK_PERIC
, 13, CLK_SET_RATE_PARENT
, 0),
1700 GATE(CLK_SCLK_IOCLK_SPI1
, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
1701 ENABLE_SCLK_PERIC
, 12,
1702 CLK_IGNORE_UNUSED
| CLK_SET_RATE_PARENT
, 0),
1703 GATE(CLK_SCLK_IOCLK_SPI0
, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
1704 ENABLE_SCLK_PERIC
, 11, CLK_SET_RATE_PARENT
, 0),
1705 GATE(CLK_SCLK_IOCLK_I2S1_BCLK
, "sclk_ioclk_i2s1_bclk",
1706 "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC
, 10,
1707 CLK_SET_RATE_PARENT
, 0),
1708 GATE(CLK_SCLK_SPDIF
, "sclk_spdif", "sclk_spdif_peric",
1709 ENABLE_SCLK_PERIC
, 8, CLK_SET_RATE_PARENT
, 0),
1710 GATE(CLK_SCLK_PCM1
, "sclk_pcm1", "sclk_pcm1_peric",
1711 ENABLE_SCLK_PERIC
, 7, CLK_SET_RATE_PARENT
, 0),
1712 GATE(CLK_SCLK_I2S1
, "sclk_i2s1", "sclk_i2s1_peric",
1713 ENABLE_SCLK_PERIC
, 6, CLK_SET_RATE_PARENT
, 0),
1714 GATE(CLK_SCLK_SPI2
, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC
,
1715 5, CLK_SET_RATE_PARENT
, 0),
1716 GATE(CLK_SCLK_SPI1
, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC
,
1717 4, CLK_IGNORE_UNUSED
| CLK_SET_RATE_PARENT
, 0),
1718 GATE(CLK_SCLK_SPI0
, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC
,
1719 3, CLK_SET_RATE_PARENT
, 0),
1720 GATE(CLK_SCLK_UART2
, "sclk_uart2", "sclk_uart2_peric",
1721 ENABLE_SCLK_PERIC
, 2, CLK_SET_RATE_PARENT
, 0),
1722 GATE(CLK_SCLK_UART1
, "sclk_uart1", "sclk_uart1_peric",
1723 ENABLE_SCLK_PERIC
, 1, CLK_SET_RATE_PARENT
, 0),
1724 GATE(CLK_SCLK_UART0
, "sclk_uart0", "sclk_uart0_peric",
1725 ENABLE_SCLK_PERIC
, 0, CLK_SET_RATE_PARENT
, 0),
1728 static struct samsung_cmu_info peric_cmu_info __initdata
= {
1729 .div_clks
= peric_div_clks
,
1730 .nr_div_clks
= ARRAY_SIZE(peric_div_clks
),
1731 .gate_clks
= peric_gate_clks
,
1732 .nr_gate_clks
= ARRAY_SIZE(peric_gate_clks
),
1733 .nr_clk_ids
= PERIC_NR_CLK
,
1734 .clk_regs
= peric_clk_regs
,
1735 .nr_clk_regs
= ARRAY_SIZE(peric_clk_regs
),
1738 static void __init
exynos5433_cmu_peric_init(struct device_node
*np
)
1740 samsung_cmu_register_one(np
, &peric_cmu_info
);
1743 CLK_OF_DECLARE(exynos5433_cmu_peric
, "samsung,exynos5433-cmu-peric",
1744 exynos5433_cmu_peric_init
);
1747 * Register offset definitions for CMU_PERIS
1749 #define ENABLE_ACLK_PERIS 0x0800
1750 #define ENABLE_PCLK_PERIS 0x0900
1751 #define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904
1752 #define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908
1753 #define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c
1754 #define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910
1755 #define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914
1756 #define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918
1757 #define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c
1758 #define ENABLE_SCLK_PERIS 0x0a00
1759 #define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04
1760 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08
1761 #define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c
1762 #define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10
1763 #define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14
1764 #define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18
1765 #define ENABLE_IP_PERIS0 0x0b00
1766 #define ENABLE_IP_PERIS1 0x0b04
1767 #define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08
1768 #define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c
1769 #define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10
1770 #define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14
1771 #define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18
1772 #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c
1773 #define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20
1775 static unsigned long peris_clk_regs
[] __initdata
= {
1778 ENABLE_PCLK_PERIS_SECURE_TZPC
,
1779 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF
,
1780 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF
,
1781 ENABLE_PCLK_PERIS_SECURE_TOPRTC
,
1782 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF
,
1783 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF
,
1784 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF
,
1786 ENABLE_SCLK_PERIS_SECURE_SECKEY
,
1787 ENABLE_SCLK_PERIS_SECURE_CHIPID
,
1788 ENABLE_SCLK_PERIS_SECURE_TOPRTC
,
1789 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE
,
1790 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT
,
1791 ENABLE_SCLK_PERIS_SECURE_OTP_CON
,
1794 ENABLE_IP_PERIS_SECURE_TZPC
,
1795 ENABLE_IP_PERIS_SECURE_SECKEY
,
1796 ENABLE_IP_PERIS_SECURE_CHIPID
,
1797 ENABLE_IP_PERIS_SECURE_TOPRTC
,
1798 ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE
,
1799 ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT
,
1800 ENABLE_IP_PERIS_SECURE_OTP_CON
,
1803 static struct samsung_gate_clock peris_gate_clks
[] __initdata
= {
1804 /* ENABLE_ACLK_PERIS */
1805 GATE(CLK_ACLK_AHB2APB_PERIS1P
, "aclk_ahb2apb_peris1p", "aclk_peris_66",
1806 ENABLE_ACLK_PERIS
, 2, CLK_IGNORE_UNUSED
, 0),
1807 GATE(CLK_ACLK_AHB2APB_PERIS0P
, "aclk_ahb2apb_peris0p", "aclk_peris_66",
1808 ENABLE_ACLK_PERIS
, 1, CLK_IGNORE_UNUSED
, 0),
1809 GATE(CLK_ACLK_PERISNP_66
, "aclk_perisnp_66", "aclk_peris_66",
1810 ENABLE_ACLK_PERIS
, 0, CLK_IGNORE_UNUSED
, 0),
1812 /* ENABLE_PCLK_PERIS */
1813 GATE(CLK_PCLK_HPM_APBIF
, "pclk_hpm_apbif", "aclk_peris_66",
1814 ENABLE_PCLK_PERIS
, 30, CLK_IGNORE_UNUSED
, 0),
1815 GATE(CLK_PCLK_TMU1_APBIF
, "pclk_tmu1_apbif", "aclk_peris_66",
1816 ENABLE_PCLK_PERIS
, 24, CLK_IGNORE_UNUSED
, 0),
1817 GATE(CLK_PCLK_TMU0_APBIF
, "pclk_tmu0_apbif", "aclk_peris_66",
1818 ENABLE_PCLK_PERIS
, 23, CLK_IGNORE_UNUSED
, 0),
1819 GATE(CLK_PCLK_PMU_PERIS
, "pclk_pmu_peris", "aclk_peris_66",
1820 ENABLE_PCLK_PERIS
, 22, CLK_IGNORE_UNUSED
, 0),
1821 GATE(CLK_PCLK_SYSREG_PERIS
, "pclk_sysreg_peris", "aclk_peris_66",
1822 ENABLE_PCLK_PERIS
, 21, CLK_IGNORE_UNUSED
, 0),
1823 GATE(CLK_PCLK_CMU_TOP_APBIF
, "pclk_cmu_top_apbif", "aclk_peris_66",
1824 ENABLE_PCLK_PERIS
, 20, CLK_IGNORE_UNUSED
, 0),
1825 GATE(CLK_PCLK_WDT_APOLLO
, "pclk_wdt_apollo", "aclk_peris_66",
1826 ENABLE_PCLK_PERIS
, 17, CLK_IGNORE_UNUSED
, 0),
1827 GATE(CLK_PCLK_WDT_ATLAS
, "pclk_wdt_atlas", "aclk_peris_66",
1828 ENABLE_PCLK_PERIS
, 16, CLK_IGNORE_UNUSED
, 0),
1829 GATE(CLK_PCLK_MCT
, "pclk_mct", "aclk_peris_66",
1830 ENABLE_PCLK_PERIS
, 15, CLK_IGNORE_UNUSED
, 0),
1831 GATE(CLK_PCLK_HDMI_CEC
, "pclk_hdmi_cec", "aclk_peris_66",
1832 ENABLE_PCLK_PERIS
, 14, CLK_IGNORE_UNUSED
, 0),
1834 /* ENABLE_PCLK_PERIS_SECURE_TZPC */
1835 GATE(CLK_PCLK_TZPC12
, "pclk_tzpc12", "aclk_peris_66",
1836 ENABLE_PCLK_PERIS_SECURE_TZPC
, 12, CLK_IGNORE_UNUSED
, 0),
1837 GATE(CLK_PCLK_TZPC11
, "pclk_tzpc11", "aclk_peris_66",
1838 ENABLE_PCLK_PERIS_SECURE_TZPC
, 11, CLK_IGNORE_UNUSED
, 0),
1839 GATE(CLK_PCLK_TZPC10
, "pclk_tzpc10", "aclk_peris_66",
1840 ENABLE_PCLK_PERIS_SECURE_TZPC
, 10, CLK_IGNORE_UNUSED
, 0),
1841 GATE(CLK_PCLK_TZPC9
, "pclk_tzpc9", "aclk_peris_66",
1842 ENABLE_PCLK_PERIS_SECURE_TZPC
, 9, CLK_IGNORE_UNUSED
, 0),
1843 GATE(CLK_PCLK_TZPC8
, "pclk_tzpc8", "aclk_peris_66",
1844 ENABLE_PCLK_PERIS_SECURE_TZPC
, 8, CLK_IGNORE_UNUSED
, 0),
1845 GATE(CLK_PCLK_TZPC7
, "pclk_tzpc7", "aclk_peris_66",
1846 ENABLE_PCLK_PERIS_SECURE_TZPC
, 7, CLK_IGNORE_UNUSED
, 0),
1847 GATE(CLK_PCLK_TZPC6
, "pclk_tzpc6", "aclk_peris_66",
1848 ENABLE_PCLK_PERIS_SECURE_TZPC
, 6, CLK_IGNORE_UNUSED
, 0),
1849 GATE(CLK_PCLK_TZPC5
, "pclk_tzpc5", "aclk_peris_66",
1850 ENABLE_PCLK_PERIS_SECURE_TZPC
, 5, CLK_IGNORE_UNUSED
, 0),
1851 GATE(CLK_PCLK_TZPC4
, "pclk_tzpc4", "aclk_peris_66",
1852 ENABLE_PCLK_PERIS_SECURE_TZPC
, 4, CLK_IGNORE_UNUSED
, 0),
1853 GATE(CLK_PCLK_TZPC3
, "pclk_tzpc3", "aclk_peris_66",
1854 ENABLE_PCLK_PERIS_SECURE_TZPC
, 3, CLK_IGNORE_UNUSED
, 0),
1855 GATE(CLK_PCLK_TZPC2
, "pclk_tzpc2", "aclk_peris_66",
1856 ENABLE_PCLK_PERIS_SECURE_TZPC
, 2, CLK_IGNORE_UNUSED
, 0),
1857 GATE(CLK_PCLK_TZPC1
, "pclk_tzpc1", "aclk_peris_66",
1858 ENABLE_PCLK_PERIS_SECURE_TZPC
, 1, CLK_IGNORE_UNUSED
, 0),
1859 GATE(CLK_PCLK_TZPC0
, "pclk_tzpc0", "aclk_peris_66",
1860 ENABLE_PCLK_PERIS_SECURE_TZPC
, 0, CLK_IGNORE_UNUSED
, 0),
1862 /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */
1863 GATE(CLK_PCLK_SECKEY_APBIF
, "pclk_seckey_apbif", "aclk_peris_66",
1864 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF
, 0, CLK_IGNORE_UNUSED
, 0),
1866 /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */
1867 GATE(CLK_PCLK_CHIPID_APBIF
, "pclk_chipid_apbif", "aclk_peris_66",
1868 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF
, 0, CLK_IGNORE_UNUSED
, 0),
1870 /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */
1871 GATE(CLK_PCLK_TOPRTC
, "pclk_toprtc", "aclk_peris_66",
1872 ENABLE_PCLK_PERIS_SECURE_TOPRTC
, 0, 0, 0),
1874 /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */
1875 GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF
, "pclk_custom_efuse_apbif",
1877 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF
, 0, 0, 0),
1879 /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */
1880 GATE(CLK_PCLK_ANTIRBK_CNT_APBIF
, "pclk_antirbk_cnt_apbif",
1882 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF
, 0, 0, 0),
1884 /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */
1885 GATE(CLK_PCLK_OTP_CON_APBIF
, "pclk_otp_con_apbif",
1887 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF
, 0, 0, 0),
1889 /* ENABLE_SCLK_PERIS */
1890 GATE(CLK_SCLK_ASV_TB
, "sclk_asv_tb", "oscclk_efuse_common",
1891 ENABLE_SCLK_PERIS
, 10, 0, 0),
1892 GATE(CLK_SCLK_TMU1
, "sclk_tmu1", "oscclk_efuse_common",
1893 ENABLE_SCLK_PERIS
, 4, 0, 0),
1894 GATE(CLK_SCLK_TMU0
, "sclk_tmu0", "oscclk_efuse_common",
1895 ENABLE_SCLK_PERIS
, 3, 0, 0),
1897 /* ENABLE_SCLK_PERIS_SECURE_SECKEY */
1898 GATE(CLK_SCLK_SECKEY
, "sclk_seckey", "oscclk_efuse_common",
1899 ENABLE_SCLK_PERIS_SECURE_SECKEY
, 0, CLK_IGNORE_UNUSED
, 0),
1901 /* ENABLE_SCLK_PERIS_SECURE_CHIPID */
1902 GATE(CLK_SCLK_CHIPID
, "sclk_chipid", "oscclk_efuse_common",
1903 ENABLE_SCLK_PERIS_SECURE_CHIPID
, 0, CLK_IGNORE_UNUSED
, 0),
1905 /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */
1906 GATE(CLK_SCLK_TOPRTC
, "sclk_toprtc", "oscclk_efuse_common",
1907 ENABLE_SCLK_PERIS_SECURE_TOPRTC
, 0, 0, 0),
1909 /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */
1910 GATE(CLK_SCLK_CUSTOM_EFUSE
, "sclk_custom_efuse", "oscclk_efuse_common",
1911 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE
, 0, 0, 0),
1913 /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */
1914 GATE(CLK_SCLK_ANTIRBK_CNT
, "sclk_antirbk_cnt", "oscclk_efuse_common",
1915 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT
, 0, 0, 0),
1917 /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */
1918 GATE(CLK_SCLK_OTP_CON
, "sclk_otp_con", "oscclk_efuse_common",
1919 ENABLE_SCLK_PERIS_SECURE_OTP_CON
, 0, 0, 0),
1922 static struct samsung_cmu_info peris_cmu_info __initdata
= {
1923 .gate_clks
= peris_gate_clks
,
1924 .nr_gate_clks
= ARRAY_SIZE(peris_gate_clks
),
1925 .nr_clk_ids
= PERIS_NR_CLK
,
1926 .clk_regs
= peris_clk_regs
,
1927 .nr_clk_regs
= ARRAY_SIZE(peris_clk_regs
),
1930 static void __init
exynos5433_cmu_peris_init(struct device_node
*np
)
1932 samsung_cmu_register_one(np
, &peris_cmu_info
);
1935 CLK_OF_DECLARE(exynos5433_cmu_peris
, "samsung,exynos5433-cmu-peris",
1936 exynos5433_cmu_peris_init
);
1939 * Register offset definitions for CMU_FSYS
1941 #define MUX_SEL_FSYS0 0x0200
1942 #define MUX_SEL_FSYS1 0x0204
1943 #define MUX_SEL_FSYS2 0x0208
1944 #define MUX_SEL_FSYS3 0x020c
1945 #define MUX_SEL_FSYS4 0x0210
1946 #define MUX_ENABLE_FSYS0 0x0300
1947 #define MUX_ENABLE_FSYS1 0x0304
1948 #define MUX_ENABLE_FSYS2 0x0308
1949 #define MUX_ENABLE_FSYS3 0x030c
1950 #define MUX_ENABLE_FSYS4 0x0310
1951 #define MUX_STAT_FSYS0 0x0400
1952 #define MUX_STAT_FSYS1 0x0404
1953 #define MUX_STAT_FSYS2 0x0408
1954 #define MUX_STAT_FSYS3 0x040c
1955 #define MUX_STAT_FSYS4 0x0410
1956 #define MUX_IGNORE_FSYS2 0x0508
1957 #define MUX_IGNORE_FSYS3 0x050c
1958 #define ENABLE_ACLK_FSYS0 0x0800
1959 #define ENABLE_ACLK_FSYS1 0x0804
1960 #define ENABLE_PCLK_FSYS 0x0900
1961 #define ENABLE_SCLK_FSYS 0x0a00
1962 #define ENABLE_IP_FSYS0 0x0b00
1963 #define ENABLE_IP_FSYS1 0x0b04
1965 /* list of all parent clock list */
1966 PNAME(mout_sclk_ufs_mphy_user_p
) = { "oscclk", "sclk_ufs_mphy", };
1967 PNAME(mout_aclk_fsys_200_user_p
) = { "oscclk", "div_aclk_fsys_200", };
1968 PNAME(mout_sclk_pcie_100_user_p
) = { "oscclk", "sclk_pcie_100_fsys",};
1969 PNAME(mout_sclk_ufsunipro_user_p
) = { "oscclk", "sclk_ufsunipro_fsys",};
1970 PNAME(mout_sclk_mmc2_user_p
) = { "oscclk", "sclk_mmc2_fsys", };
1971 PNAME(mout_sclk_mmc1_user_p
) = { "oscclk", "sclk_mmc1_fsys", };
1972 PNAME(mout_sclk_mmc0_user_p
) = { "oscclk", "sclk_mmc0_fsys", };
1973 PNAME(mout_sclk_usbhost30_user_p
) = { "oscclk", "sclk_usbhost30_fsys",};
1974 PNAME(mout_sclk_usbdrd30_user_p
) = { "oscclk", "sclk_usbdrd30_fsys", };
1976 PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p
)
1977 = { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
1978 PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p
)
1979 = { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", };
1980 PNAME(mout_phyclk_usbhost20_phy_hsic1_p
)
1981 = { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", };
1982 PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p
)
1983 = { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", };
1984 PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p
)
1985 = { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", };
1986 PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p
)
1987 = { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", };
1988 PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p
)
1989 = { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", };
1990 PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p
)
1991 = { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", };
1992 PNAME(mout_phyclk_ufs_rx1_symbol_user_p
)
1993 = { "oscclk", "phyclk_ufs_rx1_symbol_phy", };
1994 PNAME(mout_phyclk_ufs_rx0_symbol_user_p
)
1995 = { "oscclk", "phyclk_ufs_rx0_symbol_phy", };
1996 PNAME(mout_phyclk_ufs_tx1_symbol_user_p
)
1997 = { "oscclk", "phyclk_ufs_tx1_symbol_phy", };
1998 PNAME(mout_phyclk_ufs_tx0_symbol_user_p
)
1999 = { "oscclk", "phyclk_ufs_tx0_symbol_phy", };
2000 PNAME(mout_phyclk_lli_mphy_to_ufs_user_p
)
2001 = { "oscclk", "phyclk_lli_mphy_to_ufs_phy", };
2002 PNAME(mout_sclk_mphy_p
)
2003 = { "mout_sclk_ufs_mphy_user",
2004 "mout_phyclk_lli_mphy_to_ufs_user", };
2006 static unsigned long fsys_clk_regs
[] __initdata
= {
2032 static struct samsung_fixed_rate_clock fsys_fixed_clks
[] __initdata
= {
2033 /* PHY clocks from USBDRD30_PHY */
2034 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY
,
2035 "phyclk_usbdrd30_udrd30_phyclock_phy", NULL
,
2036 CLK_IS_ROOT
, 60000000),
2037 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY
,
2038 "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL
,
2039 CLK_IS_ROOT
, 125000000),
2040 /* PHY clocks from USBHOST30_PHY */
2041 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY
,
2042 "phyclk_usbhost30_uhost30_phyclock_phy", NULL
,
2043 CLK_IS_ROOT
, 60000000),
2044 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY
,
2045 "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL
,
2046 CLK_IS_ROOT
, 125000000),
2047 /* PHY clocks from USBHOST20_PHY */
2048 FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY
,
2049 "phyclk_usbhost20_phy_freeclk_phy", NULL
, CLK_IS_ROOT
,
2051 FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY
,
2052 "phyclk_usbhost20_phy_phyclock_phy", NULL
, CLK_IS_ROOT
,
2054 FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY
,
2055 "phyclk_usbhost20_phy_clk48mohci_phy", NULL
,
2056 CLK_IS_ROOT
, 48000000),
2057 FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY
,
2058 "phyclk_usbhost20_phy_hsic1_phy", NULL
, CLK_IS_ROOT
,
2060 /* PHY clocks from UFS_PHY */
2061 FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY
, "phyclk_ufs_tx0_symbol_phy",
2062 NULL
, CLK_IS_ROOT
, 300000000),
2063 FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY
, "phyclk_ufs_rx0_symbol_phy",
2064 NULL
, CLK_IS_ROOT
, 300000000),
2065 FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY
, "phyclk_ufs_tx1_symbol_phy",
2066 NULL
, CLK_IS_ROOT
, 300000000),
2067 FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY
, "phyclk_ufs_rx1_symbol_phy",
2068 NULL
, CLK_IS_ROOT
, 300000000),
2069 /* PHY clocks from LLI_PHY */
2070 FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY
, "phyclk_lli_mphy_to_ufs_phy",
2071 NULL
, CLK_IS_ROOT
, 26000000),
2074 static struct samsung_mux_clock fsys_mux_clks
[] __initdata
= {
2076 MUX(CLK_MOUT_SCLK_UFS_MPHY_USER
, "mout_sclk_ufs_mphy_user",
2077 mout_sclk_ufs_mphy_user_p
, MUX_SEL_FSYS0
, 4, 1),
2078 MUX(CLK_MOUT_ACLK_FSYS_200_USER
, "mout_aclk_fsys_200_user",
2079 mout_aclk_fsys_200_user_p
, MUX_SEL_FSYS0
, 0, 1),
2082 MUX(CLK_MOUT_SCLK_PCIE_100_USER
, "mout_sclk_pcie_100_user",
2083 mout_sclk_pcie_100_user_p
, MUX_SEL_FSYS1
, 28, 1),
2084 MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER
, "mout_sclk_ufsunipro_user",
2085 mout_sclk_ufsunipro_user_p
, MUX_SEL_FSYS1
, 24, 1),
2086 MUX(CLK_MOUT_SCLK_MMC2_USER
, "mout_sclk_mmc2_user",
2087 mout_sclk_mmc2_user_p
, MUX_SEL_FSYS1
, 20, 1),
2088 MUX(CLK_MOUT_SCLK_MMC1_USER
, "mout_sclk_mmc1_user",
2089 mout_sclk_mmc1_user_p
, MUX_SEL_FSYS1
, 16, 1),
2090 MUX(CLK_MOUT_SCLK_MMC0_USER
, "mout_sclk_mmc0_user",
2091 mout_sclk_mmc0_user_p
, MUX_SEL_FSYS1
, 12, 1),
2092 MUX(CLK_MOUT_SCLK_USBHOST30_USER
, "mout_sclk_usbhost30_user",
2093 mout_sclk_usbhost30_user_p
, MUX_SEL_FSYS1
, 4, 1),
2094 MUX(CLK_MOUT_SCLK_USBDRD30_USER
, "mout_sclk_usbdrd30_user",
2095 mout_sclk_usbdrd30_user_p
, MUX_SEL_FSYS1
, 0, 1),
2098 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER
,
2099 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2100 mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p
,
2101 MUX_SEL_FSYS2
, 28, 1),
2102 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER
,
2103 "mout_phyclk_usbhost30_uhost30_phyclock_user",
2104 mout_phyclk_usbhost30_uhost30_phyclock_user_p
,
2105 MUX_SEL_FSYS2
, 24, 1),
2106 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER
,
2107 "mout_phyclk_usbhost20_phy_hsic1",
2108 mout_phyclk_usbhost20_phy_hsic1_p
,
2109 MUX_SEL_FSYS2
, 20, 1),
2110 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER
,
2111 "mout_phyclk_usbhost20_phy_clk48mohci_user",
2112 mout_phyclk_usbhost20_phy_clk48mohci_user_p
,
2113 MUX_SEL_FSYS2
, 16, 1),
2114 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER
,
2115 "mout_phyclk_usbhost20_phy_phyclock_user",
2116 mout_phyclk_usbhost20_phy_phyclock_user_p
,
2117 MUX_SEL_FSYS2
, 12, 1),
2118 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER
,
2119 "mout_phyclk_usbhost20_phy_freeclk_user",
2120 mout_phyclk_usbhost20_phy_freeclk_user_p
,
2121 MUX_SEL_FSYS2
, 8, 1),
2122 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER
,
2123 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2124 mout_phyclk_usbdrd30_udrd30_pipe_pclk_p
,
2125 MUX_SEL_FSYS2
, 4, 1),
2126 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER
,
2127 "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2128 mout_phyclk_usbdrd30_udrd30_phyclock_user_p
,
2129 MUX_SEL_FSYS2
, 0, 1),
2132 MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER
,
2133 "mout_phyclk_ufs_rx1_symbol_user",
2134 mout_phyclk_ufs_rx1_symbol_user_p
,
2135 MUX_SEL_FSYS3
, 16, 1),
2136 MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER
,
2137 "mout_phyclk_ufs_rx0_symbol_user",
2138 mout_phyclk_ufs_rx0_symbol_user_p
,
2139 MUX_SEL_FSYS3
, 12, 1),
2140 MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER
,
2141 "mout_phyclk_ufs_tx1_symbol_user",
2142 mout_phyclk_ufs_tx1_symbol_user_p
,
2143 MUX_SEL_FSYS3
, 8, 1),
2144 MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER
,
2145 "mout_phyclk_ufs_tx0_symbol_user",
2146 mout_phyclk_ufs_tx0_symbol_user_p
,
2147 MUX_SEL_FSYS3
, 4, 1),
2148 MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER
,
2149 "mout_phyclk_lli_mphy_to_ufs_user",
2150 mout_phyclk_lli_mphy_to_ufs_user_p
,
2151 MUX_SEL_FSYS3
, 0, 1),
2154 MUX(CLK_MOUT_SCLK_MPHY
, "mout_sclk_mphy", mout_sclk_mphy_p
,
2155 MUX_SEL_FSYS4
, 0, 1),
2158 static struct samsung_gate_clock fsys_gate_clks
[] __initdata
= {
2159 /* ENABLE_ACLK_FSYS0 */
2160 GATE(CLK_ACLK_PCIE
, "aclk_pcie", "mout_aclk_fsys_200_user",
2161 ENABLE_ACLK_FSYS0
, 13, CLK_IGNORE_UNUSED
, 0),
2162 GATE(CLK_ACLK_PDMA1
, "aclk_pdma1", "mout_aclk_fsys_200_user",
2163 ENABLE_ACLK_FSYS0
, 11, CLK_IGNORE_UNUSED
, 0),
2164 GATE(CLK_ACLK_TSI
, "aclk_tsi", "mout_aclk_fsys_200_user",
2165 ENABLE_ACLK_FSYS0
, 10, CLK_IGNORE_UNUSED
, 0),
2166 GATE(CLK_ACLK_MMC2
, "aclk_mmc2", "mout_aclk_fsys_200_user",
2167 ENABLE_ACLK_FSYS0
, 8, CLK_IGNORE_UNUSED
, 0),
2168 GATE(CLK_ACLK_MMC1
, "aclk_mmc1", "mout_aclk_fsys_200_user",
2169 ENABLE_ACLK_FSYS0
, 7, CLK_IGNORE_UNUSED
, 0),
2170 GATE(CLK_ACLK_MMC0
, "aclk_mmc0", "mout_aclk_fsys_200_user",
2171 ENABLE_ACLK_FSYS0
, 6, CLK_IGNORE_UNUSED
, 0),
2172 GATE(CLK_ACLK_UFS
, "aclk_ufs", "mout_aclk_fsys_200_user",
2173 ENABLE_ACLK_FSYS0
, 5, CLK_IGNORE_UNUSED
, 0),
2174 GATE(CLK_ACLK_USBHOST20
, "aclk_usbhost20", "mout_aclk_fsys_200_user",
2175 ENABLE_ACLK_FSYS0
, 3, CLK_IGNORE_UNUSED
, 0),
2176 GATE(CLK_ACLK_USBHOST30
, "aclk_usbhost30", "mout_aclk_fsys_200_user",
2177 ENABLE_ACLK_FSYS0
, 2, CLK_IGNORE_UNUSED
, 0),
2178 GATE(CLK_ACLK_USBDRD30
, "aclk_usbdrd30", "mout_aclk_fsys_200_user",
2179 ENABLE_ACLK_FSYS0
, 1, CLK_IGNORE_UNUSED
, 0),
2180 GATE(CLK_ACLK_PDMA0
, "aclk_pdma0", "mout_aclk_fsys_200_user",
2181 ENABLE_ACLK_FSYS0
, 0, CLK_IGNORE_UNUSED
, 0),
2183 /* ENABLE_ACLK_FSYS1 */
2184 GATE(CLK_ACLK_XIU_FSYSPX
, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user",
2185 ENABLE_ACLK_FSYS1
, 27, CLK_IGNORE_UNUSED
, 0),
2186 GATE(CLK_ACLK_AHB_USBLINKH1
, "aclk_ahb_usblinkh1",
2187 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1
,
2188 26, CLK_IGNORE_UNUSED
, 0),
2189 GATE(CLK_ACLK_SMMU_PDMA1
, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2190 ENABLE_ACLK_FSYS1
, 25, CLK_IGNORE_UNUSED
, 0),
2191 GATE(CLK_ACLK_BTS_PCIE
, "aclk_bts_pcie", "mout_aclk_fsys_200_user",
2192 ENABLE_ACLK_FSYS1
, 24, 0, 0),
2193 GATE(CLK_ACLK_AXIUS_PDMA1
, "aclk_axius_pdma1",
2194 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1
,
2195 22, CLK_IGNORE_UNUSED
, 0),
2196 GATE(CLK_ACLK_SMMU_PDMA0
, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2197 ENABLE_ACLK_FSYS1
, 17, CLK_IGNORE_UNUSED
, 0),
2198 GATE(CLK_ACLK_BTS_UFS
, "aclk_bts_ufs", "mout_aclk_fsys_200_user",
2199 ENABLE_ACLK_FSYS1
, 14, CLK_IGNORE_UNUSED
, 0),
2200 GATE(CLK_ACLK_BTS_USBHOST30
, "aclk_bts_usbhost30",
2201 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1
,
2203 GATE(CLK_ACLK_BTS_USBDRD30
, "aclk_bts_usbdrd30",
2204 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1
,
2206 GATE(CLK_ACLK_AXIUS_PDMA0
, "aclk_axius_pdma0",
2207 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1
,
2208 11, CLK_IGNORE_UNUSED
, 0),
2209 GATE(CLK_ACLK_AXIUS_USBHS
, "aclk_axius_usbhs",
2210 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1
,
2211 10, CLK_IGNORE_UNUSED
, 0),
2212 GATE(CLK_ACLK_AXIUS_FSYSSX
, "aclk_axius_fsyssx",
2213 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1
,
2214 9, CLK_IGNORE_UNUSED
, 0),
2215 GATE(CLK_ACLK_AHB2APB_FSYSP
, "aclk_ahb2apb_fsysp",
2216 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1
,
2217 8, CLK_IGNORE_UNUSED
, 0),
2218 GATE(CLK_ACLK_AHB2AXI_USBHS
, "aclk_ahb2axi_usbhs",
2219 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1
,
2220 7, CLK_IGNORE_UNUSED
, 0),
2221 GATE(CLK_ACLK_AHB_USBLINKH0
, "aclk_ahb_usblinkh0",
2222 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1
,
2223 6, CLK_IGNORE_UNUSED
, 0),
2224 GATE(CLK_ACLK_AHB_USBHS
, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user",
2225 ENABLE_ACLK_FSYS1
, 5, CLK_IGNORE_UNUSED
, 0),
2226 GATE(CLK_ACLK_AHB_FSYSH
, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user",
2227 ENABLE_ACLK_FSYS1
, 4, CLK_IGNORE_UNUSED
, 0),
2228 GATE(CLK_ACLK_XIU_FSYSX
, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user",
2229 ENABLE_ACLK_FSYS1
, 3, CLK_IGNORE_UNUSED
, 0),
2230 GATE(CLK_ACLK_XIU_FSYSSX
, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user",
2231 ENABLE_ACLK_FSYS1
, 2, CLK_IGNORE_UNUSED
, 0),
2232 GATE(CLK_ACLK_FSYSNP_200
, "aclk_fsysnp_200", "mout_aclk_fsys_200_user",
2233 ENABLE_ACLK_FSYS1
, 1, CLK_IGNORE_UNUSED
, 0),
2234 GATE(CLK_ACLK_FSYSND_200
, "aclk_fsysnd_200", "mout_aclk_fsys_200_user",
2235 ENABLE_ACLK_FSYS1
, 0, CLK_IGNORE_UNUSED
, 0),
2237 /* ENABLE_PCLK_FSYS */
2238 GATE(CLK_PCLK_PCIE_CTRL
, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user",
2239 ENABLE_PCLK_FSYS
, 17, 0, 0),
2240 GATE(CLK_PCLK_SMMU_PDMA1
, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2241 ENABLE_PCLK_FSYS
, 16, CLK_IGNORE_UNUSED
, 0),
2242 GATE(CLK_PCLK_PCIE_PHY
, "pclk_pcie_phy", "mout_aclk_fsys_200_user",
2243 ENABLE_PCLK_FSYS
, 14, 0, 0),
2244 GATE(CLK_PCLK_BTS_PCIE
, "pclk_bts_pcie", "mout_aclk_fsys_200_user",
2245 ENABLE_PCLK_FSYS
, 13, 0, 0),
2246 GATE(CLK_PCLK_SMMU_PDMA0
, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2247 ENABLE_PCLK_FSYS
, 8, CLK_IGNORE_UNUSED
, 0),
2248 GATE(CLK_PCLK_BTS_UFS
, "pclk_bts_ufs", "mout_aclk_fsys_200_user",
2249 ENABLE_PCLK_FSYS
, 5, 0, 0),
2250 GATE(CLK_PCLK_BTS_USBHOST30
, "pclk_bts_usbhost30",
2251 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS
, 4, 0, 0),
2252 GATE(CLK_PCLK_BTS_USBDRD30
, "pclk_bts_usbdrd30",
2253 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS
, 3, 0, 0),
2254 GATE(CLK_PCLK_GPIO_FSYS
, "pclk_gpio_fsys", "mout_aclk_fsys_200_user",
2255 ENABLE_PCLK_FSYS
, 2, CLK_IGNORE_UNUSED
, 0),
2256 GATE(CLK_PCLK_PMU_FSYS
, "pclk_pmu_fsys", "mout_aclk_fsys_200_user",
2257 ENABLE_PCLK_FSYS
, 1, CLK_IGNORE_UNUSED
, 0),
2258 GATE(CLK_PCLK_SYSREG_FSYS
, "pclk_sysreg_fsys",
2259 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS
,
2260 0, CLK_IGNORE_UNUSED
, 0),
2262 /* ENABLE_SCLK_FSYS */
2263 GATE(CLK_SCLK_PCIE_100
, "sclk_pcie_100", "mout_sclk_pcie_100_user",
2264 ENABLE_SCLK_FSYS
, 21, 0, 0),
2265 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK
,
2266 "phyclk_usbhost30_uhost30_pipe_pclk",
2267 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2268 ENABLE_SCLK_FSYS
, 18, 0, 0),
2269 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK
,
2270 "phyclk_usbhost30_uhost30_phyclock",
2271 "mout_phyclk_usbhost30_uhost30_phyclock_user",
2272 ENABLE_SCLK_FSYS
, 17, 0, 0),
2273 GATE(CLK_PHYCLK_UFS_RX1_SYMBOL
, "phyclk_ufs_rx1_symbol",
2274 "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS
,
2276 GATE(CLK_PHYCLK_UFS_RX0_SYMBOL
, "phyclk_ufs_rx0_symbol",
2277 "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS
,
2279 GATE(CLK_PHYCLK_UFS_TX1_SYMBOL
, "phyclk_ufs_tx1_symbol",
2280 "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS
,
2282 GATE(CLK_PHYCLK_UFS_TX0_SYMBOL
, "phyclk_ufs_tx0_symbol",
2283 "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS
,
2285 GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1
, "phyclk_usbhost20_phy_hsic1",
2286 "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS
,
2288 GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI
,
2289 "phyclk_usbhost20_phy_clk48mohci",
2290 "mout_phyclk_usbhost20_phy_clk48mohci_user",
2291 ENABLE_SCLK_FSYS
, 11, 0, 0),
2292 GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK
,
2293 "phyclk_usbhost20_phy_phyclock",
2294 "mout_phyclk_usbhost20_phy_phyclock_user",
2295 ENABLE_SCLK_FSYS
, 10, 0, 0),
2296 GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK
,
2297 "phyclk_usbhost20_phy_freeclk",
2298 "mout_phyclk_usbhost20_phy_freeclk_user",
2299 ENABLE_SCLK_FSYS
, 9, 0, 0),
2300 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK
,
2301 "phyclk_usbdrd30_udrd30_pipe_pclk",
2302 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2303 ENABLE_SCLK_FSYS
, 8, 0, 0),
2304 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK
,
2305 "phyclk_usbdrd30_udrd30_phyclock",
2306 "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2307 ENABLE_SCLK_FSYS
, 7, 0, 0),
2308 GATE(CLK_SCLK_MPHY
, "sclk_mphy", "mout_sclk_mphy",
2309 ENABLE_SCLK_FSYS
, 6, 0, 0),
2310 GATE(CLK_SCLK_UFSUNIPRO
, "sclk_ufsunipro", "mout_sclk_ufsunipro_user",
2311 ENABLE_SCLK_FSYS
, 5, 0, 0),
2312 GATE(CLK_SCLK_MMC2
, "sclk_mmc2", "mout_sclk_mmc2_user",
2313 ENABLE_SCLK_FSYS
, 4, CLK_SET_RATE_PARENT
, 0),
2314 GATE(CLK_SCLK_MMC1
, "sclk_mmc1", "mout_sclk_mmc1_user",
2315 ENABLE_SCLK_FSYS
, 3, CLK_SET_RATE_PARENT
, 0),
2316 GATE(CLK_SCLK_MMC0
, "sclk_mmc0", "mout_sclk_mmc0_user",
2317 ENABLE_SCLK_FSYS
, 2, CLK_SET_RATE_PARENT
, 0),
2318 GATE(CLK_SCLK_USBHOST30
, "sclk_usbhost30", "mout_sclk_usbhost30_user",
2319 ENABLE_SCLK_FSYS
, 1, 0, 0),
2320 GATE(CLK_SCLK_USBDRD30
, "sclk_usbdrd30", "mout_sclk_usbdrd30_user",
2321 ENABLE_SCLK_FSYS
, 0, 0, 0),
2323 /* ENABLE_IP_FSYS0 */
2324 GATE(CLK_PDMA1
, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0
, 15, 0, 0),
2325 GATE(CLK_PDMA0
, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0
, 0, 0, 0),
2328 static struct samsung_cmu_info fsys_cmu_info __initdata
= {
2329 .mux_clks
= fsys_mux_clks
,
2330 .nr_mux_clks
= ARRAY_SIZE(fsys_mux_clks
),
2331 .gate_clks
= fsys_gate_clks
,
2332 .nr_gate_clks
= ARRAY_SIZE(fsys_gate_clks
),
2333 .fixed_clks
= fsys_fixed_clks
,
2334 .nr_fixed_clks
= ARRAY_SIZE(fsys_fixed_clks
),
2335 .nr_clk_ids
= FSYS_NR_CLK
,
2336 .clk_regs
= fsys_clk_regs
,
2337 .nr_clk_regs
= ARRAY_SIZE(fsys_clk_regs
),
2340 static void __init
exynos5433_cmu_fsys_init(struct device_node
*np
)
2342 samsung_cmu_register_one(np
, &fsys_cmu_info
);
2345 CLK_OF_DECLARE(exynos5433_cmu_fsys
, "samsung,exynos5433-cmu-fsys",
2346 exynos5433_cmu_fsys_init
);
2349 * Register offset definitions for CMU_G2D
2351 #define MUX_SEL_G2D0 0x0200
2352 #define MUX_SEL_ENABLE_G2D0 0x0300
2353 #define MUX_SEL_STAT_G2D0 0x0400
2354 #define DIV_G2D 0x0600
2355 #define DIV_STAT_G2D 0x0700
2356 #define DIV_ENABLE_ACLK_G2D 0x0800
2357 #define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804
2358 #define DIV_ENABLE_PCLK_G2D 0x0900
2359 #define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904
2360 #define DIV_ENABLE_IP_G2D0 0x0b00
2361 #define DIV_ENABLE_IP_G2D1 0x0b04
2362 #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08
2364 static unsigned long g2d_clk_regs
[] __initdata
= {
2366 MUX_SEL_ENABLE_G2D0
,
2370 DIV_ENABLE_ACLK_G2D
,
2371 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D
,
2372 DIV_ENABLE_PCLK_G2D
,
2373 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D
,
2376 DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D
,
2379 /* list of all parent clock list */
2380 PNAME(mout_aclk_g2d_266_user_p
) = { "oscclk", "aclk_g2d_266", };
2381 PNAME(mout_aclk_g2d_400_user_p
) = { "oscclk", "aclk_g2d_400", };
2383 static struct samsung_mux_clock g2d_mux_clks
[] __initdata
= {
2385 MUX(CLK_MUX_ACLK_G2D_266_USER
, "mout_aclk_g2d_266_user",
2386 mout_aclk_g2d_266_user_p
, MUX_SEL_G2D0
, 4, 1),
2387 MUX(CLK_MUX_ACLK_G2D_400_USER
, "mout_aclk_g2d_400_user",
2388 mout_aclk_g2d_400_user_p
, MUX_SEL_G2D0
, 0, 1),
2391 static struct samsung_div_clock g2d_div_clks
[] __initdata
= {
2393 DIV(CLK_DIV_PCLK_G2D
, "div_pclk_g2d", "mout_aclk_g2d_266_user",
2397 static struct samsung_gate_clock g2d_gate_clks
[] __initdata
= {
2398 /* DIV_ENABLE_ACLK_G2D */
2399 GATE(CLK_ACLK_SMMU_MDMA1
, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user",
2400 DIV_ENABLE_ACLK_G2D
, 12, 0, 0),
2401 GATE(CLK_ACLK_BTS_MDMA1
, "aclk_bts_mdam1", "mout_aclk_g2d_266_user",
2402 DIV_ENABLE_ACLK_G2D
, 11, 0, 0),
2403 GATE(CLK_ACLK_BTS_G2D
, "aclk_bts_g2d", "mout_aclk_g2d_400_user",
2404 DIV_ENABLE_ACLK_G2D
, 10, 0, 0),
2405 GATE(CLK_ACLK_ALB_G2D
, "aclk_alb_g2d", "mout_aclk_g2d_400_user",
2406 DIV_ENABLE_ACLK_G2D
, 9, 0, 0),
2407 GATE(CLK_ACLK_AXIUS_G2DX
, "aclk_axius_g2dx", "mout_aclk_g2d_400_user",
2408 DIV_ENABLE_ACLK_G2D
, 8, 0, 0),
2409 GATE(CLK_ACLK_ASYNCAXI_SYSX
, "aclk_asyncaxi_sysx",
2410 "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D
,
2412 GATE(CLK_ACLK_AHB2APB_G2D1P
, "aclk_ahb2apb_g2d1p", "div_pclk_g2d",
2413 DIV_ENABLE_ACLK_G2D
, 6, CLK_IGNORE_UNUSED
, 0),
2414 GATE(CLK_ACLK_AHB2APB_G2D0P
, "aclk_ahb2apb_g2d0p", "div_pclk_g2d",
2415 DIV_ENABLE_ACLK_G2D
, 5, CLK_IGNORE_UNUSED
, 0),
2416 GATE(CLK_ACLK_XIU_G2DX
, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user",
2417 DIV_ENABLE_ACLK_G2D
, 4, CLK_IGNORE_UNUSED
, 0),
2418 GATE(CLK_ACLK_G2DNP_133
, "aclk_g2dnp_133", "div_pclk_g2d",
2419 DIV_ENABLE_ACLK_G2D
, 3, CLK_IGNORE_UNUSED
, 0),
2420 GATE(CLK_ACLK_G2DND_400
, "aclk_g2dnd_400", "mout_aclk_g2d_400_user",
2421 DIV_ENABLE_ACLK_G2D
, 2, CLK_IGNORE_UNUSED
, 0),
2422 GATE(CLK_ACLK_MDMA1
, "aclk_mdma1", "mout_aclk_g2d_266_user",
2423 DIV_ENABLE_ACLK_G2D
, 1, 0, 0),
2424 GATE(CLK_ACLK_G2D
, "aclk_g2d", "mout_aclk_g2d_400_user",
2425 DIV_ENABLE_ACLK_G2D
, 0, 0, 0),
2427 /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */
2428 GATE(CLK_ACLK_SMMU_G2D
, "aclk_smmu_g2d", "mout_aclk_g2d_400_user",
2429 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D
, 0, 0, 0),
2431 /* DIV_ENABLE_PCLK_G2D */
2432 GATE(CLK_PCLK_SMMU_MDMA1
, "pclk_smmu_mdma1", "div_pclk_g2d",
2433 DIV_ENABLE_PCLK_G2D
, 7, 0, 0),
2434 GATE(CLK_PCLK_BTS_MDMA1
, "pclk_bts_mdam1", "div_pclk_g2d",
2435 DIV_ENABLE_PCLK_G2D
, 6, 0, 0),
2436 GATE(CLK_PCLK_BTS_G2D
, "pclk_bts_g2d", "div_pclk_g2d",
2437 DIV_ENABLE_PCLK_G2D
, 5, 0, 0),
2438 GATE(CLK_PCLK_ALB_G2D
, "pclk_alb_g2d", "div_pclk_g2d",
2439 DIV_ENABLE_PCLK_G2D
, 4, 0, 0),
2440 GATE(CLK_PCLK_ASYNCAXI_SYSX
, "pclk_asyncaxi_sysx", "div_pclk_g2d",
2441 DIV_ENABLE_PCLK_G2D
, 3, 0, 0),
2442 GATE(CLK_PCLK_PMU_G2D
, "pclk_pmu_g2d", "div_pclk_g2d",
2443 DIV_ENABLE_PCLK_G2D
, 2, CLK_IGNORE_UNUSED
, 0),
2444 GATE(CLK_PCLK_SYSREG_G2D
, "pclk_sysreg_g2d", "div_pclk_g2d",
2445 DIV_ENABLE_PCLK_G2D
, 1, CLK_IGNORE_UNUSED
, 0),
2446 GATE(CLK_PCLK_G2D
, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D
,
2449 /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */
2450 GATE(CLK_PCLK_SMMU_G2D
, "pclk_smmu_g2d", "div_pclk_g2d",
2451 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D
, 0, 0, 0),
2454 static struct samsung_cmu_info g2d_cmu_info __initdata
= {
2455 .mux_clks
= g2d_mux_clks
,
2456 .nr_mux_clks
= ARRAY_SIZE(g2d_mux_clks
),
2457 .div_clks
= g2d_div_clks
,
2458 .nr_div_clks
= ARRAY_SIZE(g2d_div_clks
),
2459 .gate_clks
= g2d_gate_clks
,
2460 .nr_gate_clks
= ARRAY_SIZE(g2d_gate_clks
),
2461 .nr_clk_ids
= G2D_NR_CLK
,
2462 .clk_regs
= g2d_clk_regs
,
2463 .nr_clk_regs
= ARRAY_SIZE(g2d_clk_regs
),
2466 static void __init
exynos5433_cmu_g2d_init(struct device_node
*np
)
2468 samsung_cmu_register_one(np
, &g2d_cmu_info
);
2471 CLK_OF_DECLARE(exynos5433_cmu_g2d
, "samsung,exynos5433-cmu-g2d",
2472 exynos5433_cmu_g2d_init
);
2475 * Register offset definitions for CMU_DISP
2477 #define DISP_PLL_LOCK 0x0000
2478 #define DISP_PLL_CON0 0x0100
2479 #define DISP_PLL_CON1 0x0104
2480 #define DISP_PLL_FREQ_DET 0x0108
2481 #define MUX_SEL_DISP0 0x0200
2482 #define MUX_SEL_DISP1 0x0204
2483 #define MUX_SEL_DISP2 0x0208
2484 #define MUX_SEL_DISP3 0x020c
2485 #define MUX_SEL_DISP4 0x0210
2486 #define MUX_ENABLE_DISP0 0x0300
2487 #define MUX_ENABLE_DISP1 0x0304
2488 #define MUX_ENABLE_DISP2 0x0308
2489 #define MUX_ENABLE_DISP3 0x030c
2490 #define MUX_ENABLE_DISP4 0x0310
2491 #define MUX_STAT_DISP0 0x0400
2492 #define MUX_STAT_DISP1 0x0404
2493 #define MUX_STAT_DISP2 0x0408
2494 #define MUX_STAT_DISP3 0x040c
2495 #define MUX_STAT_DISP4 0x0410
2496 #define MUX_IGNORE_DISP2 0x0508
2497 #define DIV_DISP 0x0600
2498 #define DIV_DISP_PLL_FREQ_DET 0x0604
2499 #define DIV_STAT_DISP 0x0700
2500 #define DIV_STAT_DISP_PLL_FREQ_DET 0x0704
2501 #define ENABLE_ACLK_DISP0 0x0800
2502 #define ENABLE_ACLK_DISP1 0x0804
2503 #define ENABLE_PCLK_DISP 0x0900
2504 #define ENABLE_SCLK_DISP 0x0a00
2505 #define ENABLE_IP_DISP0 0x0b00
2506 #define ENABLE_IP_DISP1 0x0b04
2507 #define CLKOUT_CMU_DISP 0x0c00
2508 #define CLKOUT_CMU_DISP_DIV_STAT 0x0c04
2510 static unsigned long disp_clk_regs
[] __initdata
= {
2532 DIV_DISP_PLL_FREQ_DET
,
2534 DIV_STAT_DISP_PLL_FREQ_DET
,
2542 CLKOUT_CMU_DISP_DIV_STAT
,
2545 /* list of all parent clock list */
2546 PNAME(mout_disp_pll_p
) = { "oscclk", "fout_disp_pll", };
2547 PNAME(mout_sclk_dsim1_user_p
) = { "oscclk", "sclk_dsim1_disp", };
2548 PNAME(mout_sclk_dsim0_user_p
) = { "oscclk", "sclk_dsim0_disp", };
2549 PNAME(mout_sclk_dsd_user_p
) = { "oscclk", "sclk_dsd_disp", };
2550 PNAME(mout_sclk_decon_tv_eclk_user_p
) = { "oscclk",
2551 "sclk_decon_tv_eclk_disp", };
2552 PNAME(mout_sclk_decon_vclk_user_p
) = { "oscclk",
2553 "sclk_decon_vclk_disp", };
2554 PNAME(mout_sclk_decon_eclk_user_p
) = { "oscclk",
2555 "sclk_decon_eclk_disp", };
2556 PNAME(mout_sclk_decon_tv_vlkc_user_p
) = { "oscclk",
2557 "sclk_decon_tv_vclk_disp", };
2558 PNAME(mout_aclk_disp_333_user_p
) = { "oscclk", "aclk_disp_333", };
2560 PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p
) = { "oscclk",
2561 "phyclk_mipidphy1_bitclkdiv8_phy", };
2562 PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p
) = { "oscclk",
2563 "phyclk_mipidphy1_rxclkesc0_phy", };
2564 PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p
) = { "oscclk",
2565 "phyclk_mipidphy0_bitclkdiv8_phy", };
2566 PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p
) = { "oscclk",
2567 "phyclk_mipidphy0_rxclkesc0_phy", };
2568 PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p
) = { "oscclk",
2569 "phyclk_hdmiphy_tmds_clko_phy", };
2570 PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p
) = { "oscclk",
2571 "phyclk_hdmiphy_pixel_clko_phy", };
2573 PNAME(mout_sclk_dsim0_p
) = { "mout_disp_pll",
2574 "mout_sclk_dsim0_user", };
2575 PNAME(mout_sclk_decon_tv_eclk_p
) = { "mout_disp_pll",
2576 "mout_sclk_decon_tv_eclk_user", };
2577 PNAME(mout_sclk_decon_vclk_p
) = { "mout_disp_pll",
2578 "mout_sclk_decon_vclk_user", };
2579 PNAME(mout_sclk_decon_eclk_p
) = { "mout_disp_pll",
2580 "mout_sclk_decon_eclk_user", };
2582 PNAME(mout_sclk_dsim1_b_disp_p
) = { "mout_sclk_dsim1_a_disp",
2583 "mout_sclk_dsim1_user", };
2584 PNAME(mout_sclk_decon_tv_vclk_c_disp_p
) = {
2585 "mout_phyclk_hdmiphy_pixel_clko_user",
2586 "mout_sclk_decon_tv_vclk_b_disp", };
2587 PNAME(mout_sclk_decon_tv_vclk_b_disp_p
) = { "mout_sclk_decon_tv_vclk_a_disp",
2588 "mout_sclk_decon_tv_vclk_user", };
2590 static struct samsung_pll_clock disp_pll_clks
[] __initdata
= {
2591 PLL(pll_35xx
, CLK_FOUT_DISP_PLL
, "fout_disp_pll", "oscclk",
2592 DISP_PLL_LOCK
, DISP_PLL_CON0
, exynos5443_pll_rates
),
2595 static struct samsung_fixed_factor_clock disp_fixed_factor_clks
[] __initdata
= {
2597 * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}.
2598 * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk}
2599 * and sclk_decon_{vclk|tv_vclk}.
2601 FFACTOR(CLK_SCLK_RGB_VCLK
, "sclk_rgb_vclk", "sclk_decon_vclk",
2603 FFACTOR(CLK_SCLK_RGB_TV_VCLK
, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk",
2607 static struct samsung_fixed_rate_clock disp_fixed_clks
[] __initdata
= {
2608 /* PHY clocks from MIPI_DPHY1 */
2609 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL
, CLK_IS_ROOT
,
2611 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL
, CLK_IS_ROOT
,
2613 /* PHY clocks from MIPI_DPHY0 */
2614 FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL
, CLK_IS_ROOT
,
2616 FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL
, CLK_IS_ROOT
,
2618 /* PHY clocks from HDMI_PHY */
2619 FRATE(0, "phyclk_hdmiphy_tmds_clko_phy", NULL
, CLK_IS_ROOT
, 300000000),
2620 FRATE(0, "phyclk_hdmiphy_pixel_clko_phy", NULL
, CLK_IS_ROOT
, 166000000),
2623 static struct samsung_mux_clock disp_mux_clks
[] __initdata
= {
2625 MUX(CLK_MOUT_DISP_PLL
, "mout_disp_pll", mout_disp_pll_p
, MUX_SEL_DISP0
,
2629 MUX(CLK_MOUT_SCLK_DSIM1_USER
, "mout_sclk_dsim1_user",
2630 mout_sclk_dsim1_user_p
, MUX_SEL_DISP1
, 28, 1),
2631 MUX(CLK_MOUT_SCLK_DSIM0_USER
, "mout_sclk_dsim0_user",
2632 mout_sclk_dsim0_user_p
, MUX_SEL_DISP1
, 24, 1),
2633 MUX(CLK_MOUT_SCLK_DSD_USER
, "mout_sclk_dsd_user", mout_sclk_dsd_user_p
,
2634 MUX_SEL_DISP1
, 20, 1),
2635 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER
, "mout_sclk_decon_tv_eclk_user",
2636 mout_sclk_decon_tv_eclk_user_p
, MUX_SEL_DISP1
, 16, 1),
2637 MUX(CLK_MOUT_SCLK_DECON_VCLK_USER
, "mout_sclk_decon_vclk_user",
2638 mout_sclk_decon_vclk_user_p
, MUX_SEL_DISP1
, 12, 1),
2639 MUX(CLK_MOUT_SCLK_DECON_ECLK_USER
, "mout_sclk_decon_eclk_user",
2640 mout_sclk_decon_eclk_user_p
, MUX_SEL_DISP1
, 8, 1),
2641 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER
, "mout_sclk_decon_tv_vclk_user",
2642 mout_sclk_decon_tv_vlkc_user_p
, MUX_SEL_DISP1
, 4, 1),
2643 MUX(CLK_MOUT_ACLK_DISP_333_USER
, "mout_aclk_disp_333_user",
2644 mout_aclk_disp_333_user_p
, MUX_SEL_DISP1
, 0, 1),
2647 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER
,
2648 "mout_phyclk_mipidphy1_bitclkdiv8_user",
2649 mout_phyclk_mipidphy1_bitclkdiv8_user_p
, MUX_SEL_DISP2
,
2651 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER
,
2652 "mout_phyclk_mipidphy1_rxclkesc0_user",
2653 mout_phyclk_mipidphy1_rxclkesc0_user_p
, MUX_SEL_DISP2
,
2655 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER
,
2656 "mout_phyclk_mipidphy0_bitclkdiv8_user",
2657 mout_phyclk_mipidphy0_bitclkdiv8_user_p
, MUX_SEL_DISP2
,
2659 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER
,
2660 "mout_phyclk_mipidphy0_rxclkesc0_user",
2661 mout_phyclk_mipidphy0_rxclkesc0_user_p
, MUX_SEL_DISP2
,
2663 MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER
,
2664 "mout_phyclk_hdmiphy_tmds_clko_user",
2665 mout_phyclk_hdmiphy_tmds_clko_user_p
, MUX_SEL_DISP2
,
2667 MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER
,
2668 "mout_phyclk_hdmiphy_pixel_clko_user",
2669 mout_phyclk_hdmiphy_pixel_clko_user_p
, MUX_SEL_DISP2
,
2673 MUX(CLK_MOUT_SCLK_DSIM0
, "mout_sclk_dsim0", mout_sclk_dsim0_p
,
2674 MUX_SEL_DISP3
, 12, 1),
2675 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK
, "mout_sclk_decon_tv_eclk",
2676 mout_sclk_decon_tv_eclk_p
, MUX_SEL_DISP3
, 8, 1),
2677 MUX(CLK_MOUT_SCLK_DECON_VCLK
, "mout_sclk_decon_vclk",
2678 mout_sclk_decon_vclk_p
, MUX_SEL_DISP3
, 4, 1),
2679 MUX(CLK_MOUT_SCLK_DECON_ECLK
, "mout_sclk_decon_eclk",
2680 mout_sclk_decon_eclk_p
, MUX_SEL_DISP3
, 0, 1),
2683 MUX(CLK_MOUT_SCLK_DSIM1_B_DISP
, "mout_sclk_dsim1_b_disp",
2684 mout_sclk_dsim1_b_disp_p
, MUX_SEL_DISP4
, 16, 1),
2685 MUX(CLK_MOUT_SCLK_DSIM1_A_DISP
, "mout_sclk_dsim1_a_disp",
2686 mout_sclk_dsim0_p
, MUX_SEL_DISP4
, 12, 1),
2687 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP
,
2688 "mout_sclk_decon_tv_vclk_c_disp",
2689 mout_sclk_decon_tv_vclk_c_disp_p
, MUX_SEL_DISP4
, 8, 1),
2690 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP
,
2691 "mout_sclk_decon_tv_vclk_b_disp",
2692 mout_sclk_decon_tv_vclk_b_disp_p
, MUX_SEL_DISP4
, 4, 1),
2693 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP
,
2694 "mout_sclk_decon_tv_vclk_a_disp",
2695 mout_sclk_decon_vclk_p
, MUX_SEL_DISP4
, 0, 1),
2698 static struct samsung_div_clock disp_div_clks
[] __initdata
= {
2700 DIV(CLK_DIV_SCLK_DSIM1_DISP
, "div_sclk_dsim1_disp",
2701 "mout_sclk_dsim1_b_disp", DIV_DISP
, 24, 3),
2702 DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP
, "div_sclk_decon_tv_vclk_disp",
2703 "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP
, 20, 3),
2704 DIV(CLK_DIV_SCLK_DSIM0_DISP
, "div_sclk_dsim0_disp", "mout_sclk_dsim0",
2706 DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP
, "div_sclk_decon_tv_eclk_disp",
2707 "mout_sclk_decon_tv_eclk", DIV_DISP
, 12, 3),
2708 DIV(CLK_DIV_SCLK_DECON_VCLK_DISP
, "div_sclk_decon_vclk_disp",
2709 "mout_sclk_decon_vclk", DIV_DISP
, 8, 3),
2710 DIV(CLK_DIV_SCLK_DECON_ECLK_DISP
, "div_sclk_decon_eclk_disp",
2711 "mout_sclk_decon_eclk", DIV_DISP
, 4, 3),
2712 DIV(CLK_DIV_PCLK_DISP
, "div_pclk_disp", "mout_aclk_disp_333_user",
2716 static struct samsung_gate_clock disp_gate_clks
[] __initdata
= {
2717 /* ENABLE_ACLK_DISP0 */
2718 GATE(CLK_ACLK_DECON_TV
, "aclk_decon_tv", "mout_aclk_disp_333_user",
2719 ENABLE_ACLK_DISP0
, 2, 0, 0),
2720 GATE(CLK_ACLK_DECON
, "aclk_decon", "mout_aclk_disp_333_user",
2721 ENABLE_ACLK_DISP0
, 0, 0, 0),
2723 /* ENABLE_ACLK_DISP1 */
2724 GATE(CLK_ACLK_SMMU_TV1X
, "aclk_smmu_tv1x", "mout_aclk_disp_333_user",
2725 ENABLE_ACLK_DISP1
, 25, 0, 0),
2726 GATE(CLK_ACLK_SMMU_TV0X
, "aclk_smmu_tv0x", "mout_aclk_disp_333_user",
2727 ENABLE_ACLK_DISP1
, 24, 0, 0),
2728 GATE(CLK_ACLK_SMMU_DECON1X
, "aclk_smmu_decon1x",
2729 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1
, 23, 0, 0),
2730 GATE(CLK_ACLK_SMMU_DECON0X
, "aclk_smmu_decon0x",
2731 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1
, 22, 0, 0),
2732 GATE(CLK_ACLK_BTS_DECON_TV_M3
, "aclk_bts_decon_tv_m3",
2733 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1
, 21, 0, 0),
2734 GATE(CLK_ACLK_BTS_DECON_TV_M2
, "aclk_bts_decon_tv_m2",
2735 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1
, 20, 0, 0),
2736 GATE(CLK_ACLK_BTS_DECON_TV_M1
, "aclk_bts_decon_tv_m1",
2737 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1
, 19, 0, 0),
2738 GATE(CLK_ACLK_BTS_DECON_TV_M0
, "aclk-bts_decon_tv_m0",
2739 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1
, 18, 0, 0),
2740 GATE(CLK_ACLK_BTS_DECON_NM4
, "aclk_bts_decon_nm4",
2741 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1
, 17, 0, 0),
2742 GATE(CLK_ACLK_BTS_DECON_NM3
, "aclk_bts_decon_nm3",
2743 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1
, 16, 0, 0),
2744 GATE(CLK_ACLK_BTS_DECON_NM2
, "aclk_bts_decon_nm2",
2745 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1
, 15, 0, 0),
2746 GATE(CLK_ACLK_BTS_DECON_NM1
, "aclk_bts_decon_nm1",
2747 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1
, 14, 0, 0),
2748 GATE(CLK_ACLK_BTS_DECON_NM0
, "aclk_bts_decon_nm0",
2749 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1
, 13, 0, 0),
2750 GATE(CLK_ACLK_AHB2APB_DISPSFR2P
, "aclk_ahb2apb_dispsfr2p",
2751 "div_pclk_disp", ENABLE_ACLK_DISP1
,
2752 12, CLK_IGNORE_UNUSED
, 0),
2753 GATE(CLK_ACLK_AHB2APB_DISPSFR1P
, "aclk_ahb2apb_dispsfr1p",
2754 "div_pclk_disp", ENABLE_ACLK_DISP1
,
2755 11, CLK_IGNORE_UNUSED
, 0),
2756 GATE(CLK_ACLK_AHB2APB_DISPSFR0P
, "aclk_ahb2apb_dispsfr0p",
2757 "div_pclk_disp", ENABLE_ACLK_DISP1
,
2758 10, CLK_IGNORE_UNUSED
, 0),
2759 GATE(CLK_ACLK_AHB_DISPH
, "aclk_ahb_disph", "div_pclk_disp",
2760 ENABLE_ACLK_DISP1
, 8, CLK_IGNORE_UNUSED
, 0),
2761 GATE(CLK_ACLK_XIU_TV1X
, "aclk_xiu_tv1x", "mout_aclk_disp_333_user",
2762 ENABLE_ACLK_DISP1
, 7, 0, 0),
2763 GATE(CLK_ACLK_XIU_TV0X
, "aclk_xiu_tv0x", "mout_aclk_disp_333_user",
2764 ENABLE_ACLK_DISP1
, 6, 0, 0),
2765 GATE(CLK_ACLK_XIU_DECON1X
, "aclk_xiu_decon1x",
2766 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1
, 5, 0, 0),
2767 GATE(CLK_ACLK_XIU_DECON0X
, "aclk_xiu_decon0x",
2768 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1
, 4, 0, 0),
2769 GATE(CLK_ACLK_XIU_DISP1X
, "aclk_xiu_disp1x", "mout_aclk_disp_333_user",
2770 ENABLE_ACLK_DISP1
, 3, CLK_IGNORE_UNUSED
, 0),
2771 GATE(CLK_ACLK_XIU_DISPNP_100
, "aclk_xiu_dispnp_100", "div_pclk_disp",
2772 ENABLE_ACLK_DISP1
, 2, CLK_IGNORE_UNUSED
, 0),
2773 GATE(CLK_ACLK_DISP1ND_333
, "aclk_disp1nd_333",
2774 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1
, 1,
2775 CLK_IGNORE_UNUSED
, 0),
2776 GATE(CLK_ACLK_DISP0ND_333
, "aclk_disp0nd_333",
2777 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1
,
2778 0, CLK_IGNORE_UNUSED
, 0),
2780 /* ENABLE_PCLK_DISP */
2781 GATE(CLK_PCLK_SMMU_TV1X
, "pclk_smmu_tv1x", "div_pclk_disp",
2782 ENABLE_PCLK_DISP
, 23, 0, 0),
2783 GATE(CLK_PCLK_SMMU_TV0X
, "pclk_smmu_tv0x", "div_pclk_disp",
2784 ENABLE_PCLK_DISP
, 22, 0, 0),
2785 GATE(CLK_PCLK_SMMU_DECON1X
, "pclk_smmu_decon1x", "div_pclk_disp",
2786 ENABLE_PCLK_DISP
, 21, 0, 0),
2787 GATE(CLK_PCLK_SMMU_DECON0X
, "pclk_smmu_decon0x", "div_pclk_disp",
2788 ENABLE_PCLK_DISP
, 20, 0, 0),
2789 GATE(CLK_PCLK_BTS_DECON_TV_M3
, "pclk_bts_decon_tv_m3", "div_pclk_disp",
2790 ENABLE_PCLK_DISP
, 19, 0, 0),
2791 GATE(CLK_PCLK_BTS_DECON_TV_M2
, "pclk_bts_decon_tv_m2", "div_pclk_disp",
2792 ENABLE_PCLK_DISP
, 18, 0, 0),
2793 GATE(CLK_PCLK_BTS_DECON_TV_M1
, "pclk_bts_decon_tv_m1", "div_pclk_disp",
2794 ENABLE_PCLK_DISP
, 17, 0, 0),
2795 GATE(CLK_PCLK_BTS_DECON_TV_M0
, "pclk_bts_decon_tv_m0", "div_pclk_disp",
2796 ENABLE_PCLK_DISP
, 16, 0, 0),
2797 GATE(CLK_PCLK_BTS_DECONM4
, "pclk_bts_deconm4", "div_pclk_disp",
2798 ENABLE_PCLK_DISP
, 15, 0, 0),
2799 GATE(CLK_PCLK_BTS_DECONM3
, "pclk_bts_deconm3", "div_pclk_disp",
2800 ENABLE_PCLK_DISP
, 14, 0, 0),
2801 GATE(CLK_PCLK_BTS_DECONM2
, "pclk_bts_deconm2", "div_pclk_disp",
2802 ENABLE_PCLK_DISP
, 13, 0, 0),
2803 GATE(CLK_PCLK_BTS_DECONM1
, "pclk_bts_deconm1", "div_pclk_disp",
2804 ENABLE_PCLK_DISP
, 12, 0, 0),
2805 GATE(CLK_PCLK_BTS_DECONM0
, "pclk_bts_deconm0", "div_pclk_disp",
2806 ENABLE_PCLK_DISP
, 11, 0, 0),
2807 GATE(CLK_PCLK_MIC1
, "pclk_mic1", "div_pclk_disp",
2808 ENABLE_PCLK_DISP
, 10, 0, 0),
2809 GATE(CLK_PCLK_PMU_DISP
, "pclk_pmu_disp", "div_pclk_disp",
2810 ENABLE_PCLK_DISP
, 9, CLK_IGNORE_UNUSED
, 0),
2811 GATE(CLK_PCLK_SYSREG_DISP
, "pclk_sysreg_disp", "div_pclk_disp",
2812 ENABLE_PCLK_DISP
, 8, CLK_IGNORE_UNUSED
, 0),
2813 GATE(CLK_PCLK_HDMIPHY
, "pclk_hdmiphy", "div_pclk_disp",
2814 ENABLE_PCLK_DISP
, 7, 0, 0),
2815 GATE(CLK_PCLK_HDMI
, "pclk_hdmi", "div_pclk_disp",
2816 ENABLE_PCLK_DISP
, 6, 0, 0),
2817 GATE(CLK_PCLK_MIC0
, "pclk_mic0", "div_pclk_disp",
2818 ENABLE_PCLK_DISP
, 5, 0, 0),
2819 GATE(CLK_PCLK_DSIM1
, "pclk_dsim1", "div_pclk_disp",
2820 ENABLE_PCLK_DISP
, 3, 0, 0),
2821 GATE(CLK_PCLK_DSIM0
, "pclk_dsim0", "div_pclk_disp",
2822 ENABLE_PCLK_DISP
, 2, 0, 0),
2823 GATE(CLK_PCLK_DECON_TV
, "pclk_decon_tv", "div_pclk_disp",
2824 ENABLE_PCLK_DISP
, 1, 0, 0),
2826 /* ENABLE_SCLK_DISP */
2827 GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8
, "phyclk_mipidphy1_bitclkdiv8",
2828 "mout_phyclk_mipidphy1_bitclkdiv8_user",
2829 ENABLE_SCLK_DISP
, 26, 0, 0),
2830 GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0
, "phyclk_mipidphy1_rxclkesc0",
2831 "mout_phyclk_mipidphy1_rxclkesc0_user",
2832 ENABLE_SCLK_DISP
, 25, 0, 0),
2833 GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1
, "sclk_rgb_tv_vclk_to_dsim1",
2834 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP
, 24, 0, 0),
2835 GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1
, "sclk_rgb_tv_vclk_to_mic1",
2836 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP
, 23, 0, 0),
2837 GATE(CLK_SCLK_DSIM1
, "sclk_dsim1", "div_sclk_dsim1_disp",
2838 ENABLE_SCLK_DISP
, 22, 0, 0),
2839 GATE(CLK_SCLK_DECON_TV_VCLK
, "sclk_decon_tv_vclk",
2840 "div_sclk_decon_tv_vclk_disp",
2841 ENABLE_SCLK_DISP
, 21, 0, 0),
2842 GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8
, "phyclk_mipidphy0_bitclkdiv8",
2843 "mout_phyclk_mipidphy0_bitclkdiv8_user",
2844 ENABLE_SCLK_DISP
, 15, 0, 0),
2845 GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0
, "phyclk_mipidphy0_rxclkesc0",
2846 "mout_phyclk_mipidphy0_rxclkesc0_user",
2847 ENABLE_SCLK_DISP
, 14, 0, 0),
2848 GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO
, "phyclk_hdmiphy_tmds_clko",
2849 "mout_phyclk_hdmiphy_tmds_clko_user",
2850 ENABLE_SCLK_DISP
, 13, 0, 0),
2851 GATE(CLK_PHYCLK_HDMI_PIXEL
, "phyclk_hdmi_pixel",
2852 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP
, 12, 0, 0),
2853 GATE(CLK_SCLK_RGB_VCLK_TO_SMIES
, "sclk_rgb_vclk_to_smies",
2854 "sclk_rgb_vclk", ENABLE_SCLK_DISP
, 11, 0, 0),
2855 GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0
, "sclk_rgb_vclk_to_dsim0",
2856 "sclk_rgb_vclk", ENABLE_SCLK_DISP
, 9, 0, 0),
2857 GATE(CLK_SCLK_RGB_VCLK_TO_MIC0
, "sclk_rgb_vclk_to_mic0",
2858 "sclk_rgb_vclk", ENABLE_SCLK_DISP
, 8, 0, 0),
2859 GATE(CLK_SCLK_DSD
, "sclk_dsd", "mout_sclk_dsd_user",
2860 ENABLE_SCLK_DISP
, 7, 0, 0),
2861 GATE(CLK_SCLK_HDMI_SPDIF
, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp",
2862 ENABLE_SCLK_DISP
, 6, 0, 0),
2863 GATE(CLK_SCLK_DSIM0
, "sclk_dsim0", "div_sclk_dsim0_disp",
2864 ENABLE_SCLK_DISP
, 5, 0, 0),
2865 GATE(CLK_SCLK_DECON_TV_ECLK
, "sclk_decon_tv_eclk",
2866 "div_sclk_decon_tv_eclk_disp",
2867 ENABLE_SCLK_DISP
, 4, 0, 0),
2868 GATE(CLK_SCLK_DECON_VCLK
, "sclk_decon_vclk",
2869 "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP
, 3, 0, 0),
2870 GATE(CLK_SCLK_DECON_ECLK
, "sclk_decon_eclk",
2871 "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP
, 2, 0, 0),
2874 static struct samsung_cmu_info disp_cmu_info __initdata
= {
2875 .pll_clks
= disp_pll_clks
,
2876 .nr_pll_clks
= ARRAY_SIZE(disp_pll_clks
),
2877 .mux_clks
= disp_mux_clks
,
2878 .nr_mux_clks
= ARRAY_SIZE(disp_mux_clks
),
2879 .div_clks
= disp_div_clks
,
2880 .nr_div_clks
= ARRAY_SIZE(disp_div_clks
),
2881 .gate_clks
= disp_gate_clks
,
2882 .nr_gate_clks
= ARRAY_SIZE(disp_gate_clks
),
2883 .fixed_clks
= disp_fixed_clks
,
2884 .nr_fixed_clks
= ARRAY_SIZE(disp_fixed_clks
),
2885 .fixed_factor_clks
= disp_fixed_factor_clks
,
2886 .nr_fixed_factor_clks
= ARRAY_SIZE(disp_fixed_factor_clks
),
2887 .nr_clk_ids
= DISP_NR_CLK
,
2888 .clk_regs
= disp_clk_regs
,
2889 .nr_clk_regs
= ARRAY_SIZE(disp_clk_regs
),
2892 static void __init
exynos5433_cmu_disp_init(struct device_node
*np
)
2894 samsung_cmu_register_one(np
, &disp_cmu_info
);
2897 CLK_OF_DECLARE(exynos5433_cmu_disp
, "samsung,exynos5433-cmu-disp",
2898 exynos5433_cmu_disp_init
);
2901 * Register offset definitions for CMU_AUD
2903 #define MUX_SEL_AUD0 0x0200
2904 #define MUX_SEL_AUD1 0x0204
2905 #define MUX_ENABLE_AUD0 0x0300
2906 #define MUX_ENABLE_AUD1 0x0304
2907 #define MUX_STAT_AUD0 0x0400
2908 #define DIV_AUD0 0x0600
2909 #define DIV_AUD1 0x0604
2910 #define DIV_STAT_AUD0 0x0700
2911 #define DIV_STAT_AUD1 0x0704
2912 #define ENABLE_ACLK_AUD 0x0800
2913 #define ENABLE_PCLK_AUD 0x0900
2914 #define ENABLE_SCLK_AUD0 0x0a00
2915 #define ENABLE_SCLK_AUD1 0x0a04
2916 #define ENABLE_IP_AUD0 0x0b00
2917 #define ENABLE_IP_AUD1 0x0b04
2919 static unsigned long aud_clk_regs
[] __initdata
= {
2937 /* list of all parent clock list */
2938 PNAME(mout_aud_pll_user_aud_p
) = { "oscclk", "fout_aud_pll", };
2939 PNAME(mout_sclk_aud_pcm_p
) = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
2941 static struct samsung_fixed_rate_clock aud_fixed_clks
[] __initdata
= {
2942 FRATE(0, "ioclk_jtag_tclk", NULL
, CLK_IS_ROOT
, 33000000),
2943 FRATE(0, "ioclk_slimbus_clk", NULL
, CLK_IS_ROOT
, 25000000),
2944 FRATE(0, "ioclk_i2s_bclk", NULL
, CLK_IS_ROOT
, 50000000),
2947 static struct samsung_mux_clock aud_mux_clks
[] __initdata
= {
2949 MUX(CLK_MOUT_AUD_PLL_USER
, "mout_aud_pll_user",
2950 mout_aud_pll_user_aud_p
, MUX_SEL_AUD0
, 0, 1),
2953 MUX(CLK_MOUT_SCLK_AUD_PCM
, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p
,
2954 MUX_SEL_AUD1
, 8, 1),
2955 MUX(CLK_MOUT_SCLK_AUD_I2S
, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p
,
2956 MUX_SEL_AUD1
, 0, 1),
2959 static struct samsung_div_clock aud_div_clks
[] __initdata
= {
2961 DIV(CLK_DIV_ATCLK_AUD
, "div_atclk_aud", "div_aud_ca5", DIV_AUD0
,
2963 DIV(CLK_DIV_PCLK_DBG_AUD
, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0
,
2965 DIV(CLK_DIV_ACLK_AUD
, "div_aclk_aud", "div_aud_ca5", DIV_AUD0
,
2967 DIV(CLK_DIV_AUD_CA5
, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0
,
2971 DIV(CLK_DIV_SCLK_AUD_SLIMBUS
, "div_sclk_aud_slimbus",
2972 "mout_aud_pll_user", DIV_AUD1
, 16, 5),
2973 DIV(CLK_DIV_SCLK_AUD_UART
, "div_sclk_aud_uart", "mout_aud_pll_user",
2975 DIV(CLK_DIV_SCLK_AUD_PCM
, "div_sclk_aud_pcm", "mout_sclk_aud_pcm",
2977 DIV(CLK_DIV_SCLK_AUD_I2S
, "div_sclk_aud_i2s", "mout_sclk_aud_i2s",
2981 static struct samsung_gate_clock aud_gate_clks
[] __initdata
= {
2982 /* ENABLE_ACLK_AUD */
2983 GATE(CLK_ACLK_INTR_CTRL
, "aclk_intr_ctrl", "div_aclk_aud",
2984 ENABLE_ACLK_AUD
, 12, 0, 0),
2985 GATE(CLK_ACLK_SMMU_LPASSX
, "aclk_smmu_lpassx", "div_aclk_aud",
2986 ENABLE_ACLK_AUD
, 7, 0, 0),
2987 GATE(CLK_ACLK_XIU_LPASSX
, "aclk_xiu_lpassx", "div_aclk_aud",
2988 ENABLE_ACLK_AUD
, 0, 4, 0),
2989 GATE(CLK_ACLK_AUDNP_133
, "aclk_audnp_133", "div_aclk_aud",
2990 ENABLE_ACLK_AUD
, 0, 3, 0),
2991 GATE(CLK_ACLK_AUDND_133
, "aclk_audnd_133", "div_aclk_aud",
2992 ENABLE_ACLK_AUD
, 0, 2, 0),
2993 GATE(CLK_ACLK_SRAMC
, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD
,
2995 GATE(CLK_ACLK_DMAC
, "aclk_dmac", "div_aclk_aud", ENABLE_ACLK_AUD
,
2996 0, CLK_IGNORE_UNUSED
, 0),
2998 /* ENABLE_PCLK_AUD */
2999 GATE(CLK_PCLK_WDT1
, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD
,
3001 GATE(CLK_PCLK_WDT0
, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD
,
3003 GATE(CLK_PCLK_SFR1
, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD
,
3005 GATE(CLK_PCLK_SMMU_LPASSX
, "pclk_smmu_lpassx", "div_aclk_aud",
3006 ENABLE_PCLK_AUD
, 10, 0, 0),
3007 GATE(CLK_PCLK_GPIO_AUD
, "pclk_gpio_aud", "div_aclk_aud",
3008 ENABLE_PCLK_AUD
, 9, CLK_IGNORE_UNUSED
, 0),
3009 GATE(CLK_PCLK_PMU_AUD
, "pclk_pmu_aud", "div_aclk_aud",
3010 ENABLE_PCLK_AUD
, 8, CLK_IGNORE_UNUSED
, 0),
3011 GATE(CLK_PCLK_SYSREG_AUD
, "pclk_sysreg_aud", "div_aclk_aud",
3012 ENABLE_PCLK_AUD
, 7, CLK_IGNORE_UNUSED
, 0),
3013 GATE(CLK_PCLK_AUD_SLIMBUS
, "pclk_aud_slimbus", "div_aclk_aud",
3014 ENABLE_PCLK_AUD
, 6, 0, 0),
3015 GATE(CLK_PCLK_AUD_UART
, "pclk_aud_uart", "div_aclk_aud",
3016 ENABLE_PCLK_AUD
, 5, 0, 0),
3017 GATE(CLK_PCLK_AUD_PCM
, "pclk_aud_pcm", "div_aclk_aud",
3018 ENABLE_PCLK_AUD
, 4, 0, 0),
3019 GATE(CLK_PCLK_AUD_I2S
, "pclk_aud_i2s", "div_aclk_aud",
3020 ENABLE_PCLK_AUD
, 3, 0, 0),
3021 GATE(CLK_PCLK_TIMER
, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD
,
3023 GATE(CLK_PCLK_SFR0_CTRL
, "pclk_sfr0_ctrl", "div_aclk_aud",
3024 ENABLE_PCLK_AUD
, 0, 0, 0),
3026 /* ENABLE_SCLK_AUD0 */
3027 GATE(CLK_ATCLK_AUD
, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0
,
3029 GATE(CLK_PCLK_DBG_AUD
, "pclk_dbg_aud", "div_pclk_dbg_aud",
3030 ENABLE_SCLK_AUD0
, 1, 0, 0),
3031 GATE(CLK_SCLK_AUD_CA5
, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0
,
3034 /* ENABLE_SCLK_AUD1 */
3035 GATE(CLK_SCLK_JTAG_TCK
, "sclk_jtag_tck", "ioclk_jtag_tclk",
3036 ENABLE_SCLK_AUD1
, 6, 0, 0),
3037 GATE(CLK_SCLK_SLIMBUS_CLKIN
, "sclk_slimbus_clkin", "ioclk_slimbus_clk",
3038 ENABLE_SCLK_AUD1
, 5, 0, 0),
3039 GATE(CLK_SCLK_AUD_SLIMBUS
, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
3040 ENABLE_SCLK_AUD1
, 4, 0, 0),
3041 GATE(CLK_SCLK_AUD_UART
, "sclk_aud_uart", "div_sclk_aud_uart",
3042 ENABLE_SCLK_AUD1
, 3, 0, 0),
3043 GATE(CLK_SCLK_AUD_PCM
, "sclk_aud_pcm", "div_sclk_aud_pcm",
3044 ENABLE_SCLK_AUD1
, 2, 0, 0),
3045 GATE(CLK_SCLK_I2S_BCLK
, "sclk_i2s_bclk", "ioclk_i2s_bclk",
3046 ENABLE_SCLK_AUD1
, 1, CLK_IGNORE_UNUSED
, 0),
3047 GATE(CLK_SCLK_AUD_I2S
, "sclk_aud_i2s", "div_sclk_aud_i2s",
3048 ENABLE_SCLK_AUD1
, 0, CLK_IGNORE_UNUSED
, 0),
3051 static struct samsung_cmu_info aud_cmu_info __initdata
= {
3052 .mux_clks
= aud_mux_clks
,
3053 .nr_mux_clks
= ARRAY_SIZE(aud_mux_clks
),
3054 .div_clks
= aud_div_clks
,
3055 .nr_div_clks
= ARRAY_SIZE(aud_div_clks
),
3056 .gate_clks
= aud_gate_clks
,
3057 .nr_gate_clks
= ARRAY_SIZE(aud_gate_clks
),
3058 .fixed_clks
= aud_fixed_clks
,
3059 .nr_fixed_clks
= ARRAY_SIZE(aud_fixed_clks
),
3060 .nr_clk_ids
= AUD_NR_CLK
,
3061 .clk_regs
= aud_clk_regs
,
3062 .nr_clk_regs
= ARRAY_SIZE(aud_clk_regs
),
3065 static void __init
exynos5433_cmu_aud_init(struct device_node
*np
)
3067 samsung_cmu_register_one(np
, &aud_cmu_info
);
3069 CLK_OF_DECLARE(exynos5433_cmu_aud
, "samsung,exynos5433-cmu-aud",
3070 exynos5433_cmu_aud_init
);
3074 * Register offset definitions for CMU_BUS{0|1|2}
3076 #define DIV_BUS 0x0600
3077 #define DIV_STAT_BUS 0x0700
3078 #define ENABLE_ACLK_BUS 0x0800
3079 #define ENABLE_PCLK_BUS 0x0900
3080 #define ENABLE_IP_BUS0 0x0b00
3081 #define ENABLE_IP_BUS1 0x0b04
3083 #define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */
3084 #define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */
3085 #define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */
3087 /* list of all parent clock list */
3088 PNAME(mout_aclk_bus2_400_p
) = { "oscclk", "aclk_bus2_400", };
3090 #define CMU_BUS_COMMON_CLK_REGS \
3098 static unsigned long bus01_clk_regs
[] __initdata
= {
3099 CMU_BUS_COMMON_CLK_REGS
,
3102 static unsigned long bus2_clk_regs
[] __initdata
= {
3106 CMU_BUS_COMMON_CLK_REGS
,
3109 static struct samsung_div_clock bus0_div_clks
[] __initdata
= {
3111 DIV(CLK_DIV_PCLK_BUS_133
, "div_pclk_bus0_133", "aclk_bus0_400",
3115 /* CMU_BUS0 clocks */
3116 static struct samsung_gate_clock bus0_gate_clks
[] __initdata
= {
3117 /* ENABLE_ACLK_BUS0 */
3118 GATE(CLK_ACLK_AHB2APB_BUSP
, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133",
3119 ENABLE_ACLK_BUS
, 4, CLK_IGNORE_UNUSED
, 0),
3120 GATE(CLK_ACLK_BUSNP_133
, "aclk_bus0np_133", "div_pclk_bus0_133",
3121 ENABLE_ACLK_BUS
, 2, CLK_IGNORE_UNUSED
, 0),
3122 GATE(CLK_ACLK_BUSND_400
, "aclk_bus0nd_400", "aclk_bus0_400",
3123 ENABLE_ACLK_BUS
, 0, CLK_IGNORE_UNUSED
, 0),
3125 /* ENABLE_PCLK_BUS0 */
3126 GATE(CLK_PCLK_BUSSRVND_133
, "pclk_bus0srvnd_133", "div_pclk_bus0_133",
3127 ENABLE_PCLK_BUS
, 2, 0, 0),
3128 GATE(CLK_PCLK_PMU_BUS
, "pclk_pmu_bus0", "div_pclk_bus0_133",
3129 ENABLE_PCLK_BUS
, 1, CLK_IGNORE_UNUSED
, 0),
3130 GATE(CLK_PCLK_SYSREG_BUS
, "pclk_sysreg_bus0", "div_pclk_bus0_133",
3131 ENABLE_PCLK_BUS
, 0, CLK_IGNORE_UNUSED
, 0),
3134 /* CMU_BUS1 clocks */
3135 static struct samsung_div_clock bus1_div_clks
[] __initdata
= {
3137 DIV(CLK_DIV_PCLK_BUS_133
, "div_pclk_bus1_133", "aclk_bus1_400",
3141 static struct samsung_gate_clock bus1_gate_clks
[] __initdata
= {
3142 /* ENABLE_ACLK_BUS1 */
3143 GATE(CLK_ACLK_AHB2APB_BUSP
, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133",
3144 ENABLE_ACLK_BUS
, 4, CLK_IGNORE_UNUSED
, 0),
3145 GATE(CLK_ACLK_BUSNP_133
, "aclk_bus1np_133", "div_pclk_bus1_133",
3146 ENABLE_ACLK_BUS
, 2, CLK_IGNORE_UNUSED
, 0),
3147 GATE(CLK_ACLK_BUSND_400
, "aclk_bus1nd_400", "aclk_bus1_400",
3148 ENABLE_ACLK_BUS
, 0, CLK_IGNORE_UNUSED
, 0),
3150 /* ENABLE_PCLK_BUS1 */
3151 GATE(CLK_PCLK_BUSSRVND_133
, "pclk_bus1srvnd_133", "div_pclk_bus1_133",
3152 ENABLE_PCLK_BUS
, 2, 0, 0),
3153 GATE(CLK_PCLK_PMU_BUS
, "pclk_pmu_bus1", "div_pclk_bus1_133",
3154 ENABLE_PCLK_BUS
, 1, CLK_IGNORE_UNUSED
, 0),
3155 GATE(CLK_PCLK_SYSREG_BUS
, "pclk_sysreg_bus1", "div_pclk_bus1_133",
3156 ENABLE_PCLK_BUS
, 0, CLK_IGNORE_UNUSED
, 0),
3159 /* CMU_BUS2 clocks */
3160 static struct samsung_mux_clock bus2_mux_clks
[] __initdata
= {
3162 MUX(CLK_MOUT_ACLK_BUS2_400_USER
, "mout_aclk_bus2_400_user",
3163 mout_aclk_bus2_400_p
, MUX_SEL_BUS2
, 0, 1),
3166 static struct samsung_div_clock bus2_div_clks
[] __initdata
= {
3168 DIV(CLK_DIV_PCLK_BUS_133
, "div_pclk_bus2_133",
3169 "mout_aclk_bus2_400_user", DIV_BUS
, 0, 3),
3172 static struct samsung_gate_clock bus2_gate_clks
[] __initdata
= {
3173 /* ENABLE_ACLK_BUS2 */
3174 GATE(CLK_ACLK_AHB2APB_BUSP
, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133",
3175 ENABLE_ACLK_BUS
, 3, CLK_IGNORE_UNUSED
, 0),
3176 GATE(CLK_ACLK_BUSNP_133
, "aclk_bus2np_133", "div_pclk_bus2_133",
3177 ENABLE_ACLK_BUS
, 2, CLK_IGNORE_UNUSED
, 0),
3178 GATE(CLK_ACLK_BUS2BEND_400
, "aclk_bus2bend_400",
3179 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS
,
3180 1, CLK_IGNORE_UNUSED
, 0),
3181 GATE(CLK_ACLK_BUS2RTND_400
, "aclk_bus2rtnd_400",
3182 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS
,
3183 0, CLK_IGNORE_UNUSED
, 0),
3185 /* ENABLE_PCLK_BUS2 */
3186 GATE(CLK_PCLK_BUSSRVND_133
, "pclk_bus2srvnd_133", "div_pclk_bus2_133",
3187 ENABLE_PCLK_BUS
, 2, 0, 0),
3188 GATE(CLK_PCLK_PMU_BUS
, "pclk_pmu_bus2", "div_pclk_bus2_133",
3189 ENABLE_PCLK_BUS
, 1, CLK_IGNORE_UNUSED
, 0),
3190 GATE(CLK_PCLK_SYSREG_BUS
, "pclk_sysreg_bus2", "div_pclk_bus2_133",
3191 ENABLE_PCLK_BUS
, 0, CLK_IGNORE_UNUSED
, 0),
3194 #define CMU_BUS_INFO_CLKS(id) \
3195 .div_clks = bus##id##_div_clks, \
3196 .nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \
3197 .gate_clks = bus##id##_gate_clks, \
3198 .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \
3199 .nr_clk_ids = BUSx_NR_CLK
3201 static struct samsung_cmu_info bus0_cmu_info __initdata
= {
3202 CMU_BUS_INFO_CLKS(0),
3203 .clk_regs
= bus01_clk_regs
,
3204 .nr_clk_regs
= ARRAY_SIZE(bus01_clk_regs
),
3207 static struct samsung_cmu_info bus1_cmu_info __initdata
= {
3208 CMU_BUS_INFO_CLKS(1),
3209 .clk_regs
= bus01_clk_regs
,
3210 .nr_clk_regs
= ARRAY_SIZE(bus01_clk_regs
),
3213 static struct samsung_cmu_info bus2_cmu_info __initdata
= {
3214 CMU_BUS_INFO_CLKS(2),
3215 .mux_clks
= bus2_mux_clks
,
3216 .nr_mux_clks
= ARRAY_SIZE(bus2_mux_clks
),
3217 .clk_regs
= bus2_clk_regs
,
3218 .nr_clk_regs
= ARRAY_SIZE(bus2_clk_regs
),
3221 #define exynos5433_cmu_bus_init(id) \
3222 static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\
3224 samsung_cmu_register_one(np, &bus##id##_cmu_info); \
3226 CLK_OF_DECLARE(exynos5433_cmu_bus##id, \
3227 "samsung,exynos5433-cmu-bus"#id, \
3228 exynos5433_cmu_bus##id##_init)
3230 exynos5433_cmu_bus_init(0);
3231 exynos5433_cmu_bus_init(1);
3232 exynos5433_cmu_bus_init(2);
3235 * Register offset definitions for CMU_G3D
3237 #define G3D_PLL_LOCK 0x0000
3238 #define G3D_PLL_CON0 0x0100
3239 #define G3D_PLL_CON1 0x0104
3240 #define G3D_PLL_FREQ_DET 0x010c
3241 #define MUX_SEL_G3D 0x0200
3242 #define MUX_ENABLE_G3D 0x0300
3243 #define MUX_STAT_G3D 0x0400
3244 #define DIV_G3D 0x0600
3245 #define DIV_G3D_PLL_FREQ_DET 0x0604
3246 #define DIV_STAT_G3D 0x0700
3247 #define DIV_STAT_G3D_PLL_FREQ_DET 0x0704
3248 #define ENABLE_ACLK_G3D 0x0800
3249 #define ENABLE_PCLK_G3D 0x0900
3250 #define ENABLE_SCLK_G3D 0x0a00
3251 #define ENABLE_IP_G3D0 0x0b00
3252 #define ENABLE_IP_G3D1 0x0b04
3253 #define CLKOUT_CMU_G3D 0x0c00
3254 #define CLKOUT_CMU_G3D_DIV_STAT 0x0c04
3255 #define CLK_STOPCTRL 0x1000
3257 static unsigned long g3d_clk_regs
[] __initdata
= {
3266 DIV_G3D_PLL_FREQ_DET
,
3268 DIV_STAT_G3D_PLL_FREQ_DET
,
3275 CLKOUT_CMU_G3D_DIV_STAT
,
3279 /* list of all parent clock list */
3280 PNAME(mout_aclk_g3d_400_p
) = { "mout_g3d_pll", "aclk_g3d_400", };
3281 PNAME(mout_g3d_pll_p
) = { "oscclk", "fout_g3d_pll", };
3283 static struct samsung_pll_clock g3d_pll_clks
[] __initdata
= {
3284 PLL(pll_35xx
, CLK_FOUT_G3D_PLL
, "fout_g3d_pll", "oscclk",
3285 G3D_PLL_LOCK
, G3D_PLL_CON0
, exynos5443_pll_rates
),
3288 static struct samsung_mux_clock g3d_mux_clks
[] __initdata
= {
3290 MUX_F(CLK_MOUT_ACLK_G3D_400
, "mout_aclk_g3d_400", mout_aclk_g3d_400_p
,
3291 MUX_SEL_G3D
, 8, 1, CLK_SET_RATE_PARENT
, 0),
3292 MUX_F(CLK_MOUT_G3D_PLL
, "mout_g3d_pll", mout_g3d_pll_p
,
3293 MUX_SEL_G3D
, 0, 1, CLK_SET_RATE_PARENT
, 0),
3296 static struct samsung_div_clock g3d_div_clks
[] __initdata
= {
3298 DIV(CLK_DIV_SCLK_HPM_G3D
, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D
,
3300 DIV(CLK_DIV_PCLK_G3D
, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D
,
3302 DIV_F(CLK_DIV_ACLK_G3D
, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D
,
3303 0, 3, CLK_SET_RATE_PARENT
, 0),
3306 static struct samsung_gate_clock g3d_gate_clks
[] __initdata
= {
3307 /* ENABLE_ACLK_G3D */
3308 GATE(CLK_ACLK_BTS_G3D1
, "aclk_bts_g3d1", "div_aclk_g3d",
3309 ENABLE_ACLK_G3D
, 7, 0, 0),
3310 GATE(CLK_ACLK_BTS_G3D0
, "aclk_bts_g3d0", "div_aclk_g3d",
3311 ENABLE_ACLK_G3D
, 6, 0, 0),
3312 GATE(CLK_ACLK_ASYNCAPBS_G3D
, "aclk_asyncapbs_g3d", "div_pclk_g3d",
3313 ENABLE_ACLK_G3D
, 5, CLK_IGNORE_UNUSED
, 0),
3314 GATE(CLK_ACLK_ASYNCAPBM_G3D
, "aclk_asyncapbm_g3d", "div_aclk_g3d",
3315 ENABLE_ACLK_G3D
, 4, CLK_IGNORE_UNUSED
, 0),
3316 GATE(CLK_ACLK_AHB2APB_G3DP
, "aclk_ahb2apb_g3dp", "div_pclk_g3d",
3317 ENABLE_ACLK_G3D
, 3, CLK_IGNORE_UNUSED
, 0),
3318 GATE(CLK_ACLK_G3DNP_150
, "aclk_g3dnp_150", "div_pclk_g3d",
3319 ENABLE_ACLK_G3D
, 2, CLK_IGNORE_UNUSED
, 0),
3320 GATE(CLK_ACLK_G3DND_600
, "aclk_g3dnd_600", "div_aclk_g3d",
3321 ENABLE_ACLK_G3D
, 1, CLK_IGNORE_UNUSED
, 0),
3322 GATE(CLK_ACLK_G3D
, "aclk_g3d", "div_aclk_g3d",
3323 ENABLE_ACLK_G3D
, 0, CLK_SET_RATE_PARENT
, 0),
3325 /* ENABLE_PCLK_G3D */
3326 GATE(CLK_PCLK_BTS_G3D1
, "pclk_bts_g3d1", "div_pclk_g3d",
3327 ENABLE_PCLK_G3D
, 3, 0, 0),
3328 GATE(CLK_PCLK_BTS_G3D0
, "pclk_bts_g3d0", "div_pclk_g3d",
3329 ENABLE_PCLK_G3D
, 2, 0, 0),
3330 GATE(CLK_PCLK_PMU_G3D
, "pclk_pmu_g3d", "div_pclk_g3d",
3331 ENABLE_PCLK_G3D
, 1, CLK_IGNORE_UNUSED
, 0),
3332 GATE(CLK_PCLK_SYSREG_G3D
, "pclk_sysreg_g3d", "div_pclk_g3d",
3333 ENABLE_PCLK_G3D
, 0, CLK_IGNORE_UNUSED
, 0),
3335 /* ENABLE_SCLK_G3D */
3336 GATE(CLK_SCLK_HPM_G3D
, "sclk_hpm_g3d", "div_sclk_hpm_g3d",
3337 ENABLE_SCLK_G3D
, 0, 0, 0),
3340 static struct samsung_cmu_info g3d_cmu_info __initdata
= {
3341 .pll_clks
= g3d_pll_clks
,
3342 .nr_pll_clks
= ARRAY_SIZE(g3d_pll_clks
),
3343 .mux_clks
= g3d_mux_clks
,
3344 .nr_mux_clks
= ARRAY_SIZE(g3d_mux_clks
),
3345 .div_clks
= g3d_div_clks
,
3346 .nr_div_clks
= ARRAY_SIZE(g3d_div_clks
),
3347 .gate_clks
= g3d_gate_clks
,
3348 .nr_gate_clks
= ARRAY_SIZE(g3d_gate_clks
),
3349 .nr_clk_ids
= G3D_NR_CLK
,
3350 .clk_regs
= g3d_clk_regs
,
3351 .nr_clk_regs
= ARRAY_SIZE(g3d_clk_regs
),
3354 static void __init
exynos5433_cmu_g3d_init(struct device_node
*np
)
3356 samsung_cmu_register_one(np
, &g3d_cmu_info
);
3358 CLK_OF_DECLARE(exynos5433_cmu_g3d
, "samsung,exynos5433-cmu-g3d",
3359 exynos5433_cmu_g3d_init
);
3362 * Register offset definitions for CMU_GSCL
3364 #define MUX_SEL_GSCL 0x0200
3365 #define MUX_ENABLE_GSCL 0x0300
3366 #define MUX_STAT_GSCL 0x0400
3367 #define ENABLE_ACLK_GSCL 0x0800
3368 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804
3369 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808
3370 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
3371 #define ENABLE_PCLK_GSCL 0x0900
3372 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904
3373 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908
3374 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c
3375 #define ENABLE_IP_GSCL0 0x0b00
3376 #define ENABLE_IP_GSCL1 0x0b04
3377 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08
3378 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c
3379 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10
3381 static unsigned long gscl_clk_regs
[] __initdata
= {
3386 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0
,
3387 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1
,
3388 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2
,
3390 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0
,
3391 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1
,
3392 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2
,
3395 ENABLE_IP_GSCL_SECURE_SMMU_GSCL0
,
3396 ENABLE_IP_GSCL_SECURE_SMMU_GSCL1
,
3397 ENABLE_IP_GSCL_SECURE_SMMU_GSCL2
,
3400 /* list of all parent clock list */
3401 PNAME(aclk_gscl_111_user_p
) = { "oscclk", "aclk_gscl_111", };
3402 PNAME(aclk_gscl_333_user_p
) = { "oscclk", "aclk_gscl_333", };
3404 static struct samsung_mux_clock gscl_mux_clks
[] __initdata
= {
3406 MUX(CLK_MOUT_ACLK_GSCL_111_USER
, "mout_aclk_gscl_111_user",
3407 aclk_gscl_111_user_p
, MUX_SEL_GSCL
, 4, 1),
3408 MUX(CLK_MOUT_ACLK_GSCL_333_USER
, "mout_aclk_gscl_333_user",
3409 aclk_gscl_333_user_p
, MUX_SEL_GSCL
, 0, 1),
3412 static struct samsung_gate_clock gscl_gate_clks
[] __initdata
= {
3413 /* ENABLE_ACLK_GSCL */
3414 GATE(CLK_ACLK_BTS_GSCL2
, "aclk_bts_gscl2", "mout_aclk_gscl_333_user",
3415 ENABLE_ACLK_GSCL
, 11, 0, 0),
3416 GATE(CLK_ACLK_BTS_GSCL1
, "aclk_bts_gscl1", "mout_aclk_gscl_333_user",
3417 ENABLE_ACLK_GSCL
, 10, 0, 0),
3418 GATE(CLK_ACLK_BTS_GSCL0
, "aclk_bts_gscl0", "mout_aclk_gscl_333_user",
3419 ENABLE_ACLK_GSCL
, 9, 0, 0),
3420 GATE(CLK_ACLK_AHB2APB_GSCLP
, "aclk_ahb2apb_gsclp",
3421 "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL
,
3422 8, CLK_IGNORE_UNUSED
, 0),
3423 GATE(CLK_ACLK_XIU_GSCLX
, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user",
3424 ENABLE_ACLK_GSCL
, 7, 0, 0),
3425 GATE(CLK_ACLK_GSCLNP_111
, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
3426 ENABLE_ACLK_GSCL
, 6, CLK_IGNORE_UNUSED
, 0),
3427 GATE(CLK_ACLK_GSCLRTND_333
, "aclk_gsclrtnd_333",
3428 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL
, 5, 0, 0),
3429 GATE(CLK_ACLK_GSCLBEND_333
, "aclk_gsclbend_333",
3430 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL
, 4, 0, 0),
3431 GATE(CLK_ACLK_GSD
, "aclk_gsd", "mout_aclk_gscl_333_user",
3432 ENABLE_ACLK_GSCL
, 3, 0, 0),
3433 GATE(CLK_ACLK_GSCL2
, "aclk_gscl2", "mout_aclk_gscl_333_user",
3434 ENABLE_ACLK_GSCL
, 2, 0, 0),
3435 GATE(CLK_ACLK_GSCL1
, "aclk_gscl1", "mout_aclk_gscl_333_user",
3436 ENABLE_ACLK_GSCL
, 1, 0, 0),
3437 GATE(CLK_ACLK_GSCL0
, "aclk_gscl0", "mout_aclk_gscl_333_user",
3438 ENABLE_ACLK_GSCL
, 0, 0, 0),
3440 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */
3441 GATE(CLK_ACLK_SMMU_GSCL0
, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user",
3442 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0
, 0, 0, 0),
3444 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */
3445 GATE(CLK_ACLK_SMMU_GSCL1
, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user",
3446 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1
, 0, 0, 0),
3448 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */
3449 GATE(CLK_ACLK_SMMU_GSCL2
, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user",
3450 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2
, 0, 0, 0),
3452 /* ENABLE_PCLK_GSCL */
3453 GATE(CLK_PCLK_BTS_GSCL2
, "pclk_bts_gscl2", "mout_aclk_gscl_111_user",
3454 ENABLE_PCLK_GSCL
, 7, 0, 0),
3455 GATE(CLK_PCLK_BTS_GSCL1
, "pclk_bts_gscl1", "mout_aclk_gscl_111_user",
3456 ENABLE_PCLK_GSCL
, 6, 0, 0),
3457 GATE(CLK_PCLK_BTS_GSCL0
, "pclk_bts_gscl0", "mout_aclk_gscl_111_user",
3458 ENABLE_PCLK_GSCL
, 5, 0, 0),
3459 GATE(CLK_PCLK_PMU_GSCL
, "pclk_pmu_gscl", "mout_aclk_gscl_111_user",
3460 ENABLE_PCLK_GSCL
, 4, CLK_IGNORE_UNUSED
, 0),
3461 GATE(CLK_PCLK_SYSREG_GSCL
, "pclk_sysreg_gscl",
3462 "mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL
,
3463 3, CLK_IGNORE_UNUSED
, 0),
3464 GATE(CLK_PCLK_GSCL2
, "pclk_gscl2", "mout_aclk_gscl_111_user",
3465 ENABLE_PCLK_GSCL
, 2, 0, 0),
3466 GATE(CLK_PCLK_GSCL1
, "pclk_gscl1", "mout_aclk_gscl_111_user",
3467 ENABLE_PCLK_GSCL
, 1, 0, 0),
3468 GATE(CLK_PCLK_GSCL0
, "pclk_gscl0", "mout_aclk_gscl_111_user",
3469 ENABLE_PCLK_GSCL
, 0, 0, 0),
3471 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */
3472 GATE(CLK_PCLK_SMMU_GSCL0
, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user",
3473 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0
, 0, 0, 0),
3475 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */
3476 GATE(CLK_PCLK_SMMU_GSCL1
, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user",
3477 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0
, 0, 0, 0),
3479 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */
3480 GATE(CLK_PCLK_SMMU_GSCL2
, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user",
3481 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0
, 0, 0, 0),
3484 static struct samsung_cmu_info gscl_cmu_info __initdata
= {
3485 .mux_clks
= gscl_mux_clks
,
3486 .nr_mux_clks
= ARRAY_SIZE(gscl_mux_clks
),
3487 .gate_clks
= gscl_gate_clks
,
3488 .nr_gate_clks
= ARRAY_SIZE(gscl_gate_clks
),
3489 .nr_clk_ids
= GSCL_NR_CLK
,
3490 .clk_regs
= gscl_clk_regs
,
3491 .nr_clk_regs
= ARRAY_SIZE(gscl_clk_regs
),
3494 static void __init
exynos5433_cmu_gscl_init(struct device_node
*np
)
3496 samsung_cmu_register_one(np
, &gscl_cmu_info
);
3498 CLK_OF_DECLARE(exynos5433_cmu_gscl
, "samsung,exynos5433-cmu-gscl",
3499 exynos5433_cmu_gscl_init
);
3502 * Register offset definitions for CMU_APOLLO
3504 #define APOLLO_PLL_LOCK 0x0000
3505 #define APOLLO_PLL_CON0 0x0100
3506 #define APOLLO_PLL_CON1 0x0104
3507 #define APOLLO_PLL_FREQ_DET 0x010c
3508 #define MUX_SEL_APOLLO0 0x0200
3509 #define MUX_SEL_APOLLO1 0x0204
3510 #define MUX_SEL_APOLLO2 0x0208
3511 #define MUX_ENABLE_APOLLO0 0x0300
3512 #define MUX_ENABLE_APOLLO1 0x0304
3513 #define MUX_ENABLE_APOLLO2 0x0308
3514 #define MUX_STAT_APOLLO0 0x0400
3515 #define MUX_STAT_APOLLO1 0x0404
3516 #define MUX_STAT_APOLLO2 0x0408
3517 #define DIV_APOLLO0 0x0600
3518 #define DIV_APOLLO1 0x0604
3519 #define DIV_APOLLO_PLL_FREQ_DET 0x0608
3520 #define DIV_STAT_APOLLO0 0x0700
3521 #define DIV_STAT_APOLLO1 0x0704
3522 #define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708
3523 #define ENABLE_ACLK_APOLLO 0x0800
3524 #define ENABLE_PCLK_APOLLO 0x0900
3525 #define ENABLE_SCLK_APOLLO 0x0a00
3526 #define ENABLE_IP_APOLLO0 0x0b00
3527 #define ENABLE_IP_APOLLO1 0x0b04
3528 #define CLKOUT_CMU_APOLLO 0x0c00
3529 #define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04
3530 #define ARMCLK_STOPCTRL 0x1000
3531 #define APOLLO_PWR_CTRL 0x1020
3532 #define APOLLO_PWR_CTRL2 0x1024
3533 #define APOLLO_INTR_SPREAD_ENABLE 0x1080
3534 #define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084
3535 #define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088
3537 static unsigned long apollo_clk_regs
[] __initdata
= {
3541 APOLLO_PLL_FREQ_DET
,
3553 DIV_APOLLO_PLL_FREQ_DET
,
3556 DIV_STAT_APOLLO_PLL_FREQ_DET
,
3563 CLKOUT_CMU_APOLLO_DIV_STAT
,
3567 APOLLO_INTR_SPREAD_ENABLE
,
3568 APOLLO_INTR_SPREAD_USE_STANDBYWFI
,
3569 APOLLO_INTR_SPREAD_BLOCKING_DURATION
,
3572 /* list of all parent clock list */
3573 PNAME(mout_apollo_pll_p
) = { "oscclk", "fout_apollo_pll", };
3574 PNAME(mout_bus_pll_apollo_user_p
) = { "oscclk", "sclk_bus_pll_apollo", };
3575 PNAME(mout_apollo_p
) = { "mout_apollo_pll",
3576 "mout_bus_pll_apollo_user", };
3578 static struct samsung_pll_clock apollo_pll_clks
[] __initdata
= {
3579 PLL(pll_35xx
, CLK_FOUT_APOLLO_PLL
, "fout_apollo_pll", "oscclk",
3580 APOLLO_PLL_LOCK
, APOLLO_PLL_CON0
, exynos5443_pll_rates
),
3583 static struct samsung_mux_clock apollo_mux_clks
[] __initdata
= {
3584 /* MUX_SEL_APOLLO0 */
3585 MUX_F(CLK_MOUT_APOLLO_PLL
, "mout_apollo_pll", mout_apollo_pll_p
,
3586 MUX_SEL_APOLLO0
, 0, 1, CLK_SET_RATE_PARENT
, 0),
3588 /* MUX_SEL_APOLLO1 */
3589 MUX(CLK_MOUT_BUS_PLL_APOLLO_USER
, "mout_bus_pll_apollo_user",
3590 mout_bus_pll_apollo_user_p
, MUX_SEL_APOLLO1
, 0, 1),
3592 /* MUX_SEL_APOLLO2 */
3593 MUX_F(CLK_MOUT_APOLLO
, "mout_apollo", mout_apollo_p
, MUX_SEL_APOLLO2
,
3594 0, 1, CLK_SET_RATE_PARENT
, 0),
3597 static struct samsung_div_clock apollo_div_clks
[] __initdata
= {
3599 DIV_F(CLK_DIV_CNTCLK_APOLLO
, "div_cntclk_apollo", "div_apollo2",
3600 DIV_APOLLO0
, 24, 3, CLK_GET_RATE_NOCACHE
,
3601 CLK_DIVIDER_READ_ONLY
),
3602 DIV_F(CLK_DIV_PCLK_DBG_APOLLO
, "div_pclk_dbg_apollo", "div_apollo2",
3603 DIV_APOLLO0
, 20, 3, CLK_GET_RATE_NOCACHE
,
3604 CLK_DIVIDER_READ_ONLY
),
3605 DIV_F(CLK_DIV_ATCLK_APOLLO
, "div_atclk_apollo", "div_apollo2",
3606 DIV_APOLLO0
, 16, 3, CLK_GET_RATE_NOCACHE
,
3607 CLK_DIVIDER_READ_ONLY
),
3608 DIV_F(CLK_DIV_PCLK_APOLLO
, "div_pclk_apollo", "div_apollo2",
3609 DIV_APOLLO0
, 12, 3, CLK_GET_RATE_NOCACHE
,
3610 CLK_DIVIDER_READ_ONLY
),
3611 DIV_F(CLK_DIV_ACLK_APOLLO
, "div_aclk_apollo", "div_apollo2",
3612 DIV_APOLLO0
, 8, 3, CLK_GET_RATE_NOCACHE
,
3613 CLK_DIVIDER_READ_ONLY
),
3614 DIV_F(CLK_DIV_APOLLO2
, "div_apollo2", "div_apollo1",
3615 DIV_APOLLO0
, 4, 3, CLK_SET_RATE_PARENT
, 0),
3616 DIV_F(CLK_DIV_APOLLO1
, "div_apollo1", "mout_apollo",
3617 DIV_APOLLO0
, 0, 3, CLK_SET_RATE_PARENT
, 0),
3620 DIV_F(CLK_DIV_SCLK_HPM_APOLLO
, "div_sclk_hpm_apollo", "mout_apollo",
3621 DIV_APOLLO1
, 4, 3, CLK_GET_RATE_NOCACHE
,
3622 CLK_DIVIDER_READ_ONLY
),
3623 DIV_F(CLK_DIV_APOLLO_PLL
, "div_apollo_pll", "mout_apollo",
3624 DIV_APOLLO1
, 0, 3, CLK_GET_RATE_NOCACHE
,
3625 CLK_DIVIDER_READ_ONLY
),
3628 static struct samsung_gate_clock apollo_gate_clks
[] __initdata
= {
3629 /* ENABLE_ACLK_APOLLO */
3630 GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS
, "aclk_asatbslv_apollo_3_cssys",
3631 "div_atclk_apollo", ENABLE_ACLK_APOLLO
,
3632 6, CLK_IGNORE_UNUSED
, 0),
3633 GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS
, "aclk_asatbslv_apollo_2_cssys",
3634 "div_atclk_apollo", ENABLE_ACLK_APOLLO
,
3635 5, CLK_IGNORE_UNUSED
, 0),
3636 GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS
, "aclk_asatbslv_apollo_1_cssys",
3637 "div_atclk_apollo", ENABLE_ACLK_APOLLO
,
3638 4, CLK_IGNORE_UNUSED
, 0),
3639 GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS
, "aclk_asatbslv_apollo_0_cssys",
3640 "div_atclk_apollo", ENABLE_ACLK_APOLLO
,
3641 3, CLK_IGNORE_UNUSED
, 0),
3642 GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI
, "aclk_asyncaces_apollo_cci",
3643 "div_aclk_apollo", ENABLE_ACLK_APOLLO
,
3644 2, CLK_IGNORE_UNUSED
, 0),
3645 GATE(CLK_ACLK_AHB2APB_APOLLOP
, "aclk_ahb2apb_apollop",
3646 "div_pclk_apollo", ENABLE_ACLK_APOLLO
,
3647 1, CLK_IGNORE_UNUSED
, 0),
3648 GATE(CLK_ACLK_APOLLONP_200
, "aclk_apollonp_200",
3649 "div_pclk_apollo", ENABLE_ACLK_APOLLO
,
3650 0, CLK_IGNORE_UNUSED
, 0),
3652 /* ENABLE_PCLK_APOLLO */
3653 GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO
, "pclk_asapbmst_cssys_apollo",
3654 "div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO
,
3655 2, CLK_IGNORE_UNUSED
, 0),
3656 GATE(CLK_PCLK_PMU_APOLLO
, "pclk_pmu_apollo", "div_pclk_apollo",
3657 ENABLE_PCLK_APOLLO
, 1, CLK_IGNORE_UNUSED
, 0),
3658 GATE(CLK_PCLK_SYSREG_APOLLO
, "pclk_sysreg_apollo",
3659 "div_pclk_apollo", ENABLE_PCLK_APOLLO
,
3660 0, CLK_IGNORE_UNUSED
, 0),
3662 /* ENABLE_SCLK_APOLLO */
3663 GATE(CLK_CNTCLK_APOLLO
, "cntclk_apollo", "div_cntclk_apollo",
3664 ENABLE_SCLK_APOLLO
, 3, CLK_IGNORE_UNUSED
, 0),
3665 GATE(CLK_SCLK_HPM_APOLLO
, "sclk_hpm_apollo", "div_sclk_hpm_apollo",
3666 ENABLE_SCLK_APOLLO
, 1, CLK_IGNORE_UNUSED
, 0),
3667 GATE(CLK_SCLK_APOLLO
, "sclk_apollo", "div_apollo2",
3668 ENABLE_SCLK_APOLLO
, 0,
3669 CLK_IGNORE_UNUSED
| CLK_SET_RATE_PARENT
, 0),
3672 static struct samsung_cmu_info apollo_cmu_info __initdata
= {
3673 .pll_clks
= apollo_pll_clks
,
3674 .nr_pll_clks
= ARRAY_SIZE(apollo_pll_clks
),
3675 .mux_clks
= apollo_mux_clks
,
3676 .nr_mux_clks
= ARRAY_SIZE(apollo_mux_clks
),
3677 .div_clks
= apollo_div_clks
,
3678 .nr_div_clks
= ARRAY_SIZE(apollo_div_clks
),
3679 .gate_clks
= apollo_gate_clks
,
3680 .nr_gate_clks
= ARRAY_SIZE(apollo_gate_clks
),
3681 .nr_clk_ids
= APOLLO_NR_CLK
,
3682 .clk_regs
= apollo_clk_regs
,
3683 .nr_clk_regs
= ARRAY_SIZE(apollo_clk_regs
),
3686 static void __init
exynos5433_cmu_apollo_init(struct device_node
*np
)
3688 samsung_cmu_register_one(np
, &apollo_cmu_info
);
3690 CLK_OF_DECLARE(exynos5433_cmu_apollo
, "samsung,exynos5433-cmu-apollo",
3691 exynos5433_cmu_apollo_init
);
3694 * Register offset definitions for CMU_ATLAS
3696 #define ATLAS_PLL_LOCK 0x0000
3697 #define ATLAS_PLL_CON0 0x0100
3698 #define ATLAS_PLL_CON1 0x0104
3699 #define ATLAS_PLL_FREQ_DET 0x010c
3700 #define MUX_SEL_ATLAS0 0x0200
3701 #define MUX_SEL_ATLAS1 0x0204
3702 #define MUX_SEL_ATLAS2 0x0208
3703 #define MUX_ENABLE_ATLAS0 0x0300
3704 #define MUX_ENABLE_ATLAS1 0x0304
3705 #define MUX_ENABLE_ATLAS2 0x0308
3706 #define MUX_STAT_ATLAS0 0x0400
3707 #define MUX_STAT_ATLAS1 0x0404
3708 #define MUX_STAT_ATLAS2 0x0408
3709 #define DIV_ATLAS0 0x0600
3710 #define DIV_ATLAS1 0x0604
3711 #define DIV_ATLAS_PLL_FREQ_DET 0x0608
3712 #define DIV_STAT_ATLAS0 0x0700
3713 #define DIV_STAT_ATLAS1 0x0704
3714 #define DIV_STAT_ATLAS_PLL_FREQ_DET 0x0708
3715 #define ENABLE_ACLK_ATLAS 0x0800
3716 #define ENABLE_PCLK_ATLAS 0x0900
3717 #define ENABLE_SCLK_ATLAS 0x0a00
3718 #define ENABLE_IP_ATLAS0 0x0b00
3719 #define ENABLE_IP_ATLAS1 0x0b04
3720 #define CLKOUT_CMU_ATLAS 0x0c00
3721 #define CLKOUT_CMU_ATLAS_DIV_STAT 0x0c04
3722 #define ARMCLK_STOPCTRL 0x1000
3723 #define ATLAS_PWR_CTRL 0x1020
3724 #define ATLAS_PWR_CTRL2 0x1024
3725 #define ATLAS_INTR_SPREAD_ENABLE 0x1080
3726 #define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084
3727 #define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088
3729 static unsigned long atlas_clk_regs
[] __initdata
= {
3745 DIV_ATLAS_PLL_FREQ_DET
,
3748 DIV_STAT_ATLAS_PLL_FREQ_DET
,
3755 CLKOUT_CMU_ATLAS_DIV_STAT
,
3759 ATLAS_INTR_SPREAD_ENABLE
,
3760 ATLAS_INTR_SPREAD_USE_STANDBYWFI
,
3761 ATLAS_INTR_SPREAD_BLOCKING_DURATION
,
3764 /* list of all parent clock list */
3765 PNAME(mout_atlas_pll_p
) = { "oscclk", "fout_atlas_pll", };
3766 PNAME(mout_bus_pll_atlas_user_p
) = { "oscclk", "sclk_bus_pll_atlas", };
3767 PNAME(mout_atlas_p
) = { "mout_atlas_pll",
3768 "mout_bus_pll_atlas_user", };
3770 static struct samsung_pll_clock atlas_pll_clks
[] __initdata
= {
3771 PLL(pll_35xx
, CLK_FOUT_ATLAS_PLL
, "fout_atlas_pll", "oscclk",
3772 ATLAS_PLL_LOCK
, ATLAS_PLL_CON0
, exynos5443_pll_rates
),
3775 static struct samsung_mux_clock atlas_mux_clks
[] __initdata
= {
3776 /* MUX_SEL_ATLAS0 */
3777 MUX_F(CLK_MOUT_ATLAS_PLL
, "mout_atlas_pll", mout_atlas_pll_p
,
3778 MUX_SEL_ATLAS0
, 0, 1, CLK_SET_RATE_PARENT
, 0),
3780 /* MUX_SEL_ATLAS1 */
3781 MUX(CLK_MOUT_BUS_PLL_ATLAS_USER
, "mout_bus_pll_atlas_user",
3782 mout_bus_pll_atlas_user_p
, MUX_SEL_ATLAS1
, 0, 1),
3784 /* MUX_SEL_ATLAS2 */
3785 MUX_F(CLK_MOUT_ATLAS
, "mout_atlas", mout_atlas_p
, MUX_SEL_ATLAS2
,
3786 0, 1, CLK_SET_RATE_PARENT
, 0),
3789 static struct samsung_div_clock atlas_div_clks
[] __initdata
= {
3791 DIV_F(CLK_DIV_CNTCLK_ATLAS
, "div_cntclk_atlas", "div_atlas2",
3792 DIV_ATLAS0
, 24, 3, CLK_GET_RATE_NOCACHE
,
3793 CLK_DIVIDER_READ_ONLY
),
3794 DIV_F(CLK_DIV_PCLK_DBG_ATLAS
, "div_pclk_dbg_atlas", "div_atclk_atlas",
3795 DIV_ATLAS0
, 20, 3, CLK_GET_RATE_NOCACHE
,
3796 CLK_DIVIDER_READ_ONLY
),
3797 DIV_F(CLK_DIV_ATCLK_ATLASO
, "div_atclk_atlas", "div_atlas2",
3798 DIV_ATLAS0
, 16, 3, CLK_GET_RATE_NOCACHE
,
3799 CLK_DIVIDER_READ_ONLY
),
3800 DIV_F(CLK_DIV_PCLK_ATLAS
, "div_pclk_atlas", "div_atlas2",
3801 DIV_ATLAS0
, 12, 3, CLK_GET_RATE_NOCACHE
,
3802 CLK_DIVIDER_READ_ONLY
),
3803 DIV_F(CLK_DIV_ACLK_ATLAS
, "div_aclk_atlas", "div_atlas2",
3804 DIV_ATLAS0
, 8, 3, CLK_GET_RATE_NOCACHE
,
3805 CLK_DIVIDER_READ_ONLY
),
3806 DIV_F(CLK_DIV_ATLAS2
, "div_atlas2", "div_atlas1",
3807 DIV_ATLAS0
, 4, 3, CLK_SET_RATE_PARENT
, 0),
3808 DIV_F(CLK_DIV_ATLAS1
, "div_atlas1", "mout_atlas",
3809 DIV_ATLAS0
, 0, 3, CLK_SET_RATE_PARENT
, 0),
3812 DIV_F(CLK_DIV_SCLK_HPM_ATLAS
, "div_sclk_hpm_atlas", "mout_atlas",
3813 DIV_ATLAS1
, 4, 3, CLK_GET_RATE_NOCACHE
,
3814 CLK_DIVIDER_READ_ONLY
),
3815 DIV_F(CLK_DIV_ATLAS_PLL
, "div_atlas_pll", "mout_atlas",
3816 DIV_ATLAS1
, 0, 3, CLK_GET_RATE_NOCACHE
,
3817 CLK_DIVIDER_READ_ONLY
),
3820 static struct samsung_gate_clock atlas_gate_clks
[] __initdata
= {
3821 /* ENABLE_ACLK_ATLAS */
3822 GATE(CLK_ACLK_ATB_AUD_CSSYS
, "aclk_atb_aud_cssys",
3823 "div_atclk_atlas", ENABLE_ACLK_ATLAS
,
3824 9, CLK_IGNORE_UNUSED
, 0),
3825 GATE(CLK_ACLK_ATB_APOLLO3_CSSYS
, "aclk_atb_apollo3_cssys",
3826 "div_atclk_atlas", ENABLE_ACLK_ATLAS
,
3827 8, CLK_IGNORE_UNUSED
, 0),
3828 GATE(CLK_ACLK_ATB_APOLLO2_CSSYS
, "aclk_atb_apollo2_cssys",
3829 "div_atclk_atlas", ENABLE_ACLK_ATLAS
,
3830 7, CLK_IGNORE_UNUSED
, 0),
3831 GATE(CLK_ACLK_ATB_APOLLO1_CSSYS
, "aclk_atb_apollo1_cssys",
3832 "div_atclk_atlas", ENABLE_ACLK_ATLAS
,
3833 6, CLK_IGNORE_UNUSED
, 0),
3834 GATE(CLK_ACLK_ATB_APOLLO0_CSSYS
, "aclk_atb_apollo0_cssys",
3835 "div_atclk_atlas", ENABLE_ACLK_ATLAS
,
3836 5, CLK_IGNORE_UNUSED
, 0),
3837 GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS
, "aclk_asyncahbs_cssys_sss",
3838 "div_atclk_atlas", ENABLE_ACLK_ATLAS
,
3839 4, CLK_IGNORE_UNUSED
, 0),
3840 GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX
, "aclk_asyncaxis_cssys_ccix",
3841 "div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS
,
3842 3, CLK_IGNORE_UNUSED
, 0),
3843 GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI
, "aclk_asyncaces_atlas_cci",
3844 "div_aclk_atlas", ENABLE_ACLK_ATLAS
,
3845 2, CLK_IGNORE_UNUSED
, 0),
3846 GATE(CLK_ACLK_AHB2APB_ATLASP
, "aclk_ahb2apb_atlasp", "div_pclk_atlas",
3847 ENABLE_ACLK_ATLAS
, 1, CLK_IGNORE_UNUSED
, 0),
3848 GATE(CLK_ACLK_ATLASNP_200
, "aclk_atlasnp_200", "div_pclk_atlas",
3849 ENABLE_ACLK_ATLAS
, 0, CLK_IGNORE_UNUSED
, 0),
3851 /* ENABLE_PCLK_ATLAS */
3852 GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS
, "pclk_asyncapb_aud_cssys",
3853 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS
,
3854 5, CLK_IGNORE_UNUSED
, 0),
3855 GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS
, "pclk_asyncapb_isp_cssys",
3856 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS
,
3857 4, CLK_IGNORE_UNUSED
, 0),
3858 GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS
, "pclk_asyncapb_apollo_cssys",
3859 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS
,
3860 3, CLK_IGNORE_UNUSED
, 0),
3861 GATE(CLK_PCLK_PMU_ATLAS
, "pclk_pmu_atlas", "div_pclk_atlas",
3862 ENABLE_PCLK_ATLAS
, 2, CLK_IGNORE_UNUSED
, 0),
3863 GATE(CLK_PCLK_SYSREG_ATLAS
, "pclk_sysreg_atlas", "div_pclk_atlas",
3864 ENABLE_PCLK_ATLAS
, 1, CLK_IGNORE_UNUSED
, 0),
3865 GATE(CLK_PCLK_SECJTAG
, "pclk_secjtag", "div_pclk_dbg_atlas",
3866 ENABLE_PCLK_ATLAS
, 0, CLK_IGNORE_UNUSED
, 0),
3868 /* ENABLE_SCLK_ATLAS */
3869 GATE(CLK_CNTCLK_ATLAS
, "cntclk_atlas", "div_cntclk_atlas",
3870 ENABLE_SCLK_ATLAS
, 10, CLK_IGNORE_UNUSED
, 0),
3871 GATE(CLK_SCLK_HPM_ATLAS
, "sclk_hpm_atlas", "div_sclk_hpm_atlas",
3872 ENABLE_SCLK_ATLAS
, 7, CLK_IGNORE_UNUSED
, 0),
3873 GATE(CLK_TRACECLK
, "traceclk", "div_atclk_atlas",
3874 ENABLE_SCLK_ATLAS
, 6, CLK_IGNORE_UNUSED
, 0),
3875 GATE(CLK_CTMCLK
, "ctmclk", "div_atclk_atlas",
3876 ENABLE_SCLK_ATLAS
, 5, CLK_IGNORE_UNUSED
, 0),
3877 GATE(CLK_HCLK_CSSYS
, "hclk_cssys", "div_atclk_atlas",
3878 ENABLE_SCLK_ATLAS
, 4, CLK_IGNORE_UNUSED
, 0),
3879 GATE(CLK_PCLK_DBG_CSSYS
, "pclk_dbg_cssys", "div_pclk_dbg_atlas",
3880 ENABLE_SCLK_ATLAS
, 3, CLK_IGNORE_UNUSED
, 0),
3881 GATE(CLK_PCLK_DBG
, "pclk_dbg", "div_pclk_dbg_atlas",
3882 ENABLE_SCLK_ATLAS
, 2, CLK_IGNORE_UNUSED
, 0),
3883 GATE(CLK_ATCLK
, "atclk", "div_atclk_atlas",
3884 ENABLE_SCLK_ATLAS
, 1, CLK_IGNORE_UNUSED
, 0),
3885 GATE(CLK_SCLK_ATLAS
, "sclk_atlas", "div_atlas2",
3886 ENABLE_SCLK_ATLAS
, 0,
3887 CLK_IGNORE_UNUSED
| CLK_SET_RATE_PARENT
, 0),
3890 static struct samsung_cmu_info atlas_cmu_info __initdata
= {
3891 .pll_clks
= atlas_pll_clks
,
3892 .nr_pll_clks
= ARRAY_SIZE(atlas_pll_clks
),
3893 .mux_clks
= atlas_mux_clks
,
3894 .nr_mux_clks
= ARRAY_SIZE(atlas_mux_clks
),
3895 .div_clks
= atlas_div_clks
,
3896 .nr_div_clks
= ARRAY_SIZE(atlas_div_clks
),
3897 .gate_clks
= atlas_gate_clks
,
3898 .nr_gate_clks
= ARRAY_SIZE(atlas_gate_clks
),
3899 .nr_clk_ids
= ATLAS_NR_CLK
,
3900 .clk_regs
= atlas_clk_regs
,
3901 .nr_clk_regs
= ARRAY_SIZE(atlas_clk_regs
),
3904 static void __init
exynos5433_cmu_atlas_init(struct device_node
*np
)
3906 samsung_cmu_register_one(np
, &atlas_cmu_info
);
3908 CLK_OF_DECLARE(exynos5433_cmu_atlas
, "samsung,exynos5433-cmu-atlas",
3909 exynos5433_cmu_atlas_init
);
3912 * Register offset definitions for CMU_MSCL
3914 #define MUX_SEL_MSCL0 0x0200
3915 #define MUX_SEL_MSCL1 0x0204
3916 #define MUX_ENABLE_MSCL0 0x0300
3917 #define MUX_ENABLE_MSCL1 0x0304
3918 #define MUX_STAT_MSCL0 0x0400
3919 #define MUX_STAT_MSCL1 0x0404
3920 #define DIV_MSCL 0x0600
3921 #define DIV_STAT_MSCL 0x0700
3922 #define ENABLE_ACLK_MSCL 0x0800
3923 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0804
3924 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0808
3925 #define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG 0x080c
3926 #define ENABLE_PCLK_MSCL 0x0900
3927 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904
3928 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908
3929 #define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x090c
3930 #define ENABLE_SCLK_MSCL 0x0a00
3931 #define ENABLE_IP_MSCL0 0x0b00
3932 #define ENABLE_IP_MSCL1 0x0b04
3933 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 0x0b08
3934 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c
3935 #define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10
3937 static unsigned long mscl_clk_regs
[] __initdata
= {
3947 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0
,
3948 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1
,
3949 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG
,
3951 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0
,
3952 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1
,
3953 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG
,
3957 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0
,
3958 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1
,
3959 ENABLE_IP_MSCL_SECURE_SMMU_JPEG
,
3962 /* list of all parent clock list */
3963 PNAME(mout_sclk_jpeg_user_p
) = { "oscclk", "sclk_jpeg_mscl", };
3964 PNAME(mout_aclk_mscl_400_user_p
) = { "oscclk", "aclk_mscl_400", };
3965 PNAME(mout_sclk_jpeg_p
) = { "mout_sclk_jpeg_user",
3966 "mout_aclk_mscl_400_user", };
3968 static struct samsung_mux_clock mscl_mux_clks
[] __initdata
= {
3970 MUX(CLK_MOUT_SCLK_JPEG_USER
, "mout_sclk_jpeg_user",
3971 mout_sclk_jpeg_user_p
, MUX_SEL_MSCL0
, 4, 1),
3972 MUX(CLK_MOUT_ACLK_MSCL_400_USER
, "mout_aclk_mscl_400_user",
3973 mout_aclk_mscl_400_user_p
, MUX_SEL_MSCL0
, 0, 1),
3976 MUX(CLK_MOUT_SCLK_JPEG
, "mout_sclk_jpeg", mout_sclk_jpeg_p
,
3977 MUX_SEL_MSCL1
, 0, 1),
3980 static struct samsung_div_clock mscl_div_clks
[] __initdata
= {
3982 DIV(CLK_DIV_PCLK_MSCL
, "div_pclk_mscl", "mout_aclk_mscl_400_user",
3986 static struct samsung_gate_clock mscl_gate_clks
[] __initdata
= {
3987 /* ENABLE_ACLK_MSCL */
3988 GATE(CLK_ACLK_BTS_JPEG
, "aclk_bts_jpeg", "mout_aclk_mscl_400_user",
3989 ENABLE_ACLK_MSCL
, 9, 0, 0),
3990 GATE(CLK_ACLK_BTS_M2MSCALER1
, "aclk_bts_m2mscaler1",
3991 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL
, 8, 0, 0),
3992 GATE(CLK_ACLK_BTS_M2MSCALER0
, "aclk_bts_m2mscaler0",
3993 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL
, 7, 0, 0),
3994 GATE(CLK_ACLK_AHB2APB_MSCL0P
, "aclk_abh2apb_mscl0p", "div_pclk_mscl",
3995 ENABLE_ACLK_MSCL
, 6, CLK_IGNORE_UNUSED
, 0),
3996 GATE(CLK_ACLK_XIU_MSCLX
, "aclk_xiu_msclx", "mout_aclk_mscl_400_user",
3997 ENABLE_ACLK_MSCL
, 5, CLK_IGNORE_UNUSED
, 0),
3998 GATE(CLK_ACLK_MSCLNP_100
, "aclk_msclnp_100", "div_pclk_mscl",
3999 ENABLE_ACLK_MSCL
, 4, CLK_IGNORE_UNUSED
, 0),
4000 GATE(CLK_ACLK_MSCLND_400
, "aclk_msclnd_400", "mout_aclk_mscl_400_user",
4001 ENABLE_ACLK_MSCL
, 3, CLK_IGNORE_UNUSED
, 0),
4002 GATE(CLK_ACLK_JPEG
, "aclk_jpeg", "mout_aclk_mscl_400_user",
4003 ENABLE_ACLK_MSCL
, 2, 0, 0),
4004 GATE(CLK_ACLK_M2MSCALER1
, "aclk_m2mscaler1", "mout_aclk_mscl_400_user",
4005 ENABLE_ACLK_MSCL
, 1, 0, 0),
4006 GATE(CLK_ACLK_M2MSCALER0
, "aclk_m2mscaler0", "mout_aclk_mscl_400_user",
4007 ENABLE_ACLK_MSCL
, 0, 0, 0),
4009 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */
4010 GATE(CLK_ACLK_SMMU_M2MSCALER0
, "aclk_smmu_m2mscaler0",
4011 "mout_aclk_mscl_400_user",
4012 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0
,
4013 0, CLK_IGNORE_UNUSED
, 0),
4015 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */
4016 GATE(CLK_ACLK_SMMU_M2MSCALER1
, "aclk_smmu_m2mscaler1",
4017 "mout_aclk_mscl_400_user",
4018 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1
,
4019 0, CLK_IGNORE_UNUSED
, 0),
4021 /* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */
4022 GATE(CLK_ACLK_SMMU_JPEG
, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user",
4023 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG
,
4024 0, CLK_IGNORE_UNUSED
, 0),
4026 /* ENABLE_PCLK_MSCL */
4027 GATE(CLK_PCLK_BTS_JPEG
, "pclk_bts_jpeg", "div_pclk_mscl",
4028 ENABLE_PCLK_MSCL
, 7, 0, 0),
4029 GATE(CLK_PCLK_BTS_M2MSCALER1
, "pclk_bts_m2mscaler1", "div_pclk_mscl",
4030 ENABLE_PCLK_MSCL
, 6, 0, 0),
4031 GATE(CLK_PCLK_BTS_M2MSCALER0
, "pclk_bts_m2mscaler0", "div_pclk_mscl",
4032 ENABLE_PCLK_MSCL
, 5, 0, 0),
4033 GATE(CLK_PCLK_PMU_MSCL
, "pclk_pmu_mscl", "div_pclk_mscl",
4034 ENABLE_PCLK_MSCL
, 4, CLK_IGNORE_UNUSED
, 0),
4035 GATE(CLK_PCLK_SYSREG_MSCL
, "pclk_sysreg_mscl", "div_pclk_mscl",
4036 ENABLE_PCLK_MSCL
, 3, CLK_IGNORE_UNUSED
, 0),
4037 GATE(CLK_PCLK_JPEG
, "pclk_jpeg", "div_pclk_mscl",
4038 ENABLE_PCLK_MSCL
, 2, 0, 0),
4039 GATE(CLK_PCLK_M2MSCALER1
, "pclk_m2mscaler1", "div_pclk_mscl",
4040 ENABLE_PCLK_MSCL
, 1, 0, 0),
4041 GATE(CLK_PCLK_M2MSCALER0
, "pclk_m2mscaler0", "div_pclk_mscl",
4042 ENABLE_PCLK_MSCL
, 0, 0, 0),
4044 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */
4045 GATE(CLK_PCLK_SMMU_M2MSCALER0
, "pclk_smmu_m2mscaler0", "div_pclk_mscl",
4046 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0
,
4047 0, CLK_IGNORE_UNUSED
, 0),
4049 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */
4050 GATE(CLK_PCLK_SMMU_M2MSCALER1
, "pclk_smmu_m2mscaler1", "div_pclk_mscl",
4051 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1
,
4052 0, CLK_IGNORE_UNUSED
, 0),
4054 /* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */
4055 GATE(CLK_PCLK_SMMU_JPEG
, "pclk_smmu_jpeg", "div_pclk_mscl",
4056 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG
,
4057 0, CLK_IGNORE_UNUSED
, 0),
4059 /* ENABLE_SCLK_MSCL */
4060 GATE(CLK_SCLK_JPEG
, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL
, 0,
4061 CLK_IGNORE_UNUSED
| CLK_SET_RATE_PARENT
, 0),
4064 static struct samsung_cmu_info mscl_cmu_info __initdata
= {
4065 .mux_clks
= mscl_mux_clks
,
4066 .nr_mux_clks
= ARRAY_SIZE(mscl_mux_clks
),
4067 .div_clks
= mscl_div_clks
,
4068 .nr_div_clks
= ARRAY_SIZE(mscl_div_clks
),
4069 .gate_clks
= mscl_gate_clks
,
4070 .nr_gate_clks
= ARRAY_SIZE(mscl_gate_clks
),
4071 .nr_clk_ids
= MSCL_NR_CLK
,
4072 .clk_regs
= mscl_clk_regs
,
4073 .nr_clk_regs
= ARRAY_SIZE(mscl_clk_regs
),
4076 static void __init
exynos5433_cmu_mscl_init(struct device_node
*np
)
4078 samsung_cmu_register_one(np
, &mscl_cmu_info
);
4080 CLK_OF_DECLARE(exynos5433_cmu_mscl
, "samsung,exynos5433-cmu-mscl",
4081 exynos5433_cmu_mscl_init
);
4084 * Register offset definitions for CMU_MFC
4086 #define MUX_SEL_MFC 0x0200
4087 #define MUX_ENABLE_MFC 0x0300
4088 #define MUX_STAT_MFC 0x0400
4089 #define DIV_MFC 0x0600
4090 #define DIV_STAT_MFC 0x0700
4091 #define ENABLE_ACLK_MFC 0x0800
4092 #define ENABLE_ACLK_MFC_SECURE_SMMU_MFC 0x0804
4093 #define ENABLE_PCLK_MFC 0x0900
4094 #define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0x0904
4095 #define ENABLE_IP_MFC0 0x0b00
4096 #define ENABLE_IP_MFC1 0x0b04
4097 #define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08
4099 static unsigned long mfc_clk_regs
[] __initdata
= {
4106 ENABLE_ACLK_MFC_SECURE_SMMU_MFC
,
4108 ENABLE_PCLK_MFC_SECURE_SMMU_MFC
,
4111 ENABLE_IP_MFC_SECURE_SMMU_MFC
,
4114 PNAME(mout_aclk_mfc_400_user_p
) = { "oscclk", "aclk_mfc_400", };
4116 static struct samsung_mux_clock mfc_mux_clks
[] __initdata
= {
4118 MUX(CLK_MOUT_ACLK_MFC_400_USER
, "mout_aclk_mfc_400_user",
4119 mout_aclk_mfc_400_user_p
, MUX_SEL_MFC
, 0, 0),
4122 static struct samsung_div_clock mfc_div_clks
[] __initdata
= {
4124 DIV(CLK_DIV_PCLK_MFC
, "div_pclk_mfc", "mout_aclk_mfc_400_user",
4128 static struct samsung_gate_clock mfc_gate_clks
[] __initdata
= {
4129 /* ENABLE_ACLK_MFC */
4130 GATE(CLK_ACLK_BTS_MFC_1
, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user",
4131 ENABLE_ACLK_MFC
, 6, 0, 0),
4132 GATE(CLK_ACLK_BTS_MFC_0
, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user",
4133 ENABLE_ACLK_MFC
, 5, 0, 0),
4134 GATE(CLK_ACLK_AHB2APB_MFCP
, "aclk_ahb2apb_mfcp", "div_pclk_mfc",
4135 ENABLE_ACLK_MFC
, 4, CLK_IGNORE_UNUSED
, 0),
4136 GATE(CLK_ACLK_XIU_MFCX
, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user",
4137 ENABLE_ACLK_MFC
, 3, CLK_IGNORE_UNUSED
, 0),
4138 GATE(CLK_ACLK_MFCNP_100
, "aclk_mfcnp_100", "div_pclk_mfc",
4139 ENABLE_ACLK_MFC
, 2, CLK_IGNORE_UNUSED
, 0),
4140 GATE(CLK_ACLK_MFCND_400
, "aclk_mfcnd_400", "mout_aclk_mfc_400_user",
4141 ENABLE_ACLK_MFC
, 1, CLK_IGNORE_UNUSED
, 0),
4142 GATE(CLK_ACLK_MFC
, "aclk_mfc", "mout_aclk_mfc_400_user",
4143 ENABLE_ACLK_MFC
, 0, 0, 0),
4145 /* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */
4146 GATE(CLK_ACLK_SMMU_MFC_1
, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user",
4147 ENABLE_ACLK_MFC_SECURE_SMMU_MFC
,
4148 1, CLK_IGNORE_UNUSED
, 0),
4149 GATE(CLK_ACLK_SMMU_MFC_0
, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user",
4150 ENABLE_ACLK_MFC_SECURE_SMMU_MFC
,
4151 0, CLK_IGNORE_UNUSED
, 0),
4153 /* ENABLE_PCLK_MFC */
4154 GATE(CLK_PCLK_BTS_MFC_1
, "pclk_bts_mfc_1", "div_pclk_mfc",
4155 ENABLE_PCLK_MFC
, 4, 0, 0),
4156 GATE(CLK_PCLK_BTS_MFC_0
, "pclk_bts_mfc_0", "div_pclk_mfc",
4157 ENABLE_PCLK_MFC
, 3, 0, 0),
4158 GATE(CLK_PCLK_PMU_MFC
, "pclk_pmu_mfc", "div_pclk_mfc",
4159 ENABLE_PCLK_MFC
, 2, CLK_IGNORE_UNUSED
, 0),
4160 GATE(CLK_PCLK_SYSREG_MFC
, "pclk_sysreg_mfc", "div_pclk_mfc",
4161 ENABLE_PCLK_MFC
, 1, CLK_IGNORE_UNUSED
, 0),
4162 GATE(CLK_PCLK_MFC
, "pclk_mfc", "div_pclk_mfc",
4163 ENABLE_PCLK_MFC
, 4, CLK_IGNORE_UNUSED
, 0),
4165 /* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */
4166 GATE(CLK_PCLK_SMMU_MFC_1
, "pclk_smmu_mfc_1", "div_pclk_mfc",
4167 ENABLE_PCLK_MFC_SECURE_SMMU_MFC
,
4168 1, CLK_IGNORE_UNUSED
, 0),
4169 GATE(CLK_PCLK_SMMU_MFC_0
, "pclk_smmu_mfc_0", "div_pclk_mfc",
4170 ENABLE_PCLK_MFC_SECURE_SMMU_MFC
,
4171 0, CLK_IGNORE_UNUSED
, 0),
4174 static struct samsung_cmu_info mfc_cmu_info __initdata
= {
4175 .mux_clks
= mfc_mux_clks
,
4176 .nr_mux_clks
= ARRAY_SIZE(mfc_mux_clks
),
4177 .div_clks
= mfc_div_clks
,
4178 .nr_div_clks
= ARRAY_SIZE(mfc_div_clks
),
4179 .gate_clks
= mfc_gate_clks
,
4180 .nr_gate_clks
= ARRAY_SIZE(mfc_gate_clks
),
4181 .nr_clk_ids
= MFC_NR_CLK
,
4182 .clk_regs
= mfc_clk_regs
,
4183 .nr_clk_regs
= ARRAY_SIZE(mfc_clk_regs
),
4186 static void __init
exynos5433_cmu_mfc_init(struct device_node
*np
)
4188 samsung_cmu_register_one(np
, &mfc_cmu_info
);
4190 CLK_OF_DECLARE(exynos5433_cmu_mfc
, "samsung,exynos5433-cmu-mfc",
4191 exynos5433_cmu_mfc_init
);
4194 * Register offset definitions for CMU_HEVC
4196 #define MUX_SEL_HEVC 0x0200
4197 #define MUX_ENABLE_HEVC 0x0300
4198 #define MUX_STAT_HEVC 0x0400
4199 #define DIV_HEVC 0x0600
4200 #define DIV_STAT_HEVC 0x0700
4201 #define ENABLE_ACLK_HEVC 0x0800
4202 #define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC 0x0804
4203 #define ENABLE_PCLK_HEVC 0x0900
4204 #define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC 0x0904
4205 #define ENABLE_IP_HEVC0 0x0b00
4206 #define ENABLE_IP_HEVC1 0x0b04
4207 #define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08
4209 static unsigned long hevc_clk_regs
[] __initdata
= {
4216 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC
,
4218 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC
,
4221 ENABLE_IP_HEVC_SECURE_SMMU_HEVC
,
4224 PNAME(mout_aclk_hevc_400_user_p
) = { "oscclk", "aclk_hevc_400", };
4226 static struct samsung_mux_clock hevc_mux_clks
[] __initdata
= {
4228 MUX(CLK_MOUT_ACLK_HEVC_400_USER
, "mout_aclk_hevc_400_user",
4229 mout_aclk_hevc_400_user_p
, MUX_SEL_HEVC
, 0, 0),
4232 static struct samsung_div_clock hevc_div_clks
[] __initdata
= {
4234 DIV(CLK_DIV_PCLK_HEVC
, "div_pclk_hevc", "mout_aclk_hevc_400_user",
4238 static struct samsung_gate_clock hevc_gate_clks
[] __initdata
= {
4239 /* ENABLE_ACLK_HEVC */
4240 GATE(CLK_ACLK_BTS_HEVC_1
, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user",
4241 ENABLE_ACLK_HEVC
, 6, 0, 0),
4242 GATE(CLK_ACLK_BTS_HEVC_0
, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user",
4243 ENABLE_ACLK_HEVC
, 5, 0, 0),
4244 GATE(CLK_ACLK_AHB2APB_HEVCP
, "aclk_ahb2apb_hevcp", "div_pclk_hevc",
4245 ENABLE_ACLK_HEVC
, 4, CLK_IGNORE_UNUSED
, 0),
4246 GATE(CLK_ACLK_XIU_HEVCX
, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user",
4247 ENABLE_ACLK_HEVC
, 3, CLK_IGNORE_UNUSED
, 0),
4248 GATE(CLK_ACLK_HEVCNP_100
, "aclk_hevcnp_100", "div_pclk_hevc",
4249 ENABLE_ACLK_HEVC
, 2, CLK_IGNORE_UNUSED
, 0),
4250 GATE(CLK_ACLK_HEVCND_400
, "aclk_hevcnd_400", "mout_aclk_hevc_400_user",
4251 ENABLE_ACLK_HEVC
, 1, CLK_IGNORE_UNUSED
, 0),
4252 GATE(CLK_ACLK_HEVC
, "aclk_hevc", "mout_aclk_hevc_400_user",
4253 ENABLE_ACLK_HEVC
, 0, 0, 0),
4255 /* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */
4256 GATE(CLK_ACLK_SMMU_HEVC_1
, "aclk_smmu_hevc_1",
4257 "mout_aclk_hevc_400_user",
4258 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC
,
4259 1, CLK_IGNORE_UNUSED
, 0),
4260 GATE(CLK_ACLK_SMMU_HEVC_0
, "aclk_smmu_hevc_0",
4261 "mout_aclk_hevc_400_user",
4262 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC
,
4263 0, CLK_IGNORE_UNUSED
, 0),
4265 /* ENABLE_PCLK_HEVC */
4266 GATE(CLK_PCLK_BTS_HEVC_1
, "pclk_bts_hevc_1", "div_pclk_hevc",
4267 ENABLE_PCLK_HEVC
, 4, 0, 0),
4268 GATE(CLK_PCLK_BTS_HEVC_0
, "pclk_bts_hevc_0", "div_pclk_hevc",
4269 ENABLE_PCLK_HEVC
, 3, 0, 0),
4270 GATE(CLK_PCLK_PMU_HEVC
, "pclk_pmu_hevc", "div_pclk_hevc",
4271 ENABLE_PCLK_HEVC
, 2, CLK_IGNORE_UNUSED
, 0),
4272 GATE(CLK_PCLK_SYSREG_HEVC
, "pclk_sysreg_hevc", "div_pclk_hevc",
4273 ENABLE_PCLK_HEVC
, 1, CLK_IGNORE_UNUSED
, 0),
4274 GATE(CLK_PCLK_HEVC
, "pclk_hevc", "div_pclk_hevc",
4275 ENABLE_PCLK_HEVC
, 4, CLK_IGNORE_UNUSED
, 0),
4277 /* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */
4278 GATE(CLK_PCLK_SMMU_HEVC_1
, "pclk_smmu_hevc_1", "div_pclk_hevc",
4279 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC
,
4280 1, CLK_IGNORE_UNUSED
, 0),
4281 GATE(CLK_PCLK_SMMU_HEVC_0
, "pclk_smmu_hevc_0", "div_pclk_hevc",
4282 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC
,
4283 0, CLK_IGNORE_UNUSED
, 0),
4286 static struct samsung_cmu_info hevc_cmu_info __initdata
= {
4287 .mux_clks
= hevc_mux_clks
,
4288 .nr_mux_clks
= ARRAY_SIZE(hevc_mux_clks
),
4289 .div_clks
= hevc_div_clks
,
4290 .nr_div_clks
= ARRAY_SIZE(hevc_div_clks
),
4291 .gate_clks
= hevc_gate_clks
,
4292 .nr_gate_clks
= ARRAY_SIZE(hevc_gate_clks
),
4293 .nr_clk_ids
= HEVC_NR_CLK
,
4294 .clk_regs
= hevc_clk_regs
,
4295 .nr_clk_regs
= ARRAY_SIZE(hevc_clk_regs
),
4298 static void __init
exynos5433_cmu_hevc_init(struct device_node
*np
)
4300 samsung_cmu_register_one(np
, &hevc_cmu_info
);
4302 CLK_OF_DECLARE(exynos5433_cmu_hevc
, "samsung,exynos5433-cmu-hevc",
4303 exynos5433_cmu_hevc_init
);
4306 * Register offset definitions for CMU_ISP
4308 #define MUX_SEL_ISP 0x0200
4309 #define MUX_ENABLE_ISP 0x0300
4310 #define MUX_STAT_ISP 0x0400
4311 #define DIV_ISP 0x0600
4312 #define DIV_STAT_ISP 0x0700
4313 #define ENABLE_ACLK_ISP0 0x0800
4314 #define ENABLE_ACLK_ISP1 0x0804
4315 #define ENABLE_ACLK_ISP2 0x0808
4316 #define ENABLE_PCLK_ISP 0x0900
4317 #define ENABLE_SCLK_ISP 0x0a00
4318 #define ENABLE_IP_ISP0 0x0b00
4319 #define ENABLE_IP_ISP1 0x0b04
4320 #define ENABLE_IP_ISP2 0x0b08
4321 #define ENABLE_IP_ISP3 0x0b0c
4323 static unsigned long isp_clk_regs
[] __initdata
= {
4340 PNAME(mout_aclk_isp_dis_400_user_p
) = { "oscclk", "aclk_isp_dis_400", };
4341 PNAME(mout_aclk_isp_400_user_p
) = { "oscclk", "aclk_isp_400", };
4343 static struct samsung_mux_clock isp_mux_clks
[] __initdata
= {
4345 MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER
, "mout_aclk_isp_dis_400_user",
4346 mout_aclk_isp_dis_400_user_p
, MUX_SEL_ISP
, 4, 0),
4347 MUX(CLK_MOUT_ACLK_ISP_400_USER
, "mout_aclk_isp_400_user",
4348 mout_aclk_isp_400_user_p
, MUX_SEL_ISP
, 0, 0),
4351 static struct samsung_div_clock isp_div_clks
[] __initdata
= {
4353 DIV(CLK_DIV_PCLK_ISP_DIS
, "div_pclk_isp_dis",
4354 "mout_aclk_isp_dis_400_user", DIV_ISP
, 12, 3),
4355 DIV(CLK_DIV_PCLK_ISP
, "div_pclk_isp", "mout_aclk_isp_400_user",
4357 DIV(CLK_DIV_ACLK_ISP_D_200
, "div_aclk_isp_d_200",
4358 "mout_aclk_isp_400_user", DIV_ISP
, 4, 3),
4359 DIV(CLK_DIV_ACLK_ISP_C_200
, "div_aclk_isp_c_200",
4360 "mout_aclk_isp_400_user", DIV_ISP
, 0, 3),
4363 static struct samsung_gate_clock isp_gate_clks
[] __initdata
= {
4364 /* ENABLE_ACLK_ISP0 */
4365 GATE(CLK_ACLK_ISP_D_GLUE
, "aclk_isp_d_glue", "mout_aclk_isp_400_user",
4366 ENABLE_ACLK_ISP0
, 6, CLK_IGNORE_UNUSED
, 0),
4367 GATE(CLK_ACLK_SCALERP
, "aclk_scalerp", "mout_aclk_isp_400_user",
4368 ENABLE_ACLK_ISP0
, 5, 0, 0),
4369 GATE(CLK_ACLK_3DNR
, "aclk_3dnr", "mout_aclk_isp_400_user",
4370 ENABLE_ACLK_ISP0
, 4, 0, 0),
4371 GATE(CLK_ACLK_DIS
, "aclk_dis", "mout_aclk_isp_dis_400_user",
4372 ENABLE_ACLK_ISP0
, 3, 0, 0),
4373 GATE(CLK_ACLK_SCALERC
, "aclk_scalerc", "mout_aclk_isp_400_user",
4374 ENABLE_ACLK_ISP0
, 2, 0, 0),
4375 GATE(CLK_ACLK_DRC
, "aclk_drc", "mout_aclk_isp_400_user",
4376 ENABLE_ACLK_ISP0
, 1, 0, 0),
4377 GATE(CLK_ACLK_ISP
, "aclk_isp", "mout_aclk_isp_400_user",
4378 ENABLE_ACLK_ISP0
, 0, 0, 0),
4380 /* ENABLE_ACLK_ISP1 */
4381 GATE(CLK_ACLK_AXIUS_SCALERP
, "aclk_axius_scalerp",
4382 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1
,
4383 17, CLK_IGNORE_UNUSED
, 0),
4384 GATE(CLK_ACLK_AXIUS_SCALERC
, "aclk_axius_scalerc",
4385 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1
,
4386 16, CLK_IGNORE_UNUSED
, 0),
4387 GATE(CLK_ACLK_AXIUS_DRC
, "aclk_axius_drc",
4388 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1
,
4389 15, CLK_IGNORE_UNUSED
, 0),
4390 GATE(CLK_ACLK_ASYNCAHBM_ISP2P
, "aclk_asyncahbm_isp2p",
4391 "div_pclk_isp", ENABLE_ACLK_ISP1
,
4392 14, CLK_IGNORE_UNUSED
, 0),
4393 GATE(CLK_ACLK_ASYNCAHBM_ISP1P
, "aclk_asyncahbm_isp1p",
4394 "div_pclk_isp", ENABLE_ACLK_ISP1
,
4395 13, CLK_IGNORE_UNUSED
, 0),
4396 GATE(CLK_ACLK_ASYNCAXIS_DIS1
, "aclk_asyncaxis_dis1",
4397 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1
,
4398 12, CLK_IGNORE_UNUSED
, 0),
4399 GATE(CLK_ACLK_ASYNCAXIS_DIS0
, "aclk_asyncaxis_dis0",
4400 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1
,
4401 11, CLK_IGNORE_UNUSED
, 0),
4402 GATE(CLK_ACLK_ASYNCAXIM_DIS1
, "aclk_asyncaxim_dis1",
4403 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1
,
4404 10, CLK_IGNORE_UNUSED
, 0),
4405 GATE(CLK_ACLK_ASYNCAXIM_DIS0
, "aclk_asyncaxim_dis0",
4406 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1
,
4407 9, CLK_IGNORE_UNUSED
, 0),
4408 GATE(CLK_ACLK_ASYNCAXIM_ISP2P
, "aclk_asyncaxim_isp2p",
4409 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1
,
4410 8, CLK_IGNORE_UNUSED
, 0),
4411 GATE(CLK_ACLK_ASYNCAXIM_ISP1P
, "aclk_asyncaxim_isp1p",
4412 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1
,
4413 7, CLK_IGNORE_UNUSED
, 0),
4414 GATE(CLK_ACLK_AHB2APB_ISP2P
, "aclk_ahb2apb_isp2p", "div_pclk_isp",
4415 ENABLE_ACLK_ISP1
, 6, CLK_IGNORE_UNUSED
, 0),
4416 GATE(CLK_ACLK_AHB2APB_ISP1P
, "aclk_ahb2apb_isp1p", "div_pclk_isp",
4417 ENABLE_ACLK_ISP1
, 5, CLK_IGNORE_UNUSED
, 0),
4418 GATE(CLK_ACLK_AXI2APB_ISP2P
, "aclk_axi2apb_isp2p",
4419 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1
,
4420 4, CLK_IGNORE_UNUSED
, 0),
4421 GATE(CLK_ACLK_AXI2APB_ISP1P
, "aclk_axi2apb_isp1p",
4422 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1
,
4423 3, CLK_IGNORE_UNUSED
, 0),
4424 GATE(CLK_ACLK_XIU_ISPEX1
, "aclk_xiu_ispex1", "mout_aclk_isp_400_user",
4425 ENABLE_ACLK_ISP1
, 2, CLK_IGNORE_UNUSED
, 0),
4426 GATE(CLK_ACLK_XIU_ISPEX0
, "aclk_xiu_ispex0", "mout_aclk_isp_400_user",
4427 ENABLE_ACLK_ISP1
, 1, CLK_IGNORE_UNUSED
, 0),
4428 GATE(CLK_ACLK_ISPND_400
, "aclk_ispnd_400", "mout_aclk_isp_400_user",
4429 ENABLE_ACLK_ISP1
, 1, CLK_IGNORE_UNUSED
, 0),
4431 /* ENABLE_ACLK_ISP2 */
4432 GATE(CLK_ACLK_SMMU_SCALERP
, "aclk_smmu_scalerp",
4433 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2
,
4434 13, CLK_IGNORE_UNUSED
, 0),
4435 GATE(CLK_ACLK_SMMU_3DNR
, "aclk_smmu_3dnr", "mout_aclk_isp_400_user",
4436 ENABLE_ACLK_ISP2
, 12, CLK_IGNORE_UNUSED
, 0),
4437 GATE(CLK_ACLK_SMMU_DIS1
, "aclk_smmu_dis1", "mout_aclk_isp_400_user",
4438 ENABLE_ACLK_ISP2
, 11, CLK_IGNORE_UNUSED
, 0),
4439 GATE(CLK_ACLK_SMMU_DIS0
, "aclk_smmu_dis0", "mout_aclk_isp_400_user",
4440 ENABLE_ACLK_ISP2
, 10, CLK_IGNORE_UNUSED
, 0),
4441 GATE(CLK_ACLK_SMMU_SCALERC
, "aclk_smmu_scalerc",
4442 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2
,
4443 9, CLK_IGNORE_UNUSED
, 0),
4444 GATE(CLK_ACLK_SMMU_DRC
, "aclk_smmu_drc", "mout_aclk_isp_400_user",
4445 ENABLE_ACLK_ISP2
, 8, CLK_IGNORE_UNUSED
, 0),
4446 GATE(CLK_ACLK_SMMU_ISP
, "aclk_smmu_isp", "mout_aclk_isp_400_user",
4447 ENABLE_ACLK_ISP2
, 7, CLK_IGNORE_UNUSED
, 0),
4448 GATE(CLK_ACLK_BTS_SCALERP
, "aclk_bts_scalerp",
4449 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2
,
4450 6, CLK_IGNORE_UNUSED
, 0),
4451 GATE(CLK_ACLK_BTS_3DR
, "aclk_bts_3dnr", "mout_aclk_isp_400_user",
4452 ENABLE_ACLK_ISP2
, 5, CLK_IGNORE_UNUSED
, 0),
4453 GATE(CLK_ACLK_BTS_DIS1
, "aclk_bts_dis1", "mout_aclk_isp_400_user",
4454 ENABLE_ACLK_ISP2
, 4, CLK_IGNORE_UNUSED
, 0),
4455 GATE(CLK_ACLK_BTS_DIS0
, "aclk_bts_dis0", "mout_aclk_isp_400_user",
4456 ENABLE_ACLK_ISP2
, 3, CLK_IGNORE_UNUSED
, 0),
4457 GATE(CLK_ACLK_BTS_SCALERC
, "aclk_bts_scalerc",
4458 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2
,
4459 2, CLK_IGNORE_UNUSED
, 0),
4460 GATE(CLK_ACLK_BTS_DRC
, "aclk_bts_drc", "mout_aclk_isp_400_user",
4461 ENABLE_ACLK_ISP2
, 1, CLK_IGNORE_UNUSED
, 0),
4462 GATE(CLK_ACLK_BTS_ISP
, "aclk_bts_isp", "mout_aclk_isp_400_user",
4463 ENABLE_ACLK_ISP2
, 0, CLK_IGNORE_UNUSED
, 0),
4465 /* ENABLE_PCLK_ISP */
4466 GATE(CLK_PCLK_SMMU_SCALERP
, "pclk_smmu_scalerp", "div_aclk_isp_d_200",
4467 ENABLE_PCLK_ISP
, 25, CLK_IGNORE_UNUSED
, 0),
4468 GATE(CLK_PCLK_SMMU_3DNR
, "pclk_smmu_3dnr", "div_aclk_isp_d_200",
4469 ENABLE_PCLK_ISP
, 24, CLK_IGNORE_UNUSED
, 0),
4470 GATE(CLK_PCLK_SMMU_DIS1
, "pclk_smmu_dis1", "div_aclk_isp_d_200",
4471 ENABLE_PCLK_ISP
, 23, CLK_IGNORE_UNUSED
, 0),
4472 GATE(CLK_PCLK_SMMU_DIS0
, "pclk_smmu_dis0", "div_aclk_isp_d_200",
4473 ENABLE_PCLK_ISP
, 22, CLK_IGNORE_UNUSED
, 0),
4474 GATE(CLK_PCLK_SMMU_SCALERC
, "pclk_smmu_scalerc", "div_aclk_isp_c_200",
4475 ENABLE_PCLK_ISP
, 21, CLK_IGNORE_UNUSED
, 0),
4476 GATE(CLK_PCLK_SMMU_DRC
, "pclk_smmu_drc", "div_aclk_isp_c_200",
4477 ENABLE_PCLK_ISP
, 20, CLK_IGNORE_UNUSED
, 0),
4478 GATE(CLK_PCLK_SMMU_ISP
, "pclk_smmu_isp", "div_aclk_isp_c_200",
4479 ENABLE_PCLK_ISP
, 19, CLK_IGNORE_UNUSED
, 0),
4480 GATE(CLK_PCLK_BTS_SCALERP
, "pclk_bts_scalerp", "div_pclk_isp",
4481 ENABLE_PCLK_ISP
, 18, CLK_IGNORE_UNUSED
, 0),
4482 GATE(CLK_PCLK_BTS_3DNR
, "pclk_bts_3dnr", "div_pclk_isp",
4483 ENABLE_PCLK_ISP
, 17, CLK_IGNORE_UNUSED
, 0),
4484 GATE(CLK_PCLK_BTS_DIS1
, "pclk_bts_dis1", "div_pclk_isp",
4485 ENABLE_PCLK_ISP
, 16, CLK_IGNORE_UNUSED
, 0),
4486 GATE(CLK_PCLK_BTS_DIS0
, "pclk_bts_dis0", "div_pclk_isp",
4487 ENABLE_PCLK_ISP
, 15, CLK_IGNORE_UNUSED
, 0),
4488 GATE(CLK_PCLK_BTS_SCALERC
, "pclk_bts_scalerc", "div_pclk_isp",
4489 ENABLE_PCLK_ISP
, 14, CLK_IGNORE_UNUSED
, 0),
4490 GATE(CLK_PCLK_BTS_DRC
, "pclk_bts_drc", "div_pclk_isp",
4491 ENABLE_PCLK_ISP
, 13, CLK_IGNORE_UNUSED
, 0),
4492 GATE(CLK_PCLK_BTS_ISP
, "pclk_bts_isp", "div_pclk_isp",
4493 ENABLE_PCLK_ISP
, 12, CLK_IGNORE_UNUSED
, 0),
4494 GATE(CLK_PCLK_ASYNCAXI_DIS1
, "pclk_asyncaxi_dis1", "div_pclk_isp",
4495 ENABLE_PCLK_ISP
, 11, CLK_IGNORE_UNUSED
, 0),
4496 GATE(CLK_PCLK_ASYNCAXI_DIS0
, "pclk_asyncaxi_dis0", "div_pclk_isp",
4497 ENABLE_PCLK_ISP
, 10, CLK_IGNORE_UNUSED
, 0),
4498 GATE(CLK_PCLK_PMU_ISP
, "pclk_pmu_isp", "div_pclk_isp",
4499 ENABLE_PCLK_ISP
, 9, CLK_IGNORE_UNUSED
, 0),
4500 GATE(CLK_PCLK_SYSREG_ISP
, "pclk_sysreg_isp", "div_pclk_isp",
4501 ENABLE_PCLK_ISP
, 8, CLK_IGNORE_UNUSED
, 0),
4502 GATE(CLK_PCLK_CMU_ISP_LOCAL
, "pclk_cmu_isp_local",
4503 "div_aclk_isp_c_200", ENABLE_PCLK_ISP
,
4504 7, CLK_IGNORE_UNUSED
, 0),
4505 GATE(CLK_PCLK_SCALERP
, "pclk_scalerp", "div_aclk_isp_d_200",
4506 ENABLE_PCLK_ISP
, 6, CLK_IGNORE_UNUSED
, 0),
4507 GATE(CLK_PCLK_3DNR
, "pclk_3dnr", "div_aclk_isp_d_200",
4508 ENABLE_PCLK_ISP
, 5, CLK_IGNORE_UNUSED
, 0),
4509 GATE(CLK_PCLK_DIS_CORE
, "pclk_dis_core", "div_pclk_isp_dis",
4510 ENABLE_PCLK_ISP
, 4, CLK_IGNORE_UNUSED
, 0),
4511 GATE(CLK_PCLK_DIS
, "pclk_dis", "div_aclk_isp_d_200",
4512 ENABLE_PCLK_ISP
, 3, CLK_IGNORE_UNUSED
, 0),
4513 GATE(CLK_PCLK_SCALERC
, "pclk_scalerc", "div_aclk_isp_c_200",
4514 ENABLE_PCLK_ISP
, 2, CLK_IGNORE_UNUSED
, 0),
4515 GATE(CLK_PCLK_DRC
, "pclk_drc", "div_aclk_isp_c_200",
4516 ENABLE_PCLK_ISP
, 1, CLK_IGNORE_UNUSED
, 0),
4517 GATE(CLK_PCLK_ISP
, "pclk_isp", "div_aclk_isp_c_200",
4518 ENABLE_PCLK_ISP
, 0, CLK_IGNORE_UNUSED
, 0),
4520 /* ENABLE_SCLK_ISP */
4521 GATE(CLK_SCLK_PIXELASYNCS_DIS
, "sclk_pixelasyncs_dis",
4522 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP
,
4523 5, CLK_IGNORE_UNUSED
, 0),
4524 GATE(CLK_SCLK_PIXELASYNCM_DIS
, "sclk_pixelasyncm_dis",
4525 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP
,
4526 4, CLK_IGNORE_UNUSED
, 0),
4527 GATE(CLK_SCLK_PIXELASYNCS_SCALERP
, "sclk_pixelasyncs_scalerp",
4528 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP
,
4529 3, CLK_IGNORE_UNUSED
, 0),
4530 GATE(CLK_SCLK_PIXELASYNCM_ISPD
, "sclk_pixelasyncm_ispd",
4531 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP
,
4532 2, CLK_IGNORE_UNUSED
, 0),
4533 GATE(CLK_SCLK_PIXELASYNCS_ISPC
, "sclk_pixelasyncs_ispc",
4534 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP
,
4535 1, CLK_IGNORE_UNUSED
, 0),
4536 GATE(CLK_SCLK_PIXELASYNCM_ISPC
, "sclk_pixelasyncm_ispc",
4537 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP
,
4538 0, CLK_IGNORE_UNUSED
, 0),
4541 static struct samsung_cmu_info isp_cmu_info __initdata
= {
4542 .mux_clks
= isp_mux_clks
,
4543 .nr_mux_clks
= ARRAY_SIZE(isp_mux_clks
),
4544 .div_clks
= isp_div_clks
,
4545 .nr_div_clks
= ARRAY_SIZE(isp_div_clks
),
4546 .gate_clks
= isp_gate_clks
,
4547 .nr_gate_clks
= ARRAY_SIZE(isp_gate_clks
),
4548 .nr_clk_ids
= ISP_NR_CLK
,
4549 .clk_regs
= isp_clk_regs
,
4550 .nr_clk_regs
= ARRAY_SIZE(isp_clk_regs
),
4553 static void __init
exynos5433_cmu_isp_init(struct device_node
*np
)
4555 samsung_cmu_register_one(np
, &isp_cmu_info
);
4557 CLK_OF_DECLARE(exynos5433_cmu_isp
, "samsung,exynos5433-cmu-isp",
4558 exynos5433_cmu_isp_init
);
4561 * Register offset definitions for CMU_CAM0
4563 #define MUX_SEL_CAM00 0x0200
4564 #define MUX_SEL_CAM01 0x0204
4565 #define MUX_SEL_CAM02 0x0208
4566 #define MUX_SEL_CAM03 0x020c
4567 #define MUX_SEL_CAM04 0x0210
4568 #define MUX_ENABLE_CAM00 0x0300
4569 #define MUX_ENABLE_CAM01 0x0304
4570 #define MUX_ENABLE_CAM02 0x0308
4571 #define MUX_ENABLE_CAM03 0x030c
4572 #define MUX_ENABLE_CAM04 0x0310
4573 #define MUX_STAT_CAM00 0x0400
4574 #define MUX_STAT_CAM01 0x0404
4575 #define MUX_STAT_CAM02 0x0408
4576 #define MUX_STAT_CAM03 0x040c
4577 #define MUX_STAT_CAM04 0x0410
4578 #define MUX_IGNORE_CAM01 0x0504
4579 #define DIV_CAM00 0x0600
4580 #define DIV_CAM01 0x0604
4581 #define DIV_CAM02 0x0608
4582 #define DIV_CAM03 0x060c
4583 #define DIV_STAT_CAM00 0x0700
4584 #define DIV_STAT_CAM01 0x0704
4585 #define DIV_STAT_CAM02 0x0708
4586 #define DIV_STAT_CAM03 0x070c
4587 #define ENABLE_ACLK_CAM00 0X0800
4588 #define ENABLE_ACLK_CAM01 0X0804
4589 #define ENABLE_ACLK_CAM02 0X0808
4590 #define ENABLE_PCLK_CAM0 0X0900
4591 #define ENABLE_SCLK_CAM0 0X0a00
4592 #define ENABLE_IP_CAM00 0X0b00
4593 #define ENABLE_IP_CAM01 0X0b04
4594 #define ENABLE_IP_CAM02 0X0b08
4595 #define ENABLE_IP_CAM03 0X0b0C
4597 static unsigned long cam0_clk_regs
[] __initdata
= {
4632 PNAME(mout_aclk_cam0_333_user_p
) = { "oscclk", "aclk_cam0_333", };
4633 PNAME(mout_aclk_cam0_400_user_p
) = { "oscclk", "aclk_cam0_400", };
4634 PNAME(mout_aclk_cam0_552_user_p
) = { "oscclk", "aclk_cam0_552", };
4636 PNAME(mout_phyclk_rxbyteclkhs0_s4_user_p
) = { "oscclk",
4637 "phyclk_rxbyteclkhs0_s4_phy", };
4638 PNAME(mout_phyclk_rxbyteclkhs0_s2a_user_p
) = { "oscclk",
4639 "phyclk_rxbyteclkhs0_s2a_phy", };
4641 PNAME(mout_aclk_lite_d_b_p
) = { "mout_aclk_lite_d_a",
4642 "mout_aclk_cam0_333_user", };
4643 PNAME(mout_aclk_lite_d_a_p
) = { "mout_aclk_cam0_552_user",
4644 "mout_aclk_cam0_400_user", };
4645 PNAME(mout_aclk_lite_b_b_p
) = { "mout_aclk_lite_b_a",
4646 "mout_aclk_cam0_333_user", };
4647 PNAME(mout_aclk_lite_b_a_p
) = { "mout_aclk_cam0_552_user",
4648 "mout_aclk_cam0_400_user", };
4649 PNAME(mout_aclk_lite_a_b_p
) = { "mout_aclk_lite_a_a",
4650 "mout_aclk_cam0_333_user", };
4651 PNAME(mout_aclk_lite_a_a_p
) = { "mout_aclk_cam0_552_user",
4652 "mout_aclk_cam0_400_user", };
4653 PNAME(mout_aclk_cam0_400_p
) = { "mout_aclk_cam0_400_user",
4654 "mout_aclk_cam0_333_user", };
4656 PNAME(mout_aclk_csis1_b_p
) = { "mout_aclk_csis1_a",
4657 "mout_aclk_cam0_333_user" };
4658 PNAME(mout_aclk_csis1_a_p
) = { "mout_aclk_cam0_552_user",
4659 "mout_aclk_cam0_400_user", };
4660 PNAME(mout_aclk_csis0_b_p
) = { "mout_aclk_csis0_a",
4661 "mout_aclk_cam0_333_user", };
4662 PNAME(mout_aclk_csis0_a_p
) = { "mout_aclk_cam0_552_user",
4663 "mout_aclk-cam0_400_user", };
4664 PNAME(mout_aclk_3aa1_b_p
) = { "mout_aclk_3aa1_a",
4665 "mout_aclk_cam0_333_user", };
4666 PNAME(mout_aclk_3aa1_a_p
) = { "mout_aclk_cam0_552_user",
4667 "mout_aclk_cam0_400_user", };
4668 PNAME(mout_aclk_3aa0_b_p
) = { "mout_aclk_3aa0_a",
4669 "mout_aclk_cam0_333_user", };
4670 PNAME(mout_aclk_3aa0_a_p
) = { "mout_aclk_cam0_552_user",
4671 "mout_aclk_cam0_400_user", };
4673 PNAME(mout_sclk_lite_freecnt_c_p
) = { "mout_sclk_lite_freecnt_b",
4674 "div_pclk_lite_d", };
4675 PNAME(mout_sclk_lite_freecnt_b_p
) = { "mout_sclk_lite_freecnt_a",
4676 "div_pclk_pixelasync_lite_c", };
4677 PNAME(mout_sclk_lite_freecnt_a_p
) = { "div_pclk_lite_a",
4678 "div_pclk_lite_b", };
4679 PNAME(mout_sclk_pixelasync_lite_c_b_p
) = { "mout_sclk_pixelasync_lite_c_a",
4680 "mout_aclk_cam0_333_user", };
4681 PNAME(mout_sclk_pixelasync_lite_c_a_p
) = { "mout_aclk_cam0_552_user",
4682 "mout_aclk_cam0_400_user", };
4683 PNAME(mout_sclk_pixelasync_lite_c_init_b_p
) = {
4684 "mout_sclk_pixelasync_lite_c_init_a",
4685 "mout_aclk_cam0_400_user", };
4686 PNAME(mout_sclk_pixelasync_lite_c_init_a_p
) = {
4687 "mout_aclk_cam0_552_user",
4688 "mout_aclk_cam0_400_user", };
4690 static struct samsung_fixed_rate_clock cam0_fixed_clks
[] __initdata
= {
4691 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY
, "phyclk_rxbyteclkhs0_s4_phy",
4692 NULL
, CLK_IS_ROOT
, 100000000),
4693 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY
, "phyclk_rxbyteclkhs0_s2a_phy",
4694 NULL
, CLK_IS_ROOT
, 100000000),
4697 static struct samsung_mux_clock cam0_mux_clks
[] __initdata
= {
4699 MUX(CLK_MOUT_ACLK_CAM0_333_USER
, "mout_aclk_cam0_333_user",
4700 mout_aclk_cam0_333_user_p
, MUX_SEL_CAM00
, 8, 1),
4701 MUX(CLK_MOUT_ACLK_CAM0_400_USER
, "mout_aclk_cam0_400_user",
4702 mout_aclk_cam0_400_user_p
, MUX_SEL_CAM00
, 4, 1),
4703 MUX(CLK_MOUT_ACLK_CAM0_552_USER
, "mout_aclk_cam0_552_user",
4704 mout_aclk_cam0_552_user_p
, MUX_SEL_CAM00
, 0, 1),
4707 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER
,
4708 "mout_phyclk_rxbyteclkhs0_s4_user",
4709 mout_phyclk_rxbyteclkhs0_s4_user_p
,
4710 MUX_SEL_CAM01
, 4, 1),
4711 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER
,
4712 "mout_phyclk_rxbyteclkhs0_s2a_user",
4713 mout_phyclk_rxbyteclkhs0_s2a_user_p
,
4714 MUX_SEL_CAM01
, 0, 1),
4717 MUX(CLK_MOUT_ACLK_LITE_D_B
, "mout_aclk_lite_d_b", mout_aclk_lite_d_b_p
,
4718 MUX_SEL_CAM02
, 24, 1),
4719 MUX(CLK_MOUT_ACLK_LITE_D_A
, "mout_aclk_lite_d_a", mout_aclk_lite_d_a_p
,
4720 MUX_SEL_CAM02
, 20, 1),
4721 MUX(CLK_MOUT_ACLK_LITE_B_B
, "mout_aclk_lite_b_b", mout_aclk_lite_b_b_p
,
4722 MUX_SEL_CAM02
, 16, 1),
4723 MUX(CLK_MOUT_ACLK_LITE_B_A
, "mout_aclk_lite_b_a", mout_aclk_lite_b_a_p
,
4724 MUX_SEL_CAM02
, 12, 1),
4725 MUX(CLK_MOUT_ACLK_LITE_A_B
, "mout_aclk_lite_a_b", mout_aclk_lite_a_b_p
,
4726 MUX_SEL_CAM02
, 8, 1),
4727 MUX(CLK_MOUT_ACLK_LITE_A_A
, "mout_aclk_lite_a_a", mout_aclk_lite_a_a_p
,
4728 MUX_SEL_CAM02
, 4, 1),
4729 MUX(CLK_MOUT_ACLK_CAM0_400
, "mout_aclk_cam0_400", mout_aclk_cam0_400_p
,
4730 MUX_SEL_CAM02
, 0, 1),
4733 MUX(CLK_MOUT_ACLK_CSIS1_B
, "mout_aclk_csis1_b", mout_aclk_csis1_b_p
,
4734 MUX_SEL_CAM03
, 28, 1),
4735 MUX(CLK_MOUT_ACLK_CSIS1_A
, "mout_aclk_csis1_a", mout_aclk_csis1_a_p
,
4736 MUX_SEL_CAM03
, 24, 1),
4737 MUX(CLK_MOUT_ACLK_CSIS0_B
, "mout_aclk_csis0_b", mout_aclk_csis0_b_p
,
4738 MUX_SEL_CAM03
, 20, 1),
4739 MUX(CLK_MOUT_ACLK_CSIS0_A
, "mout_aclk_csis0_a", mout_aclk_csis0_a_p
,
4740 MUX_SEL_CAM03
, 16, 1),
4741 MUX(CLK_MOUT_ACLK_3AA1_B
, "mout_aclk_3aa1_b", mout_aclk_3aa1_b_p
,
4742 MUX_SEL_CAM03
, 12, 1),
4743 MUX(CLK_MOUT_ACLK_3AA1_A
, "mout_aclk_3aa1_a", mout_aclk_3aa1_a_p
,
4744 MUX_SEL_CAM03
, 8, 1),
4745 MUX(CLK_MOUT_ACLK_3AA0_B
, "mout_aclk_3aa0_b", mout_aclk_3aa0_b_p
,
4746 MUX_SEL_CAM03
, 4, 1),
4747 MUX(CLK_MOUT_ACLK_3AA0_A
, "mout_aclk_3aa0_a", mout_aclk_3aa0_a_p
,
4748 MUX_SEL_CAM03
, 0, 1),
4751 MUX(CLK_MOUT_SCLK_LITE_FREECNT_C
, "mout_sclk_lite_freecnt_c",
4752 mout_sclk_lite_freecnt_c_p
, MUX_SEL_CAM04
, 24, 1),
4753 MUX(CLK_MOUT_SCLK_LITE_FREECNT_B
, "mout_sclk_lite_freecnt_b",
4754 mout_sclk_lite_freecnt_b_p
, MUX_SEL_CAM04
, 24, 1),
4755 MUX(CLK_MOUT_SCLK_LITE_FREECNT_A
, "mout_sclk_lite_freecnt_a",
4756 mout_sclk_lite_freecnt_a_p
, MUX_SEL_CAM04
, 24, 1),
4757 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B
, "mout_sclk_pixelasync_lite_c_b",
4758 mout_sclk_pixelasync_lite_c_b_p
, MUX_SEL_CAM04
, 24, 1),
4759 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A
, "mout_sclk_pixelasync_lite_c_a",
4760 mout_sclk_pixelasync_lite_c_a_p
, MUX_SEL_CAM04
, 24, 1),
4761 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B
,
4762 "mout_sclk_pixelasync_lite_c_init_b",
4763 mout_sclk_pixelasync_lite_c_init_b_p
,
4764 MUX_SEL_CAM04
, 24, 1),
4765 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A
,
4766 "mout_sclk_pixelasync_lite_c_init_a",
4767 mout_sclk_pixelasync_lite_c_init_a_p
,
4768 MUX_SEL_CAM04
, 24, 1),
4771 static struct samsung_div_clock cam0_div_clks
[] __initdata
= {
4773 DIV(CLK_DIV_PCLK_CAM0_50
, "div_pclk_cam0_50", "div_aclk_cam0_200",
4775 DIV(CLK_DIV_ACLK_CAM0_200
, "div_aclk_cam0_200", "mout_aclk_cam0_400",
4777 DIV(CLK_DIV_ACLK_CAM0_BUS_400
, "div_aclk_cam0_bus_400",
4778 "mout_aclk_cam0_400", DIV_CAM00
, 0, 3),
4781 DIV(CLK_DIV_PCLK_LITE_D
, "div_pclk_lite_d", "div_aclk_lite_d",
4783 DIV(CLK_DIV_ACLK_LITE_D
, "div_aclk_lite_d", "mout_aclk_lite_d_b",
4785 DIV(CLK_DIV_PCLK_LITE_B
, "div_pclk_lite_b", "div_aclk_lite_b",
4787 DIV(CLK_DIV_ACLK_LITE_B
, "div_aclk_lite_b", "mout_aclk_lite_b_b",
4789 DIV(CLK_DIV_PCLK_LITE_A
, "div_pclk_lite_a", "div_aclk_lite_a",
4791 DIV(CLK_DIV_ACLK_LITE_A
, "div_aclk_lite_a", "mout_aclk_lite_a_b",
4795 DIV(CLK_DIV_ACLK_CSIS1
, "div_aclk_csis1", "mout_aclk_csis1_b",
4797 DIV(CLK_DIV_ACLK_CSIS0
, "div_aclk_csis0", "mout_aclk_csis0_b",
4799 DIV(CLK_DIV_PCLK_3AA1
, "div_pclk_3aa1", "div_aclk_3aa1",
4801 DIV(CLK_DIV_ACLK_3AA1
, "div_aclk_3aa1", "mout_aclk_3aa1_b",
4803 DIV(CLK_DIV_PCLK_3AA0
, "div_pclk_3aa0", "div_aclk_3aa0",
4805 DIV(CLK_DIV_ACLK_3AA0
, "div_aclk_3aa0", "mout_aclk_3aa0_b",
4809 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C
, "div_sclk_pixelasync_lite_c",
4810 "mout_sclk_pixelasync_lite_c_b", DIV_CAM03
, 8, 3),
4811 DIV(CLK_DIV_PCLK_PIXELASYNC_LITE_C
, "div_pclk_pixelasync_lite_c",
4812 "div_sclk_pixelasync_lite_c_init", DIV_CAM03
, 4, 2),
4813 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT
,
4814 "div_sclk_pixelasync_lite_c_init",
4815 "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03
, 0, 3),
4818 static struct samsung_gate_clock cam0_gate_clks
[] __initdata
= {
4819 /* ENABLE_ACLK_CAM00 */
4820 GATE(CLK_ACLK_CSIS1
, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00
,
4822 GATE(CLK_ACLK_CSIS0
, "aclk_csis0", "div_aclk_csis0", ENABLE_ACLK_CAM00
,
4824 GATE(CLK_ACLK_3AA1
, "aclk_3aa1", "div_aclk_3aa1", ENABLE_ACLK_CAM00
,
4826 GATE(CLK_ACLK_3AA0
, "aclk_3aa0", "div_aclk_3aa0", ENABLE_ACLK_CAM00
,
4828 GATE(CLK_ACLK_LITE_D
, "aclk_lite_d", "div_aclk_lite_d",
4829 ENABLE_ACLK_CAM00
, 2, 0, 0),
4830 GATE(CLK_ACLK_LITE_B
, "aclk_lite_b", "div_aclk_lite_b",
4831 ENABLE_ACLK_CAM00
, 1, 0, 0),
4832 GATE(CLK_ACLK_LITE_A
, "aclk_lite_a", "div_aclk_lite_a",
4833 ENABLE_ACLK_CAM00
, 0, 0, 0),
4835 /* ENABLE_ACLK_CAM01 */
4836 GATE(CLK_ACLK_AHBSYNCDN
, "aclk_ahbsyncdn", "div_aclk_cam0_200",
4837 ENABLE_ACLK_CAM01
, 31, CLK_IGNORE_UNUSED
, 0),
4838 GATE(CLK_ACLK_AXIUS_LITE_D
, "aclk_axius_lite_d", "div_aclk_cam0_bus_400",
4839 ENABLE_ACLK_CAM01
, 30, CLK_IGNORE_UNUSED
, 0),
4840 GATE(CLK_ACLK_AXIUS_LITE_B
, "aclk_axius_lite_b", "div_aclk_cam0_bus_400",
4841 ENABLE_ACLK_CAM01
, 29, CLK_IGNORE_UNUSED
, 0),
4842 GATE(CLK_ACLK_AXIUS_LITE_A
, "aclk_axius_lite_a", "div_aclk_cam0_bus_400",
4843 ENABLE_ACLK_CAM01
, 28, CLK_IGNORE_UNUSED
, 0),
4844 GATE(CLK_ACLK_ASYNCAPBM_3AA1
, "aclk_asyncapbm_3aa1", "div_pclk_3aa1",
4845 ENABLE_ACLK_CAM01
, 27, CLK_IGNORE_UNUSED
, 0),
4846 GATE(CLK_ACLK_ASYNCAPBS_3AA1
, "aclk_asyncapbs_3aa1", "div_aclk_3aa1",
4847 ENABLE_ACLK_CAM01
, 26, CLK_IGNORE_UNUSED
, 0),
4848 GATE(CLK_ACLK_ASYNCAPBM_3AA0
, "aclk_asyncapbm_3aa0", "div_pclk_3aa0",
4849 ENABLE_ACLK_CAM01
, 25, CLK_IGNORE_UNUSED
, 0),
4850 GATE(CLK_ACLK_ASYNCAPBS_3AA0
, "aclk_asyncapbs_3aa0", "div_aclk_3aa0",
4851 ENABLE_ACLK_CAM01
, 24, CLK_IGNORE_UNUSED
, 0),
4852 GATE(CLK_ACLK_ASYNCAPBM_LITE_D
, "aclk_asyncapbm_lite_d",
4853 "div_pclk_lite_d", ENABLE_ACLK_CAM01
,
4854 23, CLK_IGNORE_UNUSED
, 0),
4855 GATE(CLK_ACLK_ASYNCAPBS_LITE_D
, "aclk_asyncapbs_lite_d",
4856 "div_aclk_cam0_200", ENABLE_ACLK_CAM01
,
4857 22, CLK_IGNORE_UNUSED
, 0),
4858 GATE(CLK_ACLK_ASYNCAPBM_LITE_B
, "aclk_asyncapbm_lite_b",
4859 "div_pclk_lite_b", ENABLE_ACLK_CAM01
,
4860 21, CLK_IGNORE_UNUSED
, 0),
4861 GATE(CLK_ACLK_ASYNCAPBS_LITE_B
, "aclk_asyncapbs_lite_b",
4862 "div_aclk_cam0_200", ENABLE_ACLK_CAM01
,
4863 20, CLK_IGNORE_UNUSED
, 0),
4864 GATE(CLK_ACLK_ASYNCAPBM_LITE_A
, "aclk_asyncapbm_lite_a",
4865 "div_pclk_lite_a", ENABLE_ACLK_CAM01
,
4866 19, CLK_IGNORE_UNUSED
, 0),
4867 GATE(CLK_ACLK_ASYNCAPBS_LITE_A
, "aclk_asyncapbs_lite_a",
4868 "div_aclk_cam0_200", ENABLE_ACLK_CAM01
,
4869 18, CLK_IGNORE_UNUSED
, 0),
4870 GATE(CLK_ACLK_ASYNCAXIM_ISP0P
, "aclk_asyncaxim_isp0p",
4871 "div_aclk_cam0_200", ENABLE_ACLK_CAM01
,
4872 17, CLK_IGNORE_UNUSED
, 0),
4873 GATE(CLK_ACLK_ASYNCAXIM_3AA1
, "aclk_asyncaxim_3aa1",
4874 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01
,
4875 16, CLK_IGNORE_UNUSED
, 0),
4876 GATE(CLK_ACLK_ASYNCAXIS_3AA1
, "aclk_asyncaxis_3aa1",
4877 "div_aclk_3aa1", ENABLE_ACLK_CAM01
,
4878 15, CLK_IGNORE_UNUSED
, 0),
4879 GATE(CLK_ACLK_ASYNCAXIM_3AA0
, "aclk_asyncaxim_3aa0",
4880 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01
,
4881 14, CLK_IGNORE_UNUSED
, 0),
4882 GATE(CLK_ACLK_ASYNCAXIS_3AA0
, "aclk_asyncaxis_3aa0",
4883 "div_aclk_3aa0", ENABLE_ACLK_CAM01
,
4884 13, CLK_IGNORE_UNUSED
, 0),
4885 GATE(CLK_ACLK_ASYNCAXIM_LITE_D
, "aclk_asyncaxim_lite_d",
4886 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01
,
4887 12, CLK_IGNORE_UNUSED
, 0),
4888 GATE(CLK_ACLK_ASYNCAXIS_LITE_D
, "aclk_asyncaxis_lite_d",
4889 "div_aclk_lite_d", ENABLE_ACLK_CAM01
,
4890 11, CLK_IGNORE_UNUSED
, 0),
4891 GATE(CLK_ACLK_ASYNCAXIM_LITE_B
, "aclk_asyncaxim_lite_b",
4892 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01
,
4893 10, CLK_IGNORE_UNUSED
, 0),
4894 GATE(CLK_ACLK_ASYNCAXIS_LITE_B
, "aclk_asyncaxis_lite_b",
4895 "div_aclk_lite_b", ENABLE_ACLK_CAM01
,
4896 9, CLK_IGNORE_UNUSED
, 0),
4897 GATE(CLK_ACLK_ASYNCAXIM_LITE_A
, "aclk_asyncaxim_lite_a",
4898 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01
,
4899 8, CLK_IGNORE_UNUSED
, 0),
4900 GATE(CLK_ACLK_ASYNCAXIS_LITE_A
, "aclk_asyncaxis_lite_a",
4901 "div_aclk_lite_a", ENABLE_ACLK_CAM01
,
4902 7, CLK_IGNORE_UNUSED
, 0),
4903 GATE(CLK_ACLK_AHB2APB_ISPSFRP
, "aclk_ahb2apb_ispsfrp",
4904 "div_pclk_cam0_50", ENABLE_ACLK_CAM01
,
4905 6, CLK_IGNORE_UNUSED
, 0),
4906 GATE(CLK_ACLK_AXI2APB_ISP0P
, "aclk_axi2apb_isp0p", "div_aclk_cam0_200",
4907 ENABLE_ACLK_CAM01
, 5, CLK_IGNORE_UNUSED
, 0),
4908 GATE(CLK_ACLK_AXI2AHB_ISP0P
, "aclk_axi2ahb_isp0p", "div_aclk_cam0_200",
4909 ENABLE_ACLK_CAM01
, 4, CLK_IGNORE_UNUSED
, 0),
4910 GATE(CLK_ACLK_XIU_IS0X
, "aclk_xiu_is0x", "div_aclk_cam0_200",
4911 ENABLE_ACLK_CAM01
, 3, CLK_IGNORE_UNUSED
, 0),
4912 GATE(CLK_ACLK_XIU_ISP0EX
, "aclk_xiu_isp0ex", "div_aclk_cam0_bus_400",
4913 ENABLE_ACLK_CAM01
, 2, CLK_IGNORE_UNUSED
, 0),
4914 GATE(CLK_ACLK_CAM0NP_276
, "aclk_cam0np_276", "div_aclk_cam0_200",
4915 ENABLE_ACLK_CAM01
, 1, CLK_IGNORE_UNUSED
, 0),
4916 GATE(CLK_ACLK_CAM0ND_400
, "aclk_cam0nd_400", "div_aclk_cam0_bus_400",
4917 ENABLE_ACLK_CAM01
, 0, CLK_IGNORE_UNUSED
, 0),
4919 /* ENABLE_ACLK_CAM02 */
4920 GATE(CLK_ACLK_SMMU_3AA1
, "aclk_smmu_3aa1", "div_aclk_cam0_bus_400",
4921 ENABLE_ACLK_CAM02
, 9, CLK_IGNORE_UNUSED
, 0),
4922 GATE(CLK_ACLK_SMMU_3AA0
, "aclk_smmu_3aa0", "div_aclk_cam0_bus_400",
4923 ENABLE_ACLK_CAM02
, 8, CLK_IGNORE_UNUSED
, 0),
4924 GATE(CLK_ACLK_SMMU_LITE_D
, "aclk_smmu_lite_d", "div_aclk_cam0_bus_400",
4925 ENABLE_ACLK_CAM02
, 7, CLK_IGNORE_UNUSED
, 0),
4926 GATE(CLK_ACLK_SMMU_LITE_B
, "aclk_smmu_lite_b", "div_aclk_cam0_bus_400",
4927 ENABLE_ACLK_CAM02
, 6, CLK_IGNORE_UNUSED
, 0),
4928 GATE(CLK_ACLK_SMMU_LITE_A
, "aclk_smmu_lite_a", "div_aclk_cam0_bus_400",
4929 ENABLE_ACLK_CAM02
, 5, CLK_IGNORE_UNUSED
, 0),
4930 GATE(CLK_ACLK_BTS_3AA1
, "aclk_bts_3aa1", "div_aclk_cam0_bus_400",
4931 ENABLE_ACLK_CAM02
, 4, CLK_IGNORE_UNUSED
, 0),
4932 GATE(CLK_ACLK_BTS_3AA0
, "aclk_bts_3aa0", "div_aclk_cam0_bus_400",
4933 ENABLE_ACLK_CAM02
, 3, CLK_IGNORE_UNUSED
, 0),
4934 GATE(CLK_ACLK_BTS_LITE_D
, "aclk_bts_lite_d", "div_aclk_cam0_bus_400",
4935 ENABLE_ACLK_CAM02
, 2, CLK_IGNORE_UNUSED
, 0),
4936 GATE(CLK_ACLK_BTS_LITE_B
, "aclk_bts_lite_b", "div_aclk_cam0_bus_400",
4937 ENABLE_ACLK_CAM02
, 1, CLK_IGNORE_UNUSED
, 0),
4938 GATE(CLK_ACLK_BTS_LITE_A
, "aclk_bts_lite_a", "div_aclk_cam0_bus_400",
4939 ENABLE_ACLK_CAM02
, 0, CLK_IGNORE_UNUSED
, 0),
4941 /* ENABLE_PCLK_CAM0 */
4942 GATE(CLK_PCLK_SMMU_3AA1
, "pclk_smmu_3aa1", "div_aclk_cam0_200",
4943 ENABLE_PCLK_CAM0
, 25, CLK_IGNORE_UNUSED
, 0),
4944 GATE(CLK_PCLK_SMMU_3AA0
, "pclk_smmu_3aa0", "div_aclk_cam0_200",
4945 ENABLE_PCLK_CAM0
, 24, CLK_IGNORE_UNUSED
, 0),
4946 GATE(CLK_PCLK_SMMU_LITE_D
, "pclk_smmu_lite_d", "div_aclk_cam0_200",
4947 ENABLE_PCLK_CAM0
, 23, CLK_IGNORE_UNUSED
, 0),
4948 GATE(CLK_PCLK_SMMU_LITE_B
, "pclk_smmu_lite_b", "div_aclk_cam0_200",
4949 ENABLE_PCLK_CAM0
, 22, CLK_IGNORE_UNUSED
, 0),
4950 GATE(CLK_PCLK_SMMU_LITE_A
, "pclk_smmu_lite_a", "div_aclk_cam0_200",
4951 ENABLE_PCLK_CAM0
, 21, CLK_IGNORE_UNUSED
, 0),
4952 GATE(CLK_PCLK_BTS_3AA1
, "pclk_bts_3aa1", "div_pclk_cam0_50",
4953 ENABLE_PCLK_CAM0
, 20, CLK_IGNORE_UNUSED
, 0),
4954 GATE(CLK_PCLK_BTS_3AA0
, "pclk_bts_3aa0", "div_pclk_cam0_50",
4955 ENABLE_PCLK_CAM0
, 19, CLK_IGNORE_UNUSED
, 0),
4956 GATE(CLK_PCLK_BTS_LITE_D
, "pclk_bts_lite_d", "div_pclk_cam0_50",
4957 ENABLE_PCLK_CAM0
, 18, CLK_IGNORE_UNUSED
, 0),
4958 GATE(CLK_PCLK_BTS_LITE_B
, "pclk_bts_lite_b", "div_pclk_cam0_50",
4959 ENABLE_PCLK_CAM0
, 17, CLK_IGNORE_UNUSED
, 0),
4960 GATE(CLK_PCLK_BTS_LITE_A
, "pclk_bts_lite_a", "div_pclk_cam0_50",
4961 ENABLE_PCLK_CAM0
, 16, CLK_IGNORE_UNUSED
, 0),
4962 GATE(CLK_PCLK_ASYNCAXI_CAM1
, "pclk_asyncaxi_cam1", "div_pclk_cam0_50",
4963 ENABLE_PCLK_CAM0
, 15, CLK_IGNORE_UNUSED
, 0),
4964 GATE(CLK_PCLK_ASYNCAXI_3AA1
, "pclk_asyncaxi_3aa1", "div_pclk_cam0_50",
4965 ENABLE_PCLK_CAM0
, 14, CLK_IGNORE_UNUSED
, 0),
4966 GATE(CLK_PCLK_ASYNCAXI_3AA0
, "pclk_asyncaxi_3aa0", "div_pclk_cam0_50",
4967 ENABLE_PCLK_CAM0
, 13, CLK_IGNORE_UNUSED
, 0),
4968 GATE(CLK_PCLK_ASYNCAXI_LITE_D
, "pclk_asyncaxi_lite_d",
4969 "div_pclk_cam0_50", ENABLE_PCLK_CAM0
,
4970 12, CLK_IGNORE_UNUSED
, 0),
4971 GATE(CLK_PCLK_ASYNCAXI_LITE_B
, "pclk_asyncaxi_lite_b",
4972 "div_pclk_cam0_50", ENABLE_PCLK_CAM0
,
4973 11, CLK_IGNORE_UNUSED
, 0),
4974 GATE(CLK_PCLK_ASYNCAXI_LITE_A
, "pclk_asyncaxi_lite_a",
4975 "div_pclk_cam0_50", ENABLE_PCLK_CAM0
,
4976 10, CLK_IGNORE_UNUSED
, 0),
4977 GATE(CLK_PCLK_PMU_CAM0
, "pclk_pmu_cam0", "div_pclk_cam0_50",
4978 ENABLE_PCLK_CAM0
, 9, CLK_IGNORE_UNUSED
, 0),
4979 GATE(CLK_PCLK_SYSREG_CAM0
, "pclk_sysreg_cam0", "div_pclk_cam0_50",
4980 ENABLE_PCLK_CAM0
, 8, CLK_IGNORE_UNUSED
, 0),
4981 GATE(CLK_PCLK_CMU_CAM0_LOCAL
, "pclk_cmu_cam0_local",
4982 "div_aclk_cam0_200", ENABLE_PCLK_CAM0
,
4983 7, CLK_IGNORE_UNUSED
, 0),
4984 GATE(CLK_PCLK_CSIS1
, "pclk_csis1", "div_aclk_cam0_200",
4985 ENABLE_PCLK_CAM0
, 6, CLK_IGNORE_UNUSED
, 0),
4986 GATE(CLK_PCLK_CSIS0
, "pclk_csis0", "div_aclk_cam0_200",
4987 ENABLE_PCLK_CAM0
, 5, CLK_IGNORE_UNUSED
, 0),
4988 GATE(CLK_PCLK_3AA1
, "pclk_3aa1", "div_pclk_3aa1",
4989 ENABLE_PCLK_CAM0
, 4, CLK_IGNORE_UNUSED
, 0),
4990 GATE(CLK_PCLK_3AA0
, "pclk_3aa0", "div_pclk_3aa0",
4991 ENABLE_PCLK_CAM0
, 3, CLK_IGNORE_UNUSED
, 0),
4992 GATE(CLK_PCLK_LITE_D
, "pclk_lite_d", "div_pclk_lite_d",
4993 ENABLE_PCLK_CAM0
, 2, CLK_IGNORE_UNUSED
, 0),
4994 GATE(CLK_PCLK_LITE_B
, "pclk_lite_b", "div_pclk_lite_b",
4995 ENABLE_PCLK_CAM0
, 1, CLK_IGNORE_UNUSED
, 0),
4996 GATE(CLK_PCLK_LITE_A
, "pclk_lite_a", "div_pclk_lite_a",
4997 ENABLE_PCLK_CAM0
, 0, CLK_IGNORE_UNUSED
, 0),
4999 /* ENABLE_SCLK_CAM0 */
5000 GATE(CLK_PHYCLK_RXBYTECLKHS0_S4
, "phyclk_rxbyteclkhs0_s4",
5001 "mout_phyclk_rxbyteclkhs0_s4_user",
5002 ENABLE_SCLK_CAM0
, 8, 0, 0),
5003 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2A
, "phyclk_rxbyteclkhs0_s2a",
5004 "mout_phyclk_rxbyteclkhs0_s2a_user",
5005 ENABLE_SCLK_CAM0
, 7, 0, 0),
5006 GATE(CLK_SCLK_LITE_FREECNT
, "sclk_lite_freecnt",
5007 "mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0
, 6, 0, 0),
5008 GATE(CLK_SCLK_PIXELASYNCM_3AA1
, "sclk_pixelasycm_3aa1",
5009 "div_aclk_3aa1", ENABLE_SCLK_CAM0
, 5, 0, 0),
5010 GATE(CLK_SCLK_PIXELASYNCM_3AA0
, "sclk_pixelasycm_3aa0",
5011 "div_aclk_3aa0", ENABLE_SCLK_CAM0
, 4, 0, 0),
5012 GATE(CLK_SCLK_PIXELASYNCS_3AA0
, "sclk_pixelasycs_3aa0",
5013 "div_aclk_3aa0", ENABLE_SCLK_CAM0
, 3, 0, 0),
5014 GATE(CLK_SCLK_PIXELASYNCM_LITE_C
, "sclk_pixelasyncm_lite_c",
5015 "div_sclk_pixelasync_lite_c",
5016 ENABLE_SCLK_CAM0
, 2, 0, 0),
5017 GATE(CLK_SCLK_PIXELASYNCM_LITE_C_INIT
, "sclk_pixelasyncm_lite_c_init",
5018 "div_sclk_pixelasync_lite_c_init",
5019 ENABLE_SCLK_CAM0
, 1, 0, 0),
5020 GATE(CLK_SCLK_PIXELASYNCS_LITE_C_INIT
, "sclk_pixelasyncs_lite_c_init",
5021 "div_sclk_pixelasync_lite_c",
5022 ENABLE_SCLK_CAM0
, 0, 0, 0),
5025 static struct samsung_cmu_info cam0_cmu_info __initdata
= {
5026 .mux_clks
= cam0_mux_clks
,
5027 .nr_mux_clks
= ARRAY_SIZE(cam0_mux_clks
),
5028 .div_clks
= cam0_div_clks
,
5029 .nr_div_clks
= ARRAY_SIZE(cam0_div_clks
),
5030 .gate_clks
= cam0_gate_clks
,
5031 .nr_gate_clks
= ARRAY_SIZE(cam0_gate_clks
),
5032 .fixed_clks
= cam0_fixed_clks
,
5033 .nr_fixed_clks
= ARRAY_SIZE(cam0_fixed_clks
),
5034 .nr_clk_ids
= CAM0_NR_CLK
,
5035 .clk_regs
= cam0_clk_regs
,
5036 .nr_clk_regs
= ARRAY_SIZE(cam0_clk_regs
),
5039 static void __init
exynos5433_cmu_cam0_init(struct device_node
*np
)
5041 samsung_cmu_register_one(np
, &cam0_cmu_info
);
5043 CLK_OF_DECLARE(exynos5433_cmu_cam0
, "samsung,exynos5433-cmu-cam0",
5044 exynos5433_cmu_cam0_init
);
5047 * Register offset definitions for CMU_CAM1
5049 #define MUX_SEL_CAM10 0x0200
5050 #define MUX_SEL_CAM11 0x0204
5051 #define MUX_SEL_CAM12 0x0208
5052 #define MUX_ENABLE_CAM10 0x0300
5053 #define MUX_ENABLE_CAM11 0x0304
5054 #define MUX_ENABLE_CAM12 0x0308
5055 #define MUX_STAT_CAM10 0x0400
5056 #define MUX_STAT_CAM11 0x0404
5057 #define MUX_STAT_CAM12 0x0408
5058 #define MUX_IGNORE_CAM11 0x0504
5059 #define DIV_CAM10 0x0600
5060 #define DIV_CAM11 0x0604
5061 #define DIV_STAT_CAM10 0x0700
5062 #define DIV_STAT_CAM11 0x0704
5063 #define ENABLE_ACLK_CAM10 0X0800
5064 #define ENABLE_ACLK_CAM11 0X0804
5065 #define ENABLE_ACLK_CAM12 0X0808
5066 #define ENABLE_PCLK_CAM1 0X0900
5067 #define ENABLE_SCLK_CAM1 0X0a00
5068 #define ENABLE_IP_CAM10 0X0b00
5069 #define ENABLE_IP_CAM11 0X0b04
5070 #define ENABLE_IP_CAM12 0X0b08
5072 static unsigned long cam1_clk_regs
[] __initdata
= {
5097 PNAME(mout_sclk_isp_uart_user_p
) = { "oscclk", "sclk_isp_uart_cam1", };
5098 PNAME(mout_sclk_isp_spi1_user_p
) = { "oscclk", "sclk_isp_spi1_cam1", };
5099 PNAME(mout_sclk_isp_spi0_user_p
) = { "oscclk", "sclk_isp_spi0_cam1", };
5101 PNAME(mout_aclk_cam1_333_user_p
) = { "oscclk", "aclk_cam1_333", };
5102 PNAME(mout_aclk_cam1_400_user_p
) = { "oscclk", "aclk_cam1_400", };
5103 PNAME(mout_aclk_cam1_552_user_p
) = { "oscclk", "aclk_cam1_552", };
5105 PNAME(mout_phyclk_rxbyteclkhs0_s2b_user_p
) = { "oscclk",
5106 "phyclk_rxbyteclkhs0_s2b_phy", };
5108 PNAME(mout_aclk_csis2_b_p
) = { "mout_aclk_csis2_a",
5109 "mout_aclk_cam1_333_user", };
5110 PNAME(mout_aclk_csis2_a_p
) = { "mout_aclk_cam1_552_user",
5111 "mout_aclk_cam1_400_user", };
5113 PNAME(mout_aclk_fd_b_p
) = { "mout_aclk_fd_a",
5114 "mout_aclk_cam1_333_user", };
5115 PNAME(mout_aclk_fd_a_p
) = { "mout_aclk_cam1_552_user",
5116 "mout_aclk_cam1_400_user", };
5118 PNAME(mout_aclk_lite_c_b_p
) = { "mout_aclk_lite_c_a",
5119 "mout_aclk_cam1_333_user", };
5120 PNAME(mout_aclk_lite_c_a_p
) = { "mout_aclk_cam1_552_user",
5121 "mout_aclk_cam1_400_user", };
5123 static struct samsung_fixed_rate_clock cam1_fixed_clks
[] __initdata
= {
5124 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B
, "phyclk_rxbyteclkhs0_s2b_phy", NULL
,
5125 CLK_IS_ROOT
, 100000000),
5128 static struct samsung_mux_clock cam1_mux_clks
[] __initdata
= {
5130 MUX(CLK_MOUT_SCLK_ISP_UART_USER
, "mout_sclk_isp_uart_user",
5131 mout_sclk_isp_uart_user_p
, MUX_SEL_CAM10
, 20, 1),
5132 MUX(CLK_MOUT_SCLK_ISP_SPI1_USER
, "mout_sclk_isp_spi1_user",
5133 mout_sclk_isp_spi1_user_p
, MUX_SEL_CAM10
, 16, 1),
5134 MUX(CLK_MOUT_SCLK_ISP_SPI0_USER
, "mout_sclk_isp_spi0_user",
5135 mout_sclk_isp_spi0_user_p
, MUX_SEL_CAM10
, 12, 1),
5136 MUX(CLK_MOUT_ACLK_CAM1_333_USER
, "mout_aclk_cam1_333_user",
5137 mout_aclk_cam1_333_user_p
, MUX_SEL_CAM10
, 8, 1),
5138 MUX(CLK_MOUT_ACLK_CAM1_400_USER
, "mout_aclk_cam1_400_user",
5139 mout_aclk_cam1_400_user_p
, MUX_SEL_CAM01
, 4, 1),
5140 MUX(CLK_MOUT_ACLK_CAM1_552_USER
, "mout_aclk_cam1_552_user",
5141 mout_aclk_cam1_552_user_p
, MUX_SEL_CAM01
, 0, 1),
5144 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER
,
5145 "mout_phyclk_rxbyteclkhs0_s2b_user",
5146 mout_phyclk_rxbyteclkhs0_s2b_user_p
,
5147 MUX_SEL_CAM11
, 0, 1),
5150 MUX(CLK_MOUT_ACLK_CSIS2_B
, "mout_aclk_csis2_b", mout_aclk_csis2_b_p
,
5151 MUX_SEL_CAM12
, 20, 1),
5152 MUX(CLK_MOUT_ACLK_CSIS2_A
, "mout_aclk_csis2_a", mout_aclk_csis2_a_p
,
5153 MUX_SEL_CAM12
, 16, 1),
5154 MUX(CLK_MOUT_ACLK_FD_B
, "mout_aclk_fd_b", mout_aclk_fd_b_p
,
5155 MUX_SEL_CAM12
, 12, 1),
5156 MUX(CLK_MOUT_ACLK_FD_A
, "mout_aclk_fd_a", mout_aclk_fd_a_p
,
5157 MUX_SEL_CAM12
, 8, 1),
5158 MUX(CLK_MOUT_ACLK_LITE_C_B
, "mout_aclk_lite_c_b", mout_aclk_lite_c_b_p
,
5159 MUX_SEL_CAM12
, 4, 1),
5160 MUX(CLK_MOUT_ACLK_LITE_C_A
, "mout_aclk_lite_c_a", mout_aclk_lite_c_a_p
,
5161 MUX_SEL_CAM12
, 0, 1),
5164 static struct samsung_div_clock cam1_div_clks
[] __initdata
= {
5166 DIV(CLK_DIV_SCLK_ISP_WPWM
, "div_sclk_isp_wpwm",
5167 "div_pclk_cam1_83", DIV_CAM10
, 16, 2),
5168 DIV(CLK_DIV_PCLK_CAM1_83
, "div_pclk_cam1_83",
5169 "mout_aclk_cam1_333_user", DIV_CAM10
, 12, 2),
5170 DIV(CLK_DIV_PCLK_CAM1_166
, "div_pclk_cam1_166",
5171 "mout_aclk_cam1_333_user", DIV_CAM10
, 8, 2),
5172 DIV(CLK_DIV_PCLK_DBG_CAM1
, "div_pclk_dbg_cam1",
5173 "mout_aclk_cam1_552_user", DIV_CAM10
, 4, 3),
5174 DIV(CLK_DIV_ATCLK_CAM1
, "div_atclk_cam1", "mout_aclk_cam1_552_user",
5178 DIV(CLK_DIV_ACLK_CSIS2
, "div_aclk_csis2", "mout_aclk_csis2_b",
5180 DIV(CLK_DIV_PCLK_FD
, "div_pclk_fd", "div_aclk_fd", DIV_CAM11
, 12, 2),
5181 DIV(CLK_DIV_ACLK_FD
, "div_aclk_fd", "mout_aclk_fd_b", DIV_CAM11
, 8, 3),
5182 DIV(CLK_DIV_PCLK_LITE_C
, "div_pclk_lite_c", "div_aclk_lite_c",
5184 DIV(CLK_DIV_ACLK_LITE_C
, "div_aclk_lite_c", "mout_aclk_lite_c_b",
5188 static struct samsung_gate_clock cam1_gate_clks
[] __initdata
= {
5189 /* ENABLE_ACLK_CAM10 */
5190 GATE(CLK_ACLK_ISP_GIC
, "aclk_isp_gic", "mout_aclk_cam1_333_user",
5191 ENABLE_ACLK_CAM10
, 4, 0, 0),
5192 GATE(CLK_ACLK_FD
, "aclk_fd", "div_aclk_fd",
5193 ENABLE_ACLK_CAM10
, 3, 0, 0),
5194 GATE(CLK_ACLK_LITE_C
, "aclk_lite_c", "div_aclk_lite_c",
5195 ENABLE_ACLK_CAM10
, 1, 0, 0),
5196 GATE(CLK_ACLK_CSIS2
, "aclk_csis2", "div_aclk_csis2",
5197 ENABLE_ACLK_CAM10
, 0, 0, 0),
5199 /* ENABLE_ACLK_CAM11 */
5200 GATE(CLK_ACLK_ASYNCAPBM_FD
, "aclk_asyncapbm_fd", "div_pclk_fd",
5201 ENABLE_ACLK_CAM11
, 29, CLK_IGNORE_UNUSED
, 0),
5202 GATE(CLK_ACLK_ASYNCAPBS_FD
, "aclk_asyncapbs_fd", "div_pclk_cam1_166",
5203 ENABLE_ACLK_CAM11
, 28, CLK_IGNORE_UNUSED
, 0),
5204 GATE(CLK_ACLK_ASYNCAPBM_LITE_C
, "aclk_asyncapbm_lite_c",
5205 "div_pclk_lite_c", ENABLE_ACLK_CAM11
,
5206 27, CLK_IGNORE_UNUSED
, 0),
5207 GATE(CLK_ACLK_ASYNCAPBS_LITE_C
, "aclk_asyncapbs_lite_c",
5208 "div_pclk_cam1_166", ENABLE_ACLK_CAM11
,
5209 26, CLK_IGNORE_UNUSED
, 0),
5210 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H2
, "aclk_asyncahbs_sfrisp2h2",
5211 "div_pclk_cam1_83", ENABLE_ACLK_CAM11
,
5212 25, CLK_IGNORE_UNUSED
, 0),
5213 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H1
, "aclk_asyncahbs_sfrisp2h1",
5214 "div_pclk_cam1_83", ENABLE_ACLK_CAM11
,
5215 24, CLK_IGNORE_UNUSED
, 0),
5216 GATE(CLK_ACLK_ASYNCAXIM_CA5
, "aclk_asyncaxim_ca5",
5217 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11
,
5218 23, CLK_IGNORE_UNUSED
, 0),
5219 GATE(CLK_ACLK_ASYNCAXIS_CA5
, "aclk_asyncaxis_ca5",
5220 "mout_aclk_cam1_552_user", ENABLE_ACLK_CAM11
,
5221 22, CLK_IGNORE_UNUSED
, 0),
5222 GATE(CLK_ACLK_ASYNCAXIS_ISPX2
, "aclk_asyncaxis_ispx2",
5223 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11
,
5224 21, CLK_IGNORE_UNUSED
, 0),
5225 GATE(CLK_ACLK_ASYNCAXIS_ISPX1
, "aclk_asyncaxis_ispx1",
5226 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11
,
5227 20, CLK_IGNORE_UNUSED
, 0),
5228 GATE(CLK_ACLK_ASYNCAXIS_ISPX0
, "aclk_asyncaxis_ispx0",
5229 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11
,
5230 19, CLK_IGNORE_UNUSED
, 0),
5231 GATE(CLK_ACLK_ASYNCAXIM_ISPEX
, "aclk_asyncaxim_ispex",
5232 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11
,
5233 18, CLK_IGNORE_UNUSED
, 0),
5234 GATE(CLK_ACLK_ASYNCAXIM_ISP3P
, "aclk_asyncaxim_isp3p",
5235 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11
,
5236 17, CLK_IGNORE_UNUSED
, 0),
5237 GATE(CLK_ACLK_ASYNCAXIS_ISP3P
, "aclk_asyncaxis_isp3p",
5238 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11
,
5239 16, CLK_IGNORE_UNUSED
, 0),
5240 GATE(CLK_ACLK_ASYNCAXIM_FD
, "aclk_asyncaxim_fd",
5241 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11
,
5242 15, CLK_IGNORE_UNUSED
, 0),
5243 GATE(CLK_ACLK_ASYNCAXIS_FD
, "aclk_asyncaxis_fd", "div_aclk_fd",
5244 ENABLE_ACLK_CAM11
, 14, CLK_IGNORE_UNUSED
, 0),
5245 GATE(CLK_ACLK_ASYNCAXIM_LITE_C
, "aclk_asyncaxim_lite_c",
5246 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11
,
5247 13, CLK_IGNORE_UNUSED
, 0),
5248 GATE(CLK_ACLK_ASYNCAXIS_LITE_C
, "aclk_asyncaxis_lite_c",
5249 "div_aclk_lite_c", ENABLE_ACLK_CAM11
,
5250 12, CLK_IGNORE_UNUSED
, 0),
5251 GATE(CLK_ACLK_AHB2APB_ISP5P
, "aclk_ahb2apb_isp5p", "div_pclk_cam1_83",
5252 ENABLE_ACLK_CAM11
, 11, CLK_IGNORE_UNUSED
, 0),
5253 GATE(CLK_ACLK_AHB2APB_ISP3P
, "aclk_ahb2apb_isp3p", "div_pclk_cam1_83",
5254 ENABLE_ACLK_CAM11
, 10, CLK_IGNORE_UNUSED
, 0),
5255 GATE(CLK_ACLK_AXI2APB_ISP3P
, "aclk_axi2apb_isp3p",
5256 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11
,
5257 9, CLK_IGNORE_UNUSED
, 0),
5258 GATE(CLK_ACLK_AHB_SFRISP2H
, "aclk_ahb_sfrisp2h", "div_pclk_cam1_83",
5259 ENABLE_ACLK_CAM11
, 8, CLK_IGNORE_UNUSED
, 0),
5260 GATE(CLK_ACLK_AXI_ISP_HX_R
, "aclk_axi_isp_hx_r", "div_pclk_cam1_166",
5261 ENABLE_ACLK_CAM11
, 7, CLK_IGNORE_UNUSED
, 0),
5262 GATE(CLK_ACLK_AXI_ISP_CX_R
, "aclk_axi_isp_cx_r", "div_pclk_cam1_166",
5263 ENABLE_ACLK_CAM11
, 6, CLK_IGNORE_UNUSED
, 0),
5264 GATE(CLK_ACLK_AXI_ISP_HX
, "aclk_axi_isp_hx", "mout_aclk_cam1_333_user",
5265 ENABLE_ACLK_CAM11
, 5, CLK_IGNORE_UNUSED
, 0),
5266 GATE(CLK_ACLK_AXI_ISP_CX
, "aclk_axi_isp_cx", "mout_aclk_cam1_333_user",
5267 ENABLE_ACLK_CAM11
, 4, CLK_IGNORE_UNUSED
, 0),
5268 GATE(CLK_ACLK_XIU_ISPX
, "aclk_xiu_ispx", "mout_aclk_cam1_333_user",
5269 ENABLE_ACLK_CAM11
, 3, CLK_IGNORE_UNUSED
, 0),
5270 GATE(CLK_ACLK_XIU_ISPEX
, "aclk_xiu_ispex", "mout_aclk_cam1_400_user",
5271 ENABLE_ACLK_CAM11
, 2, CLK_IGNORE_UNUSED
, 0),
5272 GATE(CLK_ACLK_CAM1NP_333
, "aclk_cam1np_333", "mout_aclk_cam1_333_user",
5273 ENABLE_ACLK_CAM11
, 1, CLK_IGNORE_UNUSED
, 0),
5274 GATE(CLK_ACLK_CAM1ND_400
, "aclk_cam1nd_400", "mout_aclk_cam1_400_user",
5275 ENABLE_ACLK_CAM11
, 0, CLK_IGNORE_UNUSED
, 0),
5277 /* ENABLE_ACLK_CAM12 */
5278 GATE(CLK_ACLK_SMMU_ISPCPU
, "aclk_smmu_ispcpu",
5279 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12
,
5280 10, CLK_IGNORE_UNUSED
, 0),
5281 GATE(CLK_ACLK_SMMU_FD
, "aclk_smmu_fd", "mout_aclk_cam1_400_user",
5282 ENABLE_ACLK_CAM12
, 9, CLK_IGNORE_UNUSED
, 0),
5283 GATE(CLK_ACLK_SMMU_LITE_C
, "aclk_smmu_lite_c",
5284 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12
,
5285 8, CLK_IGNORE_UNUSED
, 0),
5286 GATE(CLK_ACLK_BTS_ISP3P
, "aclk_bts_isp3p", "mout_aclk_cam1_400_user",
5287 ENABLE_ACLK_CAM12
, 7, CLK_IGNORE_UNUSED
, 0),
5288 GATE(CLK_ACLK_BTS_FD
, "aclk_bts_fd", "mout_aclk_cam1_400_user",
5289 ENABLE_ACLK_CAM12
, 6, CLK_IGNORE_UNUSED
, 0),
5290 GATE(CLK_ACLK_BTS_LITE_C
, "aclk_bts_lite_c", "mout_aclk_cam1_400_user",
5291 ENABLE_ACLK_CAM12
, 5, CLK_IGNORE_UNUSED
, 0),
5292 GATE(CLK_ACLK_AHBDN_SFRISP2H
, "aclk_ahbdn_sfrisp2h",
5293 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12
,
5294 4, CLK_IGNORE_UNUSED
, 0),
5295 GATE(CLK_ACLK_AHBDN_ISP5P
, "aclk_aclk-shbdn_isp5p",
5296 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12
,
5297 3, CLK_IGNORE_UNUSED
, 0),
5298 GATE(CLK_ACLK_AXIUS_ISP3P
, "aclk_axius_isp3p",
5299 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12
,
5300 2, CLK_IGNORE_UNUSED
, 0),
5301 GATE(CLK_ACLK_AXIUS_FD
, "aclk_axius_fd", "mout_aclk_cam1_400_user",
5302 ENABLE_ACLK_CAM12
, 1, CLK_IGNORE_UNUSED
, 0),
5303 GATE(CLK_ACLK_AXIUS_LITE_C
, "aclk_axius_lite_c",
5304 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12
,
5305 0, CLK_IGNORE_UNUSED
, 0),
5307 /* ENABLE_PCLK_CAM1 */
5308 GATE(CLK_PCLK_SMMU_ISPCPU
, "pclk_smmu_ispcpu", "div_pclk_cam1_166",
5309 ENABLE_PCLK_CAM1
, 27, CLK_IGNORE_UNUSED
, 0),
5310 GATE(CLK_PCLK_SMMU_FD
, "pclk_smmu_fd", "div_pclk_cam1_166",
5311 ENABLE_PCLK_CAM1
, 26, CLK_IGNORE_UNUSED
, 0),
5312 GATE(CLK_PCLK_SMMU_LITE_C
, "pclk_smmu_lite_c", "div_pclk_cam1_166",
5313 ENABLE_PCLK_CAM1
, 25, CLK_IGNORE_UNUSED
, 0),
5314 GATE(CLK_PCLK_BTS_ISP3P
, "pclk_bts_isp3p", "div_pclk_cam1_83",
5315 ENABLE_PCLK_CAM1
, 24, CLK_IGNORE_UNUSED
, 0),
5316 GATE(CLK_PCLK_BTS_FD
, "pclk_bts_fd", "div_pclk_cam1_83",
5317 ENABLE_PCLK_CAM1
, 23, CLK_IGNORE_UNUSED
, 0),
5318 GATE(CLK_PCLK_BTS_LITE_C
, "pclk_bts_lite_c", "div_pclk_cam1_83",
5319 ENABLE_PCLK_CAM1
, 22, CLK_IGNORE_UNUSED
, 0),
5320 GATE(CLK_PCLK_ASYNCAXIM_CA5
, "pclk_asyncaxim_ca5", "div_pclk_cam1_166",
5321 ENABLE_PCLK_CAM1
, 21, CLK_IGNORE_UNUSED
, 0),
5322 GATE(CLK_PCLK_ASYNCAXIM_ISPEX
, "pclk_asyncaxim_ispex",
5323 "div_pclk_cam1_83", ENABLE_PCLK_CAM1
,
5324 20, CLK_IGNORE_UNUSED
, 0),
5325 GATE(CLK_PCLK_ASYNCAXIM_ISP3P
, "pclk_asyncaxim_isp3p",
5326 "div_pclk_cam1_83", ENABLE_PCLK_CAM1
,
5327 19, CLK_IGNORE_UNUSED
, 0),
5328 GATE(CLK_PCLK_ASYNCAXIM_FD
, "pclk_asyncaxim_fd", "div_pclk_cam1_83",
5329 ENABLE_PCLK_CAM1
, 18, CLK_IGNORE_UNUSED
, 0),
5330 GATE(CLK_PCLK_ASYNCAXIM_LITE_C
, "pclk_asyncaxim_lite_c",
5331 "div_pclk_cam1_83", ENABLE_PCLK_CAM1
,
5332 17, CLK_IGNORE_UNUSED
, 0),
5333 GATE(CLK_PCLK_PMU_CAM1
, "pclk_pmu_cam1", "div_pclk_cam1_83",
5334 ENABLE_PCLK_CAM1
, 16, CLK_IGNORE_UNUSED
, 0),
5335 GATE(CLK_PCLK_SYSREG_CAM1
, "pclk_sysreg_cam1", "div_pclk_cam1_83",
5336 ENABLE_PCLK_CAM1
, 15, CLK_IGNORE_UNUSED
, 0),
5337 GATE(CLK_PCLK_CMU_CAM1_LOCAL
, "pclk_cmu_cam1_local",
5338 "div_pclk_cam1_166", ENABLE_PCLK_CAM1
,
5339 14, CLK_IGNORE_UNUSED
, 0),
5340 GATE(CLK_PCLK_ISP_MCTADC
, "pclk_isp_mctadc", "div_pclk_cam1_83",
5341 ENABLE_PCLK_CAM1
, 13, CLK_IGNORE_UNUSED
, 0),
5342 GATE(CLK_PCLK_ISP_WDT
, "pclk_isp_wdt", "div_pclk_cam1_83",
5343 ENABLE_PCLK_CAM1
, 12, CLK_IGNORE_UNUSED
, 0),
5344 GATE(CLK_PCLK_ISP_PWM
, "pclk_isp_pwm", "div_pclk_cam1_83",
5345 ENABLE_PCLK_CAM1
, 11, CLK_IGNORE_UNUSED
, 0),
5346 GATE(CLK_PCLK_ISP_UART
, "pclk_isp_uart", "div_pclk_cam1_83",
5347 ENABLE_PCLK_CAM1
, 10, CLK_IGNORE_UNUSED
, 0),
5348 GATE(CLK_PCLK_ISP_MCUCTL
, "pclk_isp_mcuctl", "div_pclk_cam1_83",
5349 ENABLE_PCLK_CAM1
, 9, CLK_IGNORE_UNUSED
, 0),
5350 GATE(CLK_PCLK_ISP_SPI1
, "pclk_isp_spi1", "div_pclk_cam1_83",
5351 ENABLE_PCLK_CAM1
, 8, CLK_IGNORE_UNUSED
, 0),
5352 GATE(CLK_PCLK_ISP_SPI0
, "pclk_isp_spi0", "div_pclk_cam1_83",
5353 ENABLE_PCLK_CAM1
, 7, CLK_IGNORE_UNUSED
, 0),
5354 GATE(CLK_PCLK_ISP_I2C2
, "pclk_isp_i2c2", "div_pclk_cam1_83",
5355 ENABLE_PCLK_CAM1
, 6, CLK_IGNORE_UNUSED
, 0),
5356 GATE(CLK_PCLK_ISP_I2C1
, "pclk_isp_i2c1", "div_pclk_cam1_83",
5357 ENABLE_PCLK_CAM1
, 5, CLK_IGNORE_UNUSED
, 0),
5358 GATE(CLK_PCLK_ISP_I2C0
, "pclk_isp_i2c0", "div_pclk_cam1_83",
5359 ENABLE_PCLK_CAM1
, 4, CLK_IGNORE_UNUSED
, 0),
5360 GATE(CLK_PCLK_ISP_MPWM
, "pclk_isp_wpwm", "div_pclk_cam1_83",
5361 ENABLE_PCLK_CAM1
, 3, CLK_IGNORE_UNUSED
, 0),
5362 GATE(CLK_PCLK_FD
, "pclk_fd", "div_pclk_fd",
5363 ENABLE_PCLK_CAM1
, 3, CLK_IGNORE_UNUSED
, 0),
5364 GATE(CLK_PCLK_LITE_C
, "pclk_lite_c", "div_pclk_lite_c",
5365 ENABLE_PCLK_CAM1
, 1, CLK_IGNORE_UNUSED
, 0),
5366 GATE(CLK_PCLK_CSIS2
, "pclk_csis2", "div_pclk_cam1_166",
5367 ENABLE_PCLK_CAM1
, 0, CLK_IGNORE_UNUSED
, 0),
5369 /* ENABLE_SCLK_CAM1 */
5370 GATE(CLK_SCLK_ISP_I2C2
, "sclk_isp_i2c2", "oscclk", ENABLE_SCLK_CAM1
,
5372 GATE(CLK_SCLK_ISP_I2C1
, "sclk_isp_i2c1", "oscclk", ENABLE_SCLK_CAM1
,
5374 GATE(CLK_SCLK_ISP_I2C0
, "sclk_isp_i2c0", "oscclk", ENABLE_SCLK_CAM1
,
5376 GATE(CLK_SCLK_ISP_PWM
, "sclk_isp_pwm", "oscclk", ENABLE_SCLK_CAM1
,
5378 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2B
, "phyclk_rxbyteclkhs0_s2b",
5379 "mout_phyclk_rxbyteclkhs0_s2b_user",
5380 ENABLE_SCLK_CAM1
, 11, 0, 0),
5381 GATE(CLK_SCLK_LITE_C_FREECNT
, "sclk_lite_c_freecnt", "div_pclk_lite_c",
5382 ENABLE_SCLK_CAM1
, 10, 0, 0),
5383 GATE(CLK_SCLK_PIXELASYNCM_FD
, "sclk_pixelasyncm_fd", "div_aclk_fd",
5384 ENABLE_SCLK_CAM1
, 9, 0, 0),
5385 GATE(CLK_SCLK_ISP_MCTADC
, "sclk_isp_mctadc", "sclk_isp_mctadc_cam1",
5386 ENABLE_SCLK_CAM1
, 7, 0, 0),
5387 GATE(CLK_SCLK_ISP_UART
, "sclk_isp_uart", "mout_sclk_isp_uart_user",
5388 ENABLE_SCLK_CAM1
, 6, 0, 0),
5389 GATE(CLK_SCLK_ISP_SPI1
, "sclk_isp_spi1", "mout_sclk_isp_spi1_user",
5390 ENABLE_SCLK_CAM1
, 5, 0, 0),
5391 GATE(CLK_SCLK_ISP_SPI0
, "sclk_isp_spi0", "mout_sclk_isp_spi0_user",
5392 ENABLE_SCLK_CAM1
, 4, 0, 0),
5393 GATE(CLK_SCLK_ISP_MPWM
, "sclk_isp_wpwm", "div_sclk_isp_wpwm",
5394 ENABLE_SCLK_CAM1
, 3, 0, 0),
5395 GATE(CLK_PCLK_DBG_ISP
, "sclk_dbg_isp", "div_pclk_dbg_cam1",
5396 ENABLE_SCLK_CAM1
, 2, 0, 0),
5397 GATE(CLK_ATCLK_ISP
, "atclk_isp", "div_atclk_cam1",
5398 ENABLE_SCLK_CAM1
, 1, 0, 0),
5399 GATE(CLK_SCLK_ISP_CA5
, "sclk_isp_ca5", "mout_aclk_cam1_552_user",
5400 ENABLE_SCLK_CAM1
, 0, 0, 0),
5403 static struct samsung_cmu_info cam1_cmu_info __initdata
= {
5404 .mux_clks
= cam1_mux_clks
,
5405 .nr_mux_clks
= ARRAY_SIZE(cam1_mux_clks
),
5406 .div_clks
= cam1_div_clks
,
5407 .nr_div_clks
= ARRAY_SIZE(cam1_div_clks
),
5408 .gate_clks
= cam1_gate_clks
,
5409 .nr_gate_clks
= ARRAY_SIZE(cam1_gate_clks
),
5410 .fixed_clks
= cam1_fixed_clks
,
5411 .nr_fixed_clks
= ARRAY_SIZE(cam1_fixed_clks
),
5412 .nr_clk_ids
= CAM1_NR_CLK
,
5413 .clk_regs
= cam1_clk_regs
,
5414 .nr_clk_regs
= ARRAY_SIZE(cam1_clk_regs
),
5417 static void __init
exynos5433_cmu_cam1_init(struct device_node
*np
)
5419 samsung_cmu_register_one(np
, &cam1_cmu_info
);
5421 CLK_OF_DECLARE(exynos5433_cmu_cam1
, "samsung,exynos5433-cmu-cam1",
5422 exynos5433_cmu_cam1_init
);