drivers/clk/samsung/clk-s3c2410-dclk.c

   1 /*
   2  * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * Common Clock Framework support for s3c24xx external clock output.
   9  */
  10
  11 #include <linux/clkdev.h>
  12 #include <linux/slab.h>
  13 #include <linux/clk.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/io.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/module.h>
  18 #include "clk.h"
  19
  20 /* legacy access to misccr, until dt conversion is finished */
  21 #include <mach/hardware.h>
  22 #include <mach/regs-gpio.h>
  23
  24 #define MUX_DCLK0       0
  25 #define MUX_DCLK1       1
  26 #define DIV_DCLK0       2
  27 #define DIV_DCLK1       3
  28 #define GATE_DCLK0      4
  29 #define GATE_DCLK1      5
  30 #define MUX_CLKOUT0     6
  31 #define MUX_CLKOUT1     7
  32 #define DCLK_MAX_CLKS   (MUX_CLKOUT1 + 1)
  33
  34 enum supported_socs {
  35         S3C2410,
  36         S3C2412,
  37         S3C2440,
  38         S3C2443,
  39 };
  40
  41 struct s3c24xx_dclk_drv_data {
  42         const char **clkout0_parent_names;
  43         int clkout0_num_parents;
  44         const char **clkout1_parent_names;
  45         int clkout1_num_parents;
  46         const char **mux_parent_names;
  47         int mux_num_parents;
  48 };
  49
  50 /*
  51  * Clock for output-parent selection in misccr
  52  */
  53
  54 struct s3c24xx_clkout {
  55         struct clk_hw           hw;
  56         u32                     mask;
  57         u8                      shift;
  58 };
  59
  60 #define to_s3c24xx_clkout(_hw) container_of(_hw, struct s3c24xx_clkout, hw)
  61
  62 static u8 s3c24xx_clkout_get_parent(struct clk_hw *hw)
  63 {
  64         struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw);
  65         int num_parents = clk_hw_get_num_parents(hw);
  66         u32 val;
  67
  68         val = readl_relaxed(S3C24XX_MISCCR) >> clkout->shift;
  69         val >>= clkout->shift;
  70         val &= clkout->mask;
  71
  72         if (val >= num_parents)
  73                 return -EINVAL;
  74
  75         return val;
  76 }
  77
  78 static int s3c24xx_clkout_set_parent(struct clk_hw *hw, u8 index)
  79 {
  80         struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw);
  81
  82         s3c2410_modify_misccr((clkout->mask << clkout->shift),
  83                               (index << clkout->shift));
  84
  85         return 0;
  86 }
  87
  88 static const struct clk_ops s3c24xx_clkout_ops = {
  89         .get_parent = s3c24xx_clkout_get_parent,
  90         .set_parent = s3c24xx_clkout_set_parent,
  91         .determine_rate = __clk_mux_determine_rate,
  92 };
  93
  94 static struct clk_hw *s3c24xx_register_clkout(struct device *dev,
  95                 const char *name, const char **parent_names, u8 num_parents,
  96                 u8 shift, u32 mask)
  97 {
  98         struct s3c24xx_clkout *clkout;
  99         struct clk_init_data init;
 100         int ret;
 101
 102         /* allocate the clkout */
 103         clkout = kzalloc(sizeof(*clkout), GFP_KERNEL);
 104         if (!clkout)
 105                 return ERR_PTR(-ENOMEM);
 106
 107         init.name = name;
 108         init.ops = &s3c24xx_clkout_ops;
 109         init.flags = 0;
 110         init.parent_names = parent_names;
 111         init.num_parents = num_parents;
 112
 113         clkout->shift = shift;
 114         clkout->mask = mask;
 115         clkout->hw.init = &init;
 116
 117         ret = clk_hw_register(dev, &clkout->hw);
 118         if (ret)
 119                 return ERR_PTR(ret);
 120
 121         return &clkout->hw;
 122 }
 123
 124 /*
 125  * dclk and clkout init
 126  */
 127
 128 struct s3c24xx_dclk {
 129         struct device *dev;
 130         void __iomem *base;
 131         struct notifier_block dclk0_div_change_nb;
 132         struct notifier_block dclk1_div_change_nb;
 133         spinlock_t dclk_lock;
 134         unsigned long reg_save;
 135         /* clk_data must be the last entry in the structure */
 136         struct clk_hw_onecell_data clk_data;
 137 };
 138
 139 #define to_s3c24xx_dclk0(x) \
 140                 container_of(x, struct s3c24xx_dclk, dclk0_div_change_nb)
 141
 142 #define to_s3c24xx_dclk1(x) \
 143                 container_of(x, struct s3c24xx_dclk, dclk1_div_change_nb)
 144
 145 static const char *dclk_s3c2410_p[] = { "pclk", "uclk" };
 146 static const char *clkout0_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
 147                              "gate_dclk0" };
 148 static const char *clkout1_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
 149                              "gate_dclk1" };
 150
 151 static const char *clkout0_s3c2412_p[] = { "mpll", "upll", "rtc_clkout",
 152                              "hclk", "pclk", "gate_dclk0" };
 153 static const char *clkout1_s3c2412_p[] = { "xti", "upll", "fclk", "hclk", "pclk",
 154                              "gate_dclk1" };
 155
 156 static const char *clkout0_s3c2440_p[] = { "xti", "upll", "fclk", "hclk", "pclk",
 157                              "gate_dclk0" };
 158 static const char *clkout1_s3c2440_p[] = { "mpll", "upll", "rtc_clkout",
 159                              "hclk", "pclk", "gate_dclk1" };
 160
 161 static const char *dclk_s3c2443_p[] = { "pclk", "epll" };
 162 static const char *clkout0_s3c2443_p[] = { "xti", "epll", "armclk", "hclk", "pclk",
 163                              "gate_dclk0" };
 164 static const char *clkout1_s3c2443_p[] = { "dummy", "epll", "rtc_clkout",
 165                              "hclk", "pclk", "gate_dclk1" };
 166
 167 #define DCLKCON_DCLK_DIV_MASK           0xf
 168 #define DCLKCON_DCLK0_DIV_SHIFT         4
 169 #define DCLKCON_DCLK0_CMP_SHIFT         8
 170 #define DCLKCON_DCLK1_DIV_SHIFT         20
 171 #define DCLKCON_DCLK1_CMP_SHIFT         24
 172
 173 static void s3c24xx_dclk_update_cmp(struct s3c24xx_dclk *s3c24xx_dclk,
 174                                     int div_shift, int cmp_shift)
 175 {
 176         unsigned long flags = 0;
 177         u32 dclk_con, div, cmp;
 178
 179         spin_lock_irqsave(&s3c24xx_dclk->dclk_lock, flags);
 180
 181         dclk_con = readl_relaxed(s3c24xx_dclk->base);
 182
 183         div = ((dclk_con >> div_shift) & DCLKCON_DCLK_DIV_MASK) + 1;
 184         cmp = ((div + 1) / 2) - 1;
 185
 186         dclk_con &= ~(DCLKCON_DCLK_DIV_MASK << cmp_shift);
 187         dclk_con |= (cmp << cmp_shift);
 188
 189         writel_relaxed(dclk_con, s3c24xx_dclk->base);
 190
 191         spin_unlock_irqrestore(&s3c24xx_dclk->dclk_lock, flags);
 192 }
 193
 194 static int s3c24xx_dclk0_div_notify(struct notifier_block *nb,
 195                                unsigned long event, void *data)
 196 {
 197         struct s3c24xx_dclk *s3c24xx_dclk = to_s3c24xx_dclk0(nb);
 198
 199         if (event == POST_RATE_CHANGE) {
 200                 s3c24xx_dclk_update_cmp(s3c24xx_dclk,
 201                         DCLKCON_DCLK0_DIV_SHIFT, DCLKCON_DCLK0_CMP_SHIFT);
 202         }
 203
 204         return NOTIFY_DONE;
 205 }
 206
 207 static int s3c24xx_dclk1_div_notify(struct notifier_block *nb,
 208                                unsigned long event, void *data)
 209 {
 210         struct s3c24xx_dclk *s3c24xx_dclk = to_s3c24xx_dclk1(nb);
 211
 212         if (event == POST_RATE_CHANGE) {
 213                 s3c24xx_dclk_update_cmp(s3c24xx_dclk,
 214                         DCLKCON_DCLK1_DIV_SHIFT, DCLKCON_DCLK1_CMP_SHIFT);
 215         }
 216
 217         return NOTIFY_DONE;
 218 }
 219
 220 #ifdef CONFIG_PM_SLEEP
 221 static int s3c24xx_dclk_suspend(struct device *dev)
 222 {
 223         struct s3c24xx_dclk *s3c24xx_dclk = dev_get_drvdata(dev);
 224
 225         s3c24xx_dclk->reg_save = readl_relaxed(s3c24xx_dclk->base);
 226         return 0;
 227 }
 228
 229 static int s3c24xx_dclk_resume(struct device *dev)
 230 {
 231         struct s3c24xx_dclk *s3c24xx_dclk = dev_get_drvdata(dev);
 232
 233         writel_relaxed(s3c24xx_dclk->reg_save, s3c24xx_dclk->base);
 234         return 0;
 235 }
 236 #endif
 237
 238 static SIMPLE_DEV_PM_OPS(s3c24xx_dclk_pm_ops,
 239                          s3c24xx_dclk_suspend, s3c24xx_dclk_resume);
 240
 241 static int s3c24xx_dclk_probe(struct platform_device *pdev)
 242 {
 243         struct s3c24xx_dclk *s3c24xx_dclk;
 244         struct resource *mem;
 245         struct s3c24xx_dclk_drv_data *dclk_variant;
 246         struct clk_hw **clk_table;
 247         int ret, i;
 248
 249         s3c24xx_dclk = devm_kzalloc(&pdev->dev,
 250                                     struct_size(s3c24xx_dclk, clk_data.hws,
 251                                                 DCLK_MAX_CLKS),
 252                                     GFP_KERNEL);
 253         if (!s3c24xx_dclk)
 254                 return -ENOMEM;
 255
 256         clk_table = s3c24xx_dclk->clk_data.hws;
 257
 258         s3c24xx_dclk->dev = &pdev->dev;
 259         s3c24xx_dclk->clk_data.num = DCLK_MAX_CLKS;
 260         platform_set_drvdata(pdev, s3c24xx_dclk);
 261         spin_lock_init(&s3c24xx_dclk->dclk_lock);
 262
 263         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 264         s3c24xx_dclk->base = devm_ioremap_resource(&pdev->dev, mem);
 265         if (IS_ERR(s3c24xx_dclk->base))
 266                 return PTR_ERR(s3c24xx_dclk->base);
 267
 268         dclk_variant = (struct s3c24xx_dclk_drv_data *)
 269                                 platform_get_device_id(pdev)->driver_data;
 270
 271
 272         clk_table[MUX_DCLK0] = clk_hw_register_mux(&pdev->dev, "mux_dclk0",
 273                                 dclk_variant->mux_parent_names,
 274                                 dclk_variant->mux_num_parents, 0,
 275                                 s3c24xx_dclk->base, 1, 1, 0,
 276                                 &s3c24xx_dclk->dclk_lock);
 277         clk_table[MUX_DCLK1] = clk_hw_register_mux(&pdev->dev, "mux_dclk1",
 278                                 dclk_variant->mux_parent_names,
 279                                 dclk_variant->mux_num_parents, 0,
 280                                 s3c24xx_dclk->base, 17, 1, 0,
 281                                 &s3c24xx_dclk->dclk_lock);
 282
 283         clk_table[DIV_DCLK0] = clk_hw_register_divider(&pdev->dev, "div_dclk0",
 284                                 "mux_dclk0", 0, s3c24xx_dclk->base,
 285                                 4, 4, 0, &s3c24xx_dclk->dclk_lock);
 286         clk_table[DIV_DCLK1] = clk_hw_register_divider(&pdev->dev, "div_dclk1",
 287                                 "mux_dclk1", 0, s3c24xx_dclk->base,
 288                                 20, 4, 0, &s3c24xx_dclk->dclk_lock);
 289
 290         clk_table[GATE_DCLK0] = clk_hw_register_gate(&pdev->dev, "gate_dclk0",
 291                                 "div_dclk0", CLK_SET_RATE_PARENT,
 292                                 s3c24xx_dclk->base, 0, 0,
 293                                 &s3c24xx_dclk->dclk_lock);
 294         clk_table[GATE_DCLK1] = clk_hw_register_gate(&pdev->dev, "gate_dclk1",
 295                                 "div_dclk1", CLK_SET_RATE_PARENT,
 296                                 s3c24xx_dclk->base, 16, 0,
 297                                 &s3c24xx_dclk->dclk_lock);
 298
 299         clk_table[MUX_CLKOUT0] = s3c24xx_register_clkout(&pdev->dev,
 300                                 "clkout0", dclk_variant->clkout0_parent_names,
 301                                 dclk_variant->clkout0_num_parents, 4, 7);
 302         clk_table[MUX_CLKOUT1] = s3c24xx_register_clkout(&pdev->dev,
 303                                 "clkout1", dclk_variant->clkout1_parent_names,
 304                                 dclk_variant->clkout1_num_parents, 8, 7);
 305
 306         for (i = 0; i < DCLK_MAX_CLKS; i++)
 307                 if (IS_ERR(clk_table[i])) {
 308                         dev_err(&pdev->dev, "clock %d failed to register\n", i);
 309                         ret = PTR_ERR(clk_table[i]);
 310                         goto err_clk_register;
 311                 }
 312
 313         ret = clk_hw_register_clkdev(clk_table[MUX_DCLK0], "dclk0", NULL);
 314         if (!ret)
 315                 ret = clk_hw_register_clkdev(clk_table[MUX_DCLK1], "dclk1",
 316                                              NULL);
 317         if (!ret)
 318                 ret = clk_hw_register_clkdev(clk_table[MUX_CLKOUT0],
 319                                              "clkout0", NULL);
 320         if (!ret)
 321                 ret = clk_hw_register_clkdev(clk_table[MUX_CLKOUT1],
 322                                              "clkout1", NULL);
 323         if (ret) {
 324                 dev_err(&pdev->dev, "failed to register aliases, %d\n", ret);
 325                 goto err_clk_register;
 326         }
 327
 328         s3c24xx_dclk->dclk0_div_change_nb.notifier_call =
 329                                                 s3c24xx_dclk0_div_notify;
 330
 331         s3c24xx_dclk->dclk1_div_change_nb.notifier_call =
 332                                                 s3c24xx_dclk1_div_notify;
 333
 334         ret = clk_notifier_register(clk_table[DIV_DCLK0]->clk,
 335                                     &s3c24xx_dclk->dclk0_div_change_nb);
 336         if (ret)
 337                 goto err_clk_register;
 338
 339         ret = clk_notifier_register(clk_table[DIV_DCLK1]->clk,
 340                                     &s3c24xx_dclk->dclk1_div_change_nb);
 341         if (ret)
 342                 goto err_dclk_notify;
 343
 344         return 0;
 345
 346 err_dclk_notify:
 347         clk_notifier_unregister(clk_table[DIV_DCLK0]->clk,
 348                                 &s3c24xx_dclk->dclk0_div_change_nb);
 349 err_clk_register:
 350         for (i = 0; i < DCLK_MAX_CLKS; i++)
 351                 if (clk_table[i] && !IS_ERR(clk_table[i]))
 352                         clk_hw_unregister(clk_table[i]);
 353
 354         return ret;
 355 }
 356
 357 static int s3c24xx_dclk_remove(struct platform_device *pdev)
 358 {
 359         struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
 360         struct clk_hw **clk_table = s3c24xx_dclk->clk_data.hws;
 361         int i;
 362
 363         clk_notifier_unregister(clk_table[DIV_DCLK1]->clk,
 364                                 &s3c24xx_dclk->dclk1_div_change_nb);
 365         clk_notifier_unregister(clk_table[DIV_DCLK0]->clk,
 366                                 &s3c24xx_dclk->dclk0_div_change_nb);
 367
 368         for (i = 0; i < DCLK_MAX_CLKS; i++)
 369                 clk_hw_unregister(clk_table[i]);
 370
 371         return 0;
 372 }
 373
 374 static struct s3c24xx_dclk_drv_data dclk_variants[] = {
 375         [S3C2410] = {
 376                 .clkout0_parent_names = clkout0_s3c2410_p,
 377                 .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2410_p),
 378                 .clkout1_parent_names = clkout1_s3c2410_p,
 379                 .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2410_p),
 380                 .mux_parent_names = dclk_s3c2410_p,
 381                 .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
 382         },
 383         [S3C2412] = {
 384                 .clkout0_parent_names = clkout0_s3c2412_p,
 385                 .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2412_p),
 386                 .clkout1_parent_names = clkout1_s3c2412_p,
 387                 .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2412_p),
 388                 .mux_parent_names = dclk_s3c2410_p,
 389                 .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
 390         },
 391         [S3C2440] = {
 392                 .clkout0_parent_names = clkout0_s3c2440_p,
 393                 .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2440_p),
 394                 .clkout1_parent_names = clkout1_s3c2440_p,
 395                 .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2440_p),
 396                 .mux_parent_names = dclk_s3c2410_p,
 397                 .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
 398         },
 399         [S3C2443] = {
 400                 .clkout0_parent_names = clkout0_s3c2443_p,
 401                 .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2443_p),
 402                 .clkout1_parent_names = clkout1_s3c2443_p,
 403                 .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2443_p),
 404                 .mux_parent_names = dclk_s3c2443_p,
 405                 .mux_num_parents = ARRAY_SIZE(dclk_s3c2443_p),
 406         },
 407 };
 408
 409 static const struct platform_device_id s3c24xx_dclk_driver_ids[] = {
 410         {
 411                 .name           = "s3c2410-dclk",
 412                 .driver_data    = (kernel_ulong_t)&dclk_variants[S3C2410],
 413         }, {
 414                 .name           = "s3c2412-dclk",
 415                 .driver_data    = (kernel_ulong_t)&dclk_variants[S3C2412],
 416         }, {
 417                 .name           = "s3c2440-dclk",
 418                 .driver_data    = (kernel_ulong_t)&dclk_variants[S3C2440],
 419         }, {
 420                 .name           = "s3c2443-dclk",
 421                 .driver_data    = (kernel_ulong_t)&dclk_variants[S3C2443],
 422         },
 423         { }
 424 };
 425
 426 MODULE_DEVICE_TABLE(platform, s3c24xx_dclk_driver_ids);
 427
 428 static struct platform_driver s3c24xx_dclk_driver = {
 429         .driver = {
 430                 .name                   = "s3c24xx-dclk",
 431                 .pm                     = &s3c24xx_dclk_pm_ops,
 432                 .suppress_bind_attrs    = true,
 433         },
 434         .probe = s3c24xx_dclk_probe,
 435         .remove = s3c24xx_dclk_remove,
 436         .id_table = s3c24xx_dclk_driver_ids,
 437 };
 438 module_platform_driver(s3c24xx_dclk_driver);
 439
 440 MODULE_LICENSE("GPL v2");
 441 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
 442 MODULE_DESCRIPTION("Driver for the S3C24XX external clock outputs");