drivers/clk/shmobile/clk-rcar-gen2.c

   1 /*
   2  * rcar_gen2 Core CPG Clocks
   3  *
   4  * Copyright (C) 2013  Ideas On Board SPRL
   5  *
   6  * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  */
  12
  13 #include <linux/clk-provider.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/clk/shmobile.h>
  16 #include <linux/init.h>
  17 #include <linux/kernel.h>
  18 #include <linux/math64.h>
  19 #include <linux/of.h>
  20 #include <linux/of_address.h>
  21 #include <linux/spinlock.h>
  22
  23 struct rcar_gen2_cpg {
  24         struct clk_onecell_data data;
  25         spinlock_t lock;
  26         void __iomem *reg;
  27 };
  28
  29 #define CPG_SDCKCR                      0x00000074
  30 #define CPG_PLL0CR                      0x000000d8
  31 #define CPG_FRQCRC                      0x000000e0
  32 #define CPG_FRQCRC_ZFC_MASK             (0x1f << 8)
  33 #define CPG_FRQCRC_ZFC_SHIFT            8
  34
  35 /* -----------------------------------------------------------------------------
  36  * Z Clock
  37  *
  38  * Traits of this clock:
  39  * prepare - clk_prepare only ensures that parents are prepared
  40  * enable - clk_enable only ensures that parents are enabled
  41  * rate - rate is adjustable.  clk->rate = parent->rate * mult / 32
  42  * parent - fixed parent.  No clk_set_parent support
  43  */
  44
  45 struct cpg_z_clk {
  46         struct clk_hw hw;
  47         void __iomem *reg;
  48 };
  49
  50 #define to_z_clk(_hw)   container_of(_hw, struct cpg_z_clk, hw)
  51
  52 static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
  53                                            unsigned long parent_rate)
  54 {
  55         struct cpg_z_clk *zclk = to_z_clk(hw);
  56         unsigned int mult;
  57         unsigned int val;
  58
  59         val = (clk_readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK)
  60             >> CPG_FRQCRC_ZFC_SHIFT;
  61         mult = 32 - val;
  62
  63         return div_u64((u64)parent_rate * mult, 32);
  64 }
  65
  66 static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
  67                                  unsigned long *parent_rate)
  68 {
  69         unsigned long prate  = *parent_rate;
  70         unsigned int mult;
  71
  72         if (!prate)
  73                 prate = 1;
  74
  75         mult = div_u64((u64)rate * 32, prate);
  76         mult = clamp(mult, 1U, 32U);
  77
  78         return *parent_rate / 32 * mult;
  79 }
  80
  81 static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
  82                               unsigned long parent_rate)
  83 {
  84         struct cpg_z_clk *zclk = to_z_clk(hw);
  85         unsigned int mult;
  86         u32 val;
  87
  88         mult = div_u64((u64)rate * 32, parent_rate);
  89         mult = clamp(mult, 1U, 32U);
  90
  91         val = clk_readl(zclk->reg);
  92         val &= ~CPG_FRQCRC_ZFC_MASK;
  93         val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT;
  94         clk_writel(val, zclk->reg);
  95
  96         return 0;
  97 }
  98
  99 static const struct clk_ops cpg_z_clk_ops = {
 100         .recalc_rate = cpg_z_clk_recalc_rate,
 101         .round_rate = cpg_z_clk_round_rate,
 102         .set_rate = cpg_z_clk_set_rate,
 103 };
 104
 105 static struct clk * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg)
 106 {
 107         static const char *parent_name = "pll0";
 108         struct clk_init_data init;
 109         struct cpg_z_clk *zclk;
 110         struct clk *clk;
 111
 112         zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
 113         if (!zclk)
 114                 return ERR_PTR(-ENOMEM);
 115
 116         init.name = "z";
 117         init.ops = &cpg_z_clk_ops;
 118         init.flags = 0;
 119         init.parent_names = &parent_name;
 120         init.num_parents = 1;
 121
 122         zclk->reg = cpg->reg + CPG_FRQCRC;
 123         zclk->hw.init = &init;
 124
 125         clk = clk_register(NULL, &zclk->hw);
 126         if (IS_ERR(clk))
 127                 kfree(zclk);
 128
 129         return clk;
 130 }
 131
 132 /* -----------------------------------------------------------------------------
 133  * CPG Clock Data
 134  */
 135
 136 /*
 137  *   MD         EXTAL           PLL0    PLL1    PLL3
 138  * 14 13 19     (MHz)           *1      *1
 139  *---------------------------------------------------
 140  * 0  0  0      15 x 1          x172/2  x208/2  x106
 141  * 0  0  1      15 x 1          x172/2  x208/2  x88
 142  * 0  1  0      20 x 1          x130/2  x156/2  x80
 143  * 0  1  1      20 x 1          x130/2  x156/2  x66
 144  * 1  0  0      26 / 2          x200/2  x240/2  x122
 145  * 1  0  1      26 / 2          x200/2  x240/2  x102
 146  * 1  1  0      30 / 2          x172/2  x208/2  x106
 147  * 1  1  1      30 / 2          x172/2  x208/2  x88
 148  *
 149  * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
 150  */
 151 #define CPG_PLL_CONFIG_INDEX(md)        ((((md) & BIT(14)) >> 12) | \
 152                                          (((md) & BIT(13)) >> 12) | \
 153                                          (((md) & BIT(19)) >> 19))
 154 struct cpg_pll_config {
 155         unsigned int extal_div;
 156         unsigned int pll1_mult;
 157         unsigned int pll3_mult;
 158 };
 159
 160 static const struct cpg_pll_config cpg_pll_configs[8] __initconst = {
 161         { 1, 208, 106 }, { 1, 208,  88 }, { 1, 156,  80 }, { 1, 156,  66 },
 162         { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208,  88 },
 163 };
 164
 165 /* SDHI divisors */
 166 static const struct clk_div_table cpg_sdh_div_table[] = {
 167         {  0,  2 }, {  1,  3 }, {  2,  4 }, {  3,  6 },
 168         {  4,  8 }, {  5, 12 }, {  6, 16 }, {  7, 18 },
 169         {  8, 24 }, { 10, 36 }, { 11, 48 }, {  0,  0 },
 170 };
 171
 172 static const struct clk_div_table cpg_sd01_div_table[] = {
 173         {  5, 12 }, {  6, 16 }, {  7, 18 }, {  8, 24 },
 174         { 10, 36 }, { 11, 48 }, { 12, 10 }, {  0,  0 },
 175 };
 176
 177 /* -----------------------------------------------------------------------------
 178  * Initialization
 179  */
 180
 181 static u32 cpg_mode __initdata;
 182
 183 static struct clk * __init
 184 rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
 185                              const struct cpg_pll_config *config,
 186                              const char *name)
 187 {
 188         const struct clk_div_table *table = NULL;
 189         const char *parent_name;
 190         unsigned int shift;
 191         unsigned int mult = 1;
 192         unsigned int div = 1;
 193
 194         if (!strcmp(name, "main")) {
 195                 parent_name = of_clk_get_parent_name(np, 0);
 196                 div = config->extal_div;
 197         } else if (!strcmp(name, "pll0")) {
 198                 /* PLL0 is a configurable multiplier clock. Register it as a
 199                  * fixed factor clock for now as there's no generic multiplier
 200                  * clock implementation and we currently have no need to change
 201                  * the multiplier value.
 202                  */
 203                 u32 value = clk_readl(cpg->reg + CPG_PLL0CR);
 204                 parent_name = "main";
 205                 mult = ((value >> 24) & ((1 << 7) - 1)) + 1;
 206         } else if (!strcmp(name, "pll1")) {
 207                 parent_name = "main";
 208                 mult = config->pll1_mult / 2;
 209         } else if (!strcmp(name, "pll3")) {
 210                 parent_name = "main";
 211                 mult = config->pll3_mult;
 212         } else if (!strcmp(name, "lb")) {
 213                 parent_name = "pll1_div2";
 214                 div = cpg_mode & BIT(18) ? 36 : 24;
 215         } else if (!strcmp(name, "qspi")) {
 216                 parent_name = "pll1_div2";
 217                 div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2)
 218                     ? 8 : 10;
 219         } else if (!strcmp(name, "sdh")) {
 220                 parent_name = "pll1_div2";
 221                 table = cpg_sdh_div_table;
 222                 shift = 8;
 223         } else if (!strcmp(name, "sd0")) {
 224                 parent_name = "pll1_div2";
 225                 table = cpg_sd01_div_table;
 226                 shift = 4;
 227         } else if (!strcmp(name, "sd1")) {
 228                 parent_name = "pll1_div2";
 229                 table = cpg_sd01_div_table;
 230                 shift = 0;
 231         } else if (!strcmp(name, "z")) {
 232                 return cpg_z_clk_register(cpg);
 233         } else {
 234                 return ERR_PTR(-EINVAL);
 235         }
 236
 237         if (!table)
 238                 return clk_register_fixed_factor(NULL, name, parent_name, 0,
 239                                                  mult, div);
 240         else
 241                 return clk_register_divider_table(NULL, name, parent_name, 0,
 242                                                  cpg->reg + CPG_SDCKCR, shift,
 243                                                  4, 0, table, &cpg->lock);
 244 }
 245
 246 static void __init rcar_gen2_cpg_clocks_init(struct device_node *np)
 247 {
 248         const struct cpg_pll_config *config;
 249         struct rcar_gen2_cpg *cpg;
 250         struct clk **clks;
 251         unsigned int i;
 252         int num_clks;
 253
 254         num_clks = of_property_count_strings(np, "clock-output-names");
 255         if (num_clks < 0) {
 256                 pr_err("%s: failed to count clocks\n", __func__);
 257                 return;
 258         }
 259
 260         cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
 261         clks = kzalloc(num_clks * sizeof(*clks), GFP_KERNEL);
 262         if (cpg == NULL || clks == NULL) {
 263                 /* We're leaking memory on purpose, there's no point in cleaning
 264                  * up as the system won't boot anyway.
 265                  */
 266                 pr_err("%s: failed to allocate cpg\n", __func__);
 267                 return;
 268         }
 269
 270         spin_lock_init(&cpg->lock);
 271
 272         cpg->data.clks = clks;
 273         cpg->data.clk_num = num_clks;
 274
 275         cpg->reg = of_iomap(np, 0);
 276         if (WARN_ON(cpg->reg == NULL))
 277                 return;
 278
 279         config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
 280
 281         for (i = 0; i < num_clks; ++i) {
 282                 const char *name;
 283                 struct clk *clk;
 284
 285                 of_property_read_string_index(np, "clock-output-names", i,
 286                                               &name);
 287
 288                 clk = rcar_gen2_cpg_register_clock(np, cpg, config, name);
 289                 if (IS_ERR(clk))
 290                         pr_err("%s: failed to register %s %s clock (%ld)\n",
 291                                __func__, np->name, name, PTR_ERR(clk));
 292                 else
 293                         cpg->data.clks[i] = clk;
 294         }
 295
 296         of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
 297 }
 298 CLK_OF_DECLARE(rcar_gen2_cpg_clks, "renesas,rcar-gen2-cpg-clocks",
 299                rcar_gen2_cpg_clocks_init);
 300
 301 void __init rcar_gen2_clocks_init(u32 mode)
 302 {
 303         cpg_mode = mode;
 304
 305         of_clk_init(NULL);
 306 }