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git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blob - drivers/clk/socfpga/clk-periph-a10.c
2 * Copyright (C) 2015 Altera Corporation. All rights reserved
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
16 #include <linux/clk-provider.h>
22 #define CLK_MGR_FREE_SHIFT 16
23 #define CLK_MGR_FREE_MASK 0x7
25 #define SOCFPGA_MPU_FREE_CLK "mpu_free_clk"
26 #define SOCFPGA_NOC_FREE_CLK "noc_free_clk"
27 #define SOCFPGA_SDMMC_FREE_CLK "sdmmc_free_clk"
28 #define to_socfpga_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw.hw)
30 static unsigned long clk_periclk_recalc_rate(struct clk_hw
*hwclk
,
31 unsigned long parent_rate
)
33 struct socfpga_periph_clk
*socfpgaclk
= to_socfpga_periph_clk(hwclk
);
36 if (socfpgaclk
->fixed_div
) {
37 div
= socfpgaclk
->fixed_div
;
38 } else if (socfpgaclk
->div_reg
) {
39 div
= readl(socfpgaclk
->div_reg
) >> socfpgaclk
->shift
;
40 div
&= div_mask(socfpgaclk
->width
);
43 div
= ((readl(socfpgaclk
->hw
.reg
) & 0x7ff) + 1);
46 return parent_rate
/ div
;
49 static u8
clk_periclk_get_parent(struct clk_hw
*hwclk
)
51 struct socfpga_periph_clk
*socfpgaclk
= to_socfpga_periph_clk(hwclk
);
54 clk_src
= readl(socfpgaclk
->hw
.reg
);
55 if (streq(hwclk
->init
->name
, SOCFPGA_MPU_FREE_CLK
) ||
56 streq(hwclk
->init
->name
, SOCFPGA_NOC_FREE_CLK
) ||
57 streq(hwclk
->init
->name
, SOCFPGA_SDMMC_FREE_CLK
))
58 return (clk_src
>> CLK_MGR_FREE_SHIFT
) &
64 static const struct clk_ops periclk_ops
= {
65 .recalc_rate
= clk_periclk_recalc_rate
,
66 .get_parent
= clk_periclk_get_parent
,
69 static __init
void __socfpga_periph_init(struct device_node
*node
,
70 const struct clk_ops
*ops
)
74 struct socfpga_periph_clk
*periph_clk
;
75 const char *clk_name
= node
->name
;
76 const char *parent_name
;
77 struct clk_init_data init
;
82 of_property_read_u32(node
, "reg", ®
);
84 periph_clk
= kzalloc(sizeof(*periph_clk
), GFP_KERNEL
);
85 if (WARN_ON(!periph_clk
))
88 periph_clk
->hw
.reg
= clk_mgr_a10_base_addr
+ reg
;
90 rc
= of_property_read_u32_array(node
, "div-reg", div_reg
, 3);
92 periph_clk
->div_reg
= clk_mgr_a10_base_addr
+ div_reg
[0];
93 periph_clk
->shift
= div_reg
[1];
94 periph_clk
->width
= div_reg
[2];
96 periph_clk
->div_reg
= NULL
;
99 rc
= of_property_read_u32(node
, "fixed-divider", &fixed_div
);
101 periph_clk
->fixed_div
= 0;
103 periph_clk
->fixed_div
= fixed_div
;
105 of_property_read_string(node
, "clock-output-names", &clk_name
);
107 init
.name
= clk_name
;
111 parent_name
= of_clk_get_parent_name(node
, 0);
112 init
.num_parents
= 1;
113 init
.parent_names
= &parent_name
;
115 periph_clk
->hw
.hw
.init
= &init
;
117 clk
= clk_register(NULL
, &periph_clk
->hw
.hw
);
118 if (WARN_ON(IS_ERR(clk
))) {
122 rc
= of_clk_add_provider(node
, of_clk_src_simple_get
, clk
);
124 pr_err("Could not register clock provider for node:%s\n",
135 void __init
socfpga_a10_periph_init(struct device_node
*node
)
137 __socfpga_periph_init(node
, &periclk_ops
);