drivers/clk/spear/spear3xx_clock.c

   1 /*
   2  * SPEAr3xx machines clock framework source file
   3  *
   4  * Copyright (C) 2012 ST Microelectronics
   5  * Viresh Kumar <viresh.kumar@st.com>
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2. This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/clkdev.h>
  14 #include <linux/err.h>
  15 #include <linux/io.h>
  16 #include <linux/of_platform.h>
  17 #include <linux/spinlock_types.h>
  18 #include <mach/misc_regs.h>
  19 #include "clk.h"
  20
  21 static DEFINE_SPINLOCK(_lock);
  22
  23 #define PLL1_CTR                        (MISC_BASE + 0x008)
  24 #define PLL1_FRQ                        (MISC_BASE + 0x00C)
  25 #define PLL2_CTR                        (MISC_BASE + 0x014)
  26 #define PLL2_FRQ                        (MISC_BASE + 0x018)
  27 #define PLL_CLK_CFG                     (MISC_BASE + 0x020)
  28         /* PLL_CLK_CFG register masks */
  29         #define MCTR_CLK_SHIFT          28
  30         #define MCTR_CLK_MASK           3
  31
  32 #define CORE_CLK_CFG                    (MISC_BASE + 0x024)
  33         /* CORE CLK CFG register masks */
  34         #define GEN_SYNTH2_3_CLK_SHIFT  18
  35         #define GEN_SYNTH2_3_CLK_MASK   1
  36
  37         #define HCLK_RATIO_SHIFT        10
  38         #define HCLK_RATIO_MASK         2
  39         #define PCLK_RATIO_SHIFT        8
  40         #define PCLK_RATIO_MASK         2
  41
  42 #define PERIP_CLK_CFG                   (MISC_BASE + 0x028)
  43         /* PERIP_CLK_CFG register masks */
  44         #define UART_CLK_SHIFT          4
  45         #define UART_CLK_MASK           1
  46         #define FIRDA_CLK_SHIFT         5
  47         #define FIRDA_CLK_MASK          2
  48         #define GPT0_CLK_SHIFT          8
  49         #define GPT1_CLK_SHIFT          11
  50         #define GPT2_CLK_SHIFT          12
  51         #define GPT_CLK_MASK            1
  52
  53 #define PERIP1_CLK_ENB                  (MISC_BASE + 0x02C)
  54         /* PERIP1_CLK_ENB register masks */
  55         #define UART_CLK_ENB            3
  56         #define SSP_CLK_ENB             5
  57         #define I2C_CLK_ENB             7
  58         #define JPEG_CLK_ENB            8
  59         #define FIRDA_CLK_ENB           10
  60         #define GPT1_CLK_ENB            11
  61         #define GPT2_CLK_ENB            12
  62         #define ADC_CLK_ENB             15
  63         #define RTC_CLK_ENB             17
  64         #define GPIO_CLK_ENB            18
  65         #define DMA_CLK_ENB             19
  66         #define SMI_CLK_ENB             21
  67         #define GMAC_CLK_ENB            23
  68         #define USBD_CLK_ENB            24
  69         #define USBH_CLK_ENB            25
  70         #define C3_CLK_ENB              31
  71
  72 #define RAS_CLK_ENB                     (MISC_BASE + 0x034)
  73         #define RAS_AHB_CLK_ENB         0
  74         #define RAS_PLL1_CLK_ENB        1
  75         #define RAS_APB_CLK_ENB         2
  76         #define RAS_32K_CLK_ENB         3
  77         #define RAS_24M_CLK_ENB         4
  78         #define RAS_48M_CLK_ENB         5
  79         #define RAS_PLL2_CLK_ENB        7
  80         #define RAS_SYNT0_CLK_ENB       8
  81         #define RAS_SYNT1_CLK_ENB       9
  82         #define RAS_SYNT2_CLK_ENB       10
  83         #define RAS_SYNT3_CLK_ENB       11
  84
  85 #define PRSC0_CLK_CFG                   (MISC_BASE + 0x044)
  86 #define PRSC1_CLK_CFG                   (MISC_BASE + 0x048)
  87 #define PRSC2_CLK_CFG                   (MISC_BASE + 0x04C)
  88 #define AMEM_CLK_CFG                    (MISC_BASE + 0x050)
  89         #define AMEM_CLK_ENB            0
  90
  91 #define CLCD_CLK_SYNT                   (MISC_BASE + 0x05C)
  92 #define FIRDA_CLK_SYNT                  (MISC_BASE + 0x060)
  93 #define UART_CLK_SYNT                   (MISC_BASE + 0x064)
  94 #define GMAC_CLK_SYNT                   (MISC_BASE + 0x068)
  95 #define GEN0_CLK_SYNT                   (MISC_BASE + 0x06C)
  96 #define GEN1_CLK_SYNT                   (MISC_BASE + 0x070)
  97 #define GEN2_CLK_SYNT                   (MISC_BASE + 0x074)
  98 #define GEN3_CLK_SYNT                   (MISC_BASE + 0x078)
  99
 100 /* pll rate configuration table, in ascending order of rates */
 101 static struct pll_rate_tbl pll_rtbl[] = {
 102         {.mode = 0, .m = 0x53, .n = 0x0C, .p = 0x1}, /* vco 332 & pll 166 MHz */
 103         {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* vco 532 & pll 266 MHz */
 104         {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* vco 664 & pll 332 MHz */
 105 };
 106
 107 /* aux rate configuration table, in ascending order of rates */
 108 static struct aux_rate_tbl aux_rtbl[] = {
 109         /* For PLL1 = 332 MHz */
 110         {.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */
 111         {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
 112         {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
 113         {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
 114 };
 115
 116 /* gpt rate configuration table, in ascending order of rates */
 117 static struct gpt_rate_tbl gpt_rtbl[] = {
 118         /* For pll1 = 332 MHz */
 119         {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
 120         {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
 121         {.mscale = 1, .nscale = 0}, /* 83 MHz */
 122 };
 123
 124 /* clock parents */
 125 static const char *uart0_parents[] = { "pll3_48m_clk", "uart_synth_gate_clk", };
 126 static const char *firda_parents[] = { "pll3_48m_clk", "firda_synth_gate_clk",
 127 };
 128 static const char *gpt0_parents[] = { "pll3_48m_clk", "gpt0_synth_clk", };
 129 static const char *gpt1_parents[] = { "pll3_48m_clk", "gpt1_synth_clk", };
 130 static const char *gpt2_parents[] = { "pll3_48m_clk", "gpt2_synth_clk", };
 131 static const char *gen2_3_parents[] = { "pll1_clk", "pll2_clk", };
 132 static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
 133         "pll2_clk", };
 134
 135 #ifdef CONFIG_MACH_SPEAR300
 136 static void __init spear300_clk_init(void)
 137 {
 138         struct clk *clk;
 139
 140         clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_48m_clk", 0,
 141                         1, 1);
 142         clk_register_clkdev(clk, NULL, "60000000.clcd");
 143
 144         clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
 145                         1);
 146         clk_register_clkdev(clk, NULL, "94000000.flash");
 147
 148         clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1,
 149                         1);
 150         clk_register_clkdev(clk, NULL, "70000000.sdhci");
 151
 152         clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1,
 153                         1);
 154         clk_register_clkdev(clk, NULL, "a9000000.gpio");
 155
 156         clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1,
 157                         1);
 158         clk_register_clkdev(clk, NULL, "a0000000.kbd");
 159 }
 160 #endif
 161
 162 /* array of all spear 310 clock lookups */
 163 #ifdef CONFIG_MACH_SPEAR310
 164 static void __init spear310_clk_init(void)
 165 {
 166         struct clk *clk;
 167
 168         clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
 169                         1);
 170         clk_register_clkdev(clk, "emi", NULL);
 171
 172         clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
 173                         1);
 174         clk_register_clkdev(clk, NULL, "44000000.flash");
 175
 176         clk = clk_register_fixed_factor(NULL, "tdm_clk", "ras_ahb_clk", 0, 1,
 177                         1);
 178         clk_register_clkdev(clk, NULL, "tdm");
 179
 180         clk = clk_register_fixed_factor(NULL, "uart1_clk", "ras_apb_clk", 0, 1,
 181                         1);
 182         clk_register_clkdev(clk, NULL, "b2000000.serial");
 183
 184         clk = clk_register_fixed_factor(NULL, "uart2_clk", "ras_apb_clk", 0, 1,
 185                         1);
 186         clk_register_clkdev(clk, NULL, "b2080000.serial");
 187
 188         clk = clk_register_fixed_factor(NULL, "uart3_clk", "ras_apb_clk", 0, 1,
 189                         1);
 190         clk_register_clkdev(clk, NULL, "b2100000.serial");
 191
 192         clk = clk_register_fixed_factor(NULL, "uart4_clk", "ras_apb_clk", 0, 1,
 193                         1);
 194         clk_register_clkdev(clk, NULL, "b2180000.serial");
 195
 196         clk = clk_register_fixed_factor(NULL, "uart5_clk", "ras_apb_clk", 0, 1,
 197                         1);
 198         clk_register_clkdev(clk, NULL, "b2200000.serial");
 199 }
 200 #endif
 201
 202 /* array of all spear 320 clock lookups */
 203 #ifdef CONFIG_MACH_SPEAR320
 204         #define SMII_PCLK_SHIFT                         18
 205         #define SMII_PCLK_MASK                          2
 206         #define SMII_PCLK_VAL_PAD                       0x0
 207         #define SMII_PCLK_VAL_PLL2                      0x1
 208         #define SMII_PCLK_VAL_SYNTH0                    0x2
 209         #define SDHCI_PCLK_SHIFT                        15
 210         #define SDHCI_PCLK_MASK                         1
 211         #define SDHCI_PCLK_VAL_48M                      0x0
 212         #define SDHCI_PCLK_VAL_SYNTH3                   0x1
 213         #define I2S_REF_PCLK_SHIFT                      8
 214         #define I2S_REF_PCLK_MASK                       1
 215         #define I2S_REF_PCLK_SYNTH_VAL                  0x1
 216         #define I2S_REF_PCLK_PLL2_VAL                   0x0
 217         #define UART1_PCLK_SHIFT                        6
 218         #define UART1_PCLK_MASK                         1
 219         #define SPEAR320_UARTX_PCLK_VAL_SYNTH1          0x0
 220         #define SPEAR320_UARTX_PCLK_VAL_APB             0x1
 221
 222 static const char *i2s_ref_parents[] = { "ras_pll2_clk",
 223         "ras_gen2_synth_gate_clk", };
 224 static const char *sdhci_parents[] = { "ras_pll3_48m_clk",
 225         "ras_gen3_synth_gate_clk",
 226 };
 227 static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk",
 228         "ras_gen0_synth_gate_clk", };
 229 static const char *uartx_parents[] = { "ras_gen1_synth_gate_clk", "ras_apb_clk",
 230 };
 231
 232 static void __init spear320_clk_init(void)
 233 {
 234         struct clk *clk;
 235
 236         clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL,
 237                         CLK_IS_ROOT, 125000000);
 238         clk_register_clkdev(clk, "smii_125m_pad", NULL);
 239
 240         clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_48m_clk", 0,
 241                         1, 1);
 242         clk_register_clkdev(clk, NULL, "90000000.clcd");
 243
 244         clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
 245                         1);
 246         clk_register_clkdev(clk, "emi", NULL);
 247
 248         clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
 249                         1);
 250         clk_register_clkdev(clk, NULL, "4c000000.flash");
 251
 252         clk = clk_register_fixed_factor(NULL, "i2c1_clk", "ras_ahb_clk", 0, 1,
 253                         1);
 254         clk_register_clkdev(clk, NULL, "a7000000.i2c");
 255
 256         clk = clk_register_fixed_factor(NULL, "pwm_clk", "ras_ahb_clk", 0, 1,
 257                         1);
 258         clk_register_clkdev(clk, "pwm", NULL);
 259
 260         clk = clk_register_fixed_factor(NULL, "ssp1_clk", "ras_ahb_clk", 0, 1,
 261                         1);
 262         clk_register_clkdev(clk, NULL, "a5000000.spi");
 263
 264         clk = clk_register_fixed_factor(NULL, "ssp2_clk", "ras_ahb_clk", 0, 1,
 265                         1);
 266         clk_register_clkdev(clk, NULL, "a6000000.spi");
 267
 268         clk = clk_register_fixed_factor(NULL, "can0_clk", "ras_apb_clk", 0, 1,
 269                         1);
 270         clk_register_clkdev(clk, NULL, "c_can_platform.0");
 271
 272         clk = clk_register_fixed_factor(NULL, "can1_clk", "ras_apb_clk", 0, 1,
 273                         1);
 274         clk_register_clkdev(clk, NULL, "c_can_platform.1");
 275
 276         clk = clk_register_fixed_factor(NULL, "i2s_clk", "ras_apb_clk", 0, 1,
 277                         1);
 278         clk_register_clkdev(clk, NULL, "i2s");
 279
 280         clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents,
 281                         ARRAY_SIZE(i2s_ref_parents), 0, SPEAR320_CONTROL_REG,
 282                         I2S_REF_PCLK_SHIFT, I2S_REF_PCLK_MASK, 0, &_lock);
 283         clk_register_clkdev(clk, "i2s_ref_clk", NULL);
 284
 285         clk = clk_register_fixed_factor(NULL, "i2s_sclk", "i2s_ref_clk", 0, 1,
 286                         4);
 287         clk_register_clkdev(clk, "i2s_sclk", NULL);
 288
 289         clk = clk_register_mux(NULL, "rs485_clk", uartx_parents,
 290                         ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
 291                         SPEAR320_RS485_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
 292                         &_lock);
 293         clk_register_clkdev(clk, NULL, "a9300000.serial");
 294
 295         clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents,
 296                         ARRAY_SIZE(sdhci_parents), 0, SPEAR320_CONTROL_REG,
 297                         SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK, 0, &_lock);
 298         clk_register_clkdev(clk, NULL, "70000000.sdhci");
 299
 300         clk = clk_register_mux(NULL, "smii_pclk", smii0_parents,
 301                         ARRAY_SIZE(smii0_parents), 0, SPEAR320_CONTROL_REG,
 302                         SMII_PCLK_SHIFT, SMII_PCLK_MASK, 0, &_lock);
 303         clk_register_clkdev(clk, NULL, "smii_pclk");
 304
 305         clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1);
 306         clk_register_clkdev(clk, NULL, "smii");
 307
 308         clk = clk_register_mux(NULL, "uart1_clk", uartx_parents,
 309                         ARRAY_SIZE(uartx_parents), 0, SPEAR320_CONTROL_REG,
 310                         UART1_PCLK_SHIFT, UART1_PCLK_MASK, 0, &_lock);
 311         clk_register_clkdev(clk, NULL, "a3000000.serial");
 312
 313         clk = clk_register_mux(NULL, "uart2_clk", uartx_parents,
 314                         ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
 315                         SPEAR320_UART2_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
 316                         &_lock);
 317         clk_register_clkdev(clk, NULL, "a4000000.serial");
 318
 319         clk = clk_register_mux(NULL, "uart3_clk", uartx_parents,
 320                         ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
 321                         SPEAR320_UART3_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
 322                         &_lock);
 323         clk_register_clkdev(clk, NULL, "a9100000.serial");
 324
 325         clk = clk_register_mux(NULL, "uart4_clk", uartx_parents,
 326                         ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
 327                         SPEAR320_UART4_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
 328                         &_lock);
 329         clk_register_clkdev(clk, NULL, "a9200000.serial");
 330
 331         clk = clk_register_mux(NULL, "uart5_clk", uartx_parents,
 332                         ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
 333                         SPEAR320_UART5_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
 334                         &_lock);
 335         clk_register_clkdev(clk, NULL, "60000000.serial");
 336
 337         clk = clk_register_mux(NULL, "uart6_clk", uartx_parents,
 338                         ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
 339                         SPEAR320_UART6_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
 340                         &_lock);
 341         clk_register_clkdev(clk, NULL, "60100000.serial");
 342 }
 343 #endif
 344
 345 void __init spear3xx_clk_init(void)
 346 {
 347         struct clk *clk, *clk1;
 348
 349         clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
 350         clk_register_clkdev(clk, "apb_pclk", NULL);
 351
 352         clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
 353                         32000);
 354         clk_register_clkdev(clk, "osc_32k_clk", NULL);
 355
 356         clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
 357                         24000000);
 358         clk_register_clkdev(clk, "osc_24m_clk", NULL);
 359
 360         /* clock derived from 32 KHz osc clk */
 361         clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
 362                         PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
 363         clk_register_clkdev(clk, NULL, "fc900000.rtc");
 364
 365         /* clock derived from 24 MHz osc clk */
 366         clk = clk_register_fixed_rate(NULL, "pll3_48m_clk", "osc_24m_clk", 0,
 367                         48000000);
 368         clk_register_clkdev(clk, "pll3_48m_clk", NULL);
 369
 370         clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_24m_clk", 0, 1,
 371                         1);
 372         clk_register_clkdev(clk, NULL, "fc880000.wdt");
 373
 374         clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL,
 375                         "osc_24m_clk", 0, PLL1_CTR, PLL1_FRQ, pll_rtbl,
 376                         ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
 377         clk_register_clkdev(clk, "vco1_clk", NULL);
 378         clk_register_clkdev(clk1, "pll1_clk", NULL);
 379
 380         clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL,
 381                         "osc_24m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl,
 382                         ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
 383         clk_register_clkdev(clk, "vco2_clk", NULL);
 384         clk_register_clkdev(clk1, "pll2_clk", NULL);
 385
 386         /* clock derived from pll1 clk */
 387         clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 1);
 388         clk_register_clkdev(clk, "cpu_clk", NULL);
 389
 390         clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
 391                         CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
 392                         HCLK_RATIO_MASK, 0, &_lock);
 393         clk_register_clkdev(clk, "ahb_clk", NULL);
 394
 395         clk = clk_register_aux("uart_synth_clk", "uart_synth_gate_clk",
 396                         "pll1_clk", 0, UART_CLK_SYNT, NULL, aux_rtbl,
 397                         ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 398         clk_register_clkdev(clk, "uart_synth_clk", NULL);
 399         clk_register_clkdev(clk1, "uart_synth_gate_clk", NULL);
 400
 401         clk = clk_register_mux(NULL, "uart0_mux_clk", uart0_parents,
 402                         ARRAY_SIZE(uart0_parents), 0, PERIP_CLK_CFG,
 403                         UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock);
 404         clk_register_clkdev(clk, "uart0_mux_clk", NULL);
 405
 406         clk = clk_register_gate(NULL, "uart0", "uart0_mux_clk", 0,
 407                         PERIP1_CLK_ENB, UART_CLK_ENB, 0, &_lock);
 408         clk_register_clkdev(clk, NULL, "d0000000.serial");
 409
 410         clk = clk_register_aux("firda_synth_clk", "firda_synth_gate_clk",
 411                         "pll1_clk", 0, FIRDA_CLK_SYNT, NULL, aux_rtbl,
 412                         ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 413         clk_register_clkdev(clk, "firda_synth_clk", NULL);
 414         clk_register_clkdev(clk1, "firda_synth_gate_clk", NULL);
 415
 416         clk = clk_register_mux(NULL, "firda_mux_clk", firda_parents,
 417                         ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG,
 418                         FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock);
 419         clk_register_clkdev(clk, "firda_mux_clk", NULL);
 420
 421         clk = clk_register_gate(NULL, "firda_clk", "firda_mux_clk", 0,
 422                         PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
 423         clk_register_clkdev(clk, NULL, "firda");
 424
 425         /* gpt clocks */
 426         clk_register_gpt("gpt0_synth_clk", "pll1_clk", 0, PRSC0_CLK_CFG,
 427                         gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
 428         clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents,
 429                         ARRAY_SIZE(gpt0_parents), 0, PERIP_CLK_CFG,
 430                         GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
 431         clk_register_clkdev(clk, NULL, "gpt0");
 432
 433         clk_register_gpt("gpt1_synth_clk", "pll1_clk", 0, PRSC1_CLK_CFG,
 434                         gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
 435         clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt1_parents,
 436                         ARRAY_SIZE(gpt1_parents), 0, PERIP_CLK_CFG,
 437                         GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
 438         clk_register_clkdev(clk, "gpt1_mux_clk", NULL);
 439         clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0,
 440                         PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
 441         clk_register_clkdev(clk, NULL, "gpt1");
 442
 443         clk_register_gpt("gpt2_synth_clk", "pll1_clk", 0, PRSC2_CLK_CFG,
 444                         gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
 445         clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt2_parents,
 446                         ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG,
 447                         GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
 448         clk_register_clkdev(clk, "gpt2_mux_clk", NULL);
 449         clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0,
 450                         PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
 451         clk_register_clkdev(clk, NULL, "gpt2");
 452
 453         /* general synths clocks */
 454         clk = clk_register_aux("gen0_synth_clk", "gen0_synth_gate_clk",
 455                         "pll1_clk", 0, GEN0_CLK_SYNT, NULL, aux_rtbl,
 456                         ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 457         clk_register_clkdev(clk, "gen0_synth_clk", NULL);
 458         clk_register_clkdev(clk1, "gen0_synth_gate_clk", NULL);
 459
 460         clk = clk_register_aux("gen1_synth_clk", "gen1_synth_gate_clk",
 461                         "pll1_clk", 0, GEN1_CLK_SYNT, NULL, aux_rtbl,
 462                         ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 463         clk_register_clkdev(clk, "gen1_synth_clk", NULL);
 464         clk_register_clkdev(clk1, "gen1_synth_gate_clk", NULL);
 465
 466         clk = clk_register_mux(NULL, "gen2_3_parent_clk", gen2_3_parents,
 467                         ARRAY_SIZE(gen2_3_parents), 0, CORE_CLK_CFG,
 468                         GEN_SYNTH2_3_CLK_SHIFT, GEN_SYNTH2_3_CLK_MASK, 0,
 469                         &_lock);
 470         clk_register_clkdev(clk, "gen2_3_parent_clk", NULL);
 471
 472         clk = clk_register_aux("gen2_synth_clk", "gen2_synth_gate_clk",
 473                         "gen2_3_parent_clk", 0, GEN2_CLK_SYNT, NULL, aux_rtbl,
 474                         ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 475         clk_register_clkdev(clk, "gen2_synth_clk", NULL);
 476         clk_register_clkdev(clk1, "gen2_synth_gate_clk", NULL);
 477
 478         clk = clk_register_aux("gen3_synth_clk", "gen3_synth_gate_clk",
 479                         "gen2_3_parent_clk", 0, GEN3_CLK_SYNT, NULL, aux_rtbl,
 480                         ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 481         clk_register_clkdev(clk, "gen3_synth_clk", NULL);
 482         clk_register_clkdev(clk1, "gen3_synth_gate_clk", NULL);
 483
 484         /* clock derived from pll3 clk */
 485         clk = clk_register_gate(NULL, "usbh_clk", "pll3_48m_clk", 0,
 486                         PERIP1_CLK_ENB, USBH_CLK_ENB, 0, &_lock);
 487         clk_register_clkdev(clk, "usbh_clk", NULL);
 488
 489         clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1,
 490                         1);
 491         clk_register_clkdev(clk, "usbh.0_clk", NULL);
 492
 493         clk = clk_register_fixed_factor(NULL, "usbh.1_clk", "usbh_clk", 0, 1,
 494                         1);
 495         clk_register_clkdev(clk, "usbh.1_clk", NULL);
 496
 497         clk = clk_register_gate(NULL, "usbd_clk", "pll3_48m_clk", 0,
 498                         PERIP1_CLK_ENB, USBD_CLK_ENB, 0, &_lock);
 499         clk_register_clkdev(clk, NULL, "designware_udc");
 500
 501         /* clock derived from ahb clk */
 502         clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
 503                         1);
 504         clk_register_clkdev(clk, "ahbmult2_clk", NULL);
 505
 506         clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
 507                         ARRAY_SIZE(ddr_parents), 0, PLL_CLK_CFG, MCTR_CLK_SHIFT,
 508                         MCTR_CLK_MASK, 0, &_lock);
 509         clk_register_clkdev(clk, "ddr_clk", NULL);
 510
 511         clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
 512                         CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
 513                         PCLK_RATIO_MASK, 0, &_lock);
 514         clk_register_clkdev(clk, "apb_clk", NULL);
 515
 516         clk = clk_register_gate(NULL, "amem_clk", "ahb_clk", 0, AMEM_CLK_CFG,
 517                         AMEM_CLK_ENB, 0, &_lock);
 518         clk_register_clkdev(clk, "amem_clk", NULL);
 519
 520         clk = clk_register_gate(NULL, "c3_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
 521                         C3_CLK_ENB, 0, &_lock);
 522         clk_register_clkdev(clk, NULL, "c3_clk");
 523
 524         clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
 525                         DMA_CLK_ENB, 0, &_lock);
 526         clk_register_clkdev(clk, NULL, "fc400000.dma");
 527
 528         clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
 529                         GMAC_CLK_ENB, 0, &_lock);
 530         clk_register_clkdev(clk, NULL, "e0800000.eth");
 531
 532         clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
 533                         I2C_CLK_ENB, 0, &_lock);
 534         clk_register_clkdev(clk, NULL, "d0180000.i2c");
 535
 536         clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
 537                         JPEG_CLK_ENB, 0, &_lock);
 538         clk_register_clkdev(clk, NULL, "jpeg");
 539
 540         clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
 541                         SMI_CLK_ENB, 0, &_lock);
 542         clk_register_clkdev(clk, NULL, "fc000000.flash");
 543
 544         /* clock derived from apb clk */
 545         clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
 546                         ADC_CLK_ENB, 0, &_lock);
 547         clk_register_clkdev(clk, NULL, "adc");
 548
 549         clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
 550                         GPIO_CLK_ENB, 0, &_lock);
 551         clk_register_clkdev(clk, NULL, "fc980000.gpio");
 552
 553         clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
 554                         SSP_CLK_ENB, 0, &_lock);
 555         clk_register_clkdev(clk, NULL, "d0100000.spi");
 556
 557         /* RAS clk enable */
 558         clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, RAS_CLK_ENB,
 559                         RAS_AHB_CLK_ENB, 0, &_lock);
 560         clk_register_clkdev(clk, "ras_ahb_clk", NULL);
 561
 562         clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB,
 563                         RAS_APB_CLK_ENB, 0, &_lock);
 564         clk_register_clkdev(clk, "ras_apb_clk", NULL);
 565
 566         clk = clk_register_gate(NULL, "ras_32k_clk", "osc_32k_clk", 0,
 567                         RAS_CLK_ENB, RAS_32K_CLK_ENB, 0, &_lock);
 568         clk_register_clkdev(clk, "ras_32k_clk", NULL);
 569
 570         clk = clk_register_gate(NULL, "ras_24m_clk", "osc_24m_clk", 0,
 571                         RAS_CLK_ENB, RAS_24M_CLK_ENB, 0, &_lock);
 572         clk_register_clkdev(clk, "ras_24m_clk", NULL);
 573
 574         clk = clk_register_gate(NULL, "ras_pll1_clk", "pll1_clk", 0,
 575                         RAS_CLK_ENB, RAS_PLL1_CLK_ENB, 0, &_lock);
 576         clk_register_clkdev(clk, "ras_pll1_clk", NULL);
 577
 578         clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
 579                         RAS_CLK_ENB, RAS_PLL2_CLK_ENB, 0, &_lock);
 580         clk_register_clkdev(clk, "ras_pll2_clk", NULL);
 581
 582         clk = clk_register_gate(NULL, "ras_pll3_48m_clk", "pll3_48m_clk", 0,
 583                         RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock);
 584         clk_register_clkdev(clk, "ras_pll3_48m_clk", NULL);
 585
 586         clk = clk_register_gate(NULL, "ras_gen0_synth_gate_clk",
 587                         "gen0_synth_gate_clk", 0, RAS_CLK_ENB,
 588                         RAS_SYNT0_CLK_ENB, 0, &_lock);
 589         clk_register_clkdev(clk, "ras_gen0_synth_gate_clk", NULL);
 590
 591         clk = clk_register_gate(NULL, "ras_gen1_synth_gate_clk",
 592                         "gen1_synth_gate_clk", 0, RAS_CLK_ENB,
 593                         RAS_SYNT1_CLK_ENB, 0, &_lock);
 594         clk_register_clkdev(clk, "ras_gen1_synth_gate_clk", NULL);
 595
 596         clk = clk_register_gate(NULL, "ras_gen2_synth_gate_clk",
 597                         "gen2_synth_gate_clk", 0, RAS_CLK_ENB,
 598                         RAS_SYNT2_CLK_ENB, 0, &_lock);
 599         clk_register_clkdev(clk, "ras_gen2_synth_gate_clk", NULL);
 600
 601         clk = clk_register_gate(NULL, "ras_gen3_synth_gate_clk",
 602                         "gen3_synth_gate_clk", 0, RAS_CLK_ENB,
 603                         RAS_SYNT3_CLK_ENB, 0, &_lock);
 604         clk_register_clkdev(clk, "ras_gen3_synth_gate_clk", NULL);
 605
 606         if (of_machine_is_compatible("st,spear300"))
 607                 spear300_clk_init();
 608         else if (of_machine_is_compatible("st,spear310"))
 609                 spear310_clk_init();
 610         else if (of_machine_is_compatible("st,spear320"))
 611                 spear320_clk_init();
 612 }