2 * Copyright 2015 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk-provider.h>
20 #include <linux/of_address.h>
21 #include <linux/reset-controller.h>
22 #include <linux/slab.h>
23 #include <linux/spinlock.h>
25 static DEFINE_SPINLOCK(ve_lock
);
27 #define SUN4I_VE_ENABLE 31
28 #define SUN4I_VE_DIVIDER_SHIFT 16
29 #define SUN4I_VE_DIVIDER_WIDTH 3
30 #define SUN4I_VE_RESET 0
33 * sunxi_ve_reset... - reset bit in ve clk registers handling
36 struct ve_reset_data
{
39 struct reset_controller_dev rcdev
;
42 static int sunxi_ve_reset_assert(struct reset_controller_dev
*rcdev
,
45 struct ve_reset_data
*data
= container_of(rcdev
,
51 spin_lock_irqsave(data
->lock
, flags
);
53 reg
= readl(data
->reg
);
54 writel(reg
& ~BIT(SUN4I_VE_RESET
), data
->reg
);
56 spin_unlock_irqrestore(data
->lock
, flags
);
61 static int sunxi_ve_reset_deassert(struct reset_controller_dev
*rcdev
,
64 struct ve_reset_data
*data
= container_of(rcdev
,
70 spin_lock_irqsave(data
->lock
, flags
);
72 reg
= readl(data
->reg
);
73 writel(reg
| BIT(SUN4I_VE_RESET
), data
->reg
);
75 spin_unlock_irqrestore(data
->lock
, flags
);
80 static int sunxi_ve_of_xlate(struct reset_controller_dev
*rcdev
,
81 const struct of_phandle_args
*reset_spec
)
83 if (WARN_ON(reset_spec
->args_count
!= 0))
89 static const struct reset_control_ops sunxi_ve_reset_ops
= {
90 .assert = sunxi_ve_reset_assert
,
91 .deassert
= sunxi_ve_reset_deassert
,
94 static void __init
sun4i_ve_clk_setup(struct device_node
*node
)
97 struct clk_divider
*div
;
98 struct clk_gate
*gate
;
99 struct ve_reset_data
*reset_data
;
101 const char *clk_name
= node
->name
;
105 reg
= of_io_request_and_map(node
, 0, of_node_full_name(node
));
109 div
= kzalloc(sizeof(*div
), GFP_KERNEL
);
113 gate
= kzalloc(sizeof(*gate
), GFP_KERNEL
);
117 of_property_read_string(node
, "clock-output-names", &clk_name
);
118 parent
= of_clk_get_parent_name(node
, 0);
121 gate
->bit_idx
= SUN4I_VE_ENABLE
;
122 gate
->lock
= &ve_lock
;
125 div
->shift
= SUN4I_VE_DIVIDER_SHIFT
;
126 div
->width
= SUN4I_VE_DIVIDER_WIDTH
;
127 div
->lock
= &ve_lock
;
129 clk
= clk_register_composite(NULL
, clk_name
, &parent
, 1,
131 &div
->hw
, &clk_divider_ops
,
132 &gate
->hw
, &clk_gate_ops
,
133 CLK_SET_RATE_PARENT
);
137 err
= of_clk_add_provider(node
, of_clk_src_simple_get
, clk
);
139 goto err_unregister_clk
;
141 reset_data
= kzalloc(sizeof(*reset_data
), GFP_KERNEL
);
143 goto err_del_provider
;
145 reset_data
->reg
= reg
;
146 reset_data
->lock
= &ve_lock
;
147 reset_data
->rcdev
.nr_resets
= 1;
148 reset_data
->rcdev
.ops
= &sunxi_ve_reset_ops
;
149 reset_data
->rcdev
.of_node
= node
;
150 reset_data
->rcdev
.of_xlate
= sunxi_ve_of_xlate
;
151 reset_data
->rcdev
.of_reset_n_cells
= 0;
152 err
= reset_controller_register(&reset_data
->rcdev
);
161 of_clk_del_provider(node
);
171 CLK_OF_DECLARE(sun4i_ve
, "allwinner,sun4i-a10-ve-clk",