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Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-hirsute-kernel.git] / drivers / clk / sunxi-ng / ccu-sun50i-a64.c
1 /*
2 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/clk-provider.h>
15 #include <linux/of_address.h>
16 #include <linux/platform_device.h>
17
18 #include "ccu_common.h"
19 #include "ccu_reset.h"
20
21 #include "ccu_div.h"
22 #include "ccu_gate.h"
23 #include "ccu_mp.h"
24 #include "ccu_mult.h"
25 #include "ccu_nk.h"
26 #include "ccu_nkm.h"
27 #include "ccu_nkmp.h"
28 #include "ccu_nm.h"
29 #include "ccu_phase.h"
30
31 #include "ccu-sun50i-a64.h"
32
33 static struct ccu_nkmp pll_cpux_clk = {
34 .enable = BIT(31),
35 .lock = BIT(28),
36 .n = _SUNXI_CCU_MULT(8, 5),
37 .k = _SUNXI_CCU_MULT(4, 2),
38 .m = _SUNXI_CCU_DIV(0, 2),
39 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
40 .common = {
41 .reg = 0x000,
42 .hw.init = CLK_HW_INIT("pll-cpux",
43 "osc24M",
44 &ccu_nkmp_ops,
45 CLK_SET_RATE_UNGATE),
46 },
47 };
48
49 /*
50 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
51 * the base (2x, 4x and 8x), and one variable divider (the one true
52 * pll audio).
53 *
54 * With sigma-delta modulation for fractional-N on the audio PLL,
55 * we have to use specific dividers. This means the variable divider
56 * can no longer be used, as the audio codec requests the exact clock
57 * rates we support through this mechanism. So we now hard code the
58 * variable divider to 1. This means the clock rates will no longer
59 * match the clock names.
60 */
61 #define SUN50I_A64_PLL_AUDIO_REG 0x008
62
63 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
64 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
65 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
66 };
67
68 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
69 "osc24M", 0x008,
70 8, 7, /* N */
71 0, 5, /* M */
72 pll_audio_sdm_table, BIT(24),
73 0x284, BIT(31),
74 BIT(31), /* gate */
75 BIT(28), /* lock */
76 CLK_SET_RATE_UNGATE);
77
78 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
79 "osc24M", 0x010,
80 192000000, /* Minimum rate */
81 1008000000, /* Maximum rate */
82 8, 7, /* N */
83 0, 4, /* M */
84 BIT(24), /* frac enable */
85 BIT(25), /* frac select */
86 270000000, /* frac rate 0 */
87 297000000, /* frac rate 1 */
88 BIT(31), /* gate */
89 BIT(28), /* lock */
90 CLK_SET_RATE_UNGATE);
91
92 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
93 "osc24M", 0x018,
94 8, 7, /* N */
95 0, 4, /* M */
96 BIT(24), /* frac enable */
97 BIT(25), /* frac select */
98 270000000, /* frac rate 0 */
99 297000000, /* frac rate 1 */
100 BIT(31), /* gate */
101 BIT(28), /* lock */
102 CLK_SET_RATE_UNGATE);
103
104 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
105 "osc24M", 0x020,
106 8, 5, /* N */
107 4, 2, /* K */
108 0, 2, /* M */
109 BIT(31), /* gate */
110 BIT(28), /* lock */
111 CLK_SET_RATE_UNGATE);
112
113 static struct ccu_nk pll_periph0_clk = {
114 .enable = BIT(31),
115 .lock = BIT(28),
116 .n = _SUNXI_CCU_MULT(8, 5),
117 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
118 .fixed_post_div = 2,
119 .common = {
120 .reg = 0x028,
121 .features = CCU_FEATURE_FIXED_POSTDIV,
122 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
123 &ccu_nk_ops, CLK_SET_RATE_UNGATE),
124 },
125 };
126
127 static struct ccu_nk pll_periph1_clk = {
128 .enable = BIT(31),
129 .lock = BIT(28),
130 .n = _SUNXI_CCU_MULT(8, 5),
131 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
132 .fixed_post_div = 2,
133 .common = {
134 .reg = 0x02c,
135 .features = CCU_FEATURE_FIXED_POSTDIV,
136 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
137 &ccu_nk_ops, CLK_SET_RATE_UNGATE),
138 },
139 };
140
141 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",
142 "osc24M", 0x030,
143 192000000, /* Minimum rate */
144 1008000000, /* Maximum rate */
145 8, 7, /* N */
146 0, 4, /* M */
147 BIT(24), /* frac enable */
148 BIT(25), /* frac select */
149 270000000, /* frac rate 0 */
150 297000000, /* frac rate 1 */
151 BIT(31), /* gate */
152 BIT(28), /* lock */
153 CLK_SET_RATE_UNGATE);
154
155 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
156 "osc24M", 0x038,
157 8, 7, /* N */
158 0, 4, /* M */
159 BIT(24), /* frac enable */
160 BIT(25), /* frac select */
161 270000000, /* frac rate 0 */
162 297000000, /* frac rate 1 */
163 BIT(31), /* gate */
164 BIT(28), /* lock */
165 CLK_SET_RATE_UNGATE);
166
167 /*
168 * The output function can be changed to something more complex that
169 * we do not handle yet.
170 *
171 * Hardcode the mode so that we don't fall in that case.
172 */
173 #define SUN50I_A64_PLL_MIPI_REG 0x040
174
175 static struct ccu_nkm pll_mipi_clk = {
176 /*
177 * The bit 23 and 22 are called "LDO{1,2}_EN" on the SoC's
178 * user manual, and by experiments the PLL doesn't work without
179 * these bits toggled.
180 */
181 .enable = BIT(31) | BIT(23) | BIT(22),
182 .lock = BIT(28),
183 .n = _SUNXI_CCU_MULT(8, 4),
184 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
185 .m = _SUNXI_CCU_DIV(0, 4),
186 .common = {
187 .reg = 0x040,
188 .hw.init = CLK_HW_INIT("pll-mipi", "pll-video0",
189 &ccu_nkm_ops, CLK_SET_RATE_UNGATE),
190 },
191 };
192
193 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
194 "osc24M", 0x044,
195 8, 7, /* N */
196 0, 4, /* M */
197 BIT(24), /* frac enable */
198 BIT(25), /* frac select */
199 270000000, /* frac rate 0 */
200 297000000, /* frac rate 1 */
201 BIT(31), /* gate */
202 BIT(28), /* lock */
203 CLK_SET_RATE_UNGATE);
204
205 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
206 "osc24M", 0x048,
207 8, 7, /* N */
208 0, 4, /* M */
209 BIT(24), /* frac enable */
210 BIT(25), /* frac select */
211 270000000, /* frac rate 0 */
212 297000000, /* frac rate 1 */
213 BIT(31), /* gate */
214 BIT(28), /* lock */
215 CLK_SET_RATE_UNGATE);
216
217 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
218 "osc24M", 0x04c,
219 8, 7, /* N */
220 0, 2, /* M */
221 BIT(31), /* gate */
222 BIT(28), /* lock */
223 CLK_SET_RATE_UNGATE);
224
225 static const char * const cpux_parents[] = { "osc32k", "osc24M",
226 "pll-cpux", "pll-cpux" };
227 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
228 0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
229
230 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
231
232 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
233 "axi", "pll-periph0" };
234 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
235 { .index = 3, .shift = 6, .width = 2 },
236 };
237 static struct ccu_div ahb1_clk = {
238 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
239
240 .mux = {
241 .shift = 12,
242 .width = 2,
243
244 .var_predivs = ahb1_predivs,
245 .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
246 },
247
248 .common = {
249 .reg = 0x054,
250 .features = CCU_FEATURE_VARIABLE_PREDIV,
251 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
252 ahb1_parents,
253 &ccu_div_ops,
254 0),
255 },
256 };
257
258 static struct clk_div_table apb1_div_table[] = {
259 { .val = 0, .div = 2 },
260 { .val = 1, .div = 2 },
261 { .val = 2, .div = 4 },
262 { .val = 3, .div = 8 },
263 { /* Sentinel */ },
264 };
265 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
266 0x054, 8, 2, apb1_div_table, 0);
267
268 static const char * const apb2_parents[] = { "osc32k", "osc24M",
269 "pll-periph0-2x",
270 "pll-periph0-2x" };
271 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
272 0, 5, /* M */
273 16, 2, /* P */
274 24, 2, /* mux */
275 0);
276
277 static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" };
278 static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = {
279 { .index = 1, .div = 2 },
280 };
281 static struct ccu_mux ahb2_clk = {
282 .mux = {
283 .shift = 0,
284 .width = 1,
285 .fixed_predivs = ahb2_fixed_predivs,
286 .n_predivs = ARRAY_SIZE(ahb2_fixed_predivs),
287 },
288
289 .common = {
290 .reg = 0x05c,
291 .features = CCU_FEATURE_FIXED_PREDIV,
292 .hw.init = CLK_HW_INIT_PARENTS("ahb2",
293 ahb2_parents,
294 &ccu_mux_ops,
295 0),
296 },
297 };
298
299 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
300 0x060, BIT(1), 0);
301 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
302 0x060, BIT(5), 0);
303 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
304 0x060, BIT(6), 0);
305 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
306 0x060, BIT(8), 0);
307 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
308 0x060, BIT(9), 0);
309 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
310 0x060, BIT(10), 0);
311 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
312 0x060, BIT(13), 0);
313 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
314 0x060, BIT(14), 0);
315 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
316 0x060, BIT(17), 0);
317 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1",
318 0x060, BIT(18), 0);
319 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
320 0x060, BIT(19), 0);
321 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
322 0x060, BIT(20), 0);
323 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
324 0x060, BIT(21), 0);
325 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
326 0x060, BIT(23), 0);
327 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
328 0x060, BIT(24), 0);
329 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2",
330 0x060, BIT(25), 0);
331 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
332 0x060, BIT(28), 0);
333 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb2",
334 0x060, BIT(29), 0);
335
336 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
337 0x064, BIT(0), 0);
338 static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",
339 0x064, BIT(3), 0);
340 static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1",
341 0x064, BIT(4), 0);
342 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1",
343 0x064, BIT(5), 0);
344 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
345 0x064, BIT(8), 0);
346 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1",
347 0x064, BIT(11), 0);
348 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
349 0x064, BIT(12), 0);
350 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
351 0x064, BIT(20), 0);
352 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
353 0x064, BIT(21), 0);
354 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
355 0x064, BIT(22), 0);
356
357 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
358 0x068, BIT(0), 0);
359 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
360 0x068, BIT(1), 0);
361 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
362 0x068, BIT(5), 0);
363 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1",
364 0x068, BIT(8), 0);
365 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
366 0x068, BIT(12), 0);
367 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
368 0x068, BIT(13), 0);
369 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
370 0x068, BIT(14), 0);
371
372 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
373 0x06c, BIT(0), 0);
374 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
375 0x06c, BIT(1), 0);
376 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
377 0x06c, BIT(2), 0);
378 static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2",
379 0x06c, BIT(5), 0);
380 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
381 0x06c, BIT(16), 0);
382 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
383 0x06c, BIT(17), 0);
384 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
385 0x06c, BIT(18), 0);
386 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
387 0x06c, BIT(19), 0);
388 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
389 0x06c, BIT(20), 0);
390
391 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
392 0x070, BIT(7), 0);
393
394 static struct clk_div_table ths_div_table[] = {
395 { .val = 0, .div = 1 },
396 { .val = 1, .div = 2 },
397 { .val = 2, .div = 4 },
398 { .val = 3, .div = 6 },
399 };
400 static const char * const ths_parents[] = { "osc24M" };
401 static struct ccu_div ths_clk = {
402 .enable = BIT(31),
403 .div = _SUNXI_CCU_DIV_TABLE(0, 2, ths_div_table),
404 .mux = _SUNXI_CCU_MUX(24, 2),
405 .common = {
406 .reg = 0x074,
407 .hw.init = CLK_HW_INIT_PARENTS("ths",
408 ths_parents,
409 &ccu_div_ops,
410 0),
411 },
412 };
413
414 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
415 "pll-periph1" };
416 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
417 0, 4, /* M */
418 16, 2, /* P */
419 24, 2, /* mux */
420 BIT(31), /* gate */
421 0);
422
423 /*
424 * MMC clocks are the new timing mode (see A83T & H3) variety, but without
425 * the mode switch. This means they have a 2x post divider between the clock
426 * and the MMC module. This is not documented in the manual, but is taken
427 * into consideration when setting the mmc module clocks in the BSP kernel.
428 * Without it, MMC performance is degraded.
429 *
430 * We model it here to be consistent with other SoCs supporting this mode.
431 * The alternative would be to add the 2x multiplier when setting the MMC
432 * module clock in the MMC driver, just for the A64.
433 */
434 static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x",
435 "pll-periph1-2x" };
436 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0",
437 mmc_default_parents, 0x088,
438 0, 4, /* M */
439 16, 2, /* P */
440 24, 2, /* mux */
441 BIT(31), /* gate */
442 2, /* post-div */
443 0);
444
445 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1",
446 mmc_default_parents, 0x08c,
447 0, 4, /* M */
448 16, 2, /* P */
449 24, 2, /* mux */
450 BIT(31), /* gate */
451 2, /* post-div */
452 0);
453
454 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2",
455 mmc_default_parents, 0x090,
456 0, 4, /* M */
457 16, 2, /* P */
458 24, 2, /* mux */
459 BIT(31), /* gate */
460 2, /* post-div */
461 0);
462
463 static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
464 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
465 0, 4, /* M */
466 16, 2, /* P */
467 24, 4, /* mux */
468 BIT(31), /* gate */
469 0);
470
471 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mmc_default_parents, 0x09c,
472 0, 4, /* M */
473 16, 2, /* P */
474 24, 2, /* mux */
475 BIT(31), /* gate */
476 0);
477
478 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
479 0, 4, /* M */
480 16, 2, /* P */
481 24, 2, /* mux */
482 BIT(31), /* gate */
483 0);
484
485 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
486 0, 4, /* M */
487 16, 2, /* P */
488 24, 2, /* mux */
489 BIT(31), /* gate */
490 0);
491
492 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
493 "pll-audio-2x", "pll-audio" };
494 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
495 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
496
497 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
498 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
499
500 static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
501 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
502
503 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
504 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
505
506 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
507 0x0cc, BIT(8), 0);
508 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
509 0x0cc, BIT(9), 0);
510 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
511 0x0cc, BIT(10), 0);
512 static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M",
513 0x0cc, BIT(11), 0);
514 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M",
515 0x0cc, BIT(16), 0);
516 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "usb-ohci0",
517 0x0cc, BIT(17), 0);
518
519 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
520 static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
521 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
522
523 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
524 0x100, BIT(0), 0);
525 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
526 0x100, BIT(1), 0);
527 static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
528 0x100, BIT(2), 0);
529 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
530 0x100, BIT(3), 0);
531
532 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
533 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
534 0x104, 0, 4, 24, 3, BIT(31),
535 CLK_SET_RATE_PARENT);
536
537 static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
538 static const u8 tcon0_table[] = { 0, 2, };
539 static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents,
540 tcon0_table, 0x118, 24, 3, BIT(31),
541 CLK_SET_RATE_PARENT);
542
543 static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
544 static const u8 tcon1_table[] = { 0, 2, };
545 static struct ccu_div tcon1_clk = {
546 .enable = BIT(31),
547 .div = _SUNXI_CCU_DIV(0, 4),
548 .mux = _SUNXI_CCU_MUX_TABLE(24, 2, tcon1_table),
549 .common = {
550 .reg = 0x11c,
551 .hw.init = CLK_HW_INIT_PARENTS("tcon1",
552 tcon1_parents,
553 &ccu_div_ops,
554 CLK_SET_RATE_PARENT),
555 },
556 };
557
558 static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
559 static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,
560 0x124, 0, 4, 24, 3, BIT(31), 0);
561
562 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M",
563 0x130, BIT(31), 0);
564
565 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
566 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
567 0x134, 16, 4, 24, 3, BIT(31), 0);
568
569 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1", "pll-periph1" };
570 static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
571 0x134, 0, 5, 8, 3, BIT(15), 0);
572
573 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
574 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
575
576 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
577 0x140, BIT(31), CLK_SET_RATE_PARENT);
578
579 static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x",
580 0x140, BIT(30), CLK_SET_RATE_PARENT);
581
582 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
583 0x144, BIT(31), 0);
584
585 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
586 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
587 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
588
589 static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
590 0x154, BIT(31), 0);
591
592 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
593 "pll-ddr0", "pll-ddr1" };
594 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
595 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
596
597 static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };
598 static const u8 dsi_dphy_table[] = { 0, 2, };
599 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
600 dsi_dphy_parents, dsi_dphy_table,
601 0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT);
602
603 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
604 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
605
606 /* Fixed Factor clocks */
607 static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 2, 1, 0);
608
609 /* We hardcode the divider to 1 for now */
610 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
611 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
612 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
613 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
614 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
615 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
616 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
617 "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
618 static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
619 "pll-periph0", 1, 2, 0);
620 static CLK_FIXED_FACTOR(pll_periph1_2x_clk, "pll-periph1-2x",
621 "pll-periph1", 1, 2, 0);
622 static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
623 "pll-video0", 1, 2, CLK_SET_RATE_PARENT);
624
625 static struct ccu_common *sun50i_a64_ccu_clks[] = {
626 &pll_cpux_clk.common,
627 &pll_audio_base_clk.common,
628 &pll_video0_clk.common,
629 &pll_ve_clk.common,
630 &pll_ddr0_clk.common,
631 &pll_periph0_clk.common,
632 &pll_periph1_clk.common,
633 &pll_video1_clk.common,
634 &pll_gpu_clk.common,
635 &pll_mipi_clk.common,
636 &pll_hsic_clk.common,
637 &pll_de_clk.common,
638 &pll_ddr1_clk.common,
639 &cpux_clk.common,
640 &axi_clk.common,
641 &ahb1_clk.common,
642 &apb1_clk.common,
643 &apb2_clk.common,
644 &ahb2_clk.common,
645 &bus_mipi_dsi_clk.common,
646 &bus_ce_clk.common,
647 &bus_dma_clk.common,
648 &bus_mmc0_clk.common,
649 &bus_mmc1_clk.common,
650 &bus_mmc2_clk.common,
651 &bus_nand_clk.common,
652 &bus_dram_clk.common,
653 &bus_emac_clk.common,
654 &bus_ts_clk.common,
655 &bus_hstimer_clk.common,
656 &bus_spi0_clk.common,
657 &bus_spi1_clk.common,
658 &bus_otg_clk.common,
659 &bus_ehci0_clk.common,
660 &bus_ehci1_clk.common,
661 &bus_ohci0_clk.common,
662 &bus_ohci1_clk.common,
663 &bus_ve_clk.common,
664 &bus_tcon0_clk.common,
665 &bus_tcon1_clk.common,
666 &bus_deinterlace_clk.common,
667 &bus_csi_clk.common,
668 &bus_hdmi_clk.common,
669 &bus_de_clk.common,
670 &bus_gpu_clk.common,
671 &bus_msgbox_clk.common,
672 &bus_spinlock_clk.common,
673 &bus_codec_clk.common,
674 &bus_spdif_clk.common,
675 &bus_pio_clk.common,
676 &bus_ths_clk.common,
677 &bus_i2s0_clk.common,
678 &bus_i2s1_clk.common,
679 &bus_i2s2_clk.common,
680 &bus_i2c0_clk.common,
681 &bus_i2c1_clk.common,
682 &bus_i2c2_clk.common,
683 &bus_scr_clk.common,
684 &bus_uart0_clk.common,
685 &bus_uart1_clk.common,
686 &bus_uart2_clk.common,
687 &bus_uart3_clk.common,
688 &bus_uart4_clk.common,
689 &bus_dbg_clk.common,
690 &ths_clk.common,
691 &nand_clk.common,
692 &mmc0_clk.common,
693 &mmc1_clk.common,
694 &mmc2_clk.common,
695 &ts_clk.common,
696 &ce_clk.common,
697 &spi0_clk.common,
698 &spi1_clk.common,
699 &i2s0_clk.common,
700 &i2s1_clk.common,
701 &i2s2_clk.common,
702 &spdif_clk.common,
703 &usb_phy0_clk.common,
704 &usb_phy1_clk.common,
705 &usb_hsic_clk.common,
706 &usb_hsic_12m_clk.common,
707 &usb_ohci0_clk.common,
708 &usb_ohci1_clk.common,
709 &dram_clk.common,
710 &dram_ve_clk.common,
711 &dram_csi_clk.common,
712 &dram_deinterlace_clk.common,
713 &dram_ts_clk.common,
714 &de_clk.common,
715 &tcon0_clk.common,
716 &tcon1_clk.common,
717 &deinterlace_clk.common,
718 &csi_misc_clk.common,
719 &csi_sclk_clk.common,
720 &csi_mclk_clk.common,
721 &ve_clk.common,
722 &ac_dig_clk.common,
723 &ac_dig_4x_clk.common,
724 &avs_clk.common,
725 &hdmi_clk.common,
726 &hdmi_ddc_clk.common,
727 &mbus_clk.common,
728 &dsi_dphy_clk.common,
729 &gpu_clk.common,
730 };
731
732 static struct clk_hw_onecell_data sun50i_a64_hw_clks = {
733 .hws = {
734 [CLK_OSC_12M] = &osc12M_clk.hw,
735 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
736 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
737 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
738 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
739 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
740 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
741 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
742 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
743 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
744 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
745 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
746 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
747 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
748 [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw,
749 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
750 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
751 [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
752 [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw,
753 [CLK_PLL_DE] = &pll_de_clk.common.hw,
754 [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
755 [CLK_CPUX] = &cpux_clk.common.hw,
756 [CLK_AXI] = &axi_clk.common.hw,
757 [CLK_AHB1] = &ahb1_clk.common.hw,
758 [CLK_APB1] = &apb1_clk.common.hw,
759 [CLK_APB2] = &apb2_clk.common.hw,
760 [CLK_AHB2] = &ahb2_clk.common.hw,
761 [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
762 [CLK_BUS_CE] = &bus_ce_clk.common.hw,
763 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
764 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
765 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
766 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
767 [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
768 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
769 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
770 [CLK_BUS_TS] = &bus_ts_clk.common.hw,
771 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
772 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
773 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
774 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
775 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
776 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
777 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
778 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
779 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
780 [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
781 [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw,
782 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
783 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
784 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
785 [CLK_BUS_DE] = &bus_de_clk.common.hw,
786 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
787 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
788 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
789 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
790 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
791 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
792 [CLK_BUS_THS] = &bus_ths_clk.common.hw,
793 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
794 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
795 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
796 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
797 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
798 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
799 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
800 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
801 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
802 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
803 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
804 [CLK_BUS_SCR] = &bus_scr_clk.common.hw,
805 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
806 [CLK_THS] = &ths_clk.common.hw,
807 [CLK_NAND] = &nand_clk.common.hw,
808 [CLK_MMC0] = &mmc0_clk.common.hw,
809 [CLK_MMC1] = &mmc1_clk.common.hw,
810 [CLK_MMC2] = &mmc2_clk.common.hw,
811 [CLK_TS] = &ts_clk.common.hw,
812 [CLK_CE] = &ce_clk.common.hw,
813 [CLK_SPI0] = &spi0_clk.common.hw,
814 [CLK_SPI1] = &spi1_clk.common.hw,
815 [CLK_I2S0] = &i2s0_clk.common.hw,
816 [CLK_I2S1] = &i2s1_clk.common.hw,
817 [CLK_I2S2] = &i2s2_clk.common.hw,
818 [CLK_SPDIF] = &spdif_clk.common.hw,
819 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
820 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
821 [CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
822 [CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw,
823 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
824 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
825 [CLK_DRAM] = &dram_clk.common.hw,
826 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
827 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
828 [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
829 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
830 [CLK_DE] = &de_clk.common.hw,
831 [CLK_TCON0] = &tcon0_clk.common.hw,
832 [CLK_TCON1] = &tcon1_clk.common.hw,
833 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
834 [CLK_CSI_MISC] = &csi_misc_clk.common.hw,
835 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
836 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
837 [CLK_VE] = &ve_clk.common.hw,
838 [CLK_AC_DIG] = &ac_dig_clk.common.hw,
839 [CLK_AC_DIG_4X] = &ac_dig_4x_clk.common.hw,
840 [CLK_AVS] = &avs_clk.common.hw,
841 [CLK_HDMI] = &hdmi_clk.common.hw,
842 [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,
843 [CLK_MBUS] = &mbus_clk.common.hw,
844 [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw,
845 [CLK_GPU] = &gpu_clk.common.hw,
846 },
847 .num = CLK_NUMBER,
848 };
849
850 static struct ccu_reset_map sun50i_a64_ccu_resets[] = {
851 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
852 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
853 [RST_USB_HSIC] = { 0x0cc, BIT(2) },
854
855 [RST_DRAM] = { 0x0f4, BIT(31) },
856 [RST_MBUS] = { 0x0fc, BIT(31) },
857
858 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
859 [RST_BUS_CE] = { 0x2c0, BIT(5) },
860 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
861 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
862 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
863 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
864 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
865 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
866 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
867 [RST_BUS_TS] = { 0x2c0, BIT(18) },
868 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
869 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
870 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
871 [RST_BUS_OTG] = { 0x2c0, BIT(23) },
872 [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
873 [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
874 [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
875 [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
876
877 [RST_BUS_VE] = { 0x2c4, BIT(0) },
878 [RST_BUS_TCON0] = { 0x2c4, BIT(3) },
879 [RST_BUS_TCON1] = { 0x2c4, BIT(4) },
880 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
881 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
882 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
883 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
884 [RST_BUS_DE] = { 0x2c4, BIT(12) },
885 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
886 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
887 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
888 [RST_BUS_DBG] = { 0x2c4, BIT(31) },
889
890 [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
891
892 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
893 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
894 [RST_BUS_THS] = { 0x2d0, BIT(8) },
895 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
896 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
897 [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
898
899 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
900 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
901 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
902 [RST_BUS_SCR] = { 0x2d8, BIT(5) },
903 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
904 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
905 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
906 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
907 [RST_BUS_UART4] = { 0x2d8, BIT(20) },
908 };
909
910 static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = {
911 .ccu_clks = sun50i_a64_ccu_clks,
912 .num_ccu_clks = ARRAY_SIZE(sun50i_a64_ccu_clks),
913
914 .hw_clks = &sun50i_a64_hw_clks,
915
916 .resets = sun50i_a64_ccu_resets,
917 .num_resets = ARRAY_SIZE(sun50i_a64_ccu_resets),
918 };
919
920 static int sun50i_a64_ccu_probe(struct platform_device *pdev)
921 {
922 struct resource *res;
923 void __iomem *reg;
924 u32 val;
925
926 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
927 reg = devm_ioremap_resource(&pdev->dev, res);
928 if (IS_ERR(reg))
929 return PTR_ERR(reg);
930
931 /* Force the PLL-Audio-1x divider to 1 */
932 val = readl(reg + SUN50I_A64_PLL_AUDIO_REG);
933 val &= ~GENMASK(19, 16);
934 writel(val | (0 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
935
936 writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
937
938 return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);
939 }
940
941 static const struct of_device_id sun50i_a64_ccu_ids[] = {
942 { .compatible = "allwinner,sun50i-a64-ccu" },
943 { }
944 };
945
946 static struct platform_driver sun50i_a64_ccu_driver = {
947 .probe = sun50i_a64_ccu_probe,
948 .driver = {
949 .name = "sun50i-a64-ccu",
950 .of_match_table = sun50i_a64_ccu_ids,
951 },
952 };
953 builtin_platform_driver(sun50i_a64_ccu_driver);
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