]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/clk/sunxi-ng/ccu-sun8i-a23.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'drm-amdkfd-fixes-2017-11-26' of git://people.freedesktop.org/~gabbayo...
[mirror_ubuntu-bionic-kernel.git] / drivers / clk / sunxi-ng / ccu-sun8i-a23.c
1 /*
2 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/clk-provider.h>
15 #include <linux/of_address.h>
16
17 #include "ccu_common.h"
18 #include "ccu_reset.h"
19
20 #include "ccu_div.h"
21 #include "ccu_gate.h"
22 #include "ccu_mp.h"
23 #include "ccu_mult.h"
24 #include "ccu_nk.h"
25 #include "ccu_nkm.h"
26 #include "ccu_nkmp.h"
27 #include "ccu_nm.h"
28 #include "ccu_phase.h"
29 #include "ccu_sdm.h"
30
31 #include "ccu-sun8i-a23-a33.h"
32
33
34 static struct ccu_nkmp pll_cpux_clk = {
35 .enable = BIT(31),
36 .lock = BIT(28),
37
38 .n = _SUNXI_CCU_MULT(8, 5),
39 .k = _SUNXI_CCU_MULT(4, 2),
40 .m = _SUNXI_CCU_DIV(0, 2),
41 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
42
43 .common = {
44 .reg = 0x000,
45 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
46 &ccu_nkmp_ops,
47 0),
48 },
49 };
50
51 /*
52 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
53 * the base (2x, 4x and 8x), and one variable divider (the one true
54 * pll audio).
55 *
56 * With sigma-delta modulation for fractional-N on the audio PLL,
57 * we have to use specific dividers. This means the variable divider
58 * can no longer be used, as the audio codec requests the exact clock
59 * rates we support through this mechanism. So we now hard code the
60 * variable divider to 1. This means the clock rates will no longer
61 * match the clock names.
62 */
63 #define SUN8I_A23_PLL_AUDIO_REG 0x008
64
65 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
66 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
67 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
68 };
69
70 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
71 "osc24M", 0x008,
72 8, 7, /* N */
73 0, 5, /* M */
74 pll_audio_sdm_table, BIT(24),
75 0x284, BIT(31),
76 BIT(31), /* gate */
77 BIT(28), /* lock */
78 CLK_SET_RATE_UNGATE);
79
80 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
81 "osc24M", 0x010,
82 8, 7, /* N */
83 0, 4, /* M */
84 BIT(24), /* frac enable */
85 BIT(25), /* frac select */
86 270000000, /* frac rate 0 */
87 297000000, /* frac rate 1 */
88 BIT(31), /* gate */
89 BIT(28), /* lock */
90 CLK_SET_RATE_UNGATE);
91
92 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
93 "osc24M", 0x018,
94 8, 7, /* N */
95 0, 4, /* M */
96 BIT(24), /* frac enable */
97 BIT(25), /* frac select */
98 270000000, /* frac rate 0 */
99 297000000, /* frac rate 1 */
100 BIT(31), /* gate */
101 BIT(28), /* lock */
102 CLK_SET_RATE_UNGATE);
103
104 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
105 "osc24M", 0x020,
106 8, 5, /* N */
107 4, 2, /* K */
108 0, 2, /* M */
109 BIT(31), /* gate */
110 BIT(28), /* lock */
111 0);
112
113 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
114 "osc24M", 0x028,
115 8, 5, /* N */
116 4, 2, /* K */
117 BIT(31), /* gate */
118 BIT(28), /* lock */
119 2, /* post-div */
120 CLK_SET_RATE_UNGATE);
121
122 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
123 "osc24M", 0x038,
124 8, 7, /* N */
125 0, 4, /* M */
126 BIT(24), /* frac enable */
127 BIT(25), /* frac select */
128 270000000, /* frac rate 0 */
129 297000000, /* frac rate 1 */
130 BIT(31), /* gate */
131 BIT(28), /* lock */
132 CLK_SET_RATE_UNGATE);
133
134 /*
135 * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
136 *
137 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
138 * integer / fractional clock with switchable multipliers and dividers.
139 * This is not supported here. We hardcode the PLL to MIPI mode.
140 */
141 #define SUN8I_A23_PLL_MIPI_REG 0x040
142 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi",
143 "pll-video", 0x040,
144 8, 4, /* N */
145 4, 2, /* K */
146 0, 4, /* M */
147 BIT(31), /* gate */
148 BIT(28), /* lock */
149 CLK_SET_RATE_UNGATE);
150
151 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
152 "osc24M", 0x044,
153 8, 7, /* N */
154 0, 4, /* M */
155 BIT(24), /* frac enable */
156 BIT(25), /* frac select */
157 270000000, /* frac rate 0 */
158 297000000, /* frac rate 1 */
159 BIT(31), /* gate */
160 BIT(28), /* lock */
161 CLK_SET_RATE_UNGATE);
162
163 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
164 "osc24M", 0x048,
165 8, 7, /* N */
166 0, 4, /* M */
167 BIT(24), /* frac enable */
168 BIT(25), /* frac select */
169 270000000, /* frac rate 0 */
170 297000000, /* frac rate 1 */
171 BIT(31), /* gate */
172 BIT(28), /* lock */
173 CLK_SET_RATE_UNGATE);
174
175 static const char * const cpux_parents[] = { "osc32k", "osc24M",
176 "pll-cpux" , "pll-cpux" };
177 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
178 0x050, 16, 2, CLK_IS_CRITICAL);
179
180 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
181
182 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
183 "axi" , "pll-periph" };
184 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
185 { .index = 3, .shift = 6, .width = 2 },
186 };
187 static struct ccu_div ahb1_clk = {
188 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
189
190 .mux = {
191 .shift = 12,
192 .width = 2,
193
194 .var_predivs = ahb1_predivs,
195 .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
196 },
197
198 .common = {
199 .reg = 0x054,
200 .features = CCU_FEATURE_VARIABLE_PREDIV,
201 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
202 ahb1_parents,
203 &ccu_div_ops,
204 0),
205 },
206 };
207
208 static struct clk_div_table apb1_div_table[] = {
209 { .val = 0, .div = 2 },
210 { .val = 1, .div = 2 },
211 { .val = 2, .div = 4 },
212 { .val = 3, .div = 8 },
213 { /* Sentinel */ },
214 };
215 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
216 0x054, 8, 2, apb1_div_table, 0);
217
218 static const char * const apb2_parents[] = { "osc32k", "osc24M",
219 "pll-periph" , "pll-periph" };
220 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
221 0, 5, /* M */
222 16, 2, /* P */
223 24, 2, /* mux */
224 0);
225
226 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
227 0x060, BIT(1), 0);
228 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
229 0x060, BIT(6), 0);
230 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
231 0x060, BIT(8), 0);
232 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
233 0x060, BIT(9), 0);
234 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
235 0x060, BIT(10), 0);
236 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
237 0x060, BIT(13), 0);
238 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
239 0x060, BIT(14), 0);
240 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
241 0x060, BIT(19), 0);
242 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
243 0x060, BIT(20), 0);
244 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
245 0x060, BIT(21), 0);
246 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
247 0x060, BIT(24), 0);
248 static SUNXI_CCU_GATE(bus_ehci_clk, "bus-ehci", "ahb1",
249 0x060, BIT(26), 0);
250 static SUNXI_CCU_GATE(bus_ohci_clk, "bus-ohci", "ahb1",
251 0x060, BIT(29), 0);
252
253 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
254 0x064, BIT(0), 0);
255 static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb1",
256 0x064, BIT(4), 0);
257 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
258 0x064, BIT(8), 0);
259 static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb1",
260 0x064, BIT(12), 0);
261 static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb1",
262 0x064, BIT(14), 0);
263 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
264 0x064, BIT(20), 0);
265 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
266 0x064, BIT(21), 0);
267 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
268 0x064, BIT(22), 0);
269 static SUNXI_CCU_GATE(bus_drc_clk, "bus-drc", "ahb1",
270 0x064, BIT(25), 0);
271
272 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
273 0x068, BIT(0), 0);
274 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
275 0x068, BIT(5), 0);
276 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
277 0x068, BIT(12), 0);
278 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
279 0x068, BIT(13), 0);
280
281 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
282 0x06c, BIT(0), 0);
283 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
284 0x06c, BIT(1), 0);
285 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
286 0x06c, BIT(2), 0);
287 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
288 0x06c, BIT(16), 0);
289 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
290 0x06c, BIT(17), 0);
291 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
292 0x06c, BIT(18), 0);
293 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
294 0x06c, BIT(19), 0);
295 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
296 0x06c, BIT(20), 0);
297
298 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
299 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
300 0, 4, /* M */
301 16, 2, /* P */
302 24, 2, /* mux */
303 BIT(31), /* gate */
304 0);
305
306 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
307 0, 4, /* M */
308 16, 2, /* P */
309 24, 2, /* mux */
310 BIT(31), /* gate */
311 0);
312
313 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
314 0x088, 20, 3, 0);
315 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
316 0x088, 8, 3, 0);
317
318 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
319 0, 4, /* M */
320 16, 2, /* P */
321 24, 2, /* mux */
322 BIT(31), /* gate */
323 0);
324
325 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
326 0x08c, 20, 3, 0);
327 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
328 0x08c, 8, 3, 0);
329
330 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
331 0, 4, /* M */
332 16, 2, /* P */
333 24, 2, /* mux */
334 BIT(31), /* gate */
335 0);
336
337 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
338 0x090, 20, 3, 0);
339 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
340 0x090, 8, 3, 0);
341
342 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
343 0, 4, /* M */
344 16, 2, /* P */
345 24, 2, /* mux */
346 BIT(31), /* gate */
347 0);
348
349 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
350 0, 4, /* M */
351 16, 2, /* P */
352 24, 2, /* mux */
353 BIT(31), /* gate */
354 0);
355
356 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
357 "pll-audio-2x", "pll-audio" };
358 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
359 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
360
361 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
362 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
363
364 /* TODO: the parent for most of the USB clocks is not known */
365 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
366 0x0cc, BIT(8), 0);
367 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
368 0x0cc, BIT(9), 0);
369 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
370 0x0cc, BIT(10), 0);
371 static SUNXI_CCU_GATE(usb_hsic_12M_clk, "usb-hsic-12M", "osc24M",
372 0x0cc, BIT(11), 0);
373 static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "osc24M",
374 0x0cc, BIT(16), 0);
375
376 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
377 0x100, BIT(0), 0);
378 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr",
379 0x100, BIT(1), 0);
380 static SUNXI_CCU_GATE(dram_drc_clk, "dram-drc", "pll-ddr",
381 0x100, BIT(16), 0);
382 static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "pll-ddr",
383 0x100, BIT(24), 0);
384 static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "pll-ddr",
385 0x100, BIT(26), 0);
386
387 static const char * const de_parents[] = { "pll-video", "pll-periph-2x",
388 "pll-gpu", "pll-de" };
389 static const u8 de_table[] = { 0, 2, 3, 5 };
390 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
391 de_parents, de_table,
392 0x104, 0, 4, 24, 3, BIT(31), 0);
393
394 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
395 de_parents, de_table,
396 0x10c, 0, 4, 24, 3, BIT(31), 0);
397
398 static const char * const lcd_ch0_parents[] = { "pll-video", "pll-video-2x",
399 "pll-mipi" };
400 static const u8 lcd_ch0_table[] = { 0, 2, 4 };
401 static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0",
402 lcd_ch0_parents, lcd_ch0_table,
403 0x118, 24, 3, BIT(31),
404 CLK_SET_RATE_PARENT);
405
406 static const char * const lcd_ch1_parents[] = { "pll-video", "pll-video-2x" };
407 static const u8 lcd_ch1_table[] = { 0, 2 };
408 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1",
409 lcd_ch1_parents, lcd_ch1_table,
410 0x12c, 0, 4, 24, 2, BIT(31), 0);
411
412 static const char * const csi_sclk_parents[] = { "pll-video", "pll-de",
413 "pll-mipi", "pll-ve" };
414 static const u8 csi_sclk_table[] = { 0, 3, 4, 5 };
415 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
416 csi_sclk_parents, csi_sclk_table,
417 0x134, 16, 4, 24, 3, BIT(31), 0);
418
419 static const char * const csi_mclk_parents[] = { "pll-video", "pll-de",
420 "osc24M" };
421 static const u8 csi_mclk_table[] = { 0, 3, 5 };
422 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
423 csi_mclk_parents, csi_mclk_table,
424 0x134, 0, 5, 8, 3, BIT(15), 0);
425
426 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
427 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
428
429 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
430 0x140, BIT(31), CLK_SET_RATE_PARENT);
431 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
432 0x144, BIT(31), 0);
433
434 static const char * const mbus_parents[] = { "osc24M", "pll-periph-2x",
435 "pll-ddr" };
436 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
437 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
438
439 static const char * const dsi_sclk_parents[] = { "pll-video", "pll-video-2x" };
440 static const u8 dsi_sclk_table[] = { 0, 2 };
441 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk",
442 dsi_sclk_parents, dsi_sclk_table,
443 0x168, 16, 4, 24, 2, BIT(31), 0);
444
445 static const char * const dsi_dphy_parents[] = { "pll-video", "pll-periph" };
446 static const u8 dsi_dphy_table[] = { 0, 2 };
447 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
448 dsi_dphy_parents, dsi_dphy_table,
449 0x168, 0, 4, 8, 2, BIT(15), 0);
450
451 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(drc_clk, "drc",
452 de_parents, de_table,
453 0x180, 0, 4, 24, 3, BIT(31), 0);
454
455 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
456 0x1a0, 0, 3, BIT(31), 0);
457
458 static const char * const ats_parents[] = { "osc24M", "pll-periph" };
459 static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", ats_parents,
460 0x1b0, 0, 3, 24, 2, BIT(31), 0);
461
462 static struct ccu_common *sun8i_a23_ccu_clks[] = {
463 &pll_cpux_clk.common,
464 &pll_audio_base_clk.common,
465 &pll_video_clk.common,
466 &pll_ve_clk.common,
467 &pll_ddr_clk.common,
468 &pll_periph_clk.common,
469 &pll_gpu_clk.common,
470 &pll_mipi_clk.common,
471 &pll_hsic_clk.common,
472 &pll_de_clk.common,
473 &cpux_clk.common,
474 &axi_clk.common,
475 &ahb1_clk.common,
476 &apb1_clk.common,
477 &apb2_clk.common,
478 &bus_mipi_dsi_clk.common,
479 &bus_dma_clk.common,
480 &bus_mmc0_clk.common,
481 &bus_mmc1_clk.common,
482 &bus_mmc2_clk.common,
483 &bus_nand_clk.common,
484 &bus_dram_clk.common,
485 &bus_hstimer_clk.common,
486 &bus_spi0_clk.common,
487 &bus_spi1_clk.common,
488 &bus_otg_clk.common,
489 &bus_ehci_clk.common,
490 &bus_ohci_clk.common,
491 &bus_ve_clk.common,
492 &bus_lcd_clk.common,
493 &bus_csi_clk.common,
494 &bus_de_fe_clk.common,
495 &bus_de_be_clk.common,
496 &bus_gpu_clk.common,
497 &bus_msgbox_clk.common,
498 &bus_spinlock_clk.common,
499 &bus_drc_clk.common,
500 &bus_codec_clk.common,
501 &bus_pio_clk.common,
502 &bus_i2s0_clk.common,
503 &bus_i2s1_clk.common,
504 &bus_i2c0_clk.common,
505 &bus_i2c1_clk.common,
506 &bus_i2c2_clk.common,
507 &bus_uart0_clk.common,
508 &bus_uart1_clk.common,
509 &bus_uart2_clk.common,
510 &bus_uart3_clk.common,
511 &bus_uart4_clk.common,
512 &nand_clk.common,
513 &mmc0_clk.common,
514 &mmc0_sample_clk.common,
515 &mmc0_output_clk.common,
516 &mmc1_clk.common,
517 &mmc1_sample_clk.common,
518 &mmc1_output_clk.common,
519 &mmc2_clk.common,
520 &mmc2_sample_clk.common,
521 &mmc2_output_clk.common,
522 &spi0_clk.common,
523 &spi1_clk.common,
524 &i2s0_clk.common,
525 &i2s1_clk.common,
526 &usb_phy0_clk.common,
527 &usb_phy1_clk.common,
528 &usb_hsic_clk.common,
529 &usb_hsic_12M_clk.common,
530 &usb_ohci_clk.common,
531 &dram_ve_clk.common,
532 &dram_csi_clk.common,
533 &dram_drc_clk.common,
534 &dram_de_fe_clk.common,
535 &dram_de_be_clk.common,
536 &de_be_clk.common,
537 &de_fe_clk.common,
538 &lcd_ch0_clk.common,
539 &lcd_ch1_clk.common,
540 &csi_sclk_clk.common,
541 &csi_mclk_clk.common,
542 &ve_clk.common,
543 &ac_dig_clk.common,
544 &avs_clk.common,
545 &mbus_clk.common,
546 &dsi_sclk_clk.common,
547 &dsi_dphy_clk.common,
548 &drc_clk.common,
549 &gpu_clk.common,
550 &ats_clk.common,
551 };
552
553 /* We hardcode the divider to 1 for now */
554 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
555 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
556 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
557 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
558 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
559 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
560 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
561 "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
562 static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x",
563 "pll-periph", 1, 2, 0);
564 static CLK_FIXED_FACTOR(pll_video_2x_clk, "pll-video-2x",
565 "pll-video", 1, 2, 0);
566
567 static struct clk_hw_onecell_data sun8i_a23_hw_clks = {
568 .hws = {
569 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
570 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
571 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
572 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
573 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
574 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
575 [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
576 [CLK_PLL_VIDEO_2X] = &pll_video_2x_clk.hw,
577 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
578 [CLK_PLL_DDR0] = &pll_ddr_clk.common.hw,
579 [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
580 [CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.hw,
581 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
582 [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
583 [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw,
584 [CLK_PLL_DE] = &pll_de_clk.common.hw,
585 [CLK_CPUX] = &cpux_clk.common.hw,
586 [CLK_AXI] = &axi_clk.common.hw,
587 [CLK_AHB1] = &ahb1_clk.common.hw,
588 [CLK_APB1] = &apb1_clk.common.hw,
589 [CLK_APB2] = &apb2_clk.common.hw,
590 [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
591 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
592 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
593 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
594 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
595 [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
596 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
597 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
598 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
599 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
600 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
601 [CLK_BUS_EHCI] = &bus_ehci_clk.common.hw,
602 [CLK_BUS_OHCI] = &bus_ohci_clk.common.hw,
603 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
604 [CLK_BUS_LCD] = &bus_lcd_clk.common.hw,
605 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
606 [CLK_BUS_DE_BE] = &bus_de_be_clk.common.hw,
607 [CLK_BUS_DE_FE] = &bus_de_fe_clk.common.hw,
608 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
609 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
610 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
611 [CLK_BUS_DRC] = &bus_drc_clk.common.hw,
612 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
613 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
614 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
615 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
616 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
617 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
618 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
619 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
620 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
621 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
622 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
623 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
624 [CLK_NAND] = &nand_clk.common.hw,
625 [CLK_MMC0] = &mmc0_clk.common.hw,
626 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
627 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
628 [CLK_MMC1] = &mmc1_clk.common.hw,
629 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
630 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
631 [CLK_MMC2] = &mmc2_clk.common.hw,
632 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
633 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
634 [CLK_SPI0] = &spi0_clk.common.hw,
635 [CLK_SPI1] = &spi1_clk.common.hw,
636 [CLK_I2S0] = &i2s0_clk.common.hw,
637 [CLK_I2S1] = &i2s1_clk.common.hw,
638 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
639 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
640 [CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
641 [CLK_USB_HSIC_12M] = &usb_hsic_12M_clk.common.hw,
642 [CLK_USB_OHCI] = &usb_ohci_clk.common.hw,
643 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
644 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
645 [CLK_DRAM_DRC] = &dram_drc_clk.common.hw,
646 [CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw,
647 [CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw,
648 [CLK_DE_BE] = &de_be_clk.common.hw,
649 [CLK_DE_FE] = &de_fe_clk.common.hw,
650 [CLK_LCD_CH0] = &lcd_ch0_clk.common.hw,
651 [CLK_LCD_CH1] = &lcd_ch1_clk.common.hw,
652 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
653 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
654 [CLK_VE] = &ve_clk.common.hw,
655 [CLK_AC_DIG] = &ac_dig_clk.common.hw,
656 [CLK_AVS] = &avs_clk.common.hw,
657 [CLK_MBUS] = &mbus_clk.common.hw,
658 [CLK_DSI_SCLK] = &dsi_sclk_clk.common.hw,
659 [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw,
660 [CLK_DRC] = &drc_clk.common.hw,
661 [CLK_GPU] = &gpu_clk.common.hw,
662 [CLK_ATS] = &ats_clk.common.hw,
663 },
664 .num = CLK_NUMBER,
665 };
666
667 static struct ccu_reset_map sun8i_a23_ccu_resets[] = {
668 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
669 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
670 [RST_USB_HSIC] = { 0x0cc, BIT(2) },
671
672 [RST_MBUS] = { 0x0fc, BIT(31) },
673
674 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
675 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
676 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
677 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
678 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
679 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
680 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
681 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
682 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
683 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
684 [RST_BUS_OTG] = { 0x2c0, BIT(24) },
685 [RST_BUS_EHCI] = { 0x2c0, BIT(26) },
686 [RST_BUS_OHCI] = { 0x2c0, BIT(29) },
687
688 [RST_BUS_VE] = { 0x2c4, BIT(0) },
689 [RST_BUS_LCD] = { 0x2c4, BIT(4) },
690 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
691 [RST_BUS_DE_BE] = { 0x2c4, BIT(12) },
692 [RST_BUS_DE_FE] = { 0x2c4, BIT(14) },
693 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
694 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
695 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
696 [RST_BUS_DRC] = { 0x2c4, BIT(25) },
697
698 [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
699
700 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
701 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
702 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
703
704 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
705 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
706 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
707 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
708 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
709 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
710 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
711 [RST_BUS_UART4] = { 0x2d8, BIT(20) },
712 };
713
714 static const struct sunxi_ccu_desc sun8i_a23_ccu_desc = {
715 .ccu_clks = sun8i_a23_ccu_clks,
716 .num_ccu_clks = ARRAY_SIZE(sun8i_a23_ccu_clks),
717
718 .hw_clks = &sun8i_a23_hw_clks,
719
720 .resets = sun8i_a23_ccu_resets,
721 .num_resets = ARRAY_SIZE(sun8i_a23_ccu_resets),
722 };
723
724 static void __init sun8i_a23_ccu_setup(struct device_node *node)
725 {
726 void __iomem *reg;
727 u32 val;
728
729 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
730 if (IS_ERR(reg)) {
731 pr_err("%pOF: Could not map the clock registers\n", node);
732 return;
733 }
734
735 /* Force the PLL-Audio-1x divider to 1 */
736 val = readl(reg + SUN8I_A23_PLL_AUDIO_REG);
737 val &= ~GENMASK(19, 16);
738 writel(val | (0 << 16), reg + SUN8I_A23_PLL_AUDIO_REG);
739
740 /* Force PLL-MIPI to MIPI mode */
741 val = readl(reg + SUN8I_A23_PLL_MIPI_REG);
742 val &= ~BIT(16);
743 writel(val, reg + SUN8I_A23_PLL_MIPI_REG);
744
745 sunxi_ccu_probe(node, reg, &sun8i_a23_ccu_desc);
746 }
747 CLK_OF_DECLARE(sun8i_a23_ccu, "allwinner,sun8i-a23-ccu",
748 sun8i_a23_ccu_setup);
ubuntu-bionic-kernel mirror