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ASoC: sti: fix missing clk_disable_unprepare() on error in uni_player_start()
[mirror_ubuntu-bionic-kernel.git] / drivers / clk / sunxi-ng / ccu-sun8i-h3.c
1 /*
2 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/clk-provider.h>
15 #include <linux/of_address.h>
16
17 #include "ccu_common.h"
18 #include "ccu_reset.h"
19
20 #include "ccu_div.h"
21 #include "ccu_gate.h"
22 #include "ccu_mp.h"
23 #include "ccu_mult.h"
24 #include "ccu_nk.h"
25 #include "ccu_nkm.h"
26 #include "ccu_nkmp.h"
27 #include "ccu_nm.h"
28 #include "ccu_phase.h"
29
30 #include "ccu-sun8i-h3.h"
31
32 static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",
33 "osc24M", 0x000,
34 8, 5, /* N */
35 4, 2, /* K */
36 0, 2, /* M */
37 16, 2, /* P */
38 BIT(31), /* gate */
39 BIT(28), /* lock */
40 0);
41
42 /*
43 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
44 * the base (2x, 4x and 8x), and one variable divider (the one true
45 * pll audio).
46 *
47 * We don't have any need for the variable divider for now, so we just
48 * hardcode it to match with the clock names
49 */
50 #define SUN8I_H3_PLL_AUDIO_REG 0x008
51
52 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
53 "osc24M", 0x008,
54 8, 7, /* N */
55 0, 5, /* M */
56 BIT(31), /* gate */
57 BIT(28), /* lock */
58 0);
59
60 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
61 "osc24M", 0x0010,
62 8, 7, /* N */
63 0, 4, /* M */
64 BIT(24), /* frac enable */
65 BIT(25), /* frac select */
66 270000000, /* frac rate 0 */
67 297000000, /* frac rate 1 */
68 BIT(31), /* gate */
69 BIT(28), /* lock */
70 0);
71
72 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
73 "osc24M", 0x0018,
74 8, 7, /* N */
75 0, 4, /* M */
76 BIT(24), /* frac enable */
77 BIT(25), /* frac select */
78 270000000, /* frac rate 0 */
79 297000000, /* frac rate 1 */
80 BIT(31), /* gate */
81 BIT(28), /* lock */
82 0);
83
84 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
85 "osc24M", 0x020,
86 8, 5, /* N */
87 4, 2, /* K */
88 0, 2, /* M */
89 BIT(31), /* gate */
90 BIT(28), /* lock */
91 0);
92
93 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",
94 "osc24M", 0x028,
95 8, 5, /* N */
96 4, 2, /* K */
97 BIT(31), /* gate */
98 BIT(28), /* lock */
99 2, /* post-div */
100 0);
101
102 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
103 "osc24M", 0x0038,
104 8, 7, /* N */
105 0, 4, /* M */
106 BIT(24), /* frac enable */
107 BIT(25), /* frac select */
108 270000000, /* frac rate 0 */
109 297000000, /* frac rate 1 */
110 BIT(31), /* gate */
111 BIT(28), /* lock */
112 0);
113
114 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",
115 "osc24M", 0x044,
116 8, 5, /* N */
117 4, 2, /* K */
118 BIT(31), /* gate */
119 BIT(28), /* lock */
120 2, /* post-div */
121 0);
122
123 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
124 "osc24M", 0x0048,
125 8, 7, /* N */
126 0, 4, /* M */
127 BIT(24), /* frac enable */
128 BIT(25), /* frac select */
129 270000000, /* frac rate 0 */
130 297000000, /* frac rate 1 */
131 BIT(31), /* gate */
132 BIT(28), /* lock */
133 0);
134
135 static const char * const cpux_parents[] = { "osc32k", "osc24M",
136 "pll-cpux" , "pll-cpux" };
137 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
138 0x050, 16, 2, CLK_IS_CRITICAL);
139
140 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
141
142 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
143 "axi" , "pll-periph0" };
144 static struct ccu_div ahb1_clk = {
145 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
146
147 .mux = {
148 .shift = 12,
149 .width = 2,
150
151 .variable_prediv = {
152 .index = 3,
153 .shift = 6,
154 .width = 2,
155 },
156 },
157
158 .common = {
159 .reg = 0x054,
160 .features = CCU_FEATURE_VARIABLE_PREDIV,
161 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
162 ahb1_parents,
163 &ccu_div_ops,
164 0),
165 },
166 };
167
168 static struct clk_div_table apb1_div_table[] = {
169 { .val = 0, .div = 2 },
170 { .val = 1, .div = 2 },
171 { .val = 2, .div = 4 },
172 { .val = 3, .div = 8 },
173 { /* Sentinel */ },
174 };
175 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
176 0x054, 8, 2, apb1_div_table, 0);
177
178 static const char * const apb2_parents[] = { "osc32k", "osc24M",
179 "pll-periph0" , "pll-periph0" };
180 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
181 0, 5, /* M */
182 16, 2, /* P */
183 24, 2, /* mux */
184 0);
185
186 static const char * const ahb2_parents[] = { "ahb1" , "pll-periph0" };
187 static struct ccu_mux ahb2_clk = {
188 .mux = {
189 .shift = 0,
190 .width = 1,
191
192 .fixed_prediv = {
193 .index = 1,
194 .div = 2,
195 },
196 },
197
198 .common = {
199 .reg = 0x05c,
200 .features = CCU_FEATURE_FIXED_PREDIV,
201 .hw.init = CLK_HW_INIT_PARENTS("ahb2",
202 ahb2_parents,
203 &ccu_mux_ops,
204 0),
205 },
206 };
207
208 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
209 0x060, BIT(5), 0);
210 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
211 0x060, BIT(6), 0);
212 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
213 0x060, BIT(8), 0);
214 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
215 0x060, BIT(9), 0);
216 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
217 0x060, BIT(10), 0);
218 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
219 0x060, BIT(13), 0);
220 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
221 0x060, BIT(14), 0);
222 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
223 0x060, BIT(17), 0);
224 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1",
225 0x060, BIT(18), 0);
226 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
227 0x060, BIT(19), 0);
228 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
229 0x060, BIT(20), 0);
230 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
231 0x060, BIT(21), 0);
232 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
233 0x060, BIT(23), 0);
234 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
235 0x060, BIT(24), 0);
236 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2",
237 0x060, BIT(25), 0);
238 static SUNXI_CCU_GATE(bus_ehci2_clk, "bus-ehci2", "ahb2",
239 0x060, BIT(26), 0);
240 static SUNXI_CCU_GATE(bus_ehci3_clk, "bus-ehci3", "ahb2",
241 0x060, BIT(27), 0);
242 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
243 0x060, BIT(28), 0);
244 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb2",
245 0x060, BIT(29), 0);
246 static SUNXI_CCU_GATE(bus_ohci2_clk, "bus-ohci2", "ahb2",
247 0x060, BIT(30), 0);
248 static SUNXI_CCU_GATE(bus_ohci3_clk, "bus-ohci3", "ahb2",
249 0x060, BIT(31), 0);
250
251 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
252 0x064, BIT(0), 0);
253 static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",
254 0x064, BIT(3), 0);
255 static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1",
256 0x064, BIT(4), 0);
257 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1",
258 0x064, BIT(5), 0);
259 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
260 0x064, BIT(8), 0);
261 static SUNXI_CCU_GATE(bus_tve_clk, "bus-tve", "ahb1",
262 0x064, BIT(9), 0);
263 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1",
264 0x064, BIT(11), 0);
265 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
266 0x064, BIT(12), 0);
267 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
268 0x064, BIT(20), 0);
269 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
270 0x064, BIT(21), 0);
271 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
272 0x064, BIT(22), 0);
273
274 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
275 0x068, BIT(0), 0);
276 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
277 0x068, BIT(1), 0);
278 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
279 0x068, BIT(5), 0);
280 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1",
281 0x068, BIT(8), 0);
282 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
283 0x068, BIT(12), 0);
284 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
285 0x068, BIT(13), 0);
286 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
287 0x068, BIT(14), 0);
288
289 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
290 0x06c, BIT(0), 0);
291 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
292 0x06c, BIT(1), 0);
293 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
294 0x06c, BIT(2), 0);
295 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
296 0x06c, BIT(16), 0);
297 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
298 0x06c, BIT(17), 0);
299 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
300 0x06c, BIT(18), 0);
301 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
302 0x06c, BIT(19), 0);
303 static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2",
304 0x06c, BIT(20), 0);
305
306 static SUNXI_CCU_GATE(bus_ephy_clk, "bus-ephy", "ahb1",
307 0x070, BIT(0), 0);
308 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
309 0x070, BIT(7), 0);
310
311 static struct clk_div_table ths_div_table[] = {
312 { .val = 0, .div = 1 },
313 { .val = 1, .div = 2 },
314 { .val = 2, .div = 4 },
315 { .val = 3, .div = 6 },
316 };
317 static SUNXI_CCU_DIV_TABLE_WITH_GATE(ths_clk, "ths", "osc24M",
318 0x074, 0, 2, ths_div_table, BIT(31), 0);
319
320 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
321 "pll-periph1" };
322 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
323 0, 4, /* M */
324 16, 2, /* P */
325 24, 2, /* mux */
326 BIT(31), /* gate */
327 0);
328
329 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
330 0, 4, /* M */
331 16, 2, /* P */
332 24, 2, /* mux */
333 BIT(31), /* gate */
334 0);
335
336 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
337 0x088, 20, 3, 0);
338 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
339 0x088, 8, 3, 0);
340
341 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
342 0, 4, /* M */
343 16, 2, /* P */
344 24, 2, /* mux */
345 BIT(31), /* gate */
346 0);
347
348 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
349 0x08c, 20, 3, 0);
350 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
351 0x08c, 8, 3, 0);
352
353 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
354 0, 4, /* M */
355 16, 2, /* P */
356 24, 2, /* mux */
357 BIT(31), /* gate */
358 0);
359
360 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
361 0x090, 20, 3, 0);
362 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
363 0x090, 8, 3, 0);
364
365 static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
366 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
367 0, 4, /* M */
368 16, 2, /* P */
369 24, 2, /* mux */
370 BIT(31), /* gate */
371 0);
372
373 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mod0_default_parents, 0x09c,
374 0, 4, /* M */
375 16, 2, /* P */
376 24, 2, /* mux */
377 BIT(31), /* gate */
378 0);
379
380 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
381 0, 4, /* M */
382 16, 2, /* P */
383 24, 2, /* mux */
384 BIT(31), /* gate */
385 0);
386
387 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
388 0, 4, /* M */
389 16, 2, /* P */
390 24, 2, /* mux */
391 BIT(31), /* gate */
392 0);
393
394 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
395 "pll-audio-2x", "pll-audio" };
396 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
397 0x0b0, 16, 2, BIT(31), 0);
398
399 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
400 0x0b4, 16, 2, BIT(31), 0);
401
402 static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
403 0x0b8, 16, 2, BIT(31), 0);
404
405 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
406 0x0c0, 0, 4, BIT(31), 0);
407
408 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
409 0x0cc, BIT(8), 0);
410 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
411 0x0cc, BIT(9), 0);
412 static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M",
413 0x0cc, BIT(10), 0);
414 static SUNXI_CCU_GATE(usb_phy3_clk, "usb-phy3", "osc24M",
415 0x0cc, BIT(11), 0);
416 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",
417 0x0cc, BIT(16), 0);
418 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc24M",
419 0x0cc, BIT(17), 0);
420 static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M",
421 0x0cc, BIT(18), 0);
422 static SUNXI_CCU_GATE(usb_ohci3_clk, "usb-ohci3", "osc24M",
423 0x0cc, BIT(19), 0);
424
425 static const char * const dram_parents[] = { "pll-ddr", "pll-periph0-2x" };
426 static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
427 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
428
429 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
430 0x100, BIT(0), 0);
431 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
432 0x100, BIT(1), 0);
433 static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
434 0x100, BIT(2), 0);
435 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
436 0x100, BIT(3), 0);
437
438 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
439 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
440 0x104, 0, 4, 24, 3, BIT(31), 0);
441
442 static const char * const tcon_parents[] = { "pll-video" };
443 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
444 0x118, 0, 4, 24, 3, BIT(31), 0);
445
446 static const char * const tve_parents[] = { "pll-de", "pll-periph1" };
447 static SUNXI_CCU_M_WITH_MUX_GATE(tve_clk, "tve", tve_parents,
448 0x120, 0, 4, 24, 3, BIT(31), 0);
449
450 static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
451 static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,
452 0x124, 0, 4, 24, 3, BIT(31), 0);
453
454 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M",
455 0x130, BIT(31), 0);
456
457 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
458 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
459 0x134, 16, 4, 24, 3, BIT(31), 0);
460
461 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video", "pll-periph0" };
462 static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
463 0x134, 0, 5, 8, 3, BIT(15), 0);
464
465 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
466 0x13c, 16, 3, BIT(31), 0);
467
468 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
469 0x140, BIT(31), 0);
470 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
471 0x144, BIT(31), 0);
472
473 static const char * const hdmi_parents[] = { "pll-video" };
474 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
475 0x150, 0, 4, 24, 2, BIT(31), 0);
476
477 static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
478 0x154, BIT(31), 0);
479
480 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", "pll-ddr" };
481 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
482 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
483
484 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
485 0x1a0, 0, 3, BIT(31), 0);
486
487 static struct ccu_common *sun8i_h3_ccu_clks[] = {
488 &pll_cpux_clk.common,
489 &pll_audio_base_clk.common,
490 &pll_video_clk.common,
491 &pll_ve_clk.common,
492 &pll_ddr_clk.common,
493 &pll_periph0_clk.common,
494 &pll_gpu_clk.common,
495 &pll_periph1_clk.common,
496 &pll_de_clk.common,
497 &cpux_clk.common,
498 &axi_clk.common,
499 &ahb1_clk.common,
500 &apb1_clk.common,
501 &apb2_clk.common,
502 &ahb2_clk.common,
503 &bus_ce_clk.common,
504 &bus_dma_clk.common,
505 &bus_mmc0_clk.common,
506 &bus_mmc1_clk.common,
507 &bus_mmc2_clk.common,
508 &bus_nand_clk.common,
509 &bus_dram_clk.common,
510 &bus_emac_clk.common,
511 &bus_ts_clk.common,
512 &bus_hstimer_clk.common,
513 &bus_spi0_clk.common,
514 &bus_spi1_clk.common,
515 &bus_otg_clk.common,
516 &bus_ehci0_clk.common,
517 &bus_ehci1_clk.common,
518 &bus_ehci2_clk.common,
519 &bus_ehci3_clk.common,
520 &bus_ohci0_clk.common,
521 &bus_ohci1_clk.common,
522 &bus_ohci2_clk.common,
523 &bus_ohci3_clk.common,
524 &bus_ve_clk.common,
525 &bus_tcon0_clk.common,
526 &bus_tcon1_clk.common,
527 &bus_deinterlace_clk.common,
528 &bus_csi_clk.common,
529 &bus_tve_clk.common,
530 &bus_hdmi_clk.common,
531 &bus_de_clk.common,
532 &bus_gpu_clk.common,
533 &bus_msgbox_clk.common,
534 &bus_spinlock_clk.common,
535 &bus_codec_clk.common,
536 &bus_spdif_clk.common,
537 &bus_pio_clk.common,
538 &bus_ths_clk.common,
539 &bus_i2s0_clk.common,
540 &bus_i2s1_clk.common,
541 &bus_i2s2_clk.common,
542 &bus_i2c0_clk.common,
543 &bus_i2c1_clk.common,
544 &bus_i2c2_clk.common,
545 &bus_uart0_clk.common,
546 &bus_uart1_clk.common,
547 &bus_uart2_clk.common,
548 &bus_uart3_clk.common,
549 &bus_scr_clk.common,
550 &bus_ephy_clk.common,
551 &bus_dbg_clk.common,
552 &ths_clk.common,
553 &nand_clk.common,
554 &mmc0_clk.common,
555 &mmc0_sample_clk.common,
556 &mmc0_output_clk.common,
557 &mmc1_clk.common,
558 &mmc1_sample_clk.common,
559 &mmc1_output_clk.common,
560 &mmc2_clk.common,
561 &mmc2_sample_clk.common,
562 &mmc2_output_clk.common,
563 &ts_clk.common,
564 &ce_clk.common,
565 &spi0_clk.common,
566 &spi1_clk.common,
567 &i2s0_clk.common,
568 &i2s1_clk.common,
569 &i2s2_clk.common,
570 &spdif_clk.common,
571 &usb_phy0_clk.common,
572 &usb_phy1_clk.common,
573 &usb_phy2_clk.common,
574 &usb_phy3_clk.common,
575 &usb_ohci0_clk.common,
576 &usb_ohci1_clk.common,
577 &usb_ohci2_clk.common,
578 &usb_ohci3_clk.common,
579 &dram_clk.common,
580 &dram_ve_clk.common,
581 &dram_csi_clk.common,
582 &dram_deinterlace_clk.common,
583 &dram_ts_clk.common,
584 &de_clk.common,
585 &tcon_clk.common,
586 &tve_clk.common,
587 &deinterlace_clk.common,
588 &csi_misc_clk.common,
589 &csi_sclk_clk.common,
590 &csi_mclk_clk.common,
591 &ve_clk.common,
592 &ac_dig_clk.common,
593 &avs_clk.common,
594 &hdmi_clk.common,
595 &hdmi_ddc_clk.common,
596 &mbus_clk.common,
597 &gpu_clk.common,
598 };
599
600 /* We hardcode the divider to 4 for now */
601 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
602 "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
603 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
604 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
605 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
606 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
607 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
608 "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
609 static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
610 "pll-periph0", 1, 2, 0);
611
612 static struct clk_hw_onecell_data sun8i_h3_hw_clks = {
613 .hws = {
614 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
615 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
616 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
617 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
618 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
619 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
620 [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
621 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
622 [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
623 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
624 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
625 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
626 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
627 [CLK_PLL_DE] = &pll_de_clk.common.hw,
628 [CLK_CPUX] = &cpux_clk.common.hw,
629 [CLK_AXI] = &axi_clk.common.hw,
630 [CLK_AHB1] = &ahb1_clk.common.hw,
631 [CLK_APB1] = &apb1_clk.common.hw,
632 [CLK_APB2] = &apb2_clk.common.hw,
633 [CLK_AHB2] = &ahb2_clk.common.hw,
634 [CLK_BUS_CE] = &bus_ce_clk.common.hw,
635 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
636 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
637 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
638 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
639 [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
640 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
641 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
642 [CLK_BUS_TS] = &bus_ts_clk.common.hw,
643 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
644 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
645 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
646 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
647 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
648 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
649 [CLK_BUS_EHCI2] = &bus_ehci2_clk.common.hw,
650 [CLK_BUS_EHCI3] = &bus_ehci3_clk.common.hw,
651 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
652 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
653 [CLK_BUS_OHCI2] = &bus_ohci2_clk.common.hw,
654 [CLK_BUS_OHCI3] = &bus_ohci3_clk.common.hw,
655 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
656 [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
657 [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw,
658 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
659 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
660 [CLK_BUS_TVE] = &bus_tve_clk.common.hw,
661 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
662 [CLK_BUS_DE] = &bus_de_clk.common.hw,
663 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
664 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
665 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
666 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
667 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
668 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
669 [CLK_BUS_THS] = &bus_ths_clk.common.hw,
670 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
671 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
672 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
673 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
674 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
675 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
676 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
677 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
678 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
679 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
680 [CLK_BUS_SCR] = &bus_scr_clk.common.hw,
681 [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw,
682 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
683 [CLK_THS] = &ths_clk.common.hw,
684 [CLK_NAND] = &nand_clk.common.hw,
685 [CLK_MMC0] = &mmc0_clk.common.hw,
686 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
687 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
688 [CLK_MMC1] = &mmc1_clk.common.hw,
689 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
690 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
691 [CLK_MMC2] = &mmc2_clk.common.hw,
692 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
693 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
694 [CLK_TS] = &ts_clk.common.hw,
695 [CLK_CE] = &ce_clk.common.hw,
696 [CLK_SPI0] = &spi0_clk.common.hw,
697 [CLK_SPI1] = &spi1_clk.common.hw,
698 [CLK_I2S0] = &i2s0_clk.common.hw,
699 [CLK_I2S1] = &i2s1_clk.common.hw,
700 [CLK_I2S2] = &i2s2_clk.common.hw,
701 [CLK_SPDIF] = &spdif_clk.common.hw,
702 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
703 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
704 [CLK_USB_PHY2] = &usb_phy2_clk.common.hw,
705 [CLK_USB_PHY3] = &usb_phy3_clk.common.hw,
706 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
707 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
708 [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
709 [CLK_USB_OHCI3] = &usb_ohci3_clk.common.hw,
710 [CLK_DRAM] = &dram_clk.common.hw,
711 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
712 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
713 [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
714 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
715 [CLK_DE] = &de_clk.common.hw,
716 [CLK_TCON0] = &tcon_clk.common.hw,
717 [CLK_TVE] = &tve_clk.common.hw,
718 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
719 [CLK_CSI_MISC] = &csi_misc_clk.common.hw,
720 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
721 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
722 [CLK_VE] = &ve_clk.common.hw,
723 [CLK_AC_DIG] = &ac_dig_clk.common.hw,
724 [CLK_AVS] = &avs_clk.common.hw,
725 [CLK_HDMI] = &hdmi_clk.common.hw,
726 [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,
727 [CLK_MBUS] = &mbus_clk.common.hw,
728 [CLK_GPU] = &gpu_clk.common.hw,
729 },
730 .num = CLK_NUMBER,
731 };
732
733 static struct ccu_reset_map sun8i_h3_ccu_resets[] = {
734 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
735 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
736 [RST_USB_PHY2] = { 0x0cc, BIT(2) },
737 [RST_USB_PHY3] = { 0x0cc, BIT(3) },
738
739 [RST_MBUS] = { 0x0fc, BIT(31) },
740
741 [RST_BUS_CE] = { 0x2c0, BIT(5) },
742 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
743 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
744 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
745 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
746 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
747 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
748 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
749 [RST_BUS_TS] = { 0x2c0, BIT(18) },
750 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
751 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
752 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
753 [RST_BUS_OTG] = { 0x2c0, BIT(23) },
754 [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
755 [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
756 [RST_BUS_EHCI2] = { 0x2c0, BIT(26) },
757 [RST_BUS_EHCI3] = { 0x2c0, BIT(27) },
758 [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
759 [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
760 [RST_BUS_OHCI2] = { 0x2c0, BIT(30) },
761 [RST_BUS_OHCI3] = { 0x2c0, BIT(31) },
762
763 [RST_BUS_VE] = { 0x2c4, BIT(0) },
764 [RST_BUS_TCON0] = { 0x2c4, BIT(3) },
765 [RST_BUS_TCON1] = { 0x2c4, BIT(4) },
766 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
767 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
768 [RST_BUS_TVE] = { 0x2c4, BIT(9) },
769 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
770 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
771 [RST_BUS_DE] = { 0x2c4, BIT(12) },
772 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
773 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
774 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
775 [RST_BUS_DBG] = { 0x2c4, BIT(31) },
776
777 [RST_BUS_EPHY] = { 0x2c8, BIT(2) },
778
779 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
780 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
781 [RST_BUS_THS] = { 0x2d0, BIT(8) },
782 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
783 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
784 [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
785
786 [RST_BUS_I2C0] = { 0x2d4, BIT(0) },
787 [RST_BUS_I2C1] = { 0x2d4, BIT(1) },
788 [RST_BUS_I2C2] = { 0x2d4, BIT(2) },
789 [RST_BUS_UART0] = { 0x2d4, BIT(16) },
790 [RST_BUS_UART1] = { 0x2d4, BIT(17) },
791 [RST_BUS_UART2] = { 0x2d4, BIT(18) },
792 [RST_BUS_UART3] = { 0x2d4, BIT(19) },
793 [RST_BUS_SCR] = { 0x2d4, BIT(20) },
794 };
795
796 static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = {
797 .ccu_clks = sun8i_h3_ccu_clks,
798 .num_ccu_clks = ARRAY_SIZE(sun8i_h3_ccu_clks),
799
800 .hw_clks = &sun8i_h3_hw_clks,
801
802 .resets = sun8i_h3_ccu_resets,
803 .num_resets = ARRAY_SIZE(sun8i_h3_ccu_resets),
804 };
805
806 static void __init sun8i_h3_ccu_setup(struct device_node *node)
807 {
808 void __iomem *reg;
809 u32 val;
810
811 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
812 if (IS_ERR(reg)) {
813 pr_err("%s: Could not map the clock registers\n",
814 of_node_full_name(node));
815 return;
816 }
817
818 /* Force the PLL-Audio-1x divider to 4 */
819 val = readl(reg + SUN8I_H3_PLL_AUDIO_REG);
820 val &= ~GENMASK(19, 16);
821 writel(val | (3 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
822
823 sunxi_ccu_probe(node, reg, &sun8i_h3_ccu_desc);
824 }
825 CLK_OF_DECLARE(sun8i_h3_ccu, "allwinner,sun8i-h3-ccu",
826 sun8i_h3_ccu_setup);
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