2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/err.h>
24 #include <soc/tegra/fuse.h>
28 static DEFINE_SPINLOCK(periph_ref_lock
);
30 /* Macros to assist peripheral gate clock */
31 #define read_enb(gate) \
32 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
33 #define write_enb_set(val, gate) \
34 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
35 #define write_enb_clr(val, gate) \
36 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
38 #define read_rst(gate) \
39 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
40 #define write_rst_clr(val, gate) \
41 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
43 #define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32))
45 #define LVL2_CLK_GATE_OVRE 0x554
47 /* Peripheral gate clock ops */
48 static int clk_periph_is_enabled(struct clk_hw
*hw
)
50 struct tegra_clk_periph_gate
*gate
= to_clk_periph_gate(hw
);
53 if (!(read_enb(gate
) & periph_clk_to_bit(gate
)))
56 if (!(gate
->flags
& TEGRA_PERIPH_NO_RESET
))
57 if (read_rst(gate
) & periph_clk_to_bit(gate
))
63 static int clk_periph_enable(struct clk_hw
*hw
)
65 struct tegra_clk_periph_gate
*gate
= to_clk_periph_gate(hw
);
66 unsigned long flags
= 0;
68 spin_lock_irqsave(&periph_ref_lock
, flags
);
70 gate
->enable_refcnt
[gate
->clk_num
]++;
71 if (gate
->enable_refcnt
[gate
->clk_num
] > 1) {
72 spin_unlock_irqrestore(&periph_ref_lock
, flags
);
76 write_enb_set(periph_clk_to_bit(gate
), gate
);
79 if (!(gate
->flags
& TEGRA_PERIPH_NO_RESET
) &&
80 !(gate
->flags
& TEGRA_PERIPH_MANUAL_RESET
)) {
81 if (read_rst(gate
) & periph_clk_to_bit(gate
)) {
82 udelay(5); /* reset propogation delay */
83 write_rst_clr(periph_clk_to_bit(gate
), gate
);
87 if (gate
->flags
& TEGRA_PERIPH_WAR_1005168
) {
88 writel_relaxed(0, gate
->clk_base
+ LVL2_CLK_GATE_OVRE
);
89 writel_relaxed(BIT(22), gate
->clk_base
+ LVL2_CLK_GATE_OVRE
);
91 writel_relaxed(0, gate
->clk_base
+ LVL2_CLK_GATE_OVRE
);
94 spin_unlock_irqrestore(&periph_ref_lock
, flags
);
99 static void clk_periph_disable(struct clk_hw
*hw
)
101 struct tegra_clk_periph_gate
*gate
= to_clk_periph_gate(hw
);
102 unsigned long flags
= 0;
104 spin_lock_irqsave(&periph_ref_lock
, flags
);
106 gate
->enable_refcnt
[gate
->clk_num
]--;
107 if (gate
->enable_refcnt
[gate
->clk_num
] > 0) {
108 spin_unlock_irqrestore(&periph_ref_lock
, flags
);
113 * If peripheral is in the APB bus then read the APB bus to
114 * flush the write operation in apb bus. This will avoid the
115 * peripheral access after disabling clock
117 if (gate
->flags
& TEGRA_PERIPH_ON_APB
)
120 write_enb_clr(periph_clk_to_bit(gate
), gate
);
122 spin_unlock_irqrestore(&periph_ref_lock
, flags
);
125 const struct clk_ops tegra_clk_periph_gate_ops
= {
126 .is_enabled
= clk_periph_is_enabled
,
127 .enable
= clk_periph_enable
,
128 .disable
= clk_periph_disable
,
131 struct clk
*tegra_clk_register_periph_gate(const char *name
,
132 const char *parent_name
, u8 gate_flags
, void __iomem
*clk_base
,
133 unsigned long flags
, int clk_num
, int *enable_refcnt
)
135 struct tegra_clk_periph_gate
*gate
;
137 struct clk_init_data init
;
138 struct tegra_clk_periph_regs
*pregs
;
140 pregs
= get_reg_bank(clk_num
);
142 return ERR_PTR(-EINVAL
);
144 gate
= kzalloc(sizeof(*gate
), GFP_KERNEL
);
146 pr_err("%s: could not allocate periph gate clk\n", __func__
);
147 return ERR_PTR(-ENOMEM
);
152 init
.parent_names
= parent_name
? &parent_name
: NULL
;
153 init
.num_parents
= parent_name
? 1 : 0;
154 init
.ops
= &tegra_clk_periph_gate_ops
;
156 gate
->magic
= TEGRA_CLK_PERIPH_GATE_MAGIC
;
157 gate
->clk_base
= clk_base
;
158 gate
->clk_num
= clk_num
;
159 gate
->flags
= gate_flags
;
160 gate
->enable_refcnt
= enable_refcnt
;
163 /* Data in .init is copied by clk_register(), so stack variable OK */
164 gate
->hw
.init
= &init
;
166 clk
= clk_register(NULL
, &gate
->hw
);