drivers/clk/tegra/clk-pll-out.c

   1 /*
   2  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/io.h>
  19 #include <linux/err.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/clk-provider.h>
  23 #include <linux/clk.h>
  24
  25 #include "clk.h"
  26
  27 #define pll_out_enb(p) (BIT(p->enb_bit_idx))
  28 #define pll_out_rst(p) (BIT(p->rst_bit_idx))
  29
  30 static int clk_pll_out_is_enabled(struct clk_hw *hw)
  31 {
  32         struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
  33         u32 val = readl_relaxed(pll_out->reg);
  34         int state;
  35
  36         state = (val & pll_out_enb(pll_out)) ? 1 : 0;
  37         if (!(val & (pll_out_rst(pll_out))))
  38                 state = 0;
  39         return state;
  40 }
  41
  42 static int clk_pll_out_enable(struct clk_hw *hw)
  43 {
  44         struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
  45         unsigned long flags = 0;
  46         u32 val;
  47
  48         if (pll_out->lock)
  49                 spin_lock_irqsave(pll_out->lock, flags);
  50
  51         val = readl_relaxed(pll_out->reg);
  52
  53         val |= (pll_out_enb(pll_out) | pll_out_rst(pll_out));
  54
  55         writel_relaxed(val, pll_out->reg);
  56         udelay(2);
  57
  58         if (pll_out->lock)
  59                 spin_unlock_irqrestore(pll_out->lock, flags);
  60
  61         return 0;
  62 }
  63
  64 static void clk_pll_out_disable(struct clk_hw *hw)
  65 {
  66         struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
  67         unsigned long flags = 0;
  68         u32 val;
  69
  70         if (pll_out->lock)
  71                 spin_lock_irqsave(pll_out->lock, flags);
  72
  73         val = readl_relaxed(pll_out->reg);
  74
  75         val &= ~(pll_out_enb(pll_out) | pll_out_rst(pll_out));
  76
  77         writel_relaxed(val, pll_out->reg);
  78         udelay(2);
  79
  80         if (pll_out->lock)
  81                 spin_unlock_irqrestore(pll_out->lock, flags);
  82 }
  83
  84 const struct clk_ops tegra_clk_pll_out_ops = {
  85         .is_enabled = clk_pll_out_is_enabled,
  86         .enable = clk_pll_out_enable,
  87         .disable = clk_pll_out_disable,
  88 };
  89
  90 struct clk *tegra_clk_register_pll_out(const char *name,
  91                 const char *parent_name, void __iomem *reg, u8 enb_bit_idx,
  92                 u8 rst_bit_idx, unsigned long flags, u8 pll_out_flags,
  93                 spinlock_t *lock)
  94 {
  95         struct tegra_clk_pll_out *pll_out;
  96         struct clk *clk;
  97         struct clk_init_data init;
  98
  99         pll_out = kzalloc(sizeof(*pll_out), GFP_KERNEL);
 100         if (!pll_out)
 101                 return ERR_PTR(-ENOMEM);
 102
 103         init.name = name;
 104         init.ops = &tegra_clk_pll_out_ops;
 105         init.parent_names = (parent_name ? &parent_name : NULL);
 106         init.num_parents = (parent_name ? 1 : 0);
 107         init.flags = flags;
 108
 109         pll_out->reg = reg;
 110         pll_out->enb_bit_idx = enb_bit_idx;
 111         pll_out->rst_bit_idx = rst_bit_idx;
 112         pll_out->flags = pll_out_flags;
 113         pll_out->lock = lock;
 114
 115         /* Data in .init is copied by clk_register(), so stack variable OK */
 116         pll_out->hw.init = &init;
 117
 118         clk = clk_register(NULL, &pll_out->hw);
 119         if (IS_ERR(clk))
 120                 kfree(pll_out);
 121
 122         return clk;
 123 }