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Merge tag 'platform-drivers-x86-v4.7-1' of git://git.infradead.org/users/dvhart/linux...
[mirror_ubuntu-artful-kernel.git] / drivers / clk / tegra / clk-tegra124.c
1 /*
2 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17 #include <linux/io.h>
18 #include <linux/clk-provider.h>
19 #include <linux/clkdev.h>
20 #include <linux/of.h>
21 #include <linux/of_address.h>
22 #include <linux/delay.h>
23 #include <linux/export.h>
24 #include <linux/clk/tegra.h>
25 #include <dt-bindings/clock/tegra124-car.h>
26 #include <dt-bindings/reset/tegra124-car.h>
27
28 #include "clk.h"
29 #include "clk-id.h"
30
31 /*
32 * TEGRA124_CAR_BANK_COUNT: the number of peripheral clock register
33 * banks present in the Tegra124/132 CAR IP block. The banks are
34 * identified by single letters, e.g.: L, H, U, V, W, X. See
35 * periph_regs[] in drivers/clk/tegra/clk.c
36 */
37 #define TEGRA124_CAR_BANK_COUNT 6
38
39 #define CLK_SOURCE_CSITE 0x1d4
40 #define CLK_SOURCE_EMC 0x19c
41
42 #define RST_DFLL_DVCO 0x2f4
43 #define DVFS_DFLL_RESET_SHIFT 0
44
45 #define PLLC_BASE 0x80
46 #define PLLC_OUT 0x84
47 #define PLLC_MISC2 0x88
48 #define PLLC_MISC 0x8c
49 #define PLLC2_BASE 0x4e8
50 #define PLLC2_MISC 0x4ec
51 #define PLLC3_BASE 0x4fc
52 #define PLLC3_MISC 0x500
53 #define PLLM_BASE 0x90
54 #define PLLM_OUT 0x94
55 #define PLLM_MISC 0x9c
56 #define PLLP_BASE 0xa0
57 #define PLLP_MISC 0xac
58 #define PLLA_BASE 0xb0
59 #define PLLA_MISC 0xbc
60 #define PLLD_BASE 0xd0
61 #define PLLD_MISC 0xdc
62 #define PLLU_BASE 0xc0
63 #define PLLU_MISC 0xcc
64 #define PLLX_BASE 0xe0
65 #define PLLX_MISC 0xe4
66 #define PLLX_MISC2 0x514
67 #define PLLX_MISC3 0x518
68 #define PLLE_BASE 0xe8
69 #define PLLE_MISC 0xec
70 #define PLLD2_BASE 0x4b8
71 #define PLLD2_MISC 0x4bc
72 #define PLLE_AUX 0x48c
73 #define PLLRE_BASE 0x4c4
74 #define PLLRE_MISC 0x4c8
75 #define PLLDP_BASE 0x590
76 #define PLLDP_MISC 0x594
77 #define PLLC4_BASE 0x5a4
78 #define PLLC4_MISC 0x5a8
79
80 #define PLLC_IDDQ_BIT 26
81 #define PLLRE_IDDQ_BIT 16
82 #define PLLSS_IDDQ_BIT 19
83
84 #define PLL_BASE_LOCK BIT(27)
85 #define PLLE_MISC_LOCK BIT(11)
86 #define PLLRE_MISC_LOCK BIT(24)
87
88 #define PLL_MISC_LOCK_ENABLE 18
89 #define PLLC_MISC_LOCK_ENABLE 24
90 #define PLLDU_MISC_LOCK_ENABLE 22
91 #define PLLE_MISC_LOCK_ENABLE 9
92 #define PLLRE_MISC_LOCK_ENABLE 30
93 #define PLLSS_MISC_LOCK_ENABLE 30
94
95 #define PLLXC_SW_MAX_P 6
96
97 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
98 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
99
100 #define CCLKG_BURST_POLICY 0x368
101
102 #define UTMIP_PLL_CFG2 0x488
103 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
104 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
105 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
106 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
107 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
108
109 #define UTMIP_PLL_CFG1 0x484
110 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
111 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
112 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
113 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
114 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
115 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
116 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
117
118 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
119 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
120 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
121 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
122 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
123 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
124 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
125 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
126 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
127
128 /* Tegra CPU clock and reset control regs */
129 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
130
131 #ifdef CONFIG_PM_SLEEP
132 static struct cpu_clk_suspend_context {
133 u32 clk_csite_src;
134 u32 cclkg_burst;
135 u32 cclkg_divider;
136 } tegra124_cpu_clk_sctx;
137 #endif
138
139 static void __iomem *clk_base;
140 static void __iomem *pmc_base;
141
142 static unsigned long osc_freq;
143 static unsigned long pll_ref_freq;
144
145 static DEFINE_SPINLOCK(pll_d_lock);
146 static DEFINE_SPINLOCK(pll_e_lock);
147 static DEFINE_SPINLOCK(pll_re_lock);
148 static DEFINE_SPINLOCK(pll_u_lock);
149 static DEFINE_SPINLOCK(emc_lock);
150
151 /* possible OSC frequencies in Hz */
152 static unsigned long tegra124_input_freq[] = {
153 [ 0] = 13000000,
154 [ 1] = 16800000,
155 [ 4] = 19200000,
156 [ 5] = 38400000,
157 [ 8] = 12000000,
158 [ 9] = 48000000,
159 [12] = 26000000,
160 };
161
162 static struct div_nmp pllxc_nmp = {
163 .divm_shift = 0,
164 .divm_width = 8,
165 .divn_shift = 8,
166 .divn_width = 8,
167 .divp_shift = 20,
168 .divp_width = 4,
169 };
170
171 static const struct pdiv_map pllxc_p[] = {
172 { .pdiv = 1, .hw_val = 0 },
173 { .pdiv = 2, .hw_val = 1 },
174 { .pdiv = 3, .hw_val = 2 },
175 { .pdiv = 4, .hw_val = 3 },
176 { .pdiv = 5, .hw_val = 4 },
177 { .pdiv = 6, .hw_val = 5 },
178 { .pdiv = 8, .hw_val = 6 },
179 { .pdiv = 10, .hw_val = 7 },
180 { .pdiv = 12, .hw_val = 8 },
181 { .pdiv = 16, .hw_val = 9 },
182 { .pdiv = 12, .hw_val = 10 },
183 { .pdiv = 16, .hw_val = 11 },
184 { .pdiv = 20, .hw_val = 12 },
185 { .pdiv = 24, .hw_val = 13 },
186 { .pdiv = 32, .hw_val = 14 },
187 { .pdiv = 0, .hw_val = 0 },
188 };
189
190 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
191 /* 1 GHz */
192 { 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */
193 { 13000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */
194 { 16800000, 1000000000, 59, 1, 1, 0 }, /* actual: 991.2 MHz */
195 { 19200000, 1000000000, 52, 1, 1, 0 }, /* actual: 998.4 MHz */
196 { 26000000, 1000000000, 76, 2, 1, 0 }, /* actual: 988.0 MHz */
197 { 0, 0, 0, 0, 0, 0 },
198 };
199
200 static struct tegra_clk_pll_params pll_x_params = {
201 .input_min = 12000000,
202 .input_max = 800000000,
203 .cf_min = 12000000,
204 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
205 .vco_min = 700000000,
206 .vco_max = 3000000000UL,
207 .base_reg = PLLX_BASE,
208 .misc_reg = PLLX_MISC,
209 .lock_mask = PLL_BASE_LOCK,
210 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
211 .lock_delay = 300,
212 .iddq_reg = PLLX_MISC3,
213 .iddq_bit_idx = 3,
214 .max_p = 6,
215 .dyn_ramp_reg = PLLX_MISC2,
216 .stepa_shift = 16,
217 .stepb_shift = 24,
218 .pdiv_tohw = pllxc_p,
219 .div_nmp = &pllxc_nmp,
220 .freq_table = pll_x_freq_table,
221 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
222 };
223
224 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
225 { 12000000, 624000000, 104, 1, 2, 0 },
226 { 12000000, 600000000, 100, 1, 2, 0 },
227 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
228 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
229 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
230 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
231 { 0, 0, 0, 0, 0, 0 },
232 };
233
234 static struct tegra_clk_pll_params pll_c_params = {
235 .input_min = 12000000,
236 .input_max = 800000000,
237 .cf_min = 12000000,
238 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
239 .vco_min = 600000000,
240 .vco_max = 1400000000,
241 .base_reg = PLLC_BASE,
242 .misc_reg = PLLC_MISC,
243 .lock_mask = PLL_BASE_LOCK,
244 .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,
245 .lock_delay = 300,
246 .iddq_reg = PLLC_MISC,
247 .iddq_bit_idx = PLLC_IDDQ_BIT,
248 .max_p = PLLXC_SW_MAX_P,
249 .dyn_ramp_reg = PLLC_MISC2,
250 .stepa_shift = 17,
251 .stepb_shift = 9,
252 .pdiv_tohw = pllxc_p,
253 .div_nmp = &pllxc_nmp,
254 .freq_table = pll_c_freq_table,
255 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
256 };
257
258 static struct div_nmp pllcx_nmp = {
259 .divm_shift = 0,
260 .divm_width = 2,
261 .divn_shift = 8,
262 .divn_width = 8,
263 .divp_shift = 20,
264 .divp_width = 3,
265 };
266
267 static const struct pdiv_map pllc_p[] = {
268 { .pdiv = 1, .hw_val = 0 },
269 { .pdiv = 2, .hw_val = 1 },
270 { .pdiv = 3, .hw_val = 2 },
271 { .pdiv = 4, .hw_val = 3 },
272 { .pdiv = 6, .hw_val = 4 },
273 { .pdiv = 8, .hw_val = 5 },
274 { .pdiv = 12, .hw_val = 6 },
275 { .pdiv = 16, .hw_val = 7 },
276 { .pdiv = 0, .hw_val = 0 },
277 };
278
279 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
280 { 12000000, 600000000, 100, 1, 2, 0 },
281 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
282 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
283 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
284 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
285 { 0, 0, 0, 0, 0, 0 },
286 };
287
288 static struct tegra_clk_pll_params pll_c2_params = {
289 .input_min = 12000000,
290 .input_max = 48000000,
291 .cf_min = 12000000,
292 .cf_max = 19200000,
293 .vco_min = 600000000,
294 .vco_max = 1200000000,
295 .base_reg = PLLC2_BASE,
296 .misc_reg = PLLC2_MISC,
297 .lock_mask = PLL_BASE_LOCK,
298 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
299 .lock_delay = 300,
300 .pdiv_tohw = pllc_p,
301 .div_nmp = &pllcx_nmp,
302 .max_p = 7,
303 .ext_misc_reg[0] = 0x4f0,
304 .ext_misc_reg[1] = 0x4f4,
305 .ext_misc_reg[2] = 0x4f8,
306 .freq_table = pll_cx_freq_table,
307 .flags = TEGRA_PLL_USE_LOCK,
308 };
309
310 static struct tegra_clk_pll_params pll_c3_params = {
311 .input_min = 12000000,
312 .input_max = 48000000,
313 .cf_min = 12000000,
314 .cf_max = 19200000,
315 .vco_min = 600000000,
316 .vco_max = 1200000000,
317 .base_reg = PLLC3_BASE,
318 .misc_reg = PLLC3_MISC,
319 .lock_mask = PLL_BASE_LOCK,
320 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
321 .lock_delay = 300,
322 .pdiv_tohw = pllc_p,
323 .div_nmp = &pllcx_nmp,
324 .max_p = 7,
325 .ext_misc_reg[0] = 0x504,
326 .ext_misc_reg[1] = 0x508,
327 .ext_misc_reg[2] = 0x50c,
328 .freq_table = pll_cx_freq_table,
329 .flags = TEGRA_PLL_USE_LOCK,
330 };
331
332 static struct div_nmp pllss_nmp = {
333 .divm_shift = 0,
334 .divm_width = 8,
335 .divn_shift = 8,
336 .divn_width = 8,
337 .divp_shift = 20,
338 .divp_width = 4,
339 };
340
341 static const struct pdiv_map pll12g_ssd_esd_p[] = {
342 { .pdiv = 1, .hw_val = 0 },
343 { .pdiv = 2, .hw_val = 1 },
344 { .pdiv = 3, .hw_val = 2 },
345 { .pdiv = 4, .hw_val = 3 },
346 { .pdiv = 5, .hw_val = 4 },
347 { .pdiv = 6, .hw_val = 5 },
348 { .pdiv = 8, .hw_val = 6 },
349 { .pdiv = 10, .hw_val = 7 },
350 { .pdiv = 12, .hw_val = 8 },
351 { .pdiv = 16, .hw_val = 9 },
352 { .pdiv = 12, .hw_val = 10 },
353 { .pdiv = 16, .hw_val = 11 },
354 { .pdiv = 20, .hw_val = 12 },
355 { .pdiv = 24, .hw_val = 13 },
356 { .pdiv = 32, .hw_val = 14 },
357 { .pdiv = 0, .hw_val = 0 },
358 };
359
360 static struct tegra_clk_pll_freq_table pll_c4_freq_table[] = {
361 { 12000000, 600000000, 100, 1, 2, 0 },
362 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
363 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
364 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
365 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
366 { 0, 0, 0, 0, 0, 0 },
367 };
368
369 static struct tegra_clk_pll_params pll_c4_params = {
370 .input_min = 12000000,
371 .input_max = 1000000000,
372 .cf_min = 12000000,
373 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
374 .vco_min = 600000000,
375 .vco_max = 1200000000,
376 .base_reg = PLLC4_BASE,
377 .misc_reg = PLLC4_MISC,
378 .lock_mask = PLL_BASE_LOCK,
379 .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
380 .lock_delay = 300,
381 .iddq_reg = PLLC4_BASE,
382 .iddq_bit_idx = PLLSS_IDDQ_BIT,
383 .pdiv_tohw = pll12g_ssd_esd_p,
384 .div_nmp = &pllss_nmp,
385 .ext_misc_reg[0] = 0x5ac,
386 .ext_misc_reg[1] = 0x5b0,
387 .ext_misc_reg[2] = 0x5b4,
388 .freq_table = pll_c4_freq_table,
389 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
390 };
391
392 static const struct pdiv_map pllm_p[] = {
393 { .pdiv = 1, .hw_val = 0 },
394 { .pdiv = 2, .hw_val = 1 },
395 { .pdiv = 3, .hw_val = 2 },
396 { .pdiv = 4, .hw_val = 3 },
397 { .pdiv = 5, .hw_val = 4 },
398 { .pdiv = 6, .hw_val = 5 },
399 { .pdiv = 8, .hw_val = 6 },
400 { .pdiv = 10, .hw_val = 7 },
401 { .pdiv = 12, .hw_val = 8 },
402 { .pdiv = 16, .hw_val = 9 },
403 { .pdiv = 12, .hw_val = 10 },
404 { .pdiv = 16, .hw_val = 11 },
405 { .pdiv = 20, .hw_val = 12 },
406 { .pdiv = 24, .hw_val = 13 },
407 { .pdiv = 32, .hw_val = 14 },
408 { .pdiv = 0, .hw_val = 0 },
409 };
410
411 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
412 { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
413 { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
414 { 16800000, 800000000, 47, 1, 1, 0 }, /* actual: 789.6 MHz */
415 { 19200000, 800000000, 41, 1, 1, 0 }, /* actual: 787.2 MHz */
416 { 26000000, 800000000, 61, 2, 1, 0 }, /* actual: 793.0 MHz */
417 { 0, 0, 0, 0, 0, 0},
418 };
419
420 static struct div_nmp pllm_nmp = {
421 .divm_shift = 0,
422 .divm_width = 8,
423 .override_divm_shift = 0,
424 .divn_shift = 8,
425 .divn_width = 8,
426 .override_divn_shift = 8,
427 .divp_shift = 20,
428 .divp_width = 1,
429 .override_divp_shift = 27,
430 };
431
432 static struct tegra_clk_pll_params pll_m_params = {
433 .input_min = 12000000,
434 .input_max = 500000000,
435 .cf_min = 12000000,
436 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
437 .vco_min = 400000000,
438 .vco_max = 1066000000,
439 .base_reg = PLLM_BASE,
440 .misc_reg = PLLM_MISC,
441 .lock_mask = PLL_BASE_LOCK,
442 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
443 .lock_delay = 300,
444 .max_p = 5,
445 .pdiv_tohw = pllm_p,
446 .div_nmp = &pllm_nmp,
447 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
448 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
449 .freq_table = pll_m_freq_table,
450 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
451 };
452
453 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
454 /* PLLE special case: use cpcon field to store cml divider value */
455 { 336000000, 100000000, 100, 21, 16, 11 },
456 { 312000000, 100000000, 200, 26, 24, 13 },
457 { 13000000, 100000000, 200, 1, 26, 13 },
458 { 12000000, 100000000, 200, 1, 24, 13 },
459 { 0, 0, 0, 0, 0, 0 },
460 };
461
462 static const struct pdiv_map plle_p[] = {
463 { .pdiv = 1, .hw_val = 0 },
464 { .pdiv = 2, .hw_val = 1 },
465 { .pdiv = 3, .hw_val = 2 },
466 { .pdiv = 4, .hw_val = 3 },
467 { .pdiv = 5, .hw_val = 4 },
468 { .pdiv = 6, .hw_val = 5 },
469 { .pdiv = 8, .hw_val = 6 },
470 { .pdiv = 10, .hw_val = 7 },
471 { .pdiv = 12, .hw_val = 8 },
472 { .pdiv = 16, .hw_val = 9 },
473 { .pdiv = 12, .hw_val = 10 },
474 { .pdiv = 16, .hw_val = 11 },
475 { .pdiv = 20, .hw_val = 12 },
476 { .pdiv = 24, .hw_val = 13 },
477 { .pdiv = 32, .hw_val = 14 },
478 { .pdiv = 1, .hw_val = 0 },
479 };
480
481 static struct div_nmp plle_nmp = {
482 .divm_shift = 0,
483 .divm_width = 8,
484 .divn_shift = 8,
485 .divn_width = 8,
486 .divp_shift = 24,
487 .divp_width = 4,
488 };
489
490 static struct tegra_clk_pll_params pll_e_params = {
491 .input_min = 12000000,
492 .input_max = 1000000000,
493 .cf_min = 12000000,
494 .cf_max = 75000000,
495 .vco_min = 1600000000,
496 .vco_max = 2400000000U,
497 .base_reg = PLLE_BASE,
498 .misc_reg = PLLE_MISC,
499 .aux_reg = PLLE_AUX,
500 .lock_mask = PLLE_MISC_LOCK,
501 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
502 .lock_delay = 300,
503 .pdiv_tohw = plle_p,
504 .div_nmp = &plle_nmp,
505 .freq_table = pll_e_freq_table,
506 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_LOCK_ENABLE,
507 .fixed_rate = 100000000,
508 };
509
510 static const struct clk_div_table pll_re_div_table[] = {
511 { .val = 0, .div = 1 },
512 { .val = 1, .div = 2 },
513 { .val = 2, .div = 3 },
514 { .val = 3, .div = 4 },
515 { .val = 4, .div = 5 },
516 { .val = 5, .div = 6 },
517 { .val = 0, .div = 0 },
518 };
519
520 static struct div_nmp pllre_nmp = {
521 .divm_shift = 0,
522 .divm_width = 8,
523 .divn_shift = 8,
524 .divn_width = 8,
525 .divp_shift = 16,
526 .divp_width = 4,
527 };
528
529 static struct tegra_clk_pll_params pll_re_vco_params = {
530 .input_min = 12000000,
531 .input_max = 1000000000,
532 .cf_min = 12000000,
533 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
534 .vco_min = 300000000,
535 .vco_max = 600000000,
536 .base_reg = PLLRE_BASE,
537 .misc_reg = PLLRE_MISC,
538 .lock_mask = PLLRE_MISC_LOCK,
539 .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
540 .lock_delay = 300,
541 .iddq_reg = PLLRE_MISC,
542 .iddq_bit_idx = PLLRE_IDDQ_BIT,
543 .div_nmp = &pllre_nmp,
544 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
545 TEGRA_PLL_LOCK_MISC,
546 };
547
548 static struct div_nmp pllp_nmp = {
549 .divm_shift = 0,
550 .divm_width = 5,
551 .divn_shift = 8,
552 .divn_width = 10,
553 .divp_shift = 20,
554 .divp_width = 3,
555 };
556
557 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
558 { 12000000, 408000000, 408, 12, 1, 8 },
559 { 13000000, 408000000, 408, 13, 1, 8 },
560 { 16800000, 408000000, 340, 14, 1, 8 },
561 { 19200000, 408000000, 340, 16, 1, 8 },
562 { 26000000, 408000000, 408, 26, 1, 8 },
563 { 0, 0, 0, 0, 0, 0 },
564 };
565
566 static struct tegra_clk_pll_params pll_p_params = {
567 .input_min = 2000000,
568 .input_max = 31000000,
569 .cf_min = 1000000,
570 .cf_max = 6000000,
571 .vco_min = 200000000,
572 .vco_max = 700000000,
573 .base_reg = PLLP_BASE,
574 .misc_reg = PLLP_MISC,
575 .lock_mask = PLL_BASE_LOCK,
576 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
577 .lock_delay = 300,
578 .div_nmp = &pllp_nmp,
579 .freq_table = pll_p_freq_table,
580 .fixed_rate = 408000000,
581 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK |
582 TEGRA_PLL_HAS_LOCK_ENABLE,
583 };
584
585 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
586 { 9600000, 282240000, 147, 5, 1, 4 },
587 { 9600000, 368640000, 192, 5, 1, 4 },
588 { 9600000, 240000000, 200, 8, 1, 8 },
589 { 28800000, 282240000, 245, 25, 1, 8 },
590 { 28800000, 368640000, 320, 25, 1, 8 },
591 { 28800000, 240000000, 200, 24, 1, 8 },
592 { 0, 0, 0, 0, 0, 0 },
593 };
594
595 static struct tegra_clk_pll_params pll_a_params = {
596 .input_min = 2000000,
597 .input_max = 31000000,
598 .cf_min = 1000000,
599 .cf_max = 6000000,
600 .vco_min = 200000000,
601 .vco_max = 700000000,
602 .base_reg = PLLA_BASE,
603 .misc_reg = PLLA_MISC,
604 .lock_mask = PLL_BASE_LOCK,
605 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
606 .lock_delay = 300,
607 .div_nmp = &pllp_nmp,
608 .freq_table = pll_a_freq_table,
609 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
610 TEGRA_PLL_HAS_LOCK_ENABLE,
611 };
612
613 static struct div_nmp plld_nmp = {
614 .divm_shift = 0,
615 .divm_width = 5,
616 .divn_shift = 8,
617 .divn_width = 11,
618 .divp_shift = 20,
619 .divp_width = 3,
620 };
621
622 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
623 { 12000000, 216000000, 864, 12, 4, 12 },
624 { 13000000, 216000000, 864, 13, 4, 12 },
625 { 16800000, 216000000, 720, 14, 4, 12 },
626 { 19200000, 216000000, 720, 16, 4, 12 },
627 { 26000000, 216000000, 864, 26, 4, 12 },
628 { 12000000, 594000000, 594, 12, 1, 12 },
629 { 13000000, 594000000, 594, 13, 1, 12 },
630 { 16800000, 594000000, 495, 14, 1, 12 },
631 { 19200000, 594000000, 495, 16, 1, 12 },
632 { 26000000, 594000000, 594, 26, 1, 12 },
633 { 12000000, 1000000000, 1000, 12, 1, 12 },
634 { 13000000, 1000000000, 1000, 13, 1, 12 },
635 { 19200000, 1000000000, 625, 12, 1, 12 },
636 { 26000000, 1000000000, 1000, 26, 1, 12 },
637 { 0, 0, 0, 0, 0, 0 },
638 };
639
640 static struct tegra_clk_pll_params pll_d_params = {
641 .input_min = 2000000,
642 .input_max = 40000000,
643 .cf_min = 1000000,
644 .cf_max = 6000000,
645 .vco_min = 500000000,
646 .vco_max = 1000000000,
647 .base_reg = PLLD_BASE,
648 .misc_reg = PLLD_MISC,
649 .lock_mask = PLL_BASE_LOCK,
650 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
651 .lock_delay = 1000,
652 .div_nmp = &plld_nmp,
653 .freq_table = pll_d_freq_table,
654 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
655 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
656 };
657
658 static struct tegra_clk_pll_freq_table tegra124_pll_d2_freq_table[] = {
659 { 12000000, 594000000, 99, 1, 2, 0 },
660 { 13000000, 594000000, 91, 1, 2, 0 }, /* actual: 591.5 MHz */
661 { 16800000, 594000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
662 { 19200000, 594000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
663 { 26000000, 594000000, 91, 2, 2, 0 }, /* actual: 591.5 MHz */
664 { 0, 0, 0, 0, 0, 0 },
665 };
666
667 static struct tegra_clk_pll_params tegra124_pll_d2_params = {
668 .input_min = 12000000,
669 .input_max = 1000000000,
670 .cf_min = 12000000,
671 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
672 .vco_min = 600000000,
673 .vco_max = 1200000000,
674 .base_reg = PLLD2_BASE,
675 .misc_reg = PLLD2_MISC,
676 .lock_mask = PLL_BASE_LOCK,
677 .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
678 .lock_delay = 300,
679 .iddq_reg = PLLD2_BASE,
680 .iddq_bit_idx = PLLSS_IDDQ_BIT,
681 .pdiv_tohw = pll12g_ssd_esd_p,
682 .div_nmp = &pllss_nmp,
683 .ext_misc_reg[0] = 0x570,
684 .ext_misc_reg[1] = 0x574,
685 .ext_misc_reg[2] = 0x578,
686 .max_p = 15,
687 .freq_table = tegra124_pll_d2_freq_table,
688 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
689 };
690
691 static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
692 { 12000000, 600000000, 100, 1, 2, 0 },
693 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
694 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
695 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
696 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
697 { 0, 0, 0, 0, 0, 0 },
698 };
699
700 static struct tegra_clk_pll_params pll_dp_params = {
701 .input_min = 12000000,
702 .input_max = 1000000000,
703 .cf_min = 12000000,
704 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
705 .vco_min = 600000000,
706 .vco_max = 1200000000,
707 .base_reg = PLLDP_BASE,
708 .misc_reg = PLLDP_MISC,
709 .lock_mask = PLL_BASE_LOCK,
710 .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
711 .lock_delay = 300,
712 .iddq_reg = PLLDP_BASE,
713 .iddq_bit_idx = PLLSS_IDDQ_BIT,
714 .pdiv_tohw = pll12g_ssd_esd_p,
715 .div_nmp = &pllss_nmp,
716 .ext_misc_reg[0] = 0x598,
717 .ext_misc_reg[1] = 0x59c,
718 .ext_misc_reg[2] = 0x5a0,
719 .max_p = 5,
720 .freq_table = pll_dp_freq_table,
721 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
722 };
723
724 static const struct pdiv_map pllu_p[] = {
725 { .pdiv = 1, .hw_val = 1 },
726 { .pdiv = 2, .hw_val = 0 },
727 { .pdiv = 0, .hw_val = 0 },
728 };
729
730 static struct div_nmp pllu_nmp = {
731 .divm_shift = 0,
732 .divm_width = 5,
733 .divn_shift = 8,
734 .divn_width = 10,
735 .divp_shift = 20,
736 .divp_width = 1,
737 };
738
739 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
740 { 12000000, 480000000, 960, 12, 2, 12 },
741 { 13000000, 480000000, 960, 13, 2, 12 },
742 { 16800000, 480000000, 400, 7, 2, 5 },
743 { 19200000, 480000000, 200, 4, 2, 3 },
744 { 26000000, 480000000, 960, 26, 2, 12 },
745 { 0, 0, 0, 0, 0, 0 },
746 };
747
748 static struct tegra_clk_pll_params pll_u_params = {
749 .input_min = 2000000,
750 .input_max = 40000000,
751 .cf_min = 1000000,
752 .cf_max = 6000000,
753 .vco_min = 480000000,
754 .vco_max = 960000000,
755 .base_reg = PLLU_BASE,
756 .misc_reg = PLLU_MISC,
757 .lock_mask = PLL_BASE_LOCK,
758 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
759 .lock_delay = 1000,
760 .pdiv_tohw = pllu_p,
761 .div_nmp = &pllu_nmp,
762 .freq_table = pll_u_freq_table,
763 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
764 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
765 };
766
767 struct utmi_clk_param {
768 /* Oscillator Frequency in KHz */
769 u32 osc_frequency;
770 /* UTMIP PLL Enable Delay Count */
771 u8 enable_delay_count;
772 /* UTMIP PLL Stable count */
773 u8 stable_count;
774 /* UTMIP PLL Active delay count */
775 u8 active_delay_count;
776 /* UTMIP PLL Xtal frequency count */
777 u8 xtal_freq_count;
778 };
779
780 static const struct utmi_clk_param utmi_parameters[] = {
781 {
782 .osc_frequency = 13000000, .enable_delay_count = 0x02,
783 .stable_count = 0x33, .active_delay_count = 0x05,
784 .xtal_freq_count = 0x7f
785 }, {
786 .osc_frequency = 19200000, .enable_delay_count = 0x03,
787 .stable_count = 0x4b, .active_delay_count = 0x06,
788 .xtal_freq_count = 0xbb
789 }, {
790 .osc_frequency = 12000000, .enable_delay_count = 0x02,
791 .stable_count = 0x2f, .active_delay_count = 0x04,
792 .xtal_freq_count = 0x76
793 }, {
794 .osc_frequency = 26000000, .enable_delay_count = 0x04,
795 .stable_count = 0x66, .active_delay_count = 0x09,
796 .xtal_freq_count = 0xfe
797 }, {
798 .osc_frequency = 16800000, .enable_delay_count = 0x03,
799 .stable_count = 0x41, .active_delay_count = 0x0a,
800 .xtal_freq_count = 0xa4
801 },
802 };
803
804 static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
805 [tegra_clk_ispb] = { .dt_id = TEGRA124_CLK_ISPB, .present = true },
806 [tegra_clk_rtc] = { .dt_id = TEGRA124_CLK_RTC, .present = true },
807 [tegra_clk_timer] = { .dt_id = TEGRA124_CLK_TIMER, .present = true },
808 [tegra_clk_uarta] = { .dt_id = TEGRA124_CLK_UARTA, .present = true },
809 [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA124_CLK_SDMMC2, .present = true },
810 [tegra_clk_i2s1] = { .dt_id = TEGRA124_CLK_I2S1, .present = true },
811 [tegra_clk_i2c1] = { .dt_id = TEGRA124_CLK_I2C1, .present = true },
812 [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA124_CLK_SDMMC1, .present = true },
813 [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true },
814 [tegra_clk_pwm] = { .dt_id = TEGRA124_CLK_PWM, .present = true },
815 [tegra_clk_i2s2] = { .dt_id = TEGRA124_CLK_I2S2, .present = true },
816 [tegra_clk_usbd] = { .dt_id = TEGRA124_CLK_USBD, .present = true },
817 [tegra_clk_isp_8] = { .dt_id = TEGRA124_CLK_ISP, .present = true },
818 [tegra_clk_disp2] = { .dt_id = TEGRA124_CLK_DISP2, .present = true },
819 [tegra_clk_disp1] = { .dt_id = TEGRA124_CLK_DISP1, .present = true },
820 [tegra_clk_host1x_8] = { .dt_id = TEGRA124_CLK_HOST1X, .present = true },
821 [tegra_clk_vcp] = { .dt_id = TEGRA124_CLK_VCP, .present = true },
822 [tegra_clk_i2s0] = { .dt_id = TEGRA124_CLK_I2S0, .present = true },
823 [tegra_clk_apbdma] = { .dt_id = TEGRA124_CLK_APBDMA, .present = true },
824 [tegra_clk_kbc] = { .dt_id = TEGRA124_CLK_KBC, .present = true },
825 [tegra_clk_kfuse] = { .dt_id = TEGRA124_CLK_KFUSE, .present = true },
826 [tegra_clk_sbc1] = { .dt_id = TEGRA124_CLK_SBC1, .present = true },
827 [tegra_clk_nor] = { .dt_id = TEGRA124_CLK_NOR, .present = true },
828 [tegra_clk_sbc2] = { .dt_id = TEGRA124_CLK_SBC2, .present = true },
829 [tegra_clk_sbc3] = { .dt_id = TEGRA124_CLK_SBC3, .present = true },
830 [tegra_clk_i2c5] = { .dt_id = TEGRA124_CLK_I2C5, .present = true },
831 [tegra_clk_mipi] = { .dt_id = TEGRA124_CLK_MIPI, .present = true },
832 [tegra_clk_hdmi] = { .dt_id = TEGRA124_CLK_HDMI, .present = true },
833 [tegra_clk_csi] = { .dt_id = TEGRA124_CLK_CSI, .present = true },
834 [tegra_clk_i2c2] = { .dt_id = TEGRA124_CLK_I2C2, .present = true },
835 [tegra_clk_uartc] = { .dt_id = TEGRA124_CLK_UARTC, .present = true },
836 [tegra_clk_mipi_cal] = { .dt_id = TEGRA124_CLK_MIPI_CAL, .present = true },
837 [tegra_clk_usb2] = { .dt_id = TEGRA124_CLK_USB2, .present = true },
838 [tegra_clk_usb3] = { .dt_id = TEGRA124_CLK_USB3, .present = true },
839 [tegra_clk_vde_8] = { .dt_id = TEGRA124_CLK_VDE, .present = true },
840 [tegra_clk_bsea] = { .dt_id = TEGRA124_CLK_BSEA, .present = true },
841 [tegra_clk_bsev] = { .dt_id = TEGRA124_CLK_BSEV, .present = true },
842 [tegra_clk_uartd] = { .dt_id = TEGRA124_CLK_UARTD, .present = true },
843 [tegra_clk_i2c3] = { .dt_id = TEGRA124_CLK_I2C3, .present = true },
844 [tegra_clk_sbc4] = { .dt_id = TEGRA124_CLK_SBC4, .present = true },
845 [tegra_clk_sdmmc3_8] = { .dt_id = TEGRA124_CLK_SDMMC3, .present = true },
846 [tegra_clk_pcie] = { .dt_id = TEGRA124_CLK_PCIE, .present = true },
847 [tegra_clk_owr] = { .dt_id = TEGRA124_CLK_OWR, .present = true },
848 [tegra_clk_afi] = { .dt_id = TEGRA124_CLK_AFI, .present = true },
849 [tegra_clk_csite] = { .dt_id = TEGRA124_CLK_CSITE, .present = true },
850 [tegra_clk_la] = { .dt_id = TEGRA124_CLK_LA, .present = true },
851 [tegra_clk_trace] = { .dt_id = TEGRA124_CLK_TRACE, .present = true },
852 [tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true },
853 [tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true },
854 [tegra_clk_i2cslow] = { .dt_id = TEGRA124_CLK_I2CSLOW, .present = true },
855 [tegra_clk_tsec] = { .dt_id = TEGRA124_CLK_TSEC, .present = true },
856 [tegra_clk_xusb_host] = { .dt_id = TEGRA124_CLK_XUSB_HOST, .present = true },
857 [tegra_clk_msenc] = { .dt_id = TEGRA124_CLK_MSENC, .present = true },
858 [tegra_clk_csus] = { .dt_id = TEGRA124_CLK_CSUS, .present = true },
859 [tegra_clk_mselect] = { .dt_id = TEGRA124_CLK_MSELECT, .present = true },
860 [tegra_clk_tsensor] = { .dt_id = TEGRA124_CLK_TSENSOR, .present = true },
861 [tegra_clk_i2s3] = { .dt_id = TEGRA124_CLK_I2S3, .present = true },
862 [tegra_clk_i2s4] = { .dt_id = TEGRA124_CLK_I2S4, .present = true },
863 [tegra_clk_i2c4] = { .dt_id = TEGRA124_CLK_I2C4, .present = true },
864 [tegra_clk_sbc5] = { .dt_id = TEGRA124_CLK_SBC5, .present = true },
865 [tegra_clk_sbc6] = { .dt_id = TEGRA124_CLK_SBC6, .present = true },
866 [tegra_clk_d_audio] = { .dt_id = TEGRA124_CLK_D_AUDIO, .present = true },
867 [tegra_clk_apbif] = { .dt_id = TEGRA124_CLK_APBIF, .present = true },
868 [tegra_clk_dam0] = { .dt_id = TEGRA124_CLK_DAM0, .present = true },
869 [tegra_clk_dam1] = { .dt_id = TEGRA124_CLK_DAM1, .present = true },
870 [tegra_clk_dam2] = { .dt_id = TEGRA124_CLK_DAM2, .present = true },
871 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA124_CLK_HDA2CODEC_2X, .present = true },
872 [tegra_clk_audio0_2x] = { .dt_id = TEGRA124_CLK_AUDIO0_2X, .present = true },
873 [tegra_clk_audio1_2x] = { .dt_id = TEGRA124_CLK_AUDIO1_2X, .present = true },
874 [tegra_clk_audio2_2x] = { .dt_id = TEGRA124_CLK_AUDIO2_2X, .present = true },
875 [tegra_clk_audio3_2x] = { .dt_id = TEGRA124_CLK_AUDIO3_2X, .present = true },
876 [tegra_clk_audio4_2x] = { .dt_id = TEGRA124_CLK_AUDIO4_2X, .present = true },
877 [tegra_clk_spdif_2x] = { .dt_id = TEGRA124_CLK_SPDIF_2X, .present = true },
878 [tegra_clk_actmon] = { .dt_id = TEGRA124_CLK_ACTMON, .present = true },
879 [tegra_clk_extern1] = { .dt_id = TEGRA124_CLK_EXTERN1, .present = true },
880 [tegra_clk_extern2] = { .dt_id = TEGRA124_CLK_EXTERN2, .present = true },
881 [tegra_clk_extern3] = { .dt_id = TEGRA124_CLK_EXTERN3, .present = true },
882 [tegra_clk_sata_oob] = { .dt_id = TEGRA124_CLK_SATA_OOB, .present = true },
883 [tegra_clk_sata] = { .dt_id = TEGRA124_CLK_SATA, .present = true },
884 [tegra_clk_hda] = { .dt_id = TEGRA124_CLK_HDA, .present = true },
885 [tegra_clk_se] = { .dt_id = TEGRA124_CLK_SE, .present = true },
886 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA124_CLK_HDA2HDMI, .present = true },
887 [tegra_clk_sata_cold] = { .dt_id = TEGRA124_CLK_SATA_COLD, .present = true },
888 [tegra_clk_cilab] = { .dt_id = TEGRA124_CLK_CILAB, .present = true },
889 [tegra_clk_cilcd] = { .dt_id = TEGRA124_CLK_CILCD, .present = true },
890 [tegra_clk_cile] = { .dt_id = TEGRA124_CLK_CILE, .present = true },
891 [tegra_clk_dsialp] = { .dt_id = TEGRA124_CLK_DSIALP, .present = true },
892 [tegra_clk_dsiblp] = { .dt_id = TEGRA124_CLK_DSIBLP, .present = true },
893 [tegra_clk_entropy] = { .dt_id = TEGRA124_CLK_ENTROPY, .present = true },
894 [tegra_clk_dds] = { .dt_id = TEGRA124_CLK_DDS, .present = true },
895 [tegra_clk_dp2] = { .dt_id = TEGRA124_CLK_DP2, .present = true },
896 [tegra_clk_amx] = { .dt_id = TEGRA124_CLK_AMX, .present = true },
897 [tegra_clk_adx] = { .dt_id = TEGRA124_CLK_ADX, .present = true },
898 [tegra_clk_xusb_ss] = { .dt_id = TEGRA124_CLK_XUSB_SS, .present = true },
899 [tegra_clk_i2c6] = { .dt_id = TEGRA124_CLK_I2C6, .present = true },
900 [tegra_clk_vim2_clk] = { .dt_id = TEGRA124_CLK_VIM2_CLK, .present = true },
901 [tegra_clk_hdmi_audio] = { .dt_id = TEGRA124_CLK_HDMI_AUDIO, .present = true },
902 [tegra_clk_clk72Mhz] = { .dt_id = TEGRA124_CLK_CLK72MHZ, .present = true },
903 [tegra_clk_vic03] = { .dt_id = TEGRA124_CLK_VIC03, .present = true },
904 [tegra_clk_adx1] = { .dt_id = TEGRA124_CLK_ADX1, .present = true },
905 [tegra_clk_dpaux] = { .dt_id = TEGRA124_CLK_DPAUX, .present = true },
906 [tegra_clk_sor0] = { .dt_id = TEGRA124_CLK_SOR0, .present = true },
907 [tegra_clk_sor0_lvds] = { .dt_id = TEGRA124_CLK_SOR0_LVDS, .present = true },
908 [tegra_clk_gpu] = { .dt_id = TEGRA124_CLK_GPU, .present = true },
909 [tegra_clk_amx1] = { .dt_id = TEGRA124_CLK_AMX1, .present = true },
910 [tegra_clk_uartb] = { .dt_id = TEGRA124_CLK_UARTB, .present = true },
911 [tegra_clk_vfir] = { .dt_id = TEGRA124_CLK_VFIR, .present = true },
912 [tegra_clk_spdif_in] = { .dt_id = TEGRA124_CLK_SPDIF_IN, .present = true },
913 [tegra_clk_spdif_out] = { .dt_id = TEGRA124_CLK_SPDIF_OUT, .present = true },
914 [tegra_clk_vi_9] = { .dt_id = TEGRA124_CLK_VI, .present = true },
915 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA124_CLK_VI_SENSOR, .present = true },
916 [tegra_clk_fuse] = { .dt_id = TEGRA124_CLK_FUSE, .present = true },
917 [tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true },
918 [tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true },
919 [tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },
920 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true },
921 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true },
922 [tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true },
923 [tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true },
924 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true },
925 [tegra_clk_pll_c2] = { .dt_id = TEGRA124_CLK_PLL_C2, .present = true },
926 [tegra_clk_pll_c3] = { .dt_id = TEGRA124_CLK_PLL_C3, .present = true },
927 [tegra_clk_pll_m] = { .dt_id = TEGRA124_CLK_PLL_M, .present = true },
928 [tegra_clk_pll_m_out1] = { .dt_id = TEGRA124_CLK_PLL_M_OUT1, .present = true },
929 [tegra_clk_pll_p] = { .dt_id = TEGRA124_CLK_PLL_P, .present = true },
930 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA124_CLK_PLL_P_OUT1, .present = true },
931 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA124_CLK_PLL_P_OUT2, .present = true },
932 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA124_CLK_PLL_P_OUT3, .present = true },
933 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA124_CLK_PLL_P_OUT4, .present = true },
934 [tegra_clk_pll_a] = { .dt_id = TEGRA124_CLK_PLL_A, .present = true },
935 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA124_CLK_PLL_A_OUT0, .present = true },
936 [tegra_clk_pll_d] = { .dt_id = TEGRA124_CLK_PLL_D, .present = true },
937 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA124_CLK_PLL_D_OUT0, .present = true },
938 [tegra_clk_pll_d2] = { .dt_id = TEGRA124_CLK_PLL_D2, .present = true },
939 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA124_CLK_PLL_D2_OUT0, .present = true },
940 [tegra_clk_pll_u] = { .dt_id = TEGRA124_CLK_PLL_U, .present = true },
941 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA124_CLK_PLL_U_480M, .present = true },
942 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA124_CLK_PLL_U_60M, .present = true },
943 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA124_CLK_PLL_U_48M, .present = true },
944 [tegra_clk_pll_u_12m] = { .dt_id = TEGRA124_CLK_PLL_U_12M, .present = true },
945 [tegra_clk_pll_x] = { .dt_id = TEGRA124_CLK_PLL_X, .present = true },
946 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA124_CLK_PLL_X_OUT0, .present = true },
947 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA124_CLK_PLL_RE_VCO, .present = true },
948 [tegra_clk_pll_re_out] = { .dt_id = TEGRA124_CLK_PLL_RE_OUT, .present = true },
949 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC, .present = true },
950 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA124_CLK_I2S0_SYNC, .present = true },
951 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA124_CLK_I2S1_SYNC, .present = true },
952 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA124_CLK_I2S2_SYNC, .present = true },
953 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA124_CLK_I2S3_SYNC, .present = true },
954 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA124_CLK_I2S4_SYNC, .present = true },
955 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA124_CLK_VIMCLK_SYNC, .present = true },
956 [tegra_clk_audio0] = { .dt_id = TEGRA124_CLK_AUDIO0, .present = true },
957 [tegra_clk_audio1] = { .dt_id = TEGRA124_CLK_AUDIO1, .present = true },
958 [tegra_clk_audio2] = { .dt_id = TEGRA124_CLK_AUDIO2, .present = true },
959 [tegra_clk_audio3] = { .dt_id = TEGRA124_CLK_AUDIO3, .present = true },
960 [tegra_clk_audio4] = { .dt_id = TEGRA124_CLK_AUDIO4, .present = true },
961 [tegra_clk_spdif] = { .dt_id = TEGRA124_CLK_SPDIF, .present = true },
962 [tegra_clk_clk_out_1] = { .dt_id = TEGRA124_CLK_CLK_OUT_1, .present = true },
963 [tegra_clk_clk_out_2] = { .dt_id = TEGRA124_CLK_CLK_OUT_2, .present = true },
964 [tegra_clk_clk_out_3] = { .dt_id = TEGRA124_CLK_CLK_OUT_3, .present = true },
965 [tegra_clk_blink] = { .dt_id = TEGRA124_CLK_BLINK, .present = true },
966 [tegra_clk_xusb_host_src] = { .dt_id = TEGRA124_CLK_XUSB_HOST_SRC, .present = true },
967 [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true },
968 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true },
969 [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA124_CLK_XUSB_SS_SRC, .present = true },
970 [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA124_CLK_XUSB_SS_DIV2, .present = true },
971 [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA124_CLK_XUSB_DEV_SRC, .present = true },
972 [tegra_clk_xusb_dev] = { .dt_id = TEGRA124_CLK_XUSB_DEV, .present = true },
973 [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA124_CLK_XUSB_HS_SRC, .present = true },
974 [tegra_clk_sclk] = { .dt_id = TEGRA124_CLK_SCLK, .present = true },
975 [tegra_clk_hclk] = { .dt_id = TEGRA124_CLK_HCLK, .present = true },
976 [tegra_clk_pclk] = { .dt_id = TEGRA124_CLK_PCLK, .present = true },
977 [tegra_clk_cclk_g] = { .dt_id = TEGRA124_CLK_CCLK_G, .present = true },
978 [tegra_clk_cclk_lp] = { .dt_id = TEGRA124_CLK_CCLK_LP, .present = true },
979 [tegra_clk_dfll_ref] = { .dt_id = TEGRA124_CLK_DFLL_REF, .present = true },
980 [tegra_clk_dfll_soc] = { .dt_id = TEGRA124_CLK_DFLL_SOC, .present = true },
981 [tegra_clk_vi_sensor2] = { .dt_id = TEGRA124_CLK_VI_SENSOR2, .present = true },
982 [tegra_clk_pll_p_out5] = { .dt_id = TEGRA124_CLK_PLL_P_OUT5, .present = true },
983 [tegra_clk_pll_c4] = { .dt_id = TEGRA124_CLK_PLL_C4, .present = true },
984 [tegra_clk_pll_dp] = { .dt_id = TEGRA124_CLK_PLL_DP, .present = true },
985 [tegra_clk_audio0_mux] = { .dt_id = TEGRA124_CLK_AUDIO0_MUX, .present = true },
986 [tegra_clk_audio1_mux] = { .dt_id = TEGRA124_CLK_AUDIO1_MUX, .present = true },
987 [tegra_clk_audio2_mux] = { .dt_id = TEGRA124_CLK_AUDIO2_MUX, .present = true },
988 [tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true },
989 [tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true },
990 [tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true },
991 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true },
992 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true },
993 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
994 };
995
996 static struct tegra_devclk devclks[] __initdata = {
997 { .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M },
998 { .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF },
999 { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
1000 { .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },
1001 { .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },
1002 { .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C },
1003 { .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 },
1004 { .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 },
1005 { .con_id = "pll_c3", .dt_id = TEGRA124_CLK_PLL_C3 },
1006 { .con_id = "pll_p", .dt_id = TEGRA124_CLK_PLL_P },
1007 { .con_id = "pll_p_out1", .dt_id = TEGRA124_CLK_PLL_P_OUT1 },
1008 { .con_id = "pll_p_out2", .dt_id = TEGRA124_CLK_PLL_P_OUT2 },
1009 { .con_id = "pll_p_out3", .dt_id = TEGRA124_CLK_PLL_P_OUT3 },
1010 { .con_id = "pll_p_out4", .dt_id = TEGRA124_CLK_PLL_P_OUT4 },
1011 { .con_id = "pll_m", .dt_id = TEGRA124_CLK_PLL_M },
1012 { .con_id = "pll_m_out1", .dt_id = TEGRA124_CLK_PLL_M_OUT1 },
1013 { .con_id = "pll_x", .dt_id = TEGRA124_CLK_PLL_X },
1014 { .con_id = "pll_x_out0", .dt_id = TEGRA124_CLK_PLL_X_OUT0 },
1015 { .con_id = "pll_u", .dt_id = TEGRA124_CLK_PLL_U },
1016 { .con_id = "pll_u_480M", .dt_id = TEGRA124_CLK_PLL_U_480M },
1017 { .con_id = "pll_u_60M", .dt_id = TEGRA124_CLK_PLL_U_60M },
1018 { .con_id = "pll_u_48M", .dt_id = TEGRA124_CLK_PLL_U_48M },
1019 { .con_id = "pll_u_12M", .dt_id = TEGRA124_CLK_PLL_U_12M },
1020 { .con_id = "pll_d", .dt_id = TEGRA124_CLK_PLL_D },
1021 { .con_id = "pll_d_out0", .dt_id = TEGRA124_CLK_PLL_D_OUT0 },
1022 { .con_id = "pll_d2", .dt_id = TEGRA124_CLK_PLL_D2 },
1023 { .con_id = "pll_d2_out0", .dt_id = TEGRA124_CLK_PLL_D2_OUT0 },
1024 { .con_id = "pll_a", .dt_id = TEGRA124_CLK_PLL_A },
1025 { .con_id = "pll_a_out0", .dt_id = TEGRA124_CLK_PLL_A_OUT0 },
1026 { .con_id = "pll_re_vco", .dt_id = TEGRA124_CLK_PLL_RE_VCO },
1027 { .con_id = "pll_re_out", .dt_id = TEGRA124_CLK_PLL_RE_OUT },
1028 { .con_id = "spdif_in_sync", .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC },
1029 { .con_id = "i2s0_sync", .dt_id = TEGRA124_CLK_I2S0_SYNC },
1030 { .con_id = "i2s1_sync", .dt_id = TEGRA124_CLK_I2S1_SYNC },
1031 { .con_id = "i2s2_sync", .dt_id = TEGRA124_CLK_I2S2_SYNC },
1032 { .con_id = "i2s3_sync", .dt_id = TEGRA124_CLK_I2S3_SYNC },
1033 { .con_id = "i2s4_sync", .dt_id = TEGRA124_CLK_I2S4_SYNC },
1034 { .con_id = "vimclk_sync", .dt_id = TEGRA124_CLK_VIMCLK_SYNC },
1035 { .con_id = "audio0", .dt_id = TEGRA124_CLK_AUDIO0 },
1036 { .con_id = "audio1", .dt_id = TEGRA124_CLK_AUDIO1 },
1037 { .con_id = "audio2", .dt_id = TEGRA124_CLK_AUDIO2 },
1038 { .con_id = "audio3", .dt_id = TEGRA124_CLK_AUDIO3 },
1039 { .con_id = "audio4", .dt_id = TEGRA124_CLK_AUDIO4 },
1040 { .con_id = "spdif", .dt_id = TEGRA124_CLK_SPDIF },
1041 { .con_id = "audio0_2x", .dt_id = TEGRA124_CLK_AUDIO0_2X },
1042 { .con_id = "audio1_2x", .dt_id = TEGRA124_CLK_AUDIO1_2X },
1043 { .con_id = "audio2_2x", .dt_id = TEGRA124_CLK_AUDIO2_2X },
1044 { .con_id = "audio3_2x", .dt_id = TEGRA124_CLK_AUDIO3_2X },
1045 { .con_id = "audio4_2x", .dt_id = TEGRA124_CLK_AUDIO4_2X },
1046 { .con_id = "spdif_2x", .dt_id = TEGRA124_CLK_SPDIF_2X },
1047 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA124_CLK_EXTERN1 },
1048 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA124_CLK_EXTERN2 },
1049 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA124_CLK_EXTERN3 },
1050 { .con_id = "blink", .dt_id = TEGRA124_CLK_BLINK },
1051 { .con_id = "cclk_g", .dt_id = TEGRA124_CLK_CCLK_G },
1052 { .con_id = "cclk_lp", .dt_id = TEGRA124_CLK_CCLK_LP },
1053 { .con_id = "sclk", .dt_id = TEGRA124_CLK_SCLK },
1054 { .con_id = "hclk", .dt_id = TEGRA124_CLK_HCLK },
1055 { .con_id = "pclk", .dt_id = TEGRA124_CLK_PCLK },
1056 { .con_id = "fuse", .dt_id = TEGRA124_CLK_FUSE },
1057 { .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC },
1058 { .dev_id = "timer", .dt_id = TEGRA124_CLK_TIMER },
1059 { .con_id = "hda", .dt_id = TEGRA124_CLK_HDA },
1060 { .con_id = "hda2codec_2x", .dt_id = TEGRA124_CLK_HDA2CODEC_2X },
1061 { .con_id = "hda2hdmi", .dt_id = TEGRA124_CLK_HDA2HDMI },
1062 };
1063
1064 static struct clk **clks;
1065
1066 static void tegra124_utmi_param_configure(void __iomem *clk_base)
1067 {
1068 unsigned int i;
1069 u32 reg;
1070
1071 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1072 if (osc_freq == utmi_parameters[i].osc_frequency)
1073 break;
1074 }
1075
1076 if (i >= ARRAY_SIZE(utmi_parameters)) {
1077 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
1078 osc_freq);
1079 return;
1080 }
1081
1082 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
1083
1084 /* Program UTMIP PLL stable and active counts */
1085 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
1086 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1087 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
1088
1089 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1090
1091 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].
1092 active_delay_count);
1093
1094 /* Remove power downs from UTMIP PLL control bits */
1095 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1096 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1097 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1098
1099 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
1100
1101 /* Program UTMIP PLL delay and oscillator frequency counts */
1102 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1103 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1104
1105 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].
1106 enable_delay_count);
1107
1108 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1109 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].
1110 xtal_freq_count);
1111
1112 /* Remove power downs from UTMIP PLL control bits */
1113 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1114 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1115 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1116 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1117 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1118
1119 /* Setup HW control of UTMIPLL */
1120 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1121 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1122 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1123 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1124 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1125
1126 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1127 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1128 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1129 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1130
1131 udelay(1);
1132
1133 /* Setup SW override of UTMIPLL assuming USB2.0
1134 ports are assigned to USB2 */
1135 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1136 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1137 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1138 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1139
1140 udelay(1);
1141
1142 /* Enable HW control UTMIPLL */
1143 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1144 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1145 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1146 }
1147
1148 static __init void tegra124_periph_clk_init(void __iomem *clk_base,
1149 void __iomem *pmc_base)
1150 {
1151 struct clk *clk;
1152
1153 /* xusb_ss_div2 */
1154 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
1155 1, 2);
1156 clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk;
1157
1158 clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base,
1159 1, 17, 181);
1160 clks[TEGRA124_CLK_DPAUX] = clk;
1161
1162 clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
1163 clk_base + PLLD_MISC, 30, 0, &pll_d_lock);
1164 clks[TEGRA124_CLK_PLL_D_DSI_OUT] = clk;
1165
1166 clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,
1167 clk_base, 0, 48,
1168 periph_clk_enb_refcnt);
1169 clks[TEGRA124_CLK_DSIA] = clk;
1170
1171 clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,
1172 clk_base, 0, 82,
1173 periph_clk_enb_refcnt);
1174 clks[TEGRA124_CLK_DSIB] = clk;
1175
1176 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
1177 &emc_lock);
1178 clks[TEGRA124_CLK_MC] = clk;
1179
1180 /* cml0 */
1181 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1182 0, 0, &pll_e_lock);
1183 clk_register_clkdev(clk, "cml0", NULL);
1184 clks[TEGRA124_CLK_CML0] = clk;
1185
1186 /* cml1 */
1187 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1188 1, 0, &pll_e_lock);
1189 clk_register_clkdev(clk, "cml1", NULL);
1190 clks[TEGRA124_CLK_CML1] = clk;
1191
1192 tegra_periph_clk_init(clk_base, pmc_base, tegra124_clks, &pll_p_params);
1193 }
1194
1195 static void __init tegra124_pll_init(void __iomem *clk_base,
1196 void __iomem *pmc)
1197 {
1198 u32 val;
1199 struct clk *clk;
1200
1201 /* PLLC */
1202 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
1203 pmc, 0, &pll_c_params, NULL);
1204 clk_register_clkdev(clk, "pll_c", NULL);
1205 clks[TEGRA124_CLK_PLL_C] = clk;
1206
1207 /* PLLC_OUT1 */
1208 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
1209 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1210 8, 8, 1, NULL);
1211 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
1212 clk_base + PLLC_OUT, 1, 0,
1213 CLK_SET_RATE_PARENT, 0, NULL);
1214 clk_register_clkdev(clk, "pll_c_out1", NULL);
1215 clks[TEGRA124_CLK_PLL_C_OUT1] = clk;
1216
1217 /* PLLC_UD */
1218 clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c",
1219 CLK_SET_RATE_PARENT, 1, 1);
1220 clk_register_clkdev(clk, "pll_c_ud", NULL);
1221 clks[TEGRA124_CLK_PLL_C_UD] = clk;
1222
1223 /* PLLC2 */
1224 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,
1225 &pll_c2_params, NULL);
1226 clk_register_clkdev(clk, "pll_c2", NULL);
1227 clks[TEGRA124_CLK_PLL_C2] = clk;
1228
1229 /* PLLC3 */
1230 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,
1231 &pll_c3_params, NULL);
1232 clk_register_clkdev(clk, "pll_c3", NULL);
1233 clks[TEGRA124_CLK_PLL_C3] = clk;
1234
1235 /* PLLM */
1236 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
1237 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1238 &pll_m_params, NULL);
1239 clk_register_clkdev(clk, "pll_m", NULL);
1240 clks[TEGRA124_CLK_PLL_M] = clk;
1241
1242 /* PLLM_OUT1 */
1243 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
1244 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1245 8, 8, 1, NULL);
1246 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
1247 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
1248 CLK_SET_RATE_PARENT, 0, NULL);
1249 clk_register_clkdev(clk, "pll_m_out1", NULL);
1250 clks[TEGRA124_CLK_PLL_M_OUT1] = clk;
1251
1252 /* PLLM_UD */
1253 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
1254 CLK_SET_RATE_PARENT, 1, 1);
1255 clk_register_clkdev(clk, "pll_m_ud", NULL);
1256 clks[TEGRA124_CLK_PLL_M_UD] = clk;
1257
1258 /* PLLU */
1259 val = readl(clk_base + pll_u_params.base_reg);
1260 val &= ~BIT(24); /* disable PLLU_OVERRIDE */
1261 writel(val, clk_base + pll_u_params.base_reg);
1262
1263 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,
1264 &pll_u_params, &pll_u_lock);
1265 clk_register_clkdev(clk, "pll_u", NULL);
1266 clks[TEGRA124_CLK_PLL_U] = clk;
1267
1268 tegra124_utmi_param_configure(clk_base);
1269
1270 /* PLLU_480M */
1271 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
1272 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
1273 22, 0, &pll_u_lock);
1274 clk_register_clkdev(clk, "pll_u_480M", NULL);
1275 clks[TEGRA124_CLK_PLL_U_480M] = clk;
1276
1277 /* PLLU_60M */
1278 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
1279 CLK_SET_RATE_PARENT, 1, 8);
1280 clk_register_clkdev(clk, "pll_u_60M", NULL);
1281 clks[TEGRA124_CLK_PLL_U_60M] = clk;
1282
1283 /* PLLU_48M */
1284 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
1285 CLK_SET_RATE_PARENT, 1, 10);
1286 clk_register_clkdev(clk, "pll_u_48M", NULL);
1287 clks[TEGRA124_CLK_PLL_U_48M] = clk;
1288
1289 /* PLLU_12M */
1290 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
1291 CLK_SET_RATE_PARENT, 1, 40);
1292 clk_register_clkdev(clk, "pll_u_12M", NULL);
1293 clks[TEGRA124_CLK_PLL_U_12M] = clk;
1294
1295 /* PLLD */
1296 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
1297 &pll_d_params, &pll_d_lock);
1298 clk_register_clkdev(clk, "pll_d", NULL);
1299 clks[TEGRA124_CLK_PLL_D] = clk;
1300
1301 /* PLLD_OUT0 */
1302 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
1303 CLK_SET_RATE_PARENT, 1, 2);
1304 clk_register_clkdev(clk, "pll_d_out0", NULL);
1305 clks[TEGRA124_CLK_PLL_D_OUT0] = clk;
1306
1307 /* PLLRE */
1308 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
1309 0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq);
1310 clk_register_clkdev(clk, "pll_re_vco", NULL);
1311 clks[TEGRA124_CLK_PLL_RE_VCO] = clk;
1312
1313 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
1314 clk_base + PLLRE_BASE, 16, 4, 0,
1315 pll_re_div_table, &pll_re_lock);
1316 clk_register_clkdev(clk, "pll_re_out", NULL);
1317 clks[TEGRA124_CLK_PLL_RE_OUT] = clk;
1318
1319 /* PLLE */
1320 clk = tegra_clk_register_plle_tegra114("pll_e", "pll_ref",
1321 clk_base, 0, &pll_e_params, NULL);
1322 clk_register_clkdev(clk, "pll_e", NULL);
1323 clks[TEGRA124_CLK_PLL_E] = clk;
1324
1325 /* PLLC4 */
1326 clk = tegra_clk_register_pllss("pll_c4", "pll_ref", clk_base, 0,
1327 &pll_c4_params, NULL);
1328 clk_register_clkdev(clk, "pll_c4", NULL);
1329 clks[TEGRA124_CLK_PLL_C4] = clk;
1330
1331 /* PLLDP */
1332 clk = tegra_clk_register_pllss("pll_dp", "pll_ref", clk_base, 0,
1333 &pll_dp_params, NULL);
1334 clk_register_clkdev(clk, "pll_dp", NULL);
1335 clks[TEGRA124_CLK_PLL_DP] = clk;
1336
1337 /* PLLD2 */
1338 clk = tegra_clk_register_pllss("pll_d2", "pll_ref", clk_base, 0,
1339 &tegra124_pll_d2_params, NULL);
1340 clk_register_clkdev(clk, "pll_d2", NULL);
1341 clks[TEGRA124_CLK_PLL_D2] = clk;
1342
1343 /* PLLD2_OUT0 */
1344 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
1345 CLK_SET_RATE_PARENT, 1, 1);
1346 clk_register_clkdev(clk, "pll_d2_out0", NULL);
1347 clks[TEGRA124_CLK_PLL_D2_OUT0] = clk;
1348
1349 }
1350
1351 /* Tegra124 CPU clock and reset control functions */
1352 static void tegra124_wait_cpu_in_reset(u32 cpu)
1353 {
1354 unsigned int reg;
1355
1356 do {
1357 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1358 cpu_relax();
1359 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
1360 }
1361
1362 static void tegra124_disable_cpu_clock(u32 cpu)
1363 {
1364 /* flow controller would take care in the power sequence. */
1365 }
1366
1367 #ifdef CONFIG_PM_SLEEP
1368 static void tegra124_cpu_clock_suspend(void)
1369 {
1370 /* switch coresite to clk_m, save off original source */
1371 tegra124_cpu_clk_sctx.clk_csite_src =
1372 readl(clk_base + CLK_SOURCE_CSITE);
1373 writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
1374
1375 tegra124_cpu_clk_sctx.cclkg_burst =
1376 readl(clk_base + CCLKG_BURST_POLICY);
1377 tegra124_cpu_clk_sctx.cclkg_divider =
1378 readl(clk_base + CCLKG_BURST_POLICY + 4);
1379 }
1380
1381 static void tegra124_cpu_clock_resume(void)
1382 {
1383 writel(tegra124_cpu_clk_sctx.clk_csite_src,
1384 clk_base + CLK_SOURCE_CSITE);
1385
1386 writel(tegra124_cpu_clk_sctx.cclkg_burst,
1387 clk_base + CCLKG_BURST_POLICY);
1388 writel(tegra124_cpu_clk_sctx.cclkg_divider,
1389 clk_base + CCLKG_BURST_POLICY + 4);
1390 }
1391 #endif
1392
1393 static struct tegra_cpu_car_ops tegra124_cpu_car_ops = {
1394 .wait_for_reset = tegra124_wait_cpu_in_reset,
1395 .disable_clock = tegra124_disable_cpu_clock,
1396 #ifdef CONFIG_PM_SLEEP
1397 .suspend = tegra124_cpu_clock_suspend,
1398 .resume = tegra124_cpu_clock_resume,
1399 #endif
1400 };
1401
1402 static const struct of_device_id pmc_match[] __initconst = {
1403 { .compatible = "nvidia,tegra124-pmc" },
1404 { },
1405 };
1406
1407 static struct tegra_clk_init_table common_init_table[] __initdata = {
1408 { TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0 },
1409 { TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0 },
1410 { TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0 },
1411 { TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0 },
1412 { TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1 },
1413 { TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1 },
1414 { TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1 },
1415 { TEGRA124_CLK_CLK_OUT_1_MUX, TEGRA124_CLK_EXTERN1, 0, 1 },
1416 { TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1 },
1417 { TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
1418 { TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
1419 { TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
1420 { TEGRA124_CLK_I2S3, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
1421 { TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
1422 { TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0 },
1423 { TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1 },
1424 { TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0 },
1425 { TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0 },
1426 { TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1 },
1427 { TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1 },
1428 { TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1 },
1429 { TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0 },
1430 { TEGRA124_CLK_PLL_C_OUT1, TEGRA124_CLK_CLK_MAX, 100000000, 0 },
1431 { TEGRA124_CLK_SBC4, TEGRA124_CLK_PLL_P, 12000000, 1 },
1432 { TEGRA124_CLK_TSEC, TEGRA124_CLK_PLL_C3, 0, 0 },
1433 { TEGRA124_CLK_MSENC, TEGRA124_CLK_PLL_C3, 0, 0 },
1434 { TEGRA124_CLK_PLL_RE_VCO, TEGRA124_CLK_CLK_MAX, 672000000, 0 },
1435 { TEGRA124_CLK_XUSB_SS_SRC, TEGRA124_CLK_PLL_U_480M, 120000000, 0 },
1436 { TEGRA124_CLK_XUSB_FS_SRC, TEGRA124_CLK_PLL_U_48M, 48000000, 0 },
1437 { TEGRA124_CLK_XUSB_HS_SRC, TEGRA124_CLK_PLL_U_60M, 60000000, 0 },
1438 { TEGRA124_CLK_XUSB_FALCON_SRC, TEGRA124_CLK_PLL_RE_OUT, 224000000, 0 },
1439 { TEGRA124_CLK_XUSB_HOST_SRC, TEGRA124_CLK_PLL_RE_OUT, 112000000, 0 },
1440 { TEGRA124_CLK_SATA, TEGRA124_CLK_PLL_P, 104000000, 0 },
1441 { TEGRA124_CLK_SATA_OOB, TEGRA124_CLK_PLL_P, 204000000, 0 },
1442 { TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1 },
1443 { TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1 },
1444 { TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0 },
1445 /* must be the last entry */
1446 { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
1447 };
1448
1449 static struct tegra_clk_init_table tegra124_init_table[] __initdata = {
1450 { TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0 },
1451 { TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1 },
1452 { TEGRA124_CLK_HDA, TEGRA124_CLK_PLL_P, 102000000, 0 },
1453 { TEGRA124_CLK_HDA2CODEC_2X, TEGRA124_CLK_PLL_P, 48000000, 0 },
1454 /* must be the last entry */
1455 { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
1456 };
1457
1458 /* Tegra132 requires the SOC_THERM clock to remain active */
1459 static struct tegra_clk_init_table tegra132_init_table[] __initdata = {
1460 { TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 1 },
1461 /* must be the last entry */
1462 { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
1463 };
1464
1465 static struct tegra_audio_clk_info tegra124_audio_plls[] = {
1466 { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
1467 };
1468
1469 /**
1470 * tegra124_clock_apply_init_table - initialize clocks on Tegra124 SoCs
1471 *
1472 * Program an initial clock rate and enable or disable clocks needed
1473 * by the rest of the kernel, for Tegra124 SoCs. It is intended to be
1474 * called by assigning a pointer to it to tegra_clk_apply_init_table -
1475 * this will be called as an arch_initcall. No return value.
1476 */
1477 static void __init tegra124_clock_apply_init_table(void)
1478 {
1479 tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX);
1480 tegra_init_from_table(tegra124_init_table, clks, TEGRA124_CLK_CLK_MAX);
1481 }
1482
1483 /**
1484 * tegra124_car_barrier - wait for pending writes to the CAR to complete
1485 *
1486 * Wait for any outstanding writes to the CAR MMIO space from this CPU
1487 * to complete before continuing execution. No return value.
1488 */
1489 static void tegra124_car_barrier(void)
1490 {
1491 readl_relaxed(clk_base + RST_DFLL_DVCO);
1492 }
1493
1494 /**
1495 * tegra124_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
1496 *
1497 * Assert the reset line of the DFLL's DVCO. No return value.
1498 */
1499 static void tegra124_clock_assert_dfll_dvco_reset(void)
1500 {
1501 u32 v;
1502
1503 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1504 v |= (1 << DVFS_DFLL_RESET_SHIFT);
1505 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1506 tegra124_car_barrier();
1507 }
1508
1509 /**
1510 * tegra124_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
1511 *
1512 * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
1513 * operate. No return value.
1514 */
1515 static void tegra124_clock_deassert_dfll_dvco_reset(void)
1516 {
1517 u32 v;
1518
1519 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1520 v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
1521 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1522 tegra124_car_barrier();
1523 }
1524
1525 static int tegra124_reset_assert(unsigned long id)
1526 {
1527 if (id == TEGRA124_RST_DFLL_DVCO)
1528 tegra124_clock_assert_dfll_dvco_reset();
1529 else
1530 return -EINVAL;
1531
1532 return 0;
1533 }
1534
1535 static int tegra124_reset_deassert(unsigned long id)
1536 {
1537 if (id == TEGRA124_RST_DFLL_DVCO)
1538 tegra124_clock_deassert_dfll_dvco_reset();
1539 else
1540 return -EINVAL;
1541
1542 return 0;
1543 }
1544
1545 /**
1546 * tegra132_clock_apply_init_table - initialize clocks on Tegra132 SoCs
1547 *
1548 * Program an initial clock rate and enable or disable clocks needed
1549 * by the rest of the kernel, for Tegra132 SoCs. It is intended to be
1550 * called by assigning a pointer to it to tegra_clk_apply_init_table -
1551 * this will be called as an arch_initcall. No return value.
1552 */
1553 static void __init tegra132_clock_apply_init_table(void)
1554 {
1555 tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX);
1556 tegra_init_from_table(tegra132_init_table, clks, TEGRA124_CLK_CLK_MAX);
1557 }
1558
1559 /**
1560 * tegra124_132_clock_init_pre - clock initialization preamble for T124/T132
1561 * @np: struct device_node * of the DT node for the SoC CAR IP block
1562 *
1563 * Register most of the clocks controlled by the CAR IP block, along
1564 * with a few clocks controlled by the PMC IP block. Everything in
1565 * this function should be common to Tegra124 and Tegra132. XXX The
1566 * PMC clock initialization should probably be moved to PMC-specific
1567 * driver code. No return value.
1568 */
1569 static void __init tegra124_132_clock_init_pre(struct device_node *np)
1570 {
1571 struct device_node *node;
1572 u32 plld_base;
1573
1574 clk_base = of_iomap(np, 0);
1575 if (!clk_base) {
1576 pr_err("ioremap tegra124/tegra132 CAR failed\n");
1577 return;
1578 }
1579
1580 node = of_find_matching_node(NULL, pmc_match);
1581 if (!node) {
1582 pr_err("Failed to find pmc node\n");
1583 WARN_ON(1);
1584 return;
1585 }
1586
1587 pmc_base = of_iomap(node, 0);
1588 if (!pmc_base) {
1589 pr_err("Can't map pmc registers\n");
1590 WARN_ON(1);
1591 return;
1592 }
1593
1594 clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX,
1595 TEGRA124_CAR_BANK_COUNT);
1596 if (!clks)
1597 return;
1598
1599 if (tegra_osc_clk_init(clk_base, tegra124_clks, tegra124_input_freq,
1600 ARRAY_SIZE(tegra124_input_freq), 1, &osc_freq,
1601 &pll_ref_freq) < 0)
1602 return;
1603
1604 tegra_fixed_clk_init(tegra124_clks);
1605 tegra124_pll_init(clk_base, pmc_base);
1606 tegra124_periph_clk_init(clk_base, pmc_base);
1607 tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks,
1608 tegra124_audio_plls,
1609 ARRAY_SIZE(tegra124_audio_plls));
1610 tegra_pmc_clk_init(pmc_base, tegra124_clks);
1611
1612 /* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
1613 plld_base = clk_readl(clk_base + PLLD_BASE);
1614 plld_base &= ~BIT(25);
1615 clk_writel(plld_base, clk_base + PLLD_BASE);
1616 }
1617
1618 /**
1619 * tegra124_132_clock_init_post - clock initialization postamble for T124/T132
1620 * @np: struct device_node * of the DT node for the SoC CAR IP block
1621 *
1622 * Register most of the along with a few clocks controlled by the PMC
1623 * IP block. Everything in this function should be common to Tegra124
1624 * and Tegra132. This function must be called after
1625 * tegra124_132_clock_init_pre(), otherwise clk_base and pmc_base will
1626 * not be set. No return value.
1627 */
1628 static void __init tegra124_132_clock_init_post(struct device_node *np)
1629 {
1630 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks,
1631 &pll_x_params);
1632 tegra_init_special_resets(1, tegra124_reset_assert,
1633 tegra124_reset_deassert);
1634 tegra_add_of_provider(np);
1635
1636 clks[TEGRA124_CLK_EMC] = tegra_clk_register_emc(clk_base, np,
1637 &emc_lock);
1638
1639 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1640
1641 tegra_cpu_car_ops = &tegra124_cpu_car_ops;
1642 }
1643
1644 /**
1645 * tegra124_clock_init - Tegra124-specific clock initialization
1646 * @np: struct device_node * of the DT node for the SoC CAR IP block
1647 *
1648 * Register most SoC clocks for the Tegra124 system-on-chip. Most of
1649 * this code is shared between the Tegra124 and Tegra132 SoCs,
1650 * although some of the initial clock settings and CPU clocks differ.
1651 * Intended to be called by the OF init code when a DT node with the
1652 * "nvidia,tegra124-car" string is encountered, and declared with
1653 * CLK_OF_DECLARE. No return value.
1654 */
1655 static void __init tegra124_clock_init(struct device_node *np)
1656 {
1657 tegra124_132_clock_init_pre(np);
1658 tegra_clk_apply_init_table = tegra124_clock_apply_init_table;
1659 tegra124_132_clock_init_post(np);
1660 }
1661
1662 /**
1663 * tegra132_clock_init - Tegra132-specific clock initialization
1664 * @np: struct device_node * of the DT node for the SoC CAR IP block
1665 *
1666 * Register most SoC clocks for the Tegra132 system-on-chip. Most of
1667 * this code is shared between the Tegra124 and Tegra132 SoCs,
1668 * although some of the initial clock settings and CPU clocks differ.
1669 * Intended to be called by the OF init code when a DT node with the
1670 * "nvidia,tegra132-car" string is encountered, and declared with
1671 * CLK_OF_DECLARE. No return value.
1672 */
1673 static void __init tegra132_clock_init(struct device_node *np)
1674 {
1675 tegra124_132_clock_init_pre(np);
1676
1677 /*
1678 * On Tegra132, these clocks are controlled by the
1679 * CLUSTER_clocks IP block, located in the CPU complex
1680 */
1681 tegra124_clks[tegra_clk_cclk_g].present = false;
1682 tegra124_clks[tegra_clk_cclk_lp].present = false;
1683 tegra124_clks[tegra_clk_pll_x].present = false;
1684 tegra124_clks[tegra_clk_pll_x_out0].present = false;
1685
1686 tegra_clk_apply_init_table = tegra132_clock_apply_init_table;
1687 tegra124_132_clock_init_post(np);
1688 }
1689 CLK_OF_DECLARE(tegra124, "nvidia,tegra124-car", tegra124_clock_init);
1690 CLK_OF_DECLARE(tegra132, "nvidia,tegra132-car", tegra132_clock_init);
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