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Merge branches 'pm-cpuidle', 'pm-cpufreq' and 'pm-sleep'
[mirror_ubuntu-artful-kernel.git] / drivers / clk / tegra / clk-tegra20.c
1 /*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17 #include <linux/io.h>
18 #include <linux/clk-provider.h>
19 #include <linux/clkdev.h>
20 #include <linux/of.h>
21 #include <linux/of_address.h>
22 #include <linux/clk/tegra.h>
23 #include <linux/delay.h>
24 #include <dt-bindings/clock/tegra20-car.h>
25
26 #include "clk.h"
27 #include "clk-id.h"
28
29 #define OSC_CTRL 0x50
30 #define OSC_CTRL_OSC_FREQ_MASK (3<<30)
31 #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
32 #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
33 #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
34 #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
35 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
36
37 #define OSC_CTRL_PLL_REF_DIV_MASK (3<<28)
38 #define OSC_CTRL_PLL_REF_DIV_1 (0<<28)
39 #define OSC_CTRL_PLL_REF_DIV_2 (1<<28)
40 #define OSC_CTRL_PLL_REF_DIV_4 (2<<28)
41
42 #define OSC_FREQ_DET 0x58
43 #define OSC_FREQ_DET_TRIG (1<<31)
44
45 #define OSC_FREQ_DET_STATUS 0x5c
46 #define OSC_FREQ_DET_BUSY (1<<31)
47 #define OSC_FREQ_DET_CNT_MASK 0xFFFF
48
49 #define TEGRA20_CLK_PERIPH_BANKS 3
50
51 #define PLLS_BASE 0xf0
52 #define PLLS_MISC 0xf4
53 #define PLLC_BASE 0x80
54 #define PLLC_MISC 0x8c
55 #define PLLM_BASE 0x90
56 #define PLLM_MISC 0x9c
57 #define PLLP_BASE 0xa0
58 #define PLLP_MISC 0xac
59 #define PLLA_BASE 0xb0
60 #define PLLA_MISC 0xbc
61 #define PLLU_BASE 0xc0
62 #define PLLU_MISC 0xcc
63 #define PLLD_BASE 0xd0
64 #define PLLD_MISC 0xdc
65 #define PLLX_BASE 0xe0
66 #define PLLX_MISC 0xe4
67 #define PLLE_BASE 0xe8
68 #define PLLE_MISC 0xec
69
70 #define PLL_BASE_LOCK BIT(27)
71 #define PLLE_MISC_LOCK BIT(11)
72
73 #define PLL_MISC_LOCK_ENABLE 18
74 #define PLLDU_MISC_LOCK_ENABLE 22
75 #define PLLE_MISC_LOCK_ENABLE 9
76
77 #define PLLC_OUT 0x84
78 #define PLLM_OUT 0x94
79 #define PLLP_OUTA 0xa4
80 #define PLLP_OUTB 0xa8
81 #define PLLA_OUT 0xb4
82
83 #define CCLK_BURST_POLICY 0x20
84 #define SUPER_CCLK_DIVIDER 0x24
85 #define SCLK_BURST_POLICY 0x28
86 #define SUPER_SCLK_DIVIDER 0x2c
87 #define CLK_SYSTEM_RATE 0x30
88
89 #define CCLK_BURST_POLICY_SHIFT 28
90 #define CCLK_RUN_POLICY_SHIFT 4
91 #define CCLK_IDLE_POLICY_SHIFT 0
92 #define CCLK_IDLE_POLICY 1
93 #define CCLK_RUN_POLICY 2
94 #define CCLK_BURST_POLICY_PLLX 8
95
96 #define CLK_SOURCE_I2S1 0x100
97 #define CLK_SOURCE_I2S2 0x104
98 #define CLK_SOURCE_PWM 0x110
99 #define CLK_SOURCE_SPI 0x114
100 #define CLK_SOURCE_XIO 0x120
101 #define CLK_SOURCE_TWC 0x12c
102 #define CLK_SOURCE_IDE 0x144
103 #define CLK_SOURCE_HDMI 0x18c
104 #define CLK_SOURCE_DISP1 0x138
105 #define CLK_SOURCE_DISP2 0x13c
106 #define CLK_SOURCE_CSITE 0x1d4
107 #define CLK_SOURCE_I2C1 0x124
108 #define CLK_SOURCE_I2C2 0x198
109 #define CLK_SOURCE_I2C3 0x1b8
110 #define CLK_SOURCE_DVC 0x128
111 #define CLK_SOURCE_UARTA 0x178
112 #define CLK_SOURCE_UARTB 0x17c
113 #define CLK_SOURCE_UARTC 0x1a0
114 #define CLK_SOURCE_UARTD 0x1c0
115 #define CLK_SOURCE_UARTE 0x1c4
116 #define CLK_SOURCE_EMC 0x19c
117
118 #define AUDIO_SYNC_CLK 0x38
119
120 /* Tegra CPU clock and reset control regs */
121 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
122 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
123 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
124
125 #define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
126 #define CPU_RESET(cpu) (0x1111ul << (cpu))
127
128 #ifdef CONFIG_PM_SLEEP
129 static struct cpu_clk_suspend_context {
130 u32 pllx_misc;
131 u32 pllx_base;
132
133 u32 cpu_burst;
134 u32 clk_csite_src;
135 u32 cclk_divider;
136 } tegra20_cpu_clk_sctx;
137 #endif
138
139 static void __iomem *clk_base;
140 static void __iomem *pmc_base;
141
142 static DEFINE_SPINLOCK(emc_lock);
143
144 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \
145 _clk_num, _gate_flags, _clk_id) \
146 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
147 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
148 _clk_num, \
149 _gate_flags, _clk_id)
150
151 #define TEGRA_INIT_DATA_DIV16(_name, _parents, _offset, \
152 _clk_num, _gate_flags, _clk_id) \
153 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
154 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \
155 _clk_num, _gate_flags, \
156 _clk_id)
157
158 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \
159 _mux_shift, _mux_width, _clk_num, \
160 _gate_flags, _clk_id) \
161 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
162 _mux_shift, _mux_width, 0, 0, 0, 0, 0, \
163 _clk_num, _gate_flags, \
164 _clk_id)
165
166 static struct clk **clks;
167
168 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
169 { 12000000, 600000000, 600, 12, 1, 8 },
170 { 13000000, 600000000, 600, 13, 1, 8 },
171 { 19200000, 600000000, 500, 16, 1, 6 },
172 { 26000000, 600000000, 600, 26, 1, 8 },
173 { 0, 0, 0, 0, 0, 0 },
174 };
175
176 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
177 { 12000000, 666000000, 666, 12, 1, 8 },
178 { 13000000, 666000000, 666, 13, 1, 8 },
179 { 19200000, 666000000, 555, 16, 1, 8 },
180 { 26000000, 666000000, 666, 26, 1, 8 },
181 { 12000000, 600000000, 600, 12, 1, 8 },
182 { 13000000, 600000000, 600, 13, 1, 8 },
183 { 19200000, 600000000, 375, 12, 1, 6 },
184 { 26000000, 600000000, 600, 26, 1, 8 },
185 { 0, 0, 0, 0, 0, 0 },
186 };
187
188 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
189 { 12000000, 216000000, 432, 12, 2, 8 },
190 { 13000000, 216000000, 432, 13, 2, 8 },
191 { 19200000, 216000000, 90, 4, 2, 1 },
192 { 26000000, 216000000, 432, 26, 2, 8 },
193 { 12000000, 432000000, 432, 12, 1, 8 },
194 { 13000000, 432000000, 432, 13, 1, 8 },
195 { 19200000, 432000000, 90, 4, 1, 1 },
196 { 26000000, 432000000, 432, 26, 1, 8 },
197 { 0, 0, 0, 0, 0, 0 },
198 };
199
200 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
201 { 28800000, 56448000, 49, 25, 1, 1 },
202 { 28800000, 73728000, 64, 25, 1, 1 },
203 { 28800000, 24000000, 5, 6, 1, 1 },
204 { 0, 0, 0, 0, 0, 0 },
205 };
206
207 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
208 { 12000000, 216000000, 216, 12, 1, 4 },
209 { 13000000, 216000000, 216, 13, 1, 4 },
210 { 19200000, 216000000, 135, 12, 1, 3 },
211 { 26000000, 216000000, 216, 26, 1, 4 },
212 { 12000000, 594000000, 594, 12, 1, 8 },
213 { 13000000, 594000000, 594, 13, 1, 8 },
214 { 19200000, 594000000, 495, 16, 1, 8 },
215 { 26000000, 594000000, 594, 26, 1, 8 },
216 { 12000000, 1000000000, 1000, 12, 1, 12 },
217 { 13000000, 1000000000, 1000, 13, 1, 12 },
218 { 19200000, 1000000000, 625, 12, 1, 8 },
219 { 26000000, 1000000000, 1000, 26, 1, 12 },
220 { 0, 0, 0, 0, 0, 0 },
221 };
222
223 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
224 { 12000000, 480000000, 960, 12, 1, 0 },
225 { 13000000, 480000000, 960, 13, 1, 0 },
226 { 19200000, 480000000, 200, 4, 1, 0 },
227 { 26000000, 480000000, 960, 26, 1, 0 },
228 { 0, 0, 0, 0, 0, 0 },
229 };
230
231 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
232 /* 1 GHz */
233 { 12000000, 1000000000, 1000, 12, 1, 12 },
234 { 13000000, 1000000000, 1000, 13, 1, 12 },
235 { 19200000, 1000000000, 625, 12, 1, 8 },
236 { 26000000, 1000000000, 1000, 26, 1, 12 },
237 /* 912 MHz */
238 { 12000000, 912000000, 912, 12, 1, 12 },
239 { 13000000, 912000000, 912, 13, 1, 12 },
240 { 19200000, 912000000, 760, 16, 1, 8 },
241 { 26000000, 912000000, 912, 26, 1, 12 },
242 /* 816 MHz */
243 { 12000000, 816000000, 816, 12, 1, 12 },
244 { 13000000, 816000000, 816, 13, 1, 12 },
245 { 19200000, 816000000, 680, 16, 1, 8 },
246 { 26000000, 816000000, 816, 26, 1, 12 },
247 /* 760 MHz */
248 { 12000000, 760000000, 760, 12, 1, 12 },
249 { 13000000, 760000000, 760, 13, 1, 12 },
250 { 19200000, 760000000, 950, 24, 1, 8 },
251 { 26000000, 760000000, 760, 26, 1, 12 },
252 /* 750 MHz */
253 { 12000000, 750000000, 750, 12, 1, 12 },
254 { 13000000, 750000000, 750, 13, 1, 12 },
255 { 19200000, 750000000, 625, 16, 1, 8 },
256 { 26000000, 750000000, 750, 26, 1, 12 },
257 /* 608 MHz */
258 { 12000000, 608000000, 608, 12, 1, 12 },
259 { 13000000, 608000000, 608, 13, 1, 12 },
260 { 19200000, 608000000, 380, 12, 1, 8 },
261 { 26000000, 608000000, 608, 26, 1, 12 },
262 /* 456 MHz */
263 { 12000000, 456000000, 456, 12, 1, 12 },
264 { 13000000, 456000000, 456, 13, 1, 12 },
265 { 19200000, 456000000, 380, 16, 1, 8 },
266 { 26000000, 456000000, 456, 26, 1, 12 },
267 /* 312 MHz */
268 { 12000000, 312000000, 312, 12, 1, 12 },
269 { 13000000, 312000000, 312, 13, 1, 12 },
270 { 19200000, 312000000, 260, 16, 1, 8 },
271 { 26000000, 312000000, 312, 26, 1, 12 },
272 { 0, 0, 0, 0, 0, 0 },
273 };
274
275 static const struct pdiv_map plle_p[] = {
276 { .pdiv = 1, .hw_val = 1 },
277 { .pdiv = 0, .hw_val = 0 },
278 };
279
280 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
281 { 12000000, 100000000, 200, 24, 1, 0 },
282 { 0, 0, 0, 0, 0, 0 },
283 };
284
285 /* PLL parameters */
286 static struct tegra_clk_pll_params pll_c_params = {
287 .input_min = 2000000,
288 .input_max = 31000000,
289 .cf_min = 1000000,
290 .cf_max = 6000000,
291 .vco_min = 20000000,
292 .vco_max = 1400000000,
293 .base_reg = PLLC_BASE,
294 .misc_reg = PLLC_MISC,
295 .lock_mask = PLL_BASE_LOCK,
296 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
297 .lock_delay = 300,
298 .freq_table = pll_c_freq_table,
299 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
300 };
301
302 static struct tegra_clk_pll_params pll_m_params = {
303 .input_min = 2000000,
304 .input_max = 31000000,
305 .cf_min = 1000000,
306 .cf_max = 6000000,
307 .vco_min = 20000000,
308 .vco_max = 1200000000,
309 .base_reg = PLLM_BASE,
310 .misc_reg = PLLM_MISC,
311 .lock_mask = PLL_BASE_LOCK,
312 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
313 .lock_delay = 300,
314 .freq_table = pll_m_freq_table,
315 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
316 };
317
318 static struct tegra_clk_pll_params pll_p_params = {
319 .input_min = 2000000,
320 .input_max = 31000000,
321 .cf_min = 1000000,
322 .cf_max = 6000000,
323 .vco_min = 20000000,
324 .vco_max = 1400000000,
325 .base_reg = PLLP_BASE,
326 .misc_reg = PLLP_MISC,
327 .lock_mask = PLL_BASE_LOCK,
328 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
329 .lock_delay = 300,
330 .freq_table = pll_p_freq_table,
331 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON |
332 TEGRA_PLL_HAS_LOCK_ENABLE,
333 .fixed_rate = 216000000,
334 };
335
336 static struct tegra_clk_pll_params pll_a_params = {
337 .input_min = 2000000,
338 .input_max = 31000000,
339 .cf_min = 1000000,
340 .cf_max = 6000000,
341 .vco_min = 20000000,
342 .vco_max = 1400000000,
343 .base_reg = PLLA_BASE,
344 .misc_reg = PLLA_MISC,
345 .lock_mask = PLL_BASE_LOCK,
346 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
347 .lock_delay = 300,
348 .freq_table = pll_a_freq_table,
349 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
350 };
351
352 static struct tegra_clk_pll_params pll_d_params = {
353 .input_min = 2000000,
354 .input_max = 40000000,
355 .cf_min = 1000000,
356 .cf_max = 6000000,
357 .vco_min = 40000000,
358 .vco_max = 1000000000,
359 .base_reg = PLLD_BASE,
360 .misc_reg = PLLD_MISC,
361 .lock_mask = PLL_BASE_LOCK,
362 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
363 .lock_delay = 1000,
364 .freq_table = pll_d_freq_table,
365 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
366 };
367
368 static const struct pdiv_map pllu_p[] = {
369 { .pdiv = 1, .hw_val = 1 },
370 { .pdiv = 2, .hw_val = 0 },
371 { .pdiv = 0, .hw_val = 0 },
372 };
373
374 static struct tegra_clk_pll_params pll_u_params = {
375 .input_min = 2000000,
376 .input_max = 40000000,
377 .cf_min = 1000000,
378 .cf_max = 6000000,
379 .vco_min = 48000000,
380 .vco_max = 960000000,
381 .base_reg = PLLU_BASE,
382 .misc_reg = PLLU_MISC,
383 .lock_mask = PLL_BASE_LOCK,
384 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
385 .lock_delay = 1000,
386 .pdiv_tohw = pllu_p,
387 .freq_table = pll_u_freq_table,
388 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
389 };
390
391 static struct tegra_clk_pll_params pll_x_params = {
392 .input_min = 2000000,
393 .input_max = 31000000,
394 .cf_min = 1000000,
395 .cf_max = 6000000,
396 .vco_min = 20000000,
397 .vco_max = 1200000000,
398 .base_reg = PLLX_BASE,
399 .misc_reg = PLLX_MISC,
400 .lock_mask = PLL_BASE_LOCK,
401 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
402 .lock_delay = 300,
403 .freq_table = pll_x_freq_table,
404 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
405 };
406
407 static struct tegra_clk_pll_params pll_e_params = {
408 .input_min = 12000000,
409 .input_max = 12000000,
410 .cf_min = 0,
411 .cf_max = 0,
412 .vco_min = 0,
413 .vco_max = 0,
414 .base_reg = PLLE_BASE,
415 .misc_reg = PLLE_MISC,
416 .lock_mask = PLLE_MISC_LOCK,
417 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
418 .lock_delay = 0,
419 .pdiv_tohw = plle_p,
420 .freq_table = pll_e_freq_table,
421 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC |
422 TEGRA_PLL_HAS_LOCK_ENABLE,
423 .fixed_rate = 100000000,
424 };
425
426 static struct tegra_devclk devclks[] __initdata = {
427 { .con_id = "pll_c", .dt_id = TEGRA20_CLK_PLL_C },
428 { .con_id = "pll_c_out1", .dt_id = TEGRA20_CLK_PLL_C_OUT1 },
429 { .con_id = "pll_p", .dt_id = TEGRA20_CLK_PLL_P },
430 { .con_id = "pll_p_out1", .dt_id = TEGRA20_CLK_PLL_P_OUT1 },
431 { .con_id = "pll_p_out2", .dt_id = TEGRA20_CLK_PLL_P_OUT2 },
432 { .con_id = "pll_p_out3", .dt_id = TEGRA20_CLK_PLL_P_OUT3 },
433 { .con_id = "pll_p_out4", .dt_id = TEGRA20_CLK_PLL_P_OUT4 },
434 { .con_id = "pll_m", .dt_id = TEGRA20_CLK_PLL_M },
435 { .con_id = "pll_m_out1", .dt_id = TEGRA20_CLK_PLL_M_OUT1 },
436 { .con_id = "pll_x", .dt_id = TEGRA20_CLK_PLL_X },
437 { .con_id = "pll_u", .dt_id = TEGRA20_CLK_PLL_U },
438 { .con_id = "pll_d", .dt_id = TEGRA20_CLK_PLL_D },
439 { .con_id = "pll_d_out0", .dt_id = TEGRA20_CLK_PLL_D_OUT0 },
440 { .con_id = "pll_a", .dt_id = TEGRA20_CLK_PLL_A },
441 { .con_id = "pll_a_out0", .dt_id = TEGRA20_CLK_PLL_A_OUT0 },
442 { .con_id = "pll_e", .dt_id = TEGRA20_CLK_PLL_E },
443 { .con_id = "cclk", .dt_id = TEGRA20_CLK_CCLK },
444 { .con_id = "sclk", .dt_id = TEGRA20_CLK_SCLK },
445 { .con_id = "hclk", .dt_id = TEGRA20_CLK_HCLK },
446 { .con_id = "pclk", .dt_id = TEGRA20_CLK_PCLK },
447 { .con_id = "fuse", .dt_id = TEGRA20_CLK_FUSE },
448 { .con_id = "twd", .dt_id = TEGRA20_CLK_TWD },
449 { .con_id = "audio", .dt_id = TEGRA20_CLK_AUDIO },
450 { .con_id = "audio_2x", .dt_id = TEGRA20_CLK_AUDIO_2X },
451 { .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 },
452 { .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA },
453 { .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC },
454 { .dev_id = "timer", .dt_id = TEGRA20_CLK_TIMER },
455 { .dev_id = "tegra-kbc", .dt_id = TEGRA20_CLK_KBC },
456 { .con_id = "csus", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSUS },
457 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_VCP },
458 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_BSEA },
459 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA20_CLK_BSEV },
460 { .con_id = "emc", .dt_id = TEGRA20_CLK_EMC },
461 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA20_CLK_USBD },
462 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA20_CLK_USB2 },
463 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA20_CLK_USB3 },
464 { .dev_id = "dsi", .dt_id = TEGRA20_CLK_DSI },
465 { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSI },
466 { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_ISP },
467 { .con_id = "pex", .dt_id = TEGRA20_CLK_PEX },
468 { .con_id = "afi", .dt_id = TEGRA20_CLK_AFI },
469 { .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 },
470 { .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 },
471 { .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K },
472 { .con_id = "blink", .dt_id = TEGRA20_CLK_BLINK },
473 { .con_id = "clk_m", .dt_id = TEGRA20_CLK_CLK_M },
474 { .con_id = "pll_ref", .dt_id = TEGRA20_CLK_PLL_REF },
475 { .dev_id = "tegra20-i2s.0", .dt_id = TEGRA20_CLK_I2S1 },
476 { .dev_id = "tegra20-i2s.1", .dt_id = TEGRA20_CLK_I2S2 },
477 { .con_id = "spdif_out", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_OUT },
478 { .con_id = "spdif_in", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_IN },
479 { .dev_id = "spi_tegra.0", .dt_id = TEGRA20_CLK_SBC1 },
480 { .dev_id = "spi_tegra.1", .dt_id = TEGRA20_CLK_SBC2 },
481 { .dev_id = "spi_tegra.2", .dt_id = TEGRA20_CLK_SBC3 },
482 { .dev_id = "spi_tegra.3", .dt_id = TEGRA20_CLK_SBC4 },
483 { .dev_id = "spi", .dt_id = TEGRA20_CLK_SPI },
484 { .dev_id = "xio", .dt_id = TEGRA20_CLK_XIO },
485 { .dev_id = "twc", .dt_id = TEGRA20_CLK_TWC },
486 { .dev_id = "ide", .dt_id = TEGRA20_CLK_IDE },
487 { .dev_id = "tegra_nand", .dt_id = TEGRA20_CLK_NDFLASH },
488 { .dev_id = "vfir", .dt_id = TEGRA20_CLK_VFIR },
489 { .dev_id = "csite", .dt_id = TEGRA20_CLK_CSITE },
490 { .dev_id = "la", .dt_id = TEGRA20_CLK_LA },
491 { .dev_id = "tegra_w1", .dt_id = TEGRA20_CLK_OWR },
492 { .dev_id = "mipi", .dt_id = TEGRA20_CLK_MIPI },
493 { .dev_id = "vde", .dt_id = TEGRA20_CLK_VDE },
494 { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI },
495 { .dev_id = "epp", .dt_id = TEGRA20_CLK_EPP },
496 { .dev_id = "mpe", .dt_id = TEGRA20_CLK_MPE },
497 { .dev_id = "host1x", .dt_id = TEGRA20_CLK_HOST1X },
498 { .dev_id = "3d", .dt_id = TEGRA20_CLK_GR3D },
499 { .dev_id = "2d", .dt_id = TEGRA20_CLK_GR2D },
500 { .dev_id = "tegra-nor", .dt_id = TEGRA20_CLK_NOR },
501 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA20_CLK_SDMMC1 },
502 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA20_CLK_SDMMC2 },
503 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA20_CLK_SDMMC3 },
504 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA20_CLK_SDMMC4 },
505 { .dev_id = "cve", .dt_id = TEGRA20_CLK_CVE },
506 { .dev_id = "tvo", .dt_id = TEGRA20_CLK_TVO },
507 { .dev_id = "tvdac", .dt_id = TEGRA20_CLK_TVDAC },
508 { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI_SENSOR },
509 { .dev_id = "hdmi", .dt_id = TEGRA20_CLK_HDMI },
510 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA20_CLK_I2C1 },
511 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA20_CLK_I2C2 },
512 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA20_CLK_I2C3 },
513 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA20_CLK_DVC },
514 { .dev_id = "tegra-pwm", .dt_id = TEGRA20_CLK_PWM },
515 { .dev_id = "tegra_uart.0", .dt_id = TEGRA20_CLK_UARTA },
516 { .dev_id = "tegra_uart.1", .dt_id = TEGRA20_CLK_UARTB },
517 { .dev_id = "tegra_uart.2", .dt_id = TEGRA20_CLK_UARTC },
518 { .dev_id = "tegra_uart.3", .dt_id = TEGRA20_CLK_UARTD },
519 { .dev_id = "tegra_uart.4", .dt_id = TEGRA20_CLK_UARTE },
520 { .dev_id = "tegradc.0", .dt_id = TEGRA20_CLK_DISP1 },
521 { .dev_id = "tegradc.1", .dt_id = TEGRA20_CLK_DISP2 },
522 };
523
524 static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {
525 [tegra_clk_spdif_out] = { .dt_id = TEGRA20_CLK_SPDIF_OUT, .present = true },
526 [tegra_clk_spdif_in] = { .dt_id = TEGRA20_CLK_SPDIF_IN, .present = true },
527 [tegra_clk_sdmmc1] = { .dt_id = TEGRA20_CLK_SDMMC1, .present = true },
528 [tegra_clk_sdmmc2] = { .dt_id = TEGRA20_CLK_SDMMC2, .present = true },
529 [tegra_clk_sdmmc3] = { .dt_id = TEGRA20_CLK_SDMMC3, .present = true },
530 [tegra_clk_sdmmc4] = { .dt_id = TEGRA20_CLK_SDMMC4, .present = true },
531 [tegra_clk_la] = { .dt_id = TEGRA20_CLK_LA, .present = true },
532 [tegra_clk_csite] = { .dt_id = TEGRA20_CLK_CSITE, .present = true },
533 [tegra_clk_vfir] = { .dt_id = TEGRA20_CLK_VFIR, .present = true },
534 [tegra_clk_mipi] = { .dt_id = TEGRA20_CLK_MIPI, .present = true },
535 [tegra_clk_nor] = { .dt_id = TEGRA20_CLK_NOR, .present = true },
536 [tegra_clk_rtc] = { .dt_id = TEGRA20_CLK_RTC, .present = true },
537 [tegra_clk_timer] = { .dt_id = TEGRA20_CLK_TIMER, .present = true },
538 [tegra_clk_kbc] = { .dt_id = TEGRA20_CLK_KBC, .present = true },
539 [tegra_clk_csus] = { .dt_id = TEGRA20_CLK_CSUS, .present = true },
540 [tegra_clk_vcp] = { .dt_id = TEGRA20_CLK_VCP, .present = true },
541 [tegra_clk_bsea] = { .dt_id = TEGRA20_CLK_BSEA, .present = true },
542 [tegra_clk_bsev] = { .dt_id = TEGRA20_CLK_BSEV, .present = true },
543 [tegra_clk_usbd] = { .dt_id = TEGRA20_CLK_USBD, .present = true },
544 [tegra_clk_usb2] = { .dt_id = TEGRA20_CLK_USB2, .present = true },
545 [tegra_clk_usb3] = { .dt_id = TEGRA20_CLK_USB3, .present = true },
546 [tegra_clk_csi] = { .dt_id = TEGRA20_CLK_CSI, .present = true },
547 [tegra_clk_isp] = { .dt_id = TEGRA20_CLK_ISP, .present = true },
548 [tegra_clk_clk_32k] = { .dt_id = TEGRA20_CLK_CLK_32K, .present = true },
549 [tegra_clk_blink] = { .dt_id = TEGRA20_CLK_BLINK, .present = true },
550 [tegra_clk_hclk] = { .dt_id = TEGRA20_CLK_HCLK, .present = true },
551 [tegra_clk_pclk] = { .dt_id = TEGRA20_CLK_PCLK, .present = true },
552 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA20_CLK_PLL_P_OUT1, .present = true },
553 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA20_CLK_PLL_P_OUT2, .present = true },
554 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA20_CLK_PLL_P_OUT3, .present = true },
555 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA20_CLK_PLL_P_OUT4, .present = true },
556 [tegra_clk_pll_p] = { .dt_id = TEGRA20_CLK_PLL_P, .present = true },
557 [tegra_clk_owr] = { .dt_id = TEGRA20_CLK_OWR, .present = true },
558 [tegra_clk_sbc1] = { .dt_id = TEGRA20_CLK_SBC1, .present = true },
559 [tegra_clk_sbc2] = { .dt_id = TEGRA20_CLK_SBC2, .present = true },
560 [tegra_clk_sbc3] = { .dt_id = TEGRA20_CLK_SBC3, .present = true },
561 [tegra_clk_sbc4] = { .dt_id = TEGRA20_CLK_SBC4, .present = true },
562 [tegra_clk_vde] = { .dt_id = TEGRA20_CLK_VDE, .present = true },
563 [tegra_clk_vi] = { .dt_id = TEGRA20_CLK_VI, .present = true },
564 [tegra_clk_epp] = { .dt_id = TEGRA20_CLK_EPP, .present = true },
565 [tegra_clk_mpe] = { .dt_id = TEGRA20_CLK_MPE, .present = true },
566 [tegra_clk_host1x] = { .dt_id = TEGRA20_CLK_HOST1X, .present = true },
567 [tegra_clk_gr2d] = { .dt_id = TEGRA20_CLK_GR2D, .present = true },
568 [tegra_clk_gr3d] = { .dt_id = TEGRA20_CLK_GR3D, .present = true },
569 [tegra_clk_ndflash] = { .dt_id = TEGRA20_CLK_NDFLASH, .present = true },
570 [tegra_clk_cve] = { .dt_id = TEGRA20_CLK_CVE, .present = true },
571 [tegra_clk_tvo] = { .dt_id = TEGRA20_CLK_TVO, .present = true },
572 [tegra_clk_tvdac] = { .dt_id = TEGRA20_CLK_TVDAC, .present = true },
573 [tegra_clk_vi_sensor] = { .dt_id = TEGRA20_CLK_VI_SENSOR, .present = true },
574 [tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present = true },
575 [tegra_clk_fuse] = { .dt_id = TEGRA20_CLK_FUSE, .present = true },
576 [tegra_clk_kfuse] = { .dt_id = TEGRA20_CLK_KFUSE, .present = true },
577 };
578
579 static unsigned long tegra20_clk_measure_input_freq(void)
580 {
581 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL);
582 u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK;
583 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
584 unsigned long input_freq;
585
586 switch (auto_clk_control) {
587 case OSC_CTRL_OSC_FREQ_12MHZ:
588 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
589 input_freq = 12000000;
590 break;
591 case OSC_CTRL_OSC_FREQ_13MHZ:
592 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
593 input_freq = 13000000;
594 break;
595 case OSC_CTRL_OSC_FREQ_19_2MHZ:
596 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
597 input_freq = 19200000;
598 break;
599 case OSC_CTRL_OSC_FREQ_26MHZ:
600 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
601 input_freq = 26000000;
602 break;
603 default:
604 pr_err("Unexpected clock autodetect value %d",
605 auto_clk_control);
606 BUG();
607 return 0;
608 }
609
610 return input_freq;
611 }
612
613 static unsigned int tegra20_get_pll_ref_div(void)
614 {
615 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) &
616 OSC_CTRL_PLL_REF_DIV_MASK;
617
618 switch (pll_ref_div) {
619 case OSC_CTRL_PLL_REF_DIV_1:
620 return 1;
621 case OSC_CTRL_PLL_REF_DIV_2:
622 return 2;
623 case OSC_CTRL_PLL_REF_DIV_4:
624 return 4;
625 default:
626 pr_err("Invalid pll ref divider %d\n", pll_ref_div);
627 BUG();
628 }
629 return 0;
630 }
631
632 static void tegra20_pll_init(void)
633 {
634 struct clk *clk;
635
636 /* PLLC */
637 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0,
638 &pll_c_params, NULL);
639 clks[TEGRA20_CLK_PLL_C] = clk;
640
641 /* PLLC_OUT1 */
642 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
643 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
644 8, 8, 1, NULL);
645 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
646 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
647 0, NULL);
648 clks[TEGRA20_CLK_PLL_C_OUT1] = clk;
649
650 /* PLLM */
651 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL,
652 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
653 &pll_m_params, NULL);
654 clks[TEGRA20_CLK_PLL_M] = clk;
655
656 /* PLLM_OUT1 */
657 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
658 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
659 8, 8, 1, NULL);
660 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
661 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
662 CLK_SET_RATE_PARENT, 0, NULL);
663 clks[TEGRA20_CLK_PLL_M_OUT1] = clk;
664
665 /* PLLX */
666 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0,
667 &pll_x_params, NULL);
668 clks[TEGRA20_CLK_PLL_X] = clk;
669
670 /* PLLU */
671 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0,
672 &pll_u_params, NULL);
673 clks[TEGRA20_CLK_PLL_U] = clk;
674
675 /* PLLD */
676 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0,
677 &pll_d_params, NULL);
678 clks[TEGRA20_CLK_PLL_D] = clk;
679
680 /* PLLD_OUT0 */
681 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
682 CLK_SET_RATE_PARENT, 1, 2);
683 clks[TEGRA20_CLK_PLL_D_OUT0] = clk;
684
685 /* PLLA */
686 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0,
687 &pll_a_params, NULL);
688 clks[TEGRA20_CLK_PLL_A] = clk;
689
690 /* PLLA_OUT0 */
691 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
692 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
693 8, 8, 1, NULL);
694 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
695 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
696 CLK_SET_RATE_PARENT, 0, NULL);
697 clks[TEGRA20_CLK_PLL_A_OUT0] = clk;
698
699 /* PLLE */
700 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base,
701 0, &pll_e_params, NULL);
702 clks[TEGRA20_CLK_PLL_E] = clk;
703 }
704
705 static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
706 "pll_p", "pll_p_out4",
707 "pll_p_out3", "clk_d", "pll_x" };
708 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
709 "pll_p_out3", "pll_p_out2", "clk_d",
710 "clk_32k", "pll_m_out1" };
711
712 static void tegra20_super_clk_init(void)
713 {
714 struct clk *clk;
715
716 /* CCLK */
717 clk = tegra_clk_register_super_mux("cclk", cclk_parents,
718 ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT,
719 clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
720 clks[TEGRA20_CLK_CCLK] = clk;
721
722 /* SCLK */
723 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
724 ARRAY_SIZE(sclk_parents), CLK_SET_RATE_PARENT,
725 clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
726 clks[TEGRA20_CLK_SCLK] = clk;
727
728 /* twd */
729 clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4);
730 clks[TEGRA20_CLK_TWD] = clk;
731 }
732
733 static const char *audio_parents[] = { "spdif_in", "i2s1", "i2s2", "unused",
734 "pll_a_out0", "unused", "unused",
735 "unused" };
736
737 static void __init tegra20_audio_clk_init(void)
738 {
739 struct clk *clk;
740
741 /* audio */
742 clk = clk_register_mux(NULL, "audio_mux", audio_parents,
743 ARRAY_SIZE(audio_parents),
744 CLK_SET_RATE_NO_REPARENT,
745 clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL);
746 clk = clk_register_gate(NULL, "audio", "audio_mux", 0,
747 clk_base + AUDIO_SYNC_CLK, 4,
748 CLK_GATE_SET_TO_DISABLE, NULL);
749 clks[TEGRA20_CLK_AUDIO] = clk;
750
751 /* audio_2x */
752 clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio",
753 CLK_SET_RATE_PARENT, 2, 1);
754 clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler",
755 TEGRA_PERIPH_NO_RESET, clk_base,
756 CLK_SET_RATE_PARENT, 89,
757 periph_clk_enb_refcnt);
758 clks[TEGRA20_CLK_AUDIO_2X] = clk;
759 }
760
761 static const char *i2s1_parents[] = { "pll_a_out0", "audio_2x", "pll_p",
762 "clk_m" };
763 static const char *i2s2_parents[] = { "pll_a_out0", "audio_2x", "pll_p",
764 "clk_m" };
765 static const char *pwm_parents[] = { "pll_p", "pll_c", "audio", "clk_m",
766 "clk_32k" };
767 static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
768 static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c",
769 "clk_m" };
770 static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" };
771
772 static struct tegra_periph_init_data tegra_periph_clk_list[] = {
773 TEGRA_INIT_DATA_MUX("i2s1", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S1),
774 TEGRA_INIT_DATA_MUX("i2s2", i2s2_parents, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S2),
775 TEGRA_INIT_DATA_MUX("spi", mux_pllpcm_clkm, CLK_SOURCE_SPI, 43, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_SPI),
776 TEGRA_INIT_DATA_MUX("xio", mux_pllpcm_clkm, CLK_SOURCE_XIO, 45, 0, TEGRA20_CLK_XIO),
777 TEGRA_INIT_DATA_MUX("twc", mux_pllpcm_clkm, CLK_SOURCE_TWC, 16, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_TWC),
778 TEGRA_INIT_DATA_MUX("ide", mux_pllpcm_clkm, CLK_SOURCE_XIO, 25, 0, TEGRA20_CLK_IDE),
779 TEGRA_INIT_DATA_DIV16("dvc", mux_pllpcm_clkm, CLK_SOURCE_DVC, 47, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_DVC),
780 TEGRA_INIT_DATA_DIV16("i2c1", mux_pllpcm_clkm, CLK_SOURCE_I2C1, 12, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C1),
781 TEGRA_INIT_DATA_DIV16("i2c2", mux_pllpcm_clkm, CLK_SOURCE_I2C2, 54, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C2),
782 TEGRA_INIT_DATA_DIV16("i2c3", mux_pllpcm_clkm, CLK_SOURCE_I2C3, 67, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C3),
783 TEGRA_INIT_DATA_MUX("hdmi", mux_pllpdc_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA20_CLK_HDMI),
784 TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_PWM),
785 };
786
787 static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
788 TEGRA_INIT_DATA_NODIV("uarta", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTA),
789 TEGRA_INIT_DATA_NODIV("uartb", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTB),
790 TEGRA_INIT_DATA_NODIV("uartc", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTC),
791 TEGRA_INIT_DATA_NODIV("uartd", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTD),
792 TEGRA_INIT_DATA_NODIV("uarte", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTE),
793 TEGRA_INIT_DATA_NODIV("disp1", mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, 0, TEGRA20_CLK_DISP1),
794 TEGRA_INIT_DATA_NODIV("disp2", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, 0, TEGRA20_CLK_DISP2),
795 };
796
797 static void __init tegra20_periph_clk_init(void)
798 {
799 struct tegra_periph_init_data *data;
800 struct clk *clk;
801 unsigned int i;
802
803 /* ac97 */
804 clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",
805 TEGRA_PERIPH_ON_APB,
806 clk_base, 0, 3, periph_clk_enb_refcnt);
807 clks[TEGRA20_CLK_AC97] = clk;
808
809 /* apbdma */
810 clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base,
811 0, 34, periph_clk_enb_refcnt);
812 clks[TEGRA20_CLK_APBDMA] = clk;
813
814 /* emc */
815 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
816 ARRAY_SIZE(mux_pllmcp_clkm),
817 CLK_SET_RATE_NO_REPARENT,
818 clk_base + CLK_SOURCE_EMC,
819 30, 2, 0, &emc_lock);
820 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
821 57, periph_clk_enb_refcnt);
822 clks[TEGRA20_CLK_EMC] = clk;
823
824 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
825 &emc_lock);
826 clks[TEGRA20_CLK_MC] = clk;
827
828 /* dsi */
829 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
830 48, periph_clk_enb_refcnt);
831 clk_register_clkdev(clk, NULL, "dsi");
832 clks[TEGRA20_CLK_DSI] = clk;
833
834 /* pex */
835 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70,
836 periph_clk_enb_refcnt);
837 clks[TEGRA20_CLK_PEX] = clk;
838
839 /* cdev1 */
840 clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, 0, 26000000);
841 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0,
842 clk_base, 0, 94, periph_clk_enb_refcnt);
843 clks[TEGRA20_CLK_CDEV1] = clk;
844
845 /* cdev2 */
846 clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, 0, 26000000);
847 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0,
848 clk_base, 0, 93, periph_clk_enb_refcnt);
849 clks[TEGRA20_CLK_CDEV2] = clk;
850
851 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
852 data = &tegra_periph_clk_list[i];
853 clk = tegra_clk_register_periph(data->name, data->p.parent_names,
854 data->num_parents, &data->periph,
855 clk_base, data->offset, data->flags);
856 clks[data->clk_id] = clk;
857 }
858
859 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
860 data = &tegra_periph_nodiv_clk_list[i];
861 clk = tegra_clk_register_periph_nodiv(data->name,
862 data->p.parent_names,
863 data->num_parents, &data->periph,
864 clk_base, data->offset);
865 clks[data->clk_id] = clk;
866 }
867
868 tegra_periph_clk_init(clk_base, pmc_base, tegra20_clks, &pll_p_params);
869 }
870
871 static void __init tegra20_osc_clk_init(void)
872 {
873 struct clk *clk;
874 unsigned long input_freq;
875 unsigned int pll_ref_div;
876
877 input_freq = tegra20_clk_measure_input_freq();
878
879 /* clk_m */
880 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IGNORE_UNUSED,
881 input_freq);
882 clks[TEGRA20_CLK_CLK_M] = clk;
883
884 /* pll_ref */
885 pll_ref_div = tegra20_get_pll_ref_div();
886 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
887 CLK_SET_RATE_PARENT, 1, pll_ref_div);
888 clks[TEGRA20_CLK_PLL_REF] = clk;
889 }
890
891 /* Tegra20 CPU clock and reset control functions */
892 static void tegra20_wait_cpu_in_reset(u32 cpu)
893 {
894 unsigned int reg;
895
896 do {
897 reg = readl(clk_base +
898 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
899 cpu_relax();
900 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
901
902 return;
903 }
904
905 static void tegra20_put_cpu_in_reset(u32 cpu)
906 {
907 writel(CPU_RESET(cpu),
908 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
909 dmb();
910 }
911
912 static void tegra20_cpu_out_of_reset(u32 cpu)
913 {
914 writel(CPU_RESET(cpu),
915 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
916 wmb();
917 }
918
919 static void tegra20_enable_cpu_clock(u32 cpu)
920 {
921 unsigned int reg;
922
923 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
924 writel(reg & ~CPU_CLOCK(cpu),
925 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
926 barrier();
927 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
928 }
929
930 static void tegra20_disable_cpu_clock(u32 cpu)
931 {
932 unsigned int reg;
933
934 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
935 writel(reg | CPU_CLOCK(cpu),
936 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
937 }
938
939 #ifdef CONFIG_PM_SLEEP
940 static bool tegra20_cpu_rail_off_ready(void)
941 {
942 unsigned int cpu_rst_status;
943
944 cpu_rst_status = readl(clk_base +
945 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
946
947 return !!(cpu_rst_status & 0x2);
948 }
949
950 static void tegra20_cpu_clock_suspend(void)
951 {
952 /* switch coresite to clk_m, save off original source */
953 tegra20_cpu_clk_sctx.clk_csite_src =
954 readl(clk_base + CLK_SOURCE_CSITE);
955 writel(3<<30, clk_base + CLK_SOURCE_CSITE);
956
957 tegra20_cpu_clk_sctx.cpu_burst =
958 readl(clk_base + CCLK_BURST_POLICY);
959 tegra20_cpu_clk_sctx.pllx_base =
960 readl(clk_base + PLLX_BASE);
961 tegra20_cpu_clk_sctx.pllx_misc =
962 readl(clk_base + PLLX_MISC);
963 tegra20_cpu_clk_sctx.cclk_divider =
964 readl(clk_base + SUPER_CCLK_DIVIDER);
965 }
966
967 static void tegra20_cpu_clock_resume(void)
968 {
969 unsigned int reg, policy;
970
971 /* Is CPU complex already running on PLLX? */
972 reg = readl(clk_base + CCLK_BURST_POLICY);
973 policy = (reg >> CCLK_BURST_POLICY_SHIFT) & 0xF;
974
975 if (policy == CCLK_IDLE_POLICY)
976 reg = (reg >> CCLK_IDLE_POLICY_SHIFT) & 0xF;
977 else if (policy == CCLK_RUN_POLICY)
978 reg = (reg >> CCLK_RUN_POLICY_SHIFT) & 0xF;
979 else
980 BUG();
981
982 if (reg != CCLK_BURST_POLICY_PLLX) {
983 /* restore PLLX settings if CPU is on different PLL */
984 writel(tegra20_cpu_clk_sctx.pllx_misc,
985 clk_base + PLLX_MISC);
986 writel(tegra20_cpu_clk_sctx.pllx_base,
987 clk_base + PLLX_BASE);
988
989 /* wait for PLL stabilization if PLLX was enabled */
990 if (tegra20_cpu_clk_sctx.pllx_base & (1 << 30))
991 udelay(300);
992 }
993
994 /*
995 * Restore original burst policy setting for calls resulting from CPU
996 * LP2 in idle or system suspend.
997 */
998 writel(tegra20_cpu_clk_sctx.cclk_divider,
999 clk_base + SUPER_CCLK_DIVIDER);
1000 writel(tegra20_cpu_clk_sctx.cpu_burst,
1001 clk_base + CCLK_BURST_POLICY);
1002
1003 writel(tegra20_cpu_clk_sctx.clk_csite_src,
1004 clk_base + CLK_SOURCE_CSITE);
1005 }
1006 #endif
1007
1008 static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
1009 .wait_for_reset = tegra20_wait_cpu_in_reset,
1010 .put_in_reset = tegra20_put_cpu_in_reset,
1011 .out_of_reset = tegra20_cpu_out_of_reset,
1012 .enable_clock = tegra20_enable_cpu_clock,
1013 .disable_clock = tegra20_disable_cpu_clock,
1014 #ifdef CONFIG_PM_SLEEP
1015 .rail_off_ready = tegra20_cpu_rail_off_ready,
1016 .suspend = tegra20_cpu_clock_suspend,
1017 .resume = tegra20_cpu_clock_resume,
1018 #endif
1019 };
1020
1021 static struct tegra_clk_init_table init_table[] __initdata = {
1022 { TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1 },
1023 { TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1 },
1024 { TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1 },
1025 { TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 },
1026 { TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 },
1027 { TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1 },
1028 { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 1 },
1029 { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 1 },
1030 { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },
1031 { TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 1 },
1032 { TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1 },
1033 { TEGRA20_CLK_EMC, TEGRA20_CLK_CLK_MAX, 0, 1 },
1034 { TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },
1035 { TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0 },
1036 { TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0 },
1037 { TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0 },
1038 { TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0 },
1039 { TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0 },
1040 { TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1 },
1041 { TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1 },
1042 { TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1 },
1043 { TEGRA20_CLK_BLINK, TEGRA20_CLK_CLK_MAX, 32768, 1 },
1044 { TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
1045 { TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
1046 { TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0 },
1047 { TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 },
1048 { TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 },
1049 { TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 },
1050 { TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 },
1051 { TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 },
1052 { TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 },
1053 { TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0 },
1054 { TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0 },
1055 { TEGRA20_CLK_DISP1, TEGRA20_CLK_PLL_P, 600000000, 0 },
1056 { TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0 },
1057 { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 },
1058 { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 },
1059 /* must be the last entry */
1060 { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
1061 };
1062
1063 static void __init tegra20_clock_apply_init_table(void)
1064 {
1065 tegra_init_from_table(init_table, clks, TEGRA20_CLK_CLK_MAX);
1066 }
1067
1068 /*
1069 * Some clocks may be used by different drivers depending on the board
1070 * configuration. List those here to register them twice in the clock lookup
1071 * table under two names.
1072 */
1073 static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1074 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "utmip-pad", NULL),
1075 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-ehci.0", NULL),
1076 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-otg", NULL),
1077 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CCLK, NULL, "cpu"),
1078 /* must be the last entry */
1079 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CLK_MAX, NULL, NULL),
1080 };
1081
1082 static const struct of_device_id pmc_match[] __initconst = {
1083 { .compatible = "nvidia,tegra20-pmc" },
1084 { },
1085 };
1086
1087 static void __init tegra20_clock_init(struct device_node *np)
1088 {
1089 struct device_node *node;
1090
1091 clk_base = of_iomap(np, 0);
1092 if (!clk_base) {
1093 pr_err("Can't map CAR registers\n");
1094 BUG();
1095 }
1096
1097 node = of_find_matching_node(NULL, pmc_match);
1098 if (!node) {
1099 pr_err("Failed to find pmc node\n");
1100 BUG();
1101 }
1102
1103 pmc_base = of_iomap(node, 0);
1104 if (!pmc_base) {
1105 pr_err("Can't map pmc registers\n");
1106 BUG();
1107 }
1108
1109 clks = tegra_clk_init(clk_base, TEGRA20_CLK_CLK_MAX,
1110 TEGRA20_CLK_PERIPH_BANKS);
1111 if (!clks)
1112 return;
1113
1114 tegra20_osc_clk_init();
1115 tegra_fixed_clk_init(tegra20_clks);
1116 tegra20_pll_init();
1117 tegra20_super_clk_init();
1118 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL);
1119 tegra20_periph_clk_init();
1120 tegra20_audio_clk_init();
1121 tegra_pmc_clk_init(pmc_base, tegra20_clks);
1122
1123 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX);
1124
1125 tegra_add_of_provider(np);
1126 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1127
1128 tegra_clk_apply_init_table = tegra20_clock_apply_init_table;
1129
1130 tegra_cpu_car_ops = &tegra20_cpu_car_ops;
1131 }
1132 CLK_OF_DECLARE(tegra20, "nvidia,tegra20-car", tegra20_clock_init);
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