2 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
20 #include <linux/clkdev.h>
22 #include <linux/of_address.h>
23 #include <linux/delay.h>
24 #include <linux/export.h>
25 #include <linux/clk/tegra.h>
26 #include <dt-bindings/clock/tegra210-car.h>
32 * TEGRA210_CAR_BANK_COUNT: the number of peripheral clock register
33 * banks present in the Tegra210 CAR IP block. The banks are
34 * identified by single letters, e.g.: L, H, U, V, W, X, Y. See
35 * periph_regs[] in drivers/clk/tegra/clk.c
37 #define TEGRA210_CAR_BANK_COUNT 7
39 #define CLK_SOURCE_CSITE 0x1d4
40 #define CLK_SOURCE_EMC 0x19c
42 #define PLLC_BASE 0x80
44 #define PLLC_MISC0 0x88
45 #define PLLC_MISC1 0x8c
46 #define PLLC_MISC2 0x5d0
47 #define PLLC_MISC3 0x5d4
49 #define PLLC2_BASE 0x4e8
50 #define PLLC2_MISC0 0x4ec
51 #define PLLC2_MISC1 0x4f0
52 #define PLLC2_MISC2 0x4f4
53 #define PLLC2_MISC3 0x4f8
55 #define PLLC3_BASE 0x4fc
56 #define PLLC3_MISC0 0x500
57 #define PLLC3_MISC1 0x504
58 #define PLLC3_MISC2 0x508
59 #define PLLC3_MISC3 0x50c
61 #define PLLM_BASE 0x90
62 #define PLLM_MISC0 0x9c
63 #define PLLM_MISC1 0x98
64 #define PLLP_BASE 0xa0
65 #define PLLP_MISC0 0xac
66 #define PLLP_MISC1 0x680
67 #define PLLA_BASE 0xb0
68 #define PLLA_MISC0 0xbc
69 #define PLLA_MISC1 0xb8
70 #define PLLA_MISC2 0x5d8
71 #define PLLD_BASE 0xd0
72 #define PLLD_MISC0 0xdc
73 #define PLLD_MISC1 0xd8
74 #define PLLU_BASE 0xc0
75 #define PLLU_OUTA 0xc4
76 #define PLLU_MISC0 0xcc
77 #define PLLU_MISC1 0xc8
78 #define PLLX_BASE 0xe0
79 #define PLLX_MISC0 0xe4
80 #define PLLX_MISC1 0x510
81 #define PLLX_MISC2 0x514
82 #define PLLX_MISC3 0x518
83 #define PLLX_MISC4 0x5f0
84 #define PLLX_MISC5 0x5f4
85 #define PLLE_BASE 0xe8
86 #define PLLE_MISC0 0xec
87 #define PLLD2_BASE 0x4b8
88 #define PLLD2_MISC0 0x4bc
89 #define PLLD2_MISC1 0x570
90 #define PLLD2_MISC2 0x574
91 #define PLLD2_MISC3 0x578
92 #define PLLE_AUX 0x48c
93 #define PLLRE_BASE 0x4c4
94 #define PLLRE_MISC0 0x4c8
95 #define PLLDP_BASE 0x590
96 #define PLLDP_MISC 0x594
98 #define PLLC4_BASE 0x5a4
99 #define PLLC4_MISC0 0x5a8
100 #define PLLC4_OUT 0x5e4
101 #define PLLMB_BASE 0x5e8
102 #define PLLMB_MISC0 0x5ec
103 #define PLLA1_BASE 0x6a4
104 #define PLLA1_MISC0 0x6a8
105 #define PLLA1_MISC1 0x6ac
106 #define PLLA1_MISC2 0x6b0
107 #define PLLA1_MISC3 0x6b4
109 #define PLLU_IDDQ_BIT 31
110 #define PLLCX_IDDQ_BIT 27
111 #define PLLRE_IDDQ_BIT 24
112 #define PLLA_IDDQ_BIT 25
113 #define PLLD_IDDQ_BIT 20
114 #define PLLSS_IDDQ_BIT 18
115 #define PLLM_IDDQ_BIT 5
116 #define PLLMB_IDDQ_BIT 17
117 #define PLLXP_IDDQ_BIT 3
119 #define PLLCX_RESET_BIT 30
121 #define PLL_BASE_LOCK BIT(27)
122 #define PLLCX_BASE_LOCK BIT(26)
123 #define PLLE_MISC_LOCK BIT(11)
124 #define PLLRE_MISC_LOCK BIT(27)
126 #define PLL_MISC_LOCK_ENABLE 18
127 #define PLLC_MISC_LOCK_ENABLE 24
128 #define PLLDU_MISC_LOCK_ENABLE 22
129 #define PLLU_MISC_LOCK_ENABLE 29
130 #define PLLE_MISC_LOCK_ENABLE 9
131 #define PLLRE_MISC_LOCK_ENABLE 30
132 #define PLLSS_MISC_LOCK_ENABLE 30
133 #define PLLP_MISC_LOCK_ENABLE 18
134 #define PLLM_MISC_LOCK_ENABLE 4
135 #define PLLMB_MISC_LOCK_ENABLE 16
136 #define PLLA_MISC_LOCK_ENABLE 28
137 #define PLLU_MISC_LOCK_ENABLE 29
138 #define PLLD_MISC_LOCK_ENABLE 18
140 #define PLLA_SDM_DIN_MASK 0xffff
141 #define PLLA_SDM_EN_MASK BIT(26)
143 #define PLLD_SDM_EN_MASK BIT(16)
145 #define PLLD2_SDM_EN_MASK BIT(31)
146 #define PLLD2_SSC_EN_MASK BIT(30)
148 #define PLLDP_SS_CFG 0x598
149 #define PLLDP_SDM_EN_MASK BIT(31)
150 #define PLLDP_SSC_EN_MASK BIT(30)
151 #define PLLDP_SS_CTRL1 0x59c
152 #define PLLDP_SS_CTRL2 0x5a0
154 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
155 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
157 #define UTMIP_PLL_CFG2 0x488
158 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
159 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
160 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
161 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
162 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
163 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
164 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
165 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
166 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
167 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
169 #define UTMIP_PLL_CFG1 0x484
170 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
171 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
172 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
173 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
174 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
175 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
176 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
178 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
179 #define UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK BIT(31)
180 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
181 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
182 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(7)
183 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
184 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
185 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
186 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
187 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
188 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
190 #define PLLU_HW_PWRDN_CFG0 0x530
191 #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28)
192 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
193 #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7)
194 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
195 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
196 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
198 #define XUSB_PLL_CFG0 0x534
199 #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
200 #define XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK (0x3ff << 14)
202 #define SPARE_REG0 0x55c
203 #define CLK_M_DIVISOR_SHIFT 2
204 #define CLK_M_DIVISOR_MASK 0x3
207 * SDM fractional divisor is 16-bit 2's complement signed number within
208 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned
209 * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to
210 * indicate that SDM is disabled.
212 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
214 #define PLL_SDM_COEFF BIT(13)
215 #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU))
216 #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat)
218 /* Tegra CPU clock and reset control regs */
219 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
221 #ifdef CONFIG_PM_SLEEP
222 static struct cpu_clk_suspend_context
{
224 } tegra210_cpu_clk_sctx
;
227 static void __iomem
*clk_base
;
228 static void __iomem
*pmc_base
;
230 static unsigned long osc_freq
;
231 static unsigned long pll_ref_freq
;
233 static DEFINE_SPINLOCK(pll_d_lock
);
234 static DEFINE_SPINLOCK(pll_e_lock
);
235 static DEFINE_SPINLOCK(pll_re_lock
);
236 static DEFINE_SPINLOCK(pll_u_lock
);
237 static DEFINE_SPINLOCK(emc_lock
);
239 /* possible OSC frequencies in Hz */
240 static unsigned long tegra210_input_freq
[] = {
245 static const char *mux_pllmcp_clkm
[] = {
246 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3",
248 #define mux_pllmcp_clkm_idx NULL
250 #define PLL_ENABLE (1 << 30)
252 #define PLLCX_MISC1_IDDQ (1 << 27)
253 #define PLLCX_MISC0_RESET (1 << 30)
255 #define PLLCX_MISC0_DEFAULT_VALUE 0x40080000
256 #define PLLCX_MISC0_WRITE_MASK 0x400ffffb
257 #define PLLCX_MISC1_DEFAULT_VALUE 0x08000000
258 #define PLLCX_MISC1_WRITE_MASK 0x08003cff
259 #define PLLCX_MISC2_DEFAULT_VALUE 0x1f720f05
260 #define PLLCX_MISC2_WRITE_MASK 0xffffff17
261 #define PLLCX_MISC3_DEFAULT_VALUE 0x000000c4
262 #define PLLCX_MISC3_WRITE_MASK 0x00ffffff
265 #define PLLA_BASE_IDDQ (1 << 25)
266 #define PLLA_BASE_LOCK (1 << 27)
268 #define PLLA_MISC0_LOCK_ENABLE (1 << 28)
269 #define PLLA_MISC0_LOCK_OVERRIDE (1 << 27)
271 #define PLLA_MISC2_EN_SDM (1 << 26)
272 #define PLLA_MISC2_EN_DYNRAMP (1 << 25)
274 #define PLLA_MISC0_DEFAULT_VALUE 0x12000020
275 #define PLLA_MISC0_WRITE_MASK 0x7fffffff
276 #define PLLA_MISC2_DEFAULT_VALUE 0x0
277 #define PLLA_MISC2_WRITE_MASK 0x06ffffff
280 #define PLLD_MISC0_EN_SDM (1 << 16)
281 #define PLLD_MISC0_LOCK_OVERRIDE (1 << 17)
282 #define PLLD_MISC0_LOCK_ENABLE (1 << 18)
283 #define PLLD_MISC0_IDDQ (1 << 20)
284 #define PLLD_MISC0_DSI_CLKENABLE (1 << 21)
286 #define PLLD_MISC0_DEFAULT_VALUE 0x00140000
287 #define PLLD_MISC0_WRITE_MASK 0x3ff7ffff
288 #define PLLD_MISC1_DEFAULT_VALUE 0x20
289 #define PLLD_MISC1_WRITE_MASK 0x00ffffff
291 /* PLLD2 and PLLDP and PLLC4 */
292 #define PLLDSS_BASE_LOCK (1 << 27)
293 #define PLLDSS_BASE_LOCK_OVERRIDE (1 << 24)
294 #define PLLDSS_BASE_IDDQ (1 << 18)
295 #define PLLDSS_BASE_REF_SEL_SHIFT 25
296 #define PLLDSS_BASE_REF_SEL_MASK (0x3 << PLLDSS_BASE_REF_SEL_SHIFT)
298 #define PLLDSS_MISC0_LOCK_ENABLE (1 << 30)
300 #define PLLDSS_MISC1_CFG_EN_SDM (1 << 31)
301 #define PLLDSS_MISC1_CFG_EN_SSC (1 << 30)
303 #define PLLD2_MISC0_DEFAULT_VALUE 0x40000020
304 #define PLLD2_MISC1_CFG_DEFAULT_VALUE 0x10000000
305 #define PLLD2_MISC2_CTRL1_DEFAULT_VALUE 0x0
306 #define PLLD2_MISC3_CTRL2_DEFAULT_VALUE 0x0
308 #define PLLDP_MISC0_DEFAULT_VALUE 0x40000020
309 #define PLLDP_MISC1_CFG_DEFAULT_VALUE 0xc0000000
310 #define PLLDP_MISC2_CTRL1_DEFAULT_VALUE 0xf400f0da
311 #define PLLDP_MISC3_CTRL2_DEFAULT_VALUE 0x2004f400
313 #define PLLDSS_MISC0_WRITE_MASK 0x47ffffff
314 #define PLLDSS_MISC1_CFG_WRITE_MASK 0xf8000000
315 #define PLLDSS_MISC2_CTRL1_WRITE_MASK 0xffffffff
316 #define PLLDSS_MISC3_CTRL2_WRITE_MASK 0xffffffff
318 #define PLLC4_MISC0_DEFAULT_VALUE 0x40000000
321 #define PLLRE_MISC0_LOCK_ENABLE (1 << 30)
322 #define PLLRE_MISC0_LOCK_OVERRIDE (1 << 29)
323 #define PLLRE_MISC0_LOCK (1 << 27)
324 #define PLLRE_MISC0_IDDQ (1 << 24)
326 #define PLLRE_BASE_DEFAULT_VALUE 0x0
327 #define PLLRE_MISC0_DEFAULT_VALUE 0x41000000
329 #define PLLRE_BASE_DEFAULT_MASK 0x1c000000
330 #define PLLRE_MISC0_WRITE_MASK 0x67ffffff
333 #define PLLX_USE_DYN_RAMP 1
334 #define PLLX_BASE_LOCK (1 << 27)
336 #define PLLX_MISC0_FO_G_DISABLE (0x1 << 28)
337 #define PLLX_MISC0_LOCK_ENABLE (0x1 << 18)
339 #define PLLX_MISC2_DYNRAMP_STEPB_SHIFT 24
340 #define PLLX_MISC2_DYNRAMP_STEPB_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPB_SHIFT)
341 #define PLLX_MISC2_DYNRAMP_STEPA_SHIFT 16
342 #define PLLX_MISC2_DYNRAMP_STEPA_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPA_SHIFT)
343 #define PLLX_MISC2_NDIV_NEW_SHIFT 8
344 #define PLLX_MISC2_NDIV_NEW_MASK (0xFF << PLLX_MISC2_NDIV_NEW_SHIFT)
345 #define PLLX_MISC2_LOCK_OVERRIDE (0x1 << 4)
346 #define PLLX_MISC2_DYNRAMP_DONE (0x1 << 2)
347 #define PLLX_MISC2_EN_DYNRAMP (0x1 << 0)
349 #define PLLX_MISC3_IDDQ (0x1 << 3)
351 #define PLLX_MISC0_DEFAULT_VALUE PLLX_MISC0_LOCK_ENABLE
352 #define PLLX_MISC0_WRITE_MASK 0x10c40000
353 #define PLLX_MISC1_DEFAULT_VALUE 0x20
354 #define PLLX_MISC1_WRITE_MASK 0x00ffffff
355 #define PLLX_MISC2_DEFAULT_VALUE 0x0
356 #define PLLX_MISC2_WRITE_MASK 0xffffff11
357 #define PLLX_MISC3_DEFAULT_VALUE PLLX_MISC3_IDDQ
358 #define PLLX_MISC3_WRITE_MASK 0x01ff0f0f
359 #define PLLX_MISC4_DEFAULT_VALUE 0x0
360 #define PLLX_MISC4_WRITE_MASK 0x8000ffff
361 #define PLLX_MISC5_DEFAULT_VALUE 0x0
362 #define PLLX_MISC5_WRITE_MASK 0x0000ffff
364 #define PLLX_HW_CTRL_CFG 0x548
365 #define PLLX_HW_CTRL_CFG_SWCTRL (0x1 << 0)
368 #define PLLMB_BASE_LOCK (1 << 27)
370 #define PLLMB_MISC0_LOCK_OVERRIDE (1 << 18)
371 #define PLLMB_MISC0_IDDQ (1 << 17)
372 #define PLLMB_MISC0_LOCK_ENABLE (1 << 16)
374 #define PLLMB_MISC0_DEFAULT_VALUE 0x00030000
375 #define PLLMB_MISC0_WRITE_MASK 0x0007ffff
378 #define PLLP_BASE_OVERRIDE (1 << 28)
379 #define PLLP_BASE_LOCK (1 << 27)
381 #define PLLP_MISC0_LOCK_ENABLE (1 << 18)
382 #define PLLP_MISC0_LOCK_OVERRIDE (1 << 17)
383 #define PLLP_MISC0_IDDQ (1 << 3)
385 #define PLLP_MISC1_HSIO_EN_SHIFT 29
386 #define PLLP_MISC1_HSIO_EN (1 << PLLP_MISC1_HSIO_EN_SHIFT)
387 #define PLLP_MISC1_XUSB_EN_SHIFT 28
388 #define PLLP_MISC1_XUSB_EN (1 << PLLP_MISC1_XUSB_EN_SHIFT)
390 #define PLLP_MISC0_DEFAULT_VALUE 0x00040008
391 #define PLLP_MISC1_DEFAULT_VALUE 0x0
393 #define PLLP_MISC0_WRITE_MASK 0xdc6000f
394 #define PLLP_MISC1_WRITE_MASK 0x70ffffff
397 #define PLLU_BASE_LOCK (1 << 27)
398 #define PLLU_BASE_OVERRIDE (1 << 24)
399 #define PLLU_BASE_CLKENABLE_USB (1 << 21)
400 #define PLLU_BASE_CLKENABLE_HSIC (1 << 22)
401 #define PLLU_BASE_CLKENABLE_ICUSB (1 << 23)
402 #define PLLU_BASE_CLKENABLE_48M (1 << 25)
403 #define PLLU_BASE_CLKENABLE_ALL (PLLU_BASE_CLKENABLE_USB |\
404 PLLU_BASE_CLKENABLE_HSIC |\
405 PLLU_BASE_CLKENABLE_ICUSB |\
406 PLLU_BASE_CLKENABLE_48M)
408 #define PLLU_MISC0_IDDQ (1 << 31)
409 #define PLLU_MISC0_LOCK_ENABLE (1 << 29)
410 #define PLLU_MISC1_LOCK_OVERRIDE (1 << 0)
412 #define PLLU_MISC0_DEFAULT_VALUE 0xa0000000
413 #define PLLU_MISC1_DEFAULT_VALUE 0x0
415 #define PLLU_MISC0_WRITE_MASK 0xbfffffff
416 #define PLLU_MISC1_WRITE_MASK 0x00000007
418 static inline void _pll_misc_chk_default(void __iomem
*base
,
419 struct tegra_clk_pll_params
*params
,
420 u8 misc_num
, u32 default_val
, u32 mask
)
422 u32 boot_val
= readl_relaxed(base
+ params
->ext_misc_reg
[misc_num
]);
426 if (boot_val
!= default_val
) {
427 pr_warn("boot misc%d 0x%x: expected 0x%x\n",
428 misc_num
, boot_val
, default_val
);
429 pr_warn(" (comparison mask = 0x%x)\n", mask
);
430 params
->defaults_set
= false;
435 * PLLCX: PLLC, PLLC2, PLLC3, PLLA1
436 * Hybrid PLLs with dynamic ramp. Dynamic ramp is allowed for any transition
437 * that changes NDIV only, while PLL is already locked.
439 static void pllcx_check_defaults(struct tegra_clk_pll_params
*params
)
443 default_val
= PLLCX_MISC0_DEFAULT_VALUE
& (~PLLCX_MISC0_RESET
);
444 _pll_misc_chk_default(clk_base
, params
, 0, default_val
,
445 PLLCX_MISC0_WRITE_MASK
);
447 default_val
= PLLCX_MISC1_DEFAULT_VALUE
& (~PLLCX_MISC1_IDDQ
);
448 _pll_misc_chk_default(clk_base
, params
, 1, default_val
,
449 PLLCX_MISC1_WRITE_MASK
);
451 default_val
= PLLCX_MISC2_DEFAULT_VALUE
;
452 _pll_misc_chk_default(clk_base
, params
, 2, default_val
,
453 PLLCX_MISC2_WRITE_MASK
);
455 default_val
= PLLCX_MISC3_DEFAULT_VALUE
;
456 _pll_misc_chk_default(clk_base
, params
, 3, default_val
,
457 PLLCX_MISC3_WRITE_MASK
);
460 void tegra210_pllcx_set_defaults(const char *name
, struct tegra_clk_pll
*pllcx
)
462 pllcx
->params
->defaults_set
= true;
464 if (readl_relaxed(clk_base
+ pllcx
->params
->base_reg
) &
466 /* PLL is ON: only check if defaults already set */
467 pllcx_check_defaults(pllcx
->params
);
468 pr_warn("%s already enabled. Postponing set full defaults\n",
473 /* Defaults assert PLL reset, and set IDDQ */
474 writel_relaxed(PLLCX_MISC0_DEFAULT_VALUE
,
475 clk_base
+ pllcx
->params
->ext_misc_reg
[0]);
476 writel_relaxed(PLLCX_MISC1_DEFAULT_VALUE
,
477 clk_base
+ pllcx
->params
->ext_misc_reg
[1]);
478 writel_relaxed(PLLCX_MISC2_DEFAULT_VALUE
,
479 clk_base
+ pllcx
->params
->ext_misc_reg
[2]);
480 writel_relaxed(PLLCX_MISC3_DEFAULT_VALUE
,
481 clk_base
+ pllcx
->params
->ext_misc_reg
[3]);
485 void _pllc_set_defaults(struct tegra_clk_pll
*pllcx
)
487 tegra210_pllcx_set_defaults("PLL_C", pllcx
);
490 void _pllc2_set_defaults(struct tegra_clk_pll
*pllcx
)
492 tegra210_pllcx_set_defaults("PLL_C2", pllcx
);
495 void _pllc3_set_defaults(struct tegra_clk_pll
*pllcx
)
497 tegra210_pllcx_set_defaults("PLL_C3", pllcx
);
500 void _plla1_set_defaults(struct tegra_clk_pll
*pllcx
)
502 tegra210_pllcx_set_defaults("PLL_A1", pllcx
);
507 * PLL with dynamic ramp and fractional SDM. Dynamic ramp is not used.
508 * Fractional SDM is allowed to provide exact audio rates.
510 void tegra210_plla_set_defaults(struct tegra_clk_pll
*plla
)
513 u32 val
= readl_relaxed(clk_base
+ plla
->params
->base_reg
);
515 plla
->params
->defaults_set
= true;
517 if (val
& PLL_ENABLE
) {
519 * PLL is ON: check if defaults already set, then set those
520 * that can be updated in flight.
522 if (val
& PLLA_BASE_IDDQ
) {
523 pr_warn("PLL_A boot enabled with IDDQ set\n");
524 plla
->params
->defaults_set
= false;
527 pr_warn("PLL_A already enabled. Postponing set full defaults\n");
529 val
= PLLA_MISC0_DEFAULT_VALUE
; /* ignore lock enable */
530 mask
= PLLA_MISC0_LOCK_ENABLE
| PLLA_MISC0_LOCK_OVERRIDE
;
531 _pll_misc_chk_default(clk_base
, plla
->params
, 0, val
,
532 ~mask
& PLLA_MISC0_WRITE_MASK
);
534 val
= PLLA_MISC2_DEFAULT_VALUE
; /* ignore all but control bit */
535 _pll_misc_chk_default(clk_base
, plla
->params
, 2, val
,
536 PLLA_MISC2_EN_DYNRAMP
);
538 /* Enable lock detect */
539 val
= readl_relaxed(clk_base
+ plla
->params
->ext_misc_reg
[0]);
541 val
|= PLLA_MISC0_DEFAULT_VALUE
& mask
;
542 writel_relaxed(val
, clk_base
+ plla
->params
->ext_misc_reg
[0]);
548 /* set IDDQ, enable lock detect, disable dynamic ramp and SDM */
549 val
|= PLLA_BASE_IDDQ
;
550 writel_relaxed(val
, clk_base
+ plla
->params
->base_reg
);
551 writel_relaxed(PLLA_MISC0_DEFAULT_VALUE
,
552 clk_base
+ plla
->params
->ext_misc_reg
[0]);
553 writel_relaxed(PLLA_MISC2_DEFAULT_VALUE
,
554 clk_base
+ plla
->params
->ext_misc_reg
[2]);
560 * PLL with fractional SDM.
562 void tegra210_plld_set_defaults(struct tegra_clk_pll
*plld
)
567 plld
->params
->defaults_set
= true;
569 if (readl_relaxed(clk_base
+ plld
->params
->base_reg
) &
571 pr_warn("PLL_D already enabled. Postponing set full defaults\n");
574 * PLL is ON: check if defaults already set, then set those
575 * that can be updated in flight.
577 val
= PLLD_MISC1_DEFAULT_VALUE
;
578 _pll_misc_chk_default(clk_base
, plld
->params
, 1,
579 val
, PLLD_MISC1_WRITE_MASK
);
581 /* ignore lock, DSI and SDM controls, make sure IDDQ not set */
582 val
= PLLD_MISC0_DEFAULT_VALUE
& (~PLLD_MISC0_IDDQ
);
583 mask
|= PLLD_MISC0_DSI_CLKENABLE
| PLLD_MISC0_LOCK_ENABLE
|
584 PLLD_MISC0_LOCK_OVERRIDE
| PLLD_MISC0_EN_SDM
;
585 _pll_misc_chk_default(clk_base
, plld
->params
, 0, val
,
586 ~mask
& PLLD_MISC0_WRITE_MASK
);
588 /* Enable lock detect */
589 mask
= PLLD_MISC0_LOCK_ENABLE
| PLLD_MISC0_LOCK_OVERRIDE
;
590 val
= readl_relaxed(clk_base
+ plld
->params
->ext_misc_reg
[0]);
592 val
|= PLLD_MISC0_DEFAULT_VALUE
& mask
;
593 writel_relaxed(val
, clk_base
+ plld
->params
->ext_misc_reg
[0]);
599 val
= readl_relaxed(clk_base
+ plld
->params
->ext_misc_reg
[0]);
600 val
&= PLLD_MISC0_DSI_CLKENABLE
;
601 val
|= PLLD_MISC0_DEFAULT_VALUE
;
602 /* set IDDQ, enable lock detect, disable SDM */
603 writel_relaxed(val
, clk_base
+ plld
->params
->ext_misc_reg
[0]);
604 writel_relaxed(PLLD_MISC1_DEFAULT_VALUE
, clk_base
+
605 plld
->params
->ext_misc_reg
[1]);
611 * PLL with fractional SDM and Spread Spectrum (SDM is a must if SSC is used).
613 static void plldss_defaults(const char *pll_name
, struct tegra_clk_pll
*plldss
,
614 u32 misc0_val
, u32 misc1_val
, u32 misc2_val
, u32 misc3_val
)
617 u32 val
= readl_relaxed(clk_base
+ plldss
->params
->base_reg
);
619 plldss
->params
->defaults_set
= true;
621 if (val
& PLL_ENABLE
) {
622 pr_warn("%s already enabled. Postponing set full defaults\n",
626 * PLL is ON: check if defaults already set, then set those
627 * that can be updated in flight.
629 if (val
& PLLDSS_BASE_IDDQ
) {
630 pr_warn("plldss boot enabled with IDDQ set\n");
631 plldss
->params
->defaults_set
= false;
634 /* ignore lock enable */
635 default_val
= misc0_val
;
636 _pll_misc_chk_default(clk_base
, plldss
->params
, 0, default_val
,
637 PLLDSS_MISC0_WRITE_MASK
&
638 (~PLLDSS_MISC0_LOCK_ENABLE
));
641 * If SSC is used, check all settings, otherwise just confirm
642 * that SSC is not used on boot as well. Do nothing when using
643 * this function for PLLC4 that has only MISC0.
645 if (plldss
->params
->ssc_ctrl_en_mask
) {
646 default_val
= misc1_val
;
647 _pll_misc_chk_default(clk_base
, plldss
->params
, 1,
648 default_val
, PLLDSS_MISC1_CFG_WRITE_MASK
);
649 default_val
= misc2_val
;
650 _pll_misc_chk_default(clk_base
, plldss
->params
, 2,
651 default_val
, PLLDSS_MISC2_CTRL1_WRITE_MASK
);
652 default_val
= misc3_val
;
653 _pll_misc_chk_default(clk_base
, plldss
->params
, 3,
654 default_val
, PLLDSS_MISC3_CTRL2_WRITE_MASK
);
655 } else if (plldss
->params
->ext_misc_reg
[1]) {
656 default_val
= misc1_val
;
657 _pll_misc_chk_default(clk_base
, plldss
->params
, 1,
658 default_val
, PLLDSS_MISC1_CFG_WRITE_MASK
&
659 (~PLLDSS_MISC1_CFG_EN_SDM
));
662 /* Enable lock detect */
663 if (val
& PLLDSS_BASE_LOCK_OVERRIDE
) {
664 val
&= ~PLLDSS_BASE_LOCK_OVERRIDE
;
665 writel_relaxed(val
, clk_base
+
666 plldss
->params
->base_reg
);
669 val
= readl_relaxed(clk_base
+ plldss
->params
->ext_misc_reg
[0]);
670 val
&= ~PLLDSS_MISC0_LOCK_ENABLE
;
671 val
|= misc0_val
& PLLDSS_MISC0_LOCK_ENABLE
;
672 writel_relaxed(val
, clk_base
+ plldss
->params
->ext_misc_reg
[0]);
678 /* set IDDQ, enable lock detect, configure SDM/SSC */
679 val
|= PLLDSS_BASE_IDDQ
;
680 val
&= ~PLLDSS_BASE_LOCK_OVERRIDE
;
681 writel_relaxed(val
, clk_base
+ plldss
->params
->base_reg
);
683 /* When using this function for PLLC4 exit here */
684 if (!plldss
->params
->ext_misc_reg
[1]) {
685 writel_relaxed(misc0_val
, clk_base
+
686 plldss
->params
->ext_misc_reg
[0]);
691 writel_relaxed(misc0_val
, clk_base
+
692 plldss
->params
->ext_misc_reg
[0]);
693 /* if SSC used set by 1st enable */
694 writel_relaxed(misc1_val
& (~PLLDSS_MISC1_CFG_EN_SSC
),
695 clk_base
+ plldss
->params
->ext_misc_reg
[1]);
696 writel_relaxed(misc2_val
, clk_base
+ plldss
->params
->ext_misc_reg
[2]);
697 writel_relaxed(misc3_val
, clk_base
+ plldss
->params
->ext_misc_reg
[3]);
701 void tegra210_plld2_set_defaults(struct tegra_clk_pll
*plld2
)
703 plldss_defaults("PLL_D2", plld2
, PLLD2_MISC0_DEFAULT_VALUE
,
704 PLLD2_MISC1_CFG_DEFAULT_VALUE
,
705 PLLD2_MISC2_CTRL1_DEFAULT_VALUE
,
706 PLLD2_MISC3_CTRL2_DEFAULT_VALUE
);
709 void tegra210_plldp_set_defaults(struct tegra_clk_pll
*plldp
)
711 plldss_defaults("PLL_DP", plldp
, PLLDP_MISC0_DEFAULT_VALUE
,
712 PLLDP_MISC1_CFG_DEFAULT_VALUE
,
713 PLLDP_MISC2_CTRL1_DEFAULT_VALUE
,
714 PLLDP_MISC3_CTRL2_DEFAULT_VALUE
);
719 * Base and misc0 layout is the same as PLLD2/PLLDP, but no SDM/SSC support.
720 * VCO is exposed to the clock tree via fixed 1/3 and 1/5 dividers.
722 void tegra210_pllc4_set_defaults(struct tegra_clk_pll
*pllc4
)
724 plldss_defaults("PLL_C4", pllc4
, PLLC4_MISC0_DEFAULT_VALUE
, 0, 0, 0);
729 * VCO is exposed to the clock tree directly along with post-divider output
731 void tegra210_pllre_set_defaults(struct tegra_clk_pll
*pllre
)
734 u32 val
= readl_relaxed(clk_base
+ pllre
->params
->base_reg
);
736 pllre
->params
->defaults_set
= true;
738 if (val
& PLL_ENABLE
) {
739 pr_warn("PLL_RE already enabled. Postponing set full defaults\n");
742 * PLL is ON: check if defaults already set, then set those
743 * that can be updated in flight.
745 val
&= PLLRE_BASE_DEFAULT_MASK
;
746 if (val
!= PLLRE_BASE_DEFAULT_VALUE
) {
747 pr_warn("pllre boot base 0x%x : expected 0x%x\n",
748 val
, PLLRE_BASE_DEFAULT_VALUE
);
749 pr_warn("(comparison mask = 0x%x)\n",
750 PLLRE_BASE_DEFAULT_MASK
);
751 pllre
->params
->defaults_set
= false;
754 /* Ignore lock enable */
755 val
= PLLRE_MISC0_DEFAULT_VALUE
& (~PLLRE_MISC0_IDDQ
);
756 mask
= PLLRE_MISC0_LOCK_ENABLE
| PLLRE_MISC0_LOCK_OVERRIDE
;
757 _pll_misc_chk_default(clk_base
, pllre
->params
, 0, val
,
758 ~mask
& PLLRE_MISC0_WRITE_MASK
);
760 /* Enable lock detect */
761 val
= readl_relaxed(clk_base
+ pllre
->params
->ext_misc_reg
[0]);
763 val
|= PLLRE_MISC0_DEFAULT_VALUE
& mask
;
764 writel_relaxed(val
, clk_base
+ pllre
->params
->ext_misc_reg
[0]);
770 /* set IDDQ, enable lock detect */
771 val
&= ~PLLRE_BASE_DEFAULT_MASK
;
772 val
|= PLLRE_BASE_DEFAULT_VALUE
& PLLRE_BASE_DEFAULT_MASK
;
773 writel_relaxed(val
, clk_base
+ pllre
->params
->base_reg
);
774 writel_relaxed(PLLRE_MISC0_DEFAULT_VALUE
,
775 clk_base
+ pllre
->params
->ext_misc_reg
[0]);
779 static void pllx_get_dyn_steps(struct clk_hw
*hw
, u32
*step_a
, u32
*step_b
)
781 unsigned long input_rate
;
783 if (!IS_ERR_OR_NULL(hw
->clk
)) {
784 input_rate
= clk_hw_get_rate(clk_hw_get_parent(hw
));
786 input_rate
/= tegra_pll_get_fixed_mdiv(hw
, input_rate
);
788 input_rate
= 38400000;
791 switch (input_rate
) {
807 pr_err("%s: Unexpected reference rate %lu\n",
808 __func__
, input_rate
);
813 static void pllx_check_defaults(struct tegra_clk_pll
*pll
)
817 default_val
= PLLX_MISC0_DEFAULT_VALUE
;
818 /* ignore lock enable */
819 _pll_misc_chk_default(clk_base
, pll
->params
, 0, default_val
,
820 PLLX_MISC0_WRITE_MASK
& (~PLLX_MISC0_LOCK_ENABLE
));
822 default_val
= PLLX_MISC1_DEFAULT_VALUE
;
823 _pll_misc_chk_default(clk_base
, pll
->params
, 1, default_val
,
824 PLLX_MISC1_WRITE_MASK
);
826 /* ignore all but control bit */
827 default_val
= PLLX_MISC2_DEFAULT_VALUE
;
828 _pll_misc_chk_default(clk_base
, pll
->params
, 2,
829 default_val
, PLLX_MISC2_EN_DYNRAMP
);
831 default_val
= PLLX_MISC3_DEFAULT_VALUE
& (~PLLX_MISC3_IDDQ
);
832 _pll_misc_chk_default(clk_base
, pll
->params
, 3, default_val
,
833 PLLX_MISC3_WRITE_MASK
);
835 default_val
= PLLX_MISC4_DEFAULT_VALUE
;
836 _pll_misc_chk_default(clk_base
, pll
->params
, 4, default_val
,
837 PLLX_MISC4_WRITE_MASK
);
839 default_val
= PLLX_MISC5_DEFAULT_VALUE
;
840 _pll_misc_chk_default(clk_base
, pll
->params
, 5, default_val
,
841 PLLX_MISC5_WRITE_MASK
);
844 void tegra210_pllx_set_defaults(struct tegra_clk_pll
*pllx
)
849 pllx
->params
->defaults_set
= true;
851 /* Get ready dyn ramp state machine settings */
852 pllx_get_dyn_steps(&pllx
->hw
, &step_a
, &step_b
);
853 val
= PLLX_MISC2_DEFAULT_VALUE
& (~PLLX_MISC2_DYNRAMP_STEPA_MASK
) &
854 (~PLLX_MISC2_DYNRAMP_STEPB_MASK
);
855 val
|= step_a
<< PLLX_MISC2_DYNRAMP_STEPA_SHIFT
;
856 val
|= step_b
<< PLLX_MISC2_DYNRAMP_STEPB_SHIFT
;
858 if (readl_relaxed(clk_base
+ pllx
->params
->base_reg
) & PLL_ENABLE
) {
859 pr_warn("PLL_X already enabled. Postponing set full defaults\n");
862 * PLL is ON: check if defaults already set, then set those
863 * that can be updated in flight.
865 pllx_check_defaults(pllx
);
867 /* Configure dyn ramp, disable lock override */
868 writel_relaxed(val
, clk_base
+ pllx
->params
->ext_misc_reg
[2]);
870 /* Enable lock detect */
871 val
= readl_relaxed(clk_base
+ pllx
->params
->ext_misc_reg
[0]);
872 val
&= ~PLLX_MISC0_LOCK_ENABLE
;
873 val
|= PLLX_MISC0_DEFAULT_VALUE
& PLLX_MISC0_LOCK_ENABLE
;
874 writel_relaxed(val
, clk_base
+ pllx
->params
->ext_misc_reg
[0]);
880 /* Enable lock detect and CPU output */
881 writel_relaxed(PLLX_MISC0_DEFAULT_VALUE
, clk_base
+
882 pllx
->params
->ext_misc_reg
[0]);
885 writel_relaxed(PLLX_MISC1_DEFAULT_VALUE
, clk_base
+
886 pllx
->params
->ext_misc_reg
[1]);
888 /* Configure dyn ramp state machine, disable lock override */
889 writel_relaxed(val
, clk_base
+ pllx
->params
->ext_misc_reg
[2]);
892 writel_relaxed(PLLX_MISC3_DEFAULT_VALUE
, clk_base
+
893 pllx
->params
->ext_misc_reg
[3]);
896 writel_relaxed(PLLX_MISC4_DEFAULT_VALUE
, clk_base
+
897 pllx
->params
->ext_misc_reg
[4]);
898 writel_relaxed(PLLX_MISC5_DEFAULT_VALUE
, clk_base
+
899 pllx
->params
->ext_misc_reg
[5]);
904 void tegra210_pllmb_set_defaults(struct tegra_clk_pll
*pllmb
)
906 u32 mask
, val
= readl_relaxed(clk_base
+ pllmb
->params
->base_reg
);
908 pllmb
->params
->defaults_set
= true;
910 if (val
& PLL_ENABLE
) {
911 pr_warn("PLL_MB already enabled. Postponing set full defaults\n");
914 * PLL is ON: check if defaults already set, then set those
915 * that can be updated in flight.
917 val
= PLLMB_MISC0_DEFAULT_VALUE
& (~PLLMB_MISC0_IDDQ
);
918 mask
= PLLMB_MISC0_LOCK_ENABLE
| PLLMB_MISC0_LOCK_OVERRIDE
;
919 _pll_misc_chk_default(clk_base
, pllmb
->params
, 0, val
,
920 ~mask
& PLLMB_MISC0_WRITE_MASK
);
922 /* Enable lock detect */
923 val
= readl_relaxed(clk_base
+ pllmb
->params
->ext_misc_reg
[0]);
925 val
|= PLLMB_MISC0_DEFAULT_VALUE
& mask
;
926 writel_relaxed(val
, clk_base
+ pllmb
->params
->ext_misc_reg
[0]);
932 /* set IDDQ, enable lock detect */
933 writel_relaxed(PLLMB_MISC0_DEFAULT_VALUE
,
934 clk_base
+ pllmb
->params
->ext_misc_reg
[0]);
940 * VCO is exposed to the clock tree directly along with post-divider output.
941 * Both VCO and post-divider output rates are fixed at 408MHz and 204MHz,
944 static void pllp_check_defaults(struct tegra_clk_pll
*pll
, bool enabled
)
948 /* Ignore lock enable (will be set), make sure not in IDDQ if enabled */
949 val
= PLLP_MISC0_DEFAULT_VALUE
& (~PLLP_MISC0_IDDQ
);
950 mask
= PLLP_MISC0_LOCK_ENABLE
| PLLP_MISC0_LOCK_OVERRIDE
;
952 mask
|= PLLP_MISC0_IDDQ
;
953 _pll_misc_chk_default(clk_base
, pll
->params
, 0, val
,
954 ~mask
& PLLP_MISC0_WRITE_MASK
);
956 /* Ignore branch controls */
957 val
= PLLP_MISC1_DEFAULT_VALUE
;
958 mask
= PLLP_MISC1_HSIO_EN
| PLLP_MISC1_XUSB_EN
;
959 _pll_misc_chk_default(clk_base
, pll
->params
, 1, val
,
960 ~mask
& PLLP_MISC1_WRITE_MASK
);
963 void tegra210_pllp_set_defaults(struct tegra_clk_pll
*pllp
)
966 u32 val
= readl_relaxed(clk_base
+ pllp
->params
->base_reg
);
968 pllp
->params
->defaults_set
= true;
970 if (val
& PLL_ENABLE
) {
971 pr_warn("PLL_P already enabled. Postponing set full defaults\n");
974 * PLL is ON: check if defaults already set, then set those
975 * that can be updated in flight.
977 pllp_check_defaults(pllp
, true);
979 /* Enable lock detect */
980 val
= readl_relaxed(clk_base
+ pllp
->params
->ext_misc_reg
[0]);
981 mask
= PLLP_MISC0_LOCK_ENABLE
| PLLP_MISC0_LOCK_OVERRIDE
;
983 val
|= PLLP_MISC0_DEFAULT_VALUE
& mask
;
984 writel_relaxed(val
, clk_base
+ pllp
->params
->ext_misc_reg
[0]);
990 /* set IDDQ, enable lock detect */
991 writel_relaxed(PLLP_MISC0_DEFAULT_VALUE
,
992 clk_base
+ pllp
->params
->ext_misc_reg
[0]);
994 /* Preserve branch control */
995 val
= readl_relaxed(clk_base
+ pllp
->params
->ext_misc_reg
[1]);
996 mask
= PLLP_MISC1_HSIO_EN
| PLLP_MISC1_XUSB_EN
;
998 val
|= ~mask
& PLLP_MISC1_DEFAULT_VALUE
;
999 writel_relaxed(val
, clk_base
+ pllp
->params
->ext_misc_reg
[1]);
1005 * VCO is exposed to the clock tree directly along with post-divider output.
1006 * Both VCO and post-divider output rates are fixed at 480MHz and 240MHz,
1009 static void pllu_check_defaults(struct tegra_clk_pll
*pll
, bool hw_control
)
1013 /* Ignore lock enable (will be set) and IDDQ if under h/w control */
1014 val
= PLLU_MISC0_DEFAULT_VALUE
& (~PLLU_MISC0_IDDQ
);
1015 mask
= PLLU_MISC0_LOCK_ENABLE
| (hw_control
? PLLU_MISC0_IDDQ
: 0);
1016 _pll_misc_chk_default(clk_base
, pll
->params
, 0, val
,
1017 ~mask
& PLLU_MISC0_WRITE_MASK
);
1019 val
= PLLU_MISC1_DEFAULT_VALUE
;
1020 mask
= PLLU_MISC1_LOCK_OVERRIDE
;
1021 _pll_misc_chk_default(clk_base
, pll
->params
, 1, val
,
1022 ~mask
& PLLU_MISC1_WRITE_MASK
);
1025 void tegra210_pllu_set_defaults(struct tegra_clk_pll
*pllu
)
1027 u32 val
= readl_relaxed(clk_base
+ pllu
->params
->base_reg
);
1029 pllu
->params
->defaults_set
= true;
1031 if (val
& PLL_ENABLE
) {
1032 pr_warn("PLL_U already enabled. Postponing set full defaults\n");
1035 * PLL is ON: check if defaults already set, then set those
1036 * that can be updated in flight.
1038 pllu_check_defaults(pllu
, false);
1040 /* Enable lock detect */
1041 val
= readl_relaxed(clk_base
+ pllu
->params
->ext_misc_reg
[0]);
1042 val
&= ~PLLU_MISC0_LOCK_ENABLE
;
1043 val
|= PLLU_MISC0_DEFAULT_VALUE
& PLLU_MISC0_LOCK_ENABLE
;
1044 writel_relaxed(val
, clk_base
+ pllu
->params
->ext_misc_reg
[0]);
1046 val
= readl_relaxed(clk_base
+ pllu
->params
->ext_misc_reg
[1]);
1047 val
&= ~PLLU_MISC1_LOCK_OVERRIDE
;
1048 val
|= PLLU_MISC1_DEFAULT_VALUE
& PLLU_MISC1_LOCK_OVERRIDE
;
1049 writel_relaxed(val
, clk_base
+ pllu
->params
->ext_misc_reg
[1]);
1055 /* set IDDQ, enable lock detect */
1056 writel_relaxed(PLLU_MISC0_DEFAULT_VALUE
,
1057 clk_base
+ pllu
->params
->ext_misc_reg
[0]);
1058 writel_relaxed(PLLU_MISC1_DEFAULT_VALUE
,
1059 clk_base
+ pllu
->params
->ext_misc_reg
[1]);
1063 #define mask(w) ((1 << (w)) - 1)
1064 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
1065 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
1066 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
1067 mask(p->params->div_nmp->divp_width))
1069 #define divm_shift(p) ((p)->params->div_nmp->divm_shift)
1070 #define divn_shift(p) ((p)->params->div_nmp->divn_shift)
1071 #define divp_shift(p) ((p)->params->div_nmp->divp_shift)
1073 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
1074 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
1075 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
1077 #define PLL_LOCKDET_DELAY 2 /* Lock detection safety delays */
1078 static int tegra210_wait_for_mask(struct tegra_clk_pll
*pll
,
1084 for (i
= 0; i
< pll
->params
->lock_delay
/ PLL_LOCKDET_DELAY
+ 1; i
++) {
1085 udelay(PLL_LOCKDET_DELAY
);
1086 val
= readl_relaxed(clk_base
+ reg
);
1087 if ((val
& mask
) == mask
) {
1088 udelay(PLL_LOCKDET_DELAY
);
1095 static int tegra210_pllx_dyn_ramp(struct tegra_clk_pll
*pllx
,
1096 struct tegra_clk_pll_freq_table
*cfg
)
1098 u32 val
, base
, ndiv_new_mask
;
1100 ndiv_new_mask
= (divn_mask(pllx
) >> pllx
->params
->div_nmp
->divn_shift
)
1101 << PLLX_MISC2_NDIV_NEW_SHIFT
;
1103 val
= readl_relaxed(clk_base
+ pllx
->params
->ext_misc_reg
[2]);
1104 val
&= (~ndiv_new_mask
);
1105 val
|= cfg
->n
<< PLLX_MISC2_NDIV_NEW_SHIFT
;
1106 writel_relaxed(val
, clk_base
+ pllx
->params
->ext_misc_reg
[2]);
1109 val
= readl_relaxed(clk_base
+ pllx
->params
->ext_misc_reg
[2]);
1110 val
|= PLLX_MISC2_EN_DYNRAMP
;
1111 writel_relaxed(val
, clk_base
+ pllx
->params
->ext_misc_reg
[2]);
1114 tegra210_wait_for_mask(pllx
, pllx
->params
->ext_misc_reg
[2],
1115 PLLX_MISC2_DYNRAMP_DONE
);
1117 base
= readl_relaxed(clk_base
+ pllx
->params
->base_reg
) &
1118 (~divn_mask_shifted(pllx
));
1119 base
|= cfg
->n
<< pllx
->params
->div_nmp
->divn_shift
;
1120 writel_relaxed(base
, clk_base
+ pllx
->params
->base_reg
);
1123 val
&= ~PLLX_MISC2_EN_DYNRAMP
;
1124 writel_relaxed(val
, clk_base
+ pllx
->params
->ext_misc_reg
[2]);
1127 pr_debug("%s: dynamic ramp to m = %u n = %u p = %u, Fout = %lu kHz\n",
1128 __clk_get_name(pllx
->hw
.clk
), cfg
->m
, cfg
->n
, cfg
->p
,
1129 cfg
->input_rate
/ cfg
->m
* cfg
->n
/
1130 pllx
->params
->pdiv_tohw
[cfg
->p
].pdiv
/ 1000);
1136 * Common configuration for PLLs with fixed input divider policy:
1137 * - always set fixed M-value based on the reference rate
1138 * - always set P-value value 1:1 for output rates above VCO minimum, and
1139 * choose minimum necessary P-value for output rates below VCO maximum
1140 * - calculate N-value based on selected M and P
1141 * - calculate SDM_DIN fractional part
1143 static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw
*hw
,
1144 struct tegra_clk_pll_freq_table
*cfg
,
1145 unsigned long rate
, unsigned long input_rate
)
1147 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
1148 struct tegra_clk_pll_params
*params
= pll
->params
;
1150 unsigned long cf
, p_rate
;
1156 if (!(params
->flags
& TEGRA_PLL_VCO_OUT
)) {
1157 p
= DIV_ROUND_UP(params
->vco_min
, rate
);
1158 p
= params
->round_p_to_pdiv(p
, &pdiv
);
1160 p
= rate
>= params
->vco_min
? 1 : -EINVAL
;
1163 if (IS_ERR_VALUE(p
))
1166 cfg
->m
= tegra_pll_get_fixed_mdiv(hw
, input_rate
);
1169 /* Store P as HW value, as that is what is expected */
1170 cfg
->p
= tegra_pll_p_div_to_hw(pll
, cfg
->p
);
1173 if (p_rate
> params
->vco_max
)
1174 p_rate
= params
->vco_max
;
1175 cf
= input_rate
/ cfg
->m
;
1176 cfg
->n
= p_rate
/ cf
;
1179 if (params
->sdm_ctrl_reg
) {
1180 unsigned long rem
= p_rate
- cf
* cfg
->n
;
1181 /* If ssc is enabled SDM enabled as well, even for integer n */
1182 if (rem
|| params
->ssc_ctrl_reg
) {
1183 u64 s
= rem
* PLL_SDM_COEFF
;
1186 s
-= PLL_SDM_COEFF
/ 2;
1187 cfg
->sdm_data
= sdin_din_to_data(s
);
1191 cfg
->input_rate
= input_rate
;
1192 cfg
->output_rate
= rate
;
1198 * clk_pll_set_gain - set gain to m, n to calculate correct VCO rate
1200 * @cfg: struct tegra_clk_pll_freq_table * cfg
1203 * Fvco = Fref * NDIV / MDIV
1205 * For fractional mode:
1206 * Fvco = Fref * (NDIV + 0.5 + SDM_DIN / PLL_SDM_COEFF) / MDIV
1208 static void tegra210_clk_pll_set_gain(struct tegra_clk_pll_freq_table
*cfg
)
1210 cfg
->n
= cfg
->n
* PLL_SDM_COEFF
+ PLL_SDM_COEFF
/2 +
1211 sdin_data_to_din(cfg
->sdm_data
);
1212 cfg
->m
*= PLL_SDM_COEFF
;
1215 unsigned long tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params
*params
,
1216 unsigned long parent_rate
)
1218 unsigned long vco_min
= params
->vco_min
;
1220 params
->vco_min
+= DIV_ROUND_UP(parent_rate
, PLL_SDM_COEFF
);
1221 vco_min
= min(vco_min
, params
->vco_min
);
1226 static struct div_nmp pllx_nmp
= {
1235 * PLL post divider maps - two types: quasi-linear and exponential
1238 #define PLL_QLIN_PDIV_MAX 16
1239 static const struct pdiv_map pll_qlin_pdiv_to_hw
[] = {
1240 { .pdiv
= 1, .hw_val
= 0 },
1241 { .pdiv
= 2, .hw_val
= 1 },
1242 { .pdiv
= 3, .hw_val
= 2 },
1243 { .pdiv
= 4, .hw_val
= 3 },
1244 { .pdiv
= 5, .hw_val
= 4 },
1245 { .pdiv
= 6, .hw_val
= 5 },
1246 { .pdiv
= 8, .hw_val
= 6 },
1247 { .pdiv
= 9, .hw_val
= 7 },
1248 { .pdiv
= 10, .hw_val
= 8 },
1249 { .pdiv
= 12, .hw_val
= 9 },
1250 { .pdiv
= 15, .hw_val
= 10 },
1251 { .pdiv
= 16, .hw_val
= 11 },
1252 { .pdiv
= 18, .hw_val
= 12 },
1253 { .pdiv
= 20, .hw_val
= 13 },
1254 { .pdiv
= 24, .hw_val
= 14 },
1255 { .pdiv
= 30, .hw_val
= 15 },
1256 { .pdiv
= 32, .hw_val
= 16 },
1259 static u32
pll_qlin_p_to_pdiv(u32 p
, u32
*pdiv
)
1264 for (i
= 0; i
<= PLL_QLIN_PDIV_MAX
; i
++) {
1265 if (p
<= pll_qlin_pdiv_to_hw
[i
].pdiv
) {
1268 return pll_qlin_pdiv_to_hw
[i
].pdiv
;
1276 #define PLL_EXPO_PDIV_MAX 7
1277 static const struct pdiv_map pll_expo_pdiv_to_hw
[] = {
1278 { .pdiv
= 1, .hw_val
= 0 },
1279 { .pdiv
= 2, .hw_val
= 1 },
1280 { .pdiv
= 4, .hw_val
= 2 },
1281 { .pdiv
= 8, .hw_val
= 3 },
1282 { .pdiv
= 16, .hw_val
= 4 },
1283 { .pdiv
= 32, .hw_val
= 5 },
1284 { .pdiv
= 64, .hw_val
= 6 },
1285 { .pdiv
= 128, .hw_val
= 7 },
1288 static u32
pll_expo_p_to_pdiv(u32 p
, u32
*pdiv
)
1296 if (i
<= PLL_EXPO_PDIV_MAX
) {
1305 static struct tegra_clk_pll_freq_table pll_x_freq_table
[] = {
1307 { 12000000, 1000000000, 166, 1, 1, 0 }, /* actual: 996.0 MHz */
1308 { 13000000, 1000000000, 153, 1, 1, 0 }, /* actual: 994.0 MHz */
1309 { 38400000, 1000000000, 156, 3, 1, 0 }, /* actual: 998.4 MHz */
1310 { 0, 0, 0, 0, 0, 0 },
1313 static struct tegra_clk_pll_params pll_x_params
= {
1314 .input_min
= 12000000,
1315 .input_max
= 800000000,
1318 .vco_min
= 1350000000,
1319 .vco_max
= 3000000000UL,
1320 .base_reg
= PLLX_BASE
,
1321 .misc_reg
= PLLX_MISC0
,
1322 .lock_mask
= PLL_BASE_LOCK
,
1323 .lock_enable_bit_idx
= PLL_MISC_LOCK_ENABLE
,
1325 .ext_misc_reg
[0] = PLLX_MISC0
,
1326 .ext_misc_reg
[1] = PLLX_MISC1
,
1327 .ext_misc_reg
[2] = PLLX_MISC2
,
1328 .ext_misc_reg
[3] = PLLX_MISC3
,
1329 .ext_misc_reg
[4] = PLLX_MISC4
,
1330 .ext_misc_reg
[5] = PLLX_MISC5
,
1331 .iddq_reg
= PLLX_MISC3
,
1332 .iddq_bit_idx
= PLLXP_IDDQ_BIT
,
1333 .max_p
= PLL_QLIN_PDIV_MAX
,
1335 .dyn_ramp_reg
= PLLX_MISC2
,
1338 .round_p_to_pdiv
= pll_qlin_p_to_pdiv
,
1339 .pdiv_tohw
= pll_qlin_pdiv_to_hw
,
1340 .div_nmp
= &pllx_nmp
,
1341 .freq_table
= pll_x_freq_table
,
1342 .flags
= TEGRA_PLL_USE_LOCK
| TEGRA_PLL_HAS_LOCK_ENABLE
,
1343 .dyn_ramp
= tegra210_pllx_dyn_ramp
,
1344 .set_defaults
= tegra210_pllx_set_defaults
,
1345 .calc_rate
= tegra210_pll_fixed_mdiv_cfg
,
1348 static struct div_nmp pllc_nmp
= {
1357 static struct tegra_clk_pll_freq_table pll_cx_freq_table
[] = {
1358 { 12000000, 510000000, 85, 1, 1, 0 },
1359 { 13000000, 510000000, 78, 1, 1, 0 }, /* actual: 507.0 MHz */
1360 { 38400000, 510000000, 79, 3, 1, 0 }, /* actual: 505.6 MHz */
1361 { 0, 0, 0, 0, 0, 0 },
1364 static struct tegra_clk_pll_params pll_c_params
= {
1365 .input_min
= 12000000,
1366 .input_max
= 700000000,
1369 .vco_min
= 600000000,
1370 .vco_max
= 1200000000,
1371 .base_reg
= PLLC_BASE
,
1372 .misc_reg
= PLLC_MISC0
,
1373 .lock_mask
= PLL_BASE_LOCK
,
1375 .iddq_reg
= PLLC_MISC1
,
1376 .iddq_bit_idx
= PLLCX_IDDQ_BIT
,
1377 .reset_reg
= PLLC_MISC0
,
1378 .reset_bit_idx
= PLLCX_RESET_BIT
,
1379 .max_p
= PLL_QLIN_PDIV_MAX
,
1380 .ext_misc_reg
[0] = PLLC_MISC0
,
1381 .ext_misc_reg
[1] = PLLC_MISC1
,
1382 .ext_misc_reg
[2] = PLLC_MISC2
,
1383 .ext_misc_reg
[3] = PLLC_MISC3
,
1384 .round_p_to_pdiv
= pll_qlin_p_to_pdiv
,
1385 .pdiv_tohw
= pll_qlin_pdiv_to_hw
,
1387 .div_nmp
= &pllc_nmp
,
1388 .freq_table
= pll_cx_freq_table
,
1389 .flags
= TEGRA_PLL_USE_LOCK
| TEGRA_PLL_HAS_LOCK_ENABLE
,
1390 .set_defaults
= _pllc_set_defaults
,
1391 .calc_rate
= tegra210_pll_fixed_mdiv_cfg
,
1394 static struct div_nmp pllcx_nmp
= {
1403 static struct tegra_clk_pll_params pll_c2_params
= {
1404 .input_min
= 12000000,
1405 .input_max
= 700000000,
1408 .vco_min
= 600000000,
1409 .vco_max
= 1200000000,
1410 .base_reg
= PLLC2_BASE
,
1411 .misc_reg
= PLLC2_MISC0
,
1412 .iddq_reg
= PLLC2_MISC1
,
1413 .iddq_bit_idx
= PLLCX_IDDQ_BIT
,
1414 .reset_reg
= PLLC2_MISC0
,
1415 .reset_bit_idx
= PLLCX_RESET_BIT
,
1416 .lock_mask
= PLLCX_BASE_LOCK
,
1418 .round_p_to_pdiv
= pll_qlin_p_to_pdiv
,
1419 .pdiv_tohw
= pll_qlin_pdiv_to_hw
,
1421 .div_nmp
= &pllcx_nmp
,
1422 .max_p
= PLL_QLIN_PDIV_MAX
,
1423 .ext_misc_reg
[0] = PLLC2_MISC0
,
1424 .ext_misc_reg
[1] = PLLC2_MISC1
,
1425 .ext_misc_reg
[2] = PLLC2_MISC2
,
1426 .ext_misc_reg
[3] = PLLC2_MISC3
,
1427 .freq_table
= pll_cx_freq_table
,
1428 .flags
= TEGRA_PLL_USE_LOCK
| TEGRA_PLL_HAS_LOCK_ENABLE
,
1429 .set_defaults
= _pllc2_set_defaults
,
1430 .calc_rate
= tegra210_pll_fixed_mdiv_cfg
,
1433 static struct tegra_clk_pll_params pll_c3_params
= {
1434 .input_min
= 12000000,
1435 .input_max
= 700000000,
1438 .vco_min
= 600000000,
1439 .vco_max
= 1200000000,
1440 .base_reg
= PLLC3_BASE
,
1441 .misc_reg
= PLLC3_MISC0
,
1442 .lock_mask
= PLLCX_BASE_LOCK
,
1444 .iddq_reg
= PLLC3_MISC1
,
1445 .iddq_bit_idx
= PLLCX_IDDQ_BIT
,
1446 .reset_reg
= PLLC3_MISC0
,
1447 .reset_bit_idx
= PLLCX_RESET_BIT
,
1448 .round_p_to_pdiv
= pll_qlin_p_to_pdiv
,
1449 .pdiv_tohw
= pll_qlin_pdiv_to_hw
,
1451 .div_nmp
= &pllcx_nmp
,
1452 .max_p
= PLL_QLIN_PDIV_MAX
,
1453 .ext_misc_reg
[0] = PLLC3_MISC0
,
1454 .ext_misc_reg
[1] = PLLC3_MISC1
,
1455 .ext_misc_reg
[2] = PLLC3_MISC2
,
1456 .ext_misc_reg
[3] = PLLC3_MISC3
,
1457 .freq_table
= pll_cx_freq_table
,
1458 .flags
= TEGRA_PLL_USE_LOCK
| TEGRA_PLL_HAS_LOCK_ENABLE
,
1459 .set_defaults
= _pllc3_set_defaults
,
1460 .calc_rate
= tegra210_pll_fixed_mdiv_cfg
,
1463 static struct div_nmp pllss_nmp
= {
1472 static struct tegra_clk_pll_freq_table pll_c4_vco_freq_table
[] = {
1473 { 12000000, 600000000, 50, 1, 0, 0 },
1474 { 13000000, 600000000, 46, 1, 0, 0 }, /* actual: 598.0 MHz */
1475 { 38400000, 600000000, 62, 4, 0, 0 }, /* actual: 595.2 MHz */
1476 { 0, 0, 0, 0, 0, 0 },
1479 static const struct clk_div_table pll_vco_post_div_table
[] = {
1480 { .val
= 0, .div
= 1 },
1481 { .val
= 1, .div
= 2 },
1482 { .val
= 2, .div
= 3 },
1483 { .val
= 3, .div
= 4 },
1484 { .val
= 4, .div
= 5 },
1485 { .val
= 5, .div
= 6 },
1486 { .val
= 6, .div
= 8 },
1487 { .val
= 7, .div
= 10 },
1488 { .val
= 8, .div
= 12 },
1489 { .val
= 9, .div
= 16 },
1490 { .val
= 10, .div
= 12 },
1491 { .val
= 11, .div
= 16 },
1492 { .val
= 12, .div
= 20 },
1493 { .val
= 13, .div
= 24 },
1494 { .val
= 14, .div
= 32 },
1495 { .val
= 0, .div
= 0 },
1498 static struct tegra_clk_pll_params pll_c4_vco_params
= {
1499 .input_min
= 9600000,
1500 .input_max
= 800000000,
1503 .vco_min
= 500000000,
1504 .vco_max
= 1080000000,
1505 .base_reg
= PLLC4_BASE
,
1506 .misc_reg
= PLLC4_MISC0
,
1507 .lock_mask
= PLL_BASE_LOCK
,
1508 .lock_enable_bit_idx
= PLLSS_MISC_LOCK_ENABLE
,
1510 .max_p
= PLL_QLIN_PDIV_MAX
,
1511 .ext_misc_reg
[0] = PLLC4_MISC0
,
1512 .iddq_reg
= PLLC4_BASE
,
1513 .iddq_bit_idx
= PLLSS_IDDQ_BIT
,
1514 .round_p_to_pdiv
= pll_qlin_p_to_pdiv
,
1515 .pdiv_tohw
= pll_qlin_pdiv_to_hw
,
1517 .div_nmp
= &pllss_nmp
,
1518 .freq_table
= pll_c4_vco_freq_table
,
1519 .set_defaults
= tegra210_pllc4_set_defaults
,
1520 .flags
= TEGRA_PLL_USE_LOCK
| TEGRA_PLL_HAS_LOCK_ENABLE
|
1522 .calc_rate
= tegra210_pll_fixed_mdiv_cfg
,
1525 static struct tegra_clk_pll_freq_table pll_m_freq_table
[] = {
1526 { 12000000, 800000000, 66, 1, 0, 0 }, /* actual: 792.0 MHz */
1527 { 13000000, 800000000, 61, 1, 0, 0 }, /* actual: 793.0 MHz */
1528 { 38400000, 297600000, 93, 4, 2, 0 },
1529 { 38400000, 400000000, 125, 4, 2, 0 },
1530 { 38400000, 532800000, 111, 4, 1, 0 },
1531 { 38400000, 665600000, 104, 3, 1, 0 },
1532 { 38400000, 800000000, 125, 3, 1, 0 },
1533 { 38400000, 931200000, 97, 4, 0, 0 },
1534 { 38400000, 1065600000, 111, 4, 0, 0 },
1535 { 38400000, 1200000000, 125, 4, 0, 0 },
1536 { 38400000, 1331200000, 104, 3, 0, 0 },
1537 { 38400000, 1459200000, 76, 2, 0, 0 },
1538 { 38400000, 1600000000, 125, 3, 0, 0 },
1539 { 0, 0, 0, 0, 0, 0 },
1542 static struct div_nmp pllm_nmp
= {
1545 .override_divm_shift
= 0,
1548 .override_divn_shift
= 8,
1551 .override_divp_shift
= 27,
1554 static struct tegra_clk_pll_params pll_m_params
= {
1555 .input_min
= 9600000,
1556 .input_max
= 500000000,
1559 .vco_min
= 800000000,
1560 .vco_max
= 1866000000,
1561 .base_reg
= PLLM_BASE
,
1562 .misc_reg
= PLLM_MISC1
,
1563 .lock_mask
= PLL_BASE_LOCK
,
1564 .lock_enable_bit_idx
= PLLM_MISC_LOCK_ENABLE
,
1566 .iddq_reg
= PLLM_MISC0
,
1567 .iddq_bit_idx
= PLLM_IDDQ_BIT
,
1568 .max_p
= PLL_QLIN_PDIV_MAX
,
1569 .ext_misc_reg
[0] = PLLM_MISC0
,
1570 .ext_misc_reg
[0] = PLLM_MISC1
,
1571 .round_p_to_pdiv
= pll_qlin_p_to_pdiv
,
1572 .pdiv_tohw
= pll_qlin_pdiv_to_hw
,
1573 .div_nmp
= &pllm_nmp
,
1574 .pmc_divnm_reg
= PMC_PLLM_WB0_OVERRIDE
,
1575 .pmc_divp_reg
= PMC_PLLM_WB0_OVERRIDE_2
,
1576 .freq_table
= pll_m_freq_table
,
1577 .flags
= TEGRA_PLL_USE_LOCK
| TEGRA_PLL_HAS_LOCK_ENABLE
,
1578 .calc_rate
= tegra210_pll_fixed_mdiv_cfg
,
1581 static struct tegra_clk_pll_params pll_mb_params
= {
1582 .input_min
= 9600000,
1583 .input_max
= 500000000,
1586 .vco_min
= 800000000,
1587 .vco_max
= 1866000000,
1588 .base_reg
= PLLMB_BASE
,
1589 .misc_reg
= PLLMB_MISC0
,
1590 .lock_mask
= PLL_BASE_LOCK
,
1591 .lock_enable_bit_idx
= PLLMB_MISC_LOCK_ENABLE
,
1593 .iddq_reg
= PLLMB_MISC0
,
1594 .iddq_bit_idx
= PLLMB_IDDQ_BIT
,
1595 .max_p
= PLL_QLIN_PDIV_MAX
,
1596 .ext_misc_reg
[0] = PLLMB_MISC0
,
1597 .round_p_to_pdiv
= pll_qlin_p_to_pdiv
,
1598 .pdiv_tohw
= pll_qlin_pdiv_to_hw
,
1599 .div_nmp
= &pllm_nmp
,
1600 .freq_table
= pll_m_freq_table
,
1601 .flags
= TEGRA_PLL_USE_LOCK
| TEGRA_PLL_HAS_LOCK_ENABLE
,
1602 .set_defaults
= tegra210_pllmb_set_defaults
,
1603 .calc_rate
= tegra210_pll_fixed_mdiv_cfg
,
1607 static struct tegra_clk_pll_freq_table pll_e_freq_table
[] = {
1608 /* PLLE special case: use cpcon field to store cml divider value */
1609 { 672000000, 100000000, 125, 42, 0, 13 },
1610 { 624000000, 100000000, 125, 39, 0, 13 },
1611 { 336000000, 100000000, 125, 21, 0, 13 },
1612 { 312000000, 100000000, 200, 26, 0, 14 },
1613 { 38400000, 100000000, 125, 2, 0, 14 },
1614 { 12000000, 100000000, 200, 1, 0, 14 },
1615 { 0, 0, 0, 0, 0, 0 },
1618 static struct div_nmp plle_nmp
= {
1627 static struct tegra_clk_pll_params pll_e_params
= {
1628 .input_min
= 12000000,
1629 .input_max
= 800000000,
1632 .vco_min
= 1600000000,
1633 .vco_max
= 2500000000U,
1634 .base_reg
= PLLE_BASE
,
1635 .misc_reg
= PLLE_MISC0
,
1636 .aux_reg
= PLLE_AUX
,
1637 .lock_mask
= PLLE_MISC_LOCK
,
1638 .lock_enable_bit_idx
= PLLE_MISC_LOCK_ENABLE
,
1640 .div_nmp
= &plle_nmp
,
1641 .freq_table
= pll_e_freq_table
,
1642 .flags
= TEGRA_PLL_FIXED
| TEGRA_PLL_LOCK_MISC
| TEGRA_PLL_USE_LOCK
|
1643 TEGRA_PLL_HAS_LOCK_ENABLE
,
1644 .fixed_rate
= 100000000,
1645 .calc_rate
= tegra210_pll_fixed_mdiv_cfg
,
1648 static struct tegra_clk_pll_freq_table pll_re_vco_freq_table
[] = {
1649 { 12000000, 672000000, 56, 1, 0, 0 },
1650 { 13000000, 672000000, 51, 1, 0, 0 }, /* actual: 663.0 MHz */
1651 { 38400000, 672000000, 70, 4, 0, 0 },
1652 { 0, 0, 0, 0, 0, 0 },
1655 static struct div_nmp pllre_nmp
= {
1664 static struct tegra_clk_pll_params pll_re_vco_params
= {
1665 .input_min
= 9600000,
1666 .input_max
= 800000000,
1669 .vco_min
= 350000000,
1670 .vco_max
= 700000000,
1671 .base_reg
= PLLRE_BASE
,
1672 .misc_reg
= PLLRE_MISC0
,
1673 .lock_mask
= PLLRE_MISC_LOCK
,
1674 .lock_enable_bit_idx
= PLLRE_MISC_LOCK_ENABLE
,
1676 .max_p
= PLL_QLIN_PDIV_MAX
,
1677 .ext_misc_reg
[0] = PLLRE_MISC0
,
1678 .iddq_reg
= PLLRE_MISC0
,
1679 .iddq_bit_idx
= PLLRE_IDDQ_BIT
,
1680 .round_p_to_pdiv
= pll_qlin_p_to_pdiv
,
1681 .pdiv_tohw
= pll_qlin_pdiv_to_hw
,
1682 .div_nmp
= &pllre_nmp
,
1683 .freq_table
= pll_re_vco_freq_table
,
1684 .flags
= TEGRA_PLL_USE_LOCK
| TEGRA_PLL_LOCK_MISC
|
1685 TEGRA_PLL_HAS_LOCK_ENABLE
| TEGRA_PLL_VCO_OUT
,
1686 .set_defaults
= tegra210_pllre_set_defaults
,
1687 .calc_rate
= tegra210_pll_fixed_mdiv_cfg
,
1690 static struct div_nmp pllp_nmp
= {
1699 static struct tegra_clk_pll_freq_table pll_p_freq_table
[] = {
1700 { 12000000, 408000000, 34, 1, 0, 0 },
1701 { 38400000, 408000000, 85, 8, 0, 0 }, /* cf = 4.8MHz, allowed exception */
1702 { 0, 0, 0, 0, 0, 0 },
1705 static struct tegra_clk_pll_params pll_p_params
= {
1706 .input_min
= 9600000,
1707 .input_max
= 800000000,
1710 .vco_min
= 350000000,
1711 .vco_max
= 700000000,
1712 .base_reg
= PLLP_BASE
,
1713 .misc_reg
= PLLP_MISC0
,
1714 .lock_mask
= PLL_BASE_LOCK
,
1715 .lock_enable_bit_idx
= PLLP_MISC_LOCK_ENABLE
,
1717 .iddq_reg
= PLLP_MISC0
,
1718 .iddq_bit_idx
= PLLXP_IDDQ_BIT
,
1719 .ext_misc_reg
[0] = PLLP_MISC0
,
1720 .ext_misc_reg
[1] = PLLP_MISC1
,
1721 .div_nmp
= &pllp_nmp
,
1722 .freq_table
= pll_p_freq_table
,
1723 .fixed_rate
= 408000000,
1724 .flags
= TEGRA_PLL_FIXED
| TEGRA_PLL_USE_LOCK
|
1725 TEGRA_PLL_HAS_LOCK_ENABLE
| TEGRA_PLL_VCO_OUT
,
1726 .set_defaults
= tegra210_pllp_set_defaults
,
1727 .calc_rate
= tegra210_pll_fixed_mdiv_cfg
,
1730 static struct tegra_clk_pll_params pll_a1_params
= {
1731 .input_min
= 12000000,
1732 .input_max
= 700000000,
1735 .vco_min
= 600000000,
1736 .vco_max
= 1200000000,
1737 .base_reg
= PLLA1_BASE
,
1738 .misc_reg
= PLLA1_MISC0
,
1739 .lock_mask
= PLLCX_BASE_LOCK
,
1741 .iddq_reg
= PLLA1_MISC0
,
1742 .iddq_bit_idx
= PLLCX_IDDQ_BIT
,
1743 .reset_reg
= PLLA1_MISC0
,
1744 .reset_bit_idx
= PLLCX_RESET_BIT
,
1745 .round_p_to_pdiv
= pll_qlin_p_to_pdiv
,
1746 .pdiv_tohw
= pll_qlin_pdiv_to_hw
,
1747 .div_nmp
= &pllc_nmp
,
1748 .ext_misc_reg
[0] = PLLA1_MISC0
,
1749 .ext_misc_reg
[1] = PLLA1_MISC1
,
1750 .ext_misc_reg
[2] = PLLA1_MISC2
,
1751 .ext_misc_reg
[3] = PLLA1_MISC3
,
1752 .freq_table
= pll_cx_freq_table
,
1753 .flags
= TEGRA_PLL_USE_LOCK
| TEGRA_PLL_HAS_LOCK_ENABLE
,
1754 .set_defaults
= _plla1_set_defaults
,
1755 .calc_rate
= tegra210_pll_fixed_mdiv_cfg
,
1758 static struct div_nmp plla_nmp
= {
1767 static struct tegra_clk_pll_freq_table pll_a_freq_table
[] = {
1768 { 12000000, 282240000, 47, 1, 1, 1, 0xf148 }, /* actual: 282240234 */
1769 { 12000000, 368640000, 61, 1, 1, 1, 0xfe15 }, /* actual: 368640381 */
1770 { 12000000, 240000000, 60, 1, 2, 1, 0 },
1771 { 13000000, 282240000, 43, 1, 1, 1, 0xfd7d }, /* actual: 282239807 */
1772 { 13000000, 368640000, 56, 1, 1, 1, 0x06d8 }, /* actual: 368640137 */
1773 { 13000000, 240000000, 55, 1, 2, 1, 0 }, /* actual: 238.3 MHz */
1774 { 38400000, 282240000, 44, 3, 1, 1, 0xf333 }, /* actual: 282239844 */
1775 { 38400000, 368640000, 57, 3, 1, 1, 0x0333 }, /* actual: 368639844 */
1776 { 38400000, 240000000, 75, 3, 3, 1, 0 },
1777 { 0, 0, 0, 0, 0, 0, 0 },
1780 static struct tegra_clk_pll_params pll_a_params
= {
1781 .input_min
= 12000000,
1782 .input_max
= 800000000,
1785 .vco_min
= 500000000,
1786 .vco_max
= 1000000000,
1787 .base_reg
= PLLA_BASE
,
1788 .misc_reg
= PLLA_MISC0
,
1789 .lock_mask
= PLL_BASE_LOCK
,
1790 .lock_enable_bit_idx
= PLLA_MISC_LOCK_ENABLE
,
1792 .round_p_to_pdiv
= pll_qlin_p_to_pdiv
,
1793 .pdiv_tohw
= pll_qlin_pdiv_to_hw
,
1794 .iddq_reg
= PLLA_BASE
,
1795 .iddq_bit_idx
= PLLA_IDDQ_BIT
,
1796 .div_nmp
= &plla_nmp
,
1797 .sdm_din_reg
= PLLA_MISC1
,
1798 .sdm_din_mask
= PLLA_SDM_DIN_MASK
,
1799 .sdm_ctrl_reg
= PLLA_MISC2
,
1800 .sdm_ctrl_en_mask
= PLLA_SDM_EN_MASK
,
1801 .ext_misc_reg
[0] = PLLA_MISC0
,
1802 .ext_misc_reg
[1] = PLLA_MISC1
,
1803 .ext_misc_reg
[2] = PLLA_MISC2
,
1804 .freq_table
= pll_a_freq_table
,
1805 .flags
= TEGRA_PLL_USE_LOCK
| TEGRA_MDIV_NEW
|
1806 TEGRA_PLL_HAS_LOCK_ENABLE
,
1807 .set_defaults
= tegra210_plla_set_defaults
,
1808 .calc_rate
= tegra210_pll_fixed_mdiv_cfg
,
1809 .set_gain
= tegra210_clk_pll_set_gain
,
1810 .adjust_vco
= tegra210_clk_adjust_vco_min
,
1813 static struct div_nmp plld_nmp
= {
1822 static struct tegra_clk_pll_freq_table pll_d_freq_table
[] = {
1823 { 12000000, 594000000, 99, 1, 1, 0, 0 },
1824 { 13000000, 594000000, 91, 1, 1, 0, 0xfc4f }, /* actual: 594000183 */
1825 { 38400000, 594000000, 30, 1, 1, 0, 0x0e00 },
1826 { 0, 0, 0, 0, 0, 0, 0 },
1829 static struct tegra_clk_pll_params pll_d_params
= {
1830 .input_min
= 12000000,
1831 .input_max
= 800000000,
1834 .vco_min
= 750000000,
1835 .vco_max
= 1500000000,
1836 .base_reg
= PLLD_BASE
,
1837 .misc_reg
= PLLD_MISC0
,
1838 .lock_mask
= PLL_BASE_LOCK
,
1839 .lock_enable_bit_idx
= PLLD_MISC_LOCK_ENABLE
,
1841 .iddq_reg
= PLLD_MISC0
,
1842 .iddq_bit_idx
= PLLD_IDDQ_BIT
,
1843 .round_p_to_pdiv
= pll_expo_p_to_pdiv
,
1844 .pdiv_tohw
= pll_expo_pdiv_to_hw
,
1845 .div_nmp
= &plld_nmp
,
1846 .sdm_din_reg
= PLLD_MISC0
,
1847 .sdm_din_mask
= PLLA_SDM_DIN_MASK
,
1848 .sdm_ctrl_reg
= PLLD_MISC0
,
1849 .sdm_ctrl_en_mask
= PLLD_SDM_EN_MASK
,
1850 .ext_misc_reg
[0] = PLLD_MISC0
,
1851 .ext_misc_reg
[1] = PLLD_MISC1
,
1852 .freq_table
= pll_d_freq_table
,
1853 .flags
= TEGRA_PLL_USE_LOCK
| TEGRA_PLL_HAS_LOCK_ENABLE
,
1855 .set_defaults
= tegra210_plld_set_defaults
,
1856 .calc_rate
= tegra210_pll_fixed_mdiv_cfg
,
1857 .set_gain
= tegra210_clk_pll_set_gain
,
1858 .adjust_vco
= tegra210_clk_adjust_vco_min
,
1861 static struct tegra_clk_pll_freq_table tegra210_pll_d2_freq_table
[] = {
1862 { 12000000, 594000000, 99, 1, 1, 0, 0xf000 },
1863 { 13000000, 594000000, 91, 1, 1, 0, 0xfc4f }, /* actual: 594000183 */
1864 { 38400000, 594000000, 30, 1, 1, 0, 0x0e00 },
1865 { 0, 0, 0, 0, 0, 0, 0 },
1868 /* s/w policy, always tegra_pll_ref */
1869 static struct tegra_clk_pll_params pll_d2_params
= {
1870 .input_min
= 12000000,
1871 .input_max
= 800000000,
1874 .vco_min
= 750000000,
1875 .vco_max
= 1500000000,
1876 .base_reg
= PLLD2_BASE
,
1877 .misc_reg
= PLLD2_MISC0
,
1878 .lock_mask
= PLL_BASE_LOCK
,
1879 .lock_enable_bit_idx
= PLLSS_MISC_LOCK_ENABLE
,
1881 .iddq_reg
= PLLD2_BASE
,
1882 .iddq_bit_idx
= PLLSS_IDDQ_BIT
,
1883 .sdm_din_reg
= PLLD2_MISC3
,
1884 .sdm_din_mask
= PLLA_SDM_DIN_MASK
,
1885 .sdm_ctrl_reg
= PLLD2_MISC1
,
1886 .sdm_ctrl_en_mask
= PLLD2_SDM_EN_MASK
,
1887 .ssc_ctrl_reg
= PLLD2_MISC1
,
1888 .ssc_ctrl_en_mask
= PLLD2_SSC_EN_MASK
,
1889 .round_p_to_pdiv
= pll_qlin_p_to_pdiv
,
1890 .pdiv_tohw
= pll_qlin_pdiv_to_hw
,
1891 .div_nmp
= &pllss_nmp
,
1892 .ext_misc_reg
[0] = PLLD2_MISC0
,
1893 .ext_misc_reg
[1] = PLLD2_MISC1
,
1894 .ext_misc_reg
[2] = PLLD2_MISC2
,
1895 .ext_misc_reg
[3] = PLLD2_MISC3
,
1896 .max_p
= PLL_QLIN_PDIV_MAX
,
1898 .freq_table
= tegra210_pll_d2_freq_table
,
1899 .set_defaults
= tegra210_plld2_set_defaults
,
1900 .flags
= TEGRA_PLL_USE_LOCK
| TEGRA_PLL_HAS_LOCK_ENABLE
,
1901 .calc_rate
= tegra210_pll_fixed_mdiv_cfg
,
1902 .set_gain
= tegra210_clk_pll_set_gain
,
1903 .adjust_vco
= tegra210_clk_adjust_vco_min
,
1906 static struct tegra_clk_pll_freq_table pll_dp_freq_table
[] = {
1907 { 12000000, 270000000, 90, 1, 3, 0, 0xf000 },
1908 { 13000000, 270000000, 83, 1, 3, 0, 0xf000 }, /* actual: 269.8 MHz */
1909 { 38400000, 270000000, 28, 1, 3, 0, 0xf400 },
1910 { 0, 0, 0, 0, 0, 0, 0 },
1913 static struct tegra_clk_pll_params pll_dp_params
= {
1914 .input_min
= 12000000,
1915 .input_max
= 800000000,
1918 .vco_min
= 750000000,
1919 .vco_max
= 1500000000,
1920 .base_reg
= PLLDP_BASE
,
1921 .misc_reg
= PLLDP_MISC
,
1922 .lock_mask
= PLL_BASE_LOCK
,
1923 .lock_enable_bit_idx
= PLLSS_MISC_LOCK_ENABLE
,
1925 .iddq_reg
= PLLDP_BASE
,
1926 .iddq_bit_idx
= PLLSS_IDDQ_BIT
,
1927 .sdm_din_reg
= PLLDP_SS_CTRL2
,
1928 .sdm_din_mask
= PLLA_SDM_DIN_MASK
,
1929 .sdm_ctrl_reg
= PLLDP_SS_CFG
,
1930 .sdm_ctrl_en_mask
= PLLDP_SDM_EN_MASK
,
1931 .ssc_ctrl_reg
= PLLDP_SS_CFG
,
1932 .ssc_ctrl_en_mask
= PLLDP_SSC_EN_MASK
,
1933 .round_p_to_pdiv
= pll_qlin_p_to_pdiv
,
1934 .pdiv_tohw
= pll_qlin_pdiv_to_hw
,
1935 .div_nmp
= &pllss_nmp
,
1936 .ext_misc_reg
[0] = PLLDP_MISC
,
1937 .ext_misc_reg
[1] = PLLDP_SS_CFG
,
1938 .ext_misc_reg
[2] = PLLDP_SS_CTRL1
,
1939 .ext_misc_reg
[3] = PLLDP_SS_CTRL2
,
1940 .max_p
= PLL_QLIN_PDIV_MAX
,
1942 .freq_table
= pll_dp_freq_table
,
1943 .set_defaults
= tegra210_plldp_set_defaults
,
1944 .flags
= TEGRA_PLL_USE_LOCK
| TEGRA_PLL_HAS_LOCK_ENABLE
,
1945 .calc_rate
= tegra210_pll_fixed_mdiv_cfg
,
1946 .set_gain
= tegra210_clk_pll_set_gain
,
1947 .adjust_vco
= tegra210_clk_adjust_vco_min
,
1950 static struct div_nmp pllu_nmp
= {
1959 static struct tegra_clk_pll_freq_table pll_u_freq_table
[] = {
1960 { 12000000, 480000000, 40, 1, 0, 0 },
1961 { 13000000, 480000000, 36, 1, 0, 0 }, /* actual: 468.0 MHz */
1962 { 38400000, 480000000, 25, 2, 0, 0 },
1963 { 0, 0, 0, 0, 0, 0 },
1966 static struct tegra_clk_pll_params pll_u_vco_params
= {
1967 .input_min
= 9600000,
1968 .input_max
= 800000000,
1971 .vco_min
= 350000000,
1972 .vco_max
= 700000000,
1973 .base_reg
= PLLU_BASE
,
1974 .misc_reg
= PLLU_MISC0
,
1975 .lock_mask
= PLL_BASE_LOCK
,
1976 .lock_enable_bit_idx
= PLLU_MISC_LOCK_ENABLE
,
1978 .iddq_reg
= PLLU_MISC0
,
1979 .iddq_bit_idx
= PLLU_IDDQ_BIT
,
1980 .ext_misc_reg
[0] = PLLU_MISC0
,
1981 .ext_misc_reg
[1] = PLLU_MISC1
,
1982 .round_p_to_pdiv
= pll_qlin_p_to_pdiv
,
1983 .pdiv_tohw
= pll_qlin_pdiv_to_hw
,
1984 .div_nmp
= &pllu_nmp
,
1985 .freq_table
= pll_u_freq_table
,
1986 .flags
= TEGRA_PLLU
| TEGRA_PLL_USE_LOCK
| TEGRA_PLL_HAS_LOCK_ENABLE
|
1988 .set_defaults
= tegra210_pllu_set_defaults
,
1989 .calc_rate
= tegra210_pll_fixed_mdiv_cfg
,
1992 struct utmi_clk_param
{
1993 /* Oscillator Frequency in KHz */
1995 /* UTMIP PLL Enable Delay Count */
1996 u8 enable_delay_count
;
1997 /* UTMIP PLL Stable count */
1999 /* UTMIP PLL Active delay count */
2000 u8 active_delay_count
;
2001 /* UTMIP PLL Xtal frequency count */
2002 u16 xtal_freq_count
;
2005 static const struct utmi_clk_param utmi_parameters
[] = {
2007 .osc_frequency
= 38400000, .enable_delay_count
= 0x0,
2008 .stable_count
= 0x0, .active_delay_count
= 0x6,
2009 .xtal_freq_count
= 0x80
2011 .osc_frequency
= 13000000, .enable_delay_count
= 0x02,
2012 .stable_count
= 0x33, .active_delay_count
= 0x05,
2013 .xtal_freq_count
= 0x7f
2015 .osc_frequency
= 19200000, .enable_delay_count
= 0x03,
2016 .stable_count
= 0x4b, .active_delay_count
= 0x06,
2017 .xtal_freq_count
= 0xbb
2019 .osc_frequency
= 12000000, .enable_delay_count
= 0x02,
2020 .stable_count
= 0x2f, .active_delay_count
= 0x08,
2021 .xtal_freq_count
= 0x76
2023 .osc_frequency
= 26000000, .enable_delay_count
= 0x04,
2024 .stable_count
= 0x66, .active_delay_count
= 0x09,
2025 .xtal_freq_count
= 0xfe
2027 .osc_frequency
= 16800000, .enable_delay_count
= 0x03,
2028 .stable_count
= 0x41, .active_delay_count
= 0x0a,
2029 .xtal_freq_count
= 0xa4
2033 static struct tegra_clk tegra210_clks
[tegra_clk_max
] __initdata
= {
2034 [tegra_clk_ispb
] = { .dt_id
= TEGRA210_CLK_ISPB
, .present
= true },
2035 [tegra_clk_rtc
] = { .dt_id
= TEGRA210_CLK_RTC
, .present
= true },
2036 [tegra_clk_timer
] = { .dt_id
= TEGRA210_CLK_TIMER
, .present
= true },
2037 [tegra_clk_uarta_8
] = { .dt_id
= TEGRA210_CLK_UARTA
, .present
= true },
2038 [tegra_clk_sdmmc2_9
] = { .dt_id
= TEGRA210_CLK_SDMMC2
, .present
= true },
2039 [tegra_clk_i2s1
] = { .dt_id
= TEGRA210_CLK_I2S1
, .present
= true },
2040 [tegra_clk_i2c1
] = { .dt_id
= TEGRA210_CLK_I2C1
, .present
= true },
2041 [tegra_clk_sdmmc1_9
] = { .dt_id
= TEGRA210_CLK_SDMMC1
, .present
= true },
2042 [tegra_clk_sdmmc4_9
] = { .dt_id
= TEGRA210_CLK_SDMMC4
, .present
= true },
2043 [tegra_clk_pwm
] = { .dt_id
= TEGRA210_CLK_PWM
, .present
= true },
2044 [tegra_clk_i2s2
] = { .dt_id
= TEGRA210_CLK_I2S2
, .present
= true },
2045 [tegra_clk_usbd
] = { .dt_id
= TEGRA210_CLK_USBD
, .present
= true },
2046 [tegra_clk_isp_9
] = { .dt_id
= TEGRA210_CLK_ISP
, .present
= true },
2047 [tegra_clk_disp2_8
] = { .dt_id
= TEGRA210_CLK_DISP2
, .present
= true },
2048 [tegra_clk_disp1_8
] = { .dt_id
= TEGRA210_CLK_DISP1
, .present
= true },
2049 [tegra_clk_host1x_9
] = { .dt_id
= TEGRA210_CLK_HOST1X
, .present
= true },
2050 [tegra_clk_i2s0
] = { .dt_id
= TEGRA210_CLK_I2S0
, .present
= true },
2051 [tegra_clk_apbdma
] = { .dt_id
= TEGRA210_CLK_APBDMA
, .present
= true },
2052 [tegra_clk_kfuse
] = { .dt_id
= TEGRA210_CLK_KFUSE
, .present
= true },
2053 [tegra_clk_sbc1_9
] = { .dt_id
= TEGRA210_CLK_SBC1
, .present
= true },
2054 [tegra_clk_sbc2_9
] = { .dt_id
= TEGRA210_CLK_SBC2
, .present
= true },
2055 [tegra_clk_sbc3_9
] = { .dt_id
= TEGRA210_CLK_SBC3
, .present
= true },
2056 [tegra_clk_i2c5
] = { .dt_id
= TEGRA210_CLK_I2C5
, .present
= true },
2057 [tegra_clk_csi
] = { .dt_id
= TEGRA210_CLK_CSI
, .present
= true },
2058 [tegra_clk_i2c2
] = { .dt_id
= TEGRA210_CLK_I2C2
, .present
= true },
2059 [tegra_clk_uartc_8
] = { .dt_id
= TEGRA210_CLK_UARTC
, .present
= true },
2060 [tegra_clk_mipi_cal
] = { .dt_id
= TEGRA210_CLK_MIPI_CAL
, .present
= true },
2061 [tegra_clk_emc
] = { .dt_id
= TEGRA210_CLK_EMC
, .present
= true },
2062 [tegra_clk_usb2
] = { .dt_id
= TEGRA210_CLK_USB2
, .present
= true },
2063 [tegra_clk_bsev
] = { .dt_id
= TEGRA210_CLK_BSEV
, .present
= true },
2064 [tegra_clk_uartd_8
] = { .dt_id
= TEGRA210_CLK_UARTD
, .present
= true },
2065 [tegra_clk_i2c3
] = { .dt_id
= TEGRA210_CLK_I2C3
, .present
= true },
2066 [tegra_clk_sbc4_9
] = { .dt_id
= TEGRA210_CLK_SBC4
, .present
= true },
2067 [tegra_clk_sdmmc3_9
] = { .dt_id
= TEGRA210_CLK_SDMMC3
, .present
= true },
2068 [tegra_clk_pcie
] = { .dt_id
= TEGRA210_CLK_PCIE
, .present
= true },
2069 [tegra_clk_owr_8
] = { .dt_id
= TEGRA210_CLK_OWR
, .present
= true },
2070 [tegra_clk_afi
] = { .dt_id
= TEGRA210_CLK_AFI
, .present
= true },
2071 [tegra_clk_csite_8
] = { .dt_id
= TEGRA210_CLK_CSITE
, .present
= true },
2072 [tegra_clk_soc_therm_8
] = { .dt_id
= TEGRA210_CLK_SOC_THERM
, .present
= true },
2073 [tegra_clk_dtv
] = { .dt_id
= TEGRA210_CLK_DTV
, .present
= true },
2074 [tegra_clk_i2cslow
] = { .dt_id
= TEGRA210_CLK_I2CSLOW
, .present
= true },
2075 [tegra_clk_tsec_8
] = { .dt_id
= TEGRA210_CLK_TSEC
, .present
= true },
2076 [tegra_clk_xusb_host
] = { .dt_id
= TEGRA210_CLK_XUSB_HOST
, .present
= true },
2077 [tegra_clk_csus
] = { .dt_id
= TEGRA210_CLK_CSUS
, .present
= true },
2078 [tegra_clk_mselect
] = { .dt_id
= TEGRA210_CLK_MSELECT
, .present
= true },
2079 [tegra_clk_tsensor
] = { .dt_id
= TEGRA210_CLK_TSENSOR
, .present
= true },
2080 [tegra_clk_i2s3
] = { .dt_id
= TEGRA210_CLK_I2S3
, .present
= true },
2081 [tegra_clk_i2s4
] = { .dt_id
= TEGRA210_CLK_I2S4
, .present
= true },
2082 [tegra_clk_i2c4
] = { .dt_id
= TEGRA210_CLK_I2C4
, .present
= true },
2083 [tegra_clk_d_audio
] = { .dt_id
= TEGRA210_CLK_D_AUDIO
, .present
= true },
2084 [tegra_clk_hda2codec_2x_8
] = { .dt_id
= TEGRA210_CLK_HDA2CODEC_2X
, .present
= true },
2085 [tegra_clk_spdif_2x
] = { .dt_id
= TEGRA210_CLK_SPDIF_2X
, .present
= true },
2086 [tegra_clk_actmon
] = { .dt_id
= TEGRA210_CLK_ACTMON
, .present
= true },
2087 [tegra_clk_extern1
] = { .dt_id
= TEGRA210_CLK_EXTERN1
, .present
= true },
2088 [tegra_clk_extern2
] = { .dt_id
= TEGRA210_CLK_EXTERN2
, .present
= true },
2089 [tegra_clk_extern3
] = { .dt_id
= TEGRA210_CLK_EXTERN3
, .present
= true },
2090 [tegra_clk_sata_oob_8
] = { .dt_id
= TEGRA210_CLK_SATA_OOB
, .present
= true },
2091 [tegra_clk_sata_8
] = { .dt_id
= TEGRA210_CLK_SATA
, .present
= true },
2092 [tegra_clk_hda_8
] = { .dt_id
= TEGRA210_CLK_HDA
, .present
= true },
2093 [tegra_clk_hda2hdmi
] = { .dt_id
= TEGRA210_CLK_HDA2HDMI
, .present
= true },
2094 [tegra_clk_cilab
] = { .dt_id
= TEGRA210_CLK_CILAB
, .present
= true },
2095 [tegra_clk_cilcd
] = { .dt_id
= TEGRA210_CLK_CILCD
, .present
= true },
2096 [tegra_clk_cile
] = { .dt_id
= TEGRA210_CLK_CILE
, .present
= true },
2097 [tegra_clk_dsialp
] = { .dt_id
= TEGRA210_CLK_DSIALP
, .present
= true },
2098 [tegra_clk_dsiblp
] = { .dt_id
= TEGRA210_CLK_DSIBLP
, .present
= true },
2099 [tegra_clk_entropy_8
] = { .dt_id
= TEGRA210_CLK_ENTROPY
, .present
= true },
2100 [tegra_clk_xusb_ss
] = { .dt_id
= TEGRA210_CLK_XUSB_SS
, .present
= true },
2101 [tegra_clk_i2c6
] = { .dt_id
= TEGRA210_CLK_I2C6
, .present
= true },
2102 [tegra_clk_vim2_clk
] = { .dt_id
= TEGRA210_CLK_VIM2_CLK
, .present
= true },
2103 [tegra_clk_clk72Mhz_8
] = { .dt_id
= TEGRA210_CLK_CLK72MHZ
, .present
= true },
2104 [tegra_clk_vic03_8
] = { .dt_id
= TEGRA210_CLK_VIC03
, .present
= true },
2105 [tegra_clk_dpaux
] = { .dt_id
= TEGRA210_CLK_DPAUX
, .present
= true },
2106 [tegra_clk_sor0
] = { .dt_id
= TEGRA210_CLK_SOR0
, .present
= true },
2107 [tegra_clk_sor0_lvds
] = { .dt_id
= TEGRA210_CLK_SOR0_LVDS
, .present
= true },
2108 [tegra_clk_gpu
] = { .dt_id
= TEGRA210_CLK_GPU
, .present
= true },
2109 [tegra_clk_pll_g_ref
] = { .dt_id
= TEGRA210_CLK_PLL_G_REF
, .present
= true, },
2110 [tegra_clk_uartb_8
] = { .dt_id
= TEGRA210_CLK_UARTB
, .present
= true },
2111 [tegra_clk_vfir
] = { .dt_id
= TEGRA210_CLK_VFIR
, .present
= true },
2112 [tegra_clk_spdif_in_8
] = { .dt_id
= TEGRA210_CLK_SPDIF_IN
, .present
= true },
2113 [tegra_clk_spdif_out
] = { .dt_id
= TEGRA210_CLK_SPDIF_OUT
, .present
= true },
2114 [tegra_clk_vi_10
] = { .dt_id
= TEGRA210_CLK_VI
, .present
= true },
2115 [tegra_clk_vi_sensor_8
] = { .dt_id
= TEGRA210_CLK_VI_SENSOR
, .present
= true },
2116 [tegra_clk_fuse
] = { .dt_id
= TEGRA210_CLK_FUSE
, .present
= true },
2117 [tegra_clk_fuse_burn
] = { .dt_id
= TEGRA210_CLK_FUSE_BURN
, .present
= true },
2118 [tegra_clk_clk_32k
] = { .dt_id
= TEGRA210_CLK_CLK_32K
, .present
= true },
2119 [tegra_clk_clk_m
] = { .dt_id
= TEGRA210_CLK_CLK_M
, .present
= true },
2120 [tegra_clk_clk_m_div2
] = { .dt_id
= TEGRA210_CLK_CLK_M_DIV2
, .present
= true },
2121 [tegra_clk_clk_m_div4
] = { .dt_id
= TEGRA210_CLK_CLK_M_DIV4
, .present
= true },
2122 [tegra_clk_pll_ref
] = { .dt_id
= TEGRA210_CLK_PLL_REF
, .present
= true },
2123 [tegra_clk_pll_c
] = { .dt_id
= TEGRA210_CLK_PLL_C
, .present
= true },
2124 [tegra_clk_pll_c_out1
] = { .dt_id
= TEGRA210_CLK_PLL_C_OUT1
, .present
= true },
2125 [tegra_clk_pll_c2
] = { .dt_id
= TEGRA210_CLK_PLL_C2
, .present
= true },
2126 [tegra_clk_pll_c3
] = { .dt_id
= TEGRA210_CLK_PLL_C3
, .present
= true },
2127 [tegra_clk_pll_m
] = { .dt_id
= TEGRA210_CLK_PLL_M
, .present
= true },
2128 [tegra_clk_pll_m_out1
] = { .dt_id
= TEGRA210_CLK_PLL_M_OUT1
, .present
= true },
2129 [tegra_clk_pll_p
] = { .dt_id
= TEGRA210_CLK_PLL_P
, .present
= true },
2130 [tegra_clk_pll_p_out1
] = { .dt_id
= TEGRA210_CLK_PLL_P_OUT1
, .present
= true },
2131 [tegra_clk_pll_p_out3
] = { .dt_id
= TEGRA210_CLK_PLL_P_OUT3
, .present
= true },
2132 [tegra_clk_pll_p_out4_cpu
] = { .dt_id
= TEGRA210_CLK_PLL_P_OUT4
, .present
= true },
2133 [tegra_clk_pll_p_out_hsio
] = { .dt_id
= TEGRA210_CLK_PLL_P_OUT_HSIO
, .present
= true },
2134 [tegra_clk_pll_p_out_xusb
] = { .dt_id
= TEGRA210_CLK_PLL_P_OUT_XUSB
, .present
= true },
2135 [tegra_clk_pll_p_out_cpu
] = { .dt_id
= TEGRA210_CLK_PLL_P_OUT_CPU
, .present
= true },
2136 [tegra_clk_pll_p_out_adsp
] = { .dt_id
= TEGRA210_CLK_PLL_P_OUT_ADSP
, .present
= true },
2137 [tegra_clk_pll_a
] = { .dt_id
= TEGRA210_CLK_PLL_A
, .present
= true },
2138 [tegra_clk_pll_a_out0
] = { .dt_id
= TEGRA210_CLK_PLL_A_OUT0
, .present
= true },
2139 [tegra_clk_pll_d
] = { .dt_id
= TEGRA210_CLK_PLL_D
, .present
= true },
2140 [tegra_clk_pll_d_out0
] = { .dt_id
= TEGRA210_CLK_PLL_D_OUT0
, .present
= true },
2141 [tegra_clk_pll_d2
] = { .dt_id
= TEGRA210_CLK_PLL_D2
, .present
= true },
2142 [tegra_clk_pll_d2_out0
] = { .dt_id
= TEGRA210_CLK_PLL_D2_OUT0
, .present
= true },
2143 [tegra_clk_pll_u
] = { .dt_id
= TEGRA210_CLK_PLL_U
, .present
= true },
2144 [tegra_clk_pll_u_out
] = { .dt_id
= TEGRA210_CLK_PLL_U_OUT
, .present
= true },
2145 [tegra_clk_pll_u_out1
] = { .dt_id
= TEGRA210_CLK_PLL_U_OUT1
, .present
= true },
2146 [tegra_clk_pll_u_out2
] = { .dt_id
= TEGRA210_CLK_PLL_U_OUT2
, .present
= true },
2147 [tegra_clk_pll_u_480m
] = { .dt_id
= TEGRA210_CLK_PLL_U_480M
, .present
= true },
2148 [tegra_clk_pll_u_60m
] = { .dt_id
= TEGRA210_CLK_PLL_U_60M
, .present
= true },
2149 [tegra_clk_pll_u_48m
] = { .dt_id
= TEGRA210_CLK_PLL_U_48M
, .present
= true },
2150 [tegra_clk_pll_x
] = { .dt_id
= TEGRA210_CLK_PLL_X
, .present
= true },
2151 [tegra_clk_pll_x_out0
] = { .dt_id
= TEGRA210_CLK_PLL_X_OUT0
, .present
= true },
2152 [tegra_clk_pll_re_vco
] = { .dt_id
= TEGRA210_CLK_PLL_RE_VCO
, .present
= true },
2153 [tegra_clk_pll_re_out
] = { .dt_id
= TEGRA210_CLK_PLL_RE_OUT
, .present
= true },
2154 [tegra_clk_spdif_in_sync
] = { .dt_id
= TEGRA210_CLK_SPDIF_IN_SYNC
, .present
= true },
2155 [tegra_clk_i2s0_sync
] = { .dt_id
= TEGRA210_CLK_I2S0_SYNC
, .present
= true },
2156 [tegra_clk_i2s1_sync
] = { .dt_id
= TEGRA210_CLK_I2S1_SYNC
, .present
= true },
2157 [tegra_clk_i2s2_sync
] = { .dt_id
= TEGRA210_CLK_I2S2_SYNC
, .present
= true },
2158 [tegra_clk_i2s3_sync
] = { .dt_id
= TEGRA210_CLK_I2S3_SYNC
, .present
= true },
2159 [tegra_clk_i2s4_sync
] = { .dt_id
= TEGRA210_CLK_I2S4_SYNC
, .present
= true },
2160 [tegra_clk_vimclk_sync
] = { .dt_id
= TEGRA210_CLK_VIMCLK_SYNC
, .present
= true },
2161 [tegra_clk_audio0
] = { .dt_id
= TEGRA210_CLK_AUDIO0
, .present
= true },
2162 [tegra_clk_audio1
] = { .dt_id
= TEGRA210_CLK_AUDIO1
, .present
= true },
2163 [tegra_clk_audio2
] = { .dt_id
= TEGRA210_CLK_AUDIO2
, .present
= true },
2164 [tegra_clk_audio3
] = { .dt_id
= TEGRA210_CLK_AUDIO3
, .present
= true },
2165 [tegra_clk_audio4
] = { .dt_id
= TEGRA210_CLK_AUDIO4
, .present
= true },
2166 [tegra_clk_spdif
] = { .dt_id
= TEGRA210_CLK_SPDIF
, .present
= true },
2167 [tegra_clk_clk_out_1
] = { .dt_id
= TEGRA210_CLK_CLK_OUT_1
, .present
= true },
2168 [tegra_clk_clk_out_2
] = { .dt_id
= TEGRA210_CLK_CLK_OUT_2
, .present
= true },
2169 [tegra_clk_clk_out_3
] = { .dt_id
= TEGRA210_CLK_CLK_OUT_3
, .present
= true },
2170 [tegra_clk_blink
] = { .dt_id
= TEGRA210_CLK_BLINK
, .present
= true },
2171 [tegra_clk_xusb_gate
] = { .dt_id
= TEGRA210_CLK_XUSB_GATE
, .present
= true },
2172 [tegra_clk_xusb_host_src_8
] = { .dt_id
= TEGRA210_CLK_XUSB_HOST_SRC
, .present
= true },
2173 [tegra_clk_xusb_falcon_src_8
] = { .dt_id
= TEGRA210_CLK_XUSB_FALCON_SRC
, .present
= true },
2174 [tegra_clk_xusb_fs_src
] = { .dt_id
= TEGRA210_CLK_XUSB_FS_SRC
, .present
= true },
2175 [tegra_clk_xusb_ss_src_8
] = { .dt_id
= TEGRA210_CLK_XUSB_SS_SRC
, .present
= true },
2176 [tegra_clk_xusb_ss_div2
] = { .dt_id
= TEGRA210_CLK_XUSB_SS_DIV2
, .present
= true },
2177 [tegra_clk_xusb_dev_src_8
] = { .dt_id
= TEGRA210_CLK_XUSB_DEV_SRC
, .present
= true },
2178 [tegra_clk_xusb_dev
] = { .dt_id
= TEGRA210_CLK_XUSB_DEV
, .present
= true },
2179 [tegra_clk_xusb_hs_src_4
] = { .dt_id
= TEGRA210_CLK_XUSB_HS_SRC
, .present
= true },
2180 [tegra_clk_xusb_ssp_src
] = { .dt_id
= TEGRA210_CLK_XUSB_SSP_SRC
, .present
= true },
2181 [tegra_clk_usb2_hsic_trk
] = { .dt_id
= TEGRA210_CLK_USB2_HSIC_TRK
, .present
= true },
2182 [tegra_clk_hsic_trk
] = { .dt_id
= TEGRA210_CLK_HSIC_TRK
, .present
= true },
2183 [tegra_clk_usb2_trk
] = { .dt_id
= TEGRA210_CLK_USB2_TRK
, .present
= true },
2184 [tegra_clk_sclk
] = { .dt_id
= TEGRA210_CLK_SCLK
, .present
= true },
2185 [tegra_clk_sclk_mux
] = { .dt_id
= TEGRA210_CLK_SCLK_MUX
, .present
= true },
2186 [tegra_clk_hclk
] = { .dt_id
= TEGRA210_CLK_HCLK
, .present
= true },
2187 [tegra_clk_pclk
] = { .dt_id
= TEGRA210_CLK_PCLK
, .present
= true },
2188 [tegra_clk_cclk_g
] = { .dt_id
= TEGRA210_CLK_CCLK_G
, .present
= true },
2189 [tegra_clk_cclk_lp
] = { .dt_id
= TEGRA210_CLK_CCLK_LP
, .present
= true },
2190 [tegra_clk_dfll_ref
] = { .dt_id
= TEGRA210_CLK_DFLL_REF
, .present
= true },
2191 [tegra_clk_dfll_soc
] = { .dt_id
= TEGRA210_CLK_DFLL_SOC
, .present
= true },
2192 [tegra_clk_vi_sensor2_8
] = { .dt_id
= TEGRA210_CLK_VI_SENSOR2
, .present
= true },
2193 [tegra_clk_pll_p_out5
] = { .dt_id
= TEGRA210_CLK_PLL_P_OUT5
, .present
= true },
2194 [tegra_clk_pll_c4
] = { .dt_id
= TEGRA210_CLK_PLL_C4
, .present
= true },
2195 [tegra_clk_pll_dp
] = { .dt_id
= TEGRA210_CLK_PLL_DP
, .present
= true },
2196 [tegra_clk_audio0_mux
] = { .dt_id
= TEGRA210_CLK_AUDIO0_MUX
, .present
= true },
2197 [tegra_clk_audio1_mux
] = { .dt_id
= TEGRA210_CLK_AUDIO1_MUX
, .present
= true },
2198 [tegra_clk_audio2_mux
] = { .dt_id
= TEGRA210_CLK_AUDIO2_MUX
, .present
= true },
2199 [tegra_clk_audio3_mux
] = { .dt_id
= TEGRA210_CLK_AUDIO3_MUX
, .present
= true },
2200 [tegra_clk_audio4_mux
] = { .dt_id
= TEGRA210_CLK_AUDIO4_MUX
, .present
= true },
2201 [tegra_clk_spdif_mux
] = { .dt_id
= TEGRA210_CLK_SPDIF_MUX
, .present
= true },
2202 [tegra_clk_clk_out_1_mux
] = { .dt_id
= TEGRA210_CLK_CLK_OUT_1_MUX
, .present
= true },
2203 [tegra_clk_clk_out_2_mux
] = { .dt_id
= TEGRA210_CLK_CLK_OUT_2_MUX
, .present
= true },
2204 [tegra_clk_clk_out_3_mux
] = { .dt_id
= TEGRA210_CLK_CLK_OUT_3_MUX
, .present
= true },
2205 [tegra_clk_maud
] = { .dt_id
= TEGRA210_CLK_MAUD
, .present
= true },
2206 [tegra_clk_mipibif
] = { .dt_id
= TEGRA210_CLK_MIPIBIF
, .present
= true },
2207 [tegra_clk_qspi
] = { .dt_id
= TEGRA210_CLK_QSPI
, .present
= true },
2208 [tegra_clk_sdmmc_legacy
] = { .dt_id
= TEGRA210_CLK_SDMMC_LEGACY
, .present
= true },
2209 [tegra_clk_tsecb
] = { .dt_id
= TEGRA210_CLK_TSECB
, .present
= true },
2210 [tegra_clk_uartape
] = { .dt_id
= TEGRA210_CLK_UARTAPE
, .present
= true },
2211 [tegra_clk_vi_i2c
] = { .dt_id
= TEGRA210_CLK_VI_I2C
, .present
= true },
2212 [tegra_clk_ape
] = { .dt_id
= TEGRA210_CLK_APE
, .present
= true },
2213 [tegra_clk_dbgapb
] = { .dt_id
= TEGRA210_CLK_DBGAPB
, .present
= true },
2214 [tegra_clk_nvdec
] = { .dt_id
= TEGRA210_CLK_NVDEC
, .present
= true },
2215 [tegra_clk_nvenc
] = { .dt_id
= TEGRA210_CLK_NVENC
, .present
= true },
2216 [tegra_clk_nvjpg
] = { .dt_id
= TEGRA210_CLK_NVJPG
, .present
= true },
2217 [tegra_clk_pll_c4_out0
] = { .dt_id
= TEGRA210_CLK_PLL_C4_OUT0
, .present
= true },
2218 [tegra_clk_pll_c4_out1
] = { .dt_id
= TEGRA210_CLK_PLL_C4_OUT1
, .present
= true },
2219 [tegra_clk_pll_c4_out2
] = { .dt_id
= TEGRA210_CLK_PLL_C4_OUT2
, .present
= true },
2220 [tegra_clk_pll_c4_out3
] = { .dt_id
= TEGRA210_CLK_PLL_C4_OUT3
, .present
= true },
2223 static struct tegra_devclk devclks
[] __initdata
= {
2224 { .con_id
= "clk_m", .dt_id
= TEGRA210_CLK_CLK_M
},
2225 { .con_id
= "pll_ref", .dt_id
= TEGRA210_CLK_PLL_REF
},
2226 { .con_id
= "clk_32k", .dt_id
= TEGRA210_CLK_CLK_32K
},
2227 { .con_id
= "clk_m_div2", .dt_id
= TEGRA210_CLK_CLK_M_DIV2
},
2228 { .con_id
= "clk_m_div4", .dt_id
= TEGRA210_CLK_CLK_M_DIV4
},
2229 { .con_id
= "pll_c", .dt_id
= TEGRA210_CLK_PLL_C
},
2230 { .con_id
= "pll_c_out1", .dt_id
= TEGRA210_CLK_PLL_C_OUT1
},
2231 { .con_id
= "pll_c2", .dt_id
= TEGRA210_CLK_PLL_C2
},
2232 { .con_id
= "pll_c3", .dt_id
= TEGRA210_CLK_PLL_C3
},
2233 { .con_id
= "pll_p", .dt_id
= TEGRA210_CLK_PLL_P
},
2234 { .con_id
= "pll_p_out1", .dt_id
= TEGRA210_CLK_PLL_P_OUT1
},
2235 { .con_id
= "pll_p_out2", .dt_id
= TEGRA210_CLK_PLL_P_OUT2
},
2236 { .con_id
= "pll_p_out3", .dt_id
= TEGRA210_CLK_PLL_P_OUT3
},
2237 { .con_id
= "pll_p_out4", .dt_id
= TEGRA210_CLK_PLL_P_OUT4
},
2238 { .con_id
= "pll_m", .dt_id
= TEGRA210_CLK_PLL_M
},
2239 { .con_id
= "pll_m_out1", .dt_id
= TEGRA210_CLK_PLL_M_OUT1
},
2240 { .con_id
= "pll_x", .dt_id
= TEGRA210_CLK_PLL_X
},
2241 { .con_id
= "pll_x_out0", .dt_id
= TEGRA210_CLK_PLL_X_OUT0
},
2242 { .con_id
= "pll_u", .dt_id
= TEGRA210_CLK_PLL_U
},
2243 { .con_id
= "pll_u_out", .dt_id
= TEGRA210_CLK_PLL_U_OUT
},
2244 { .con_id
= "pll_u_out1", .dt_id
= TEGRA210_CLK_PLL_U_OUT1
},
2245 { .con_id
= "pll_u_out2", .dt_id
= TEGRA210_CLK_PLL_U_OUT2
},
2246 { .con_id
= "pll_u_480M", .dt_id
= TEGRA210_CLK_PLL_U_480M
},
2247 { .con_id
= "pll_u_60M", .dt_id
= TEGRA210_CLK_PLL_U_60M
},
2248 { .con_id
= "pll_u_48M", .dt_id
= TEGRA210_CLK_PLL_U_48M
},
2249 { .con_id
= "pll_d", .dt_id
= TEGRA210_CLK_PLL_D
},
2250 { .con_id
= "pll_d_out0", .dt_id
= TEGRA210_CLK_PLL_D_OUT0
},
2251 { .con_id
= "pll_d2", .dt_id
= TEGRA210_CLK_PLL_D2
},
2252 { .con_id
= "pll_d2_out0", .dt_id
= TEGRA210_CLK_PLL_D2_OUT0
},
2253 { .con_id
= "pll_a", .dt_id
= TEGRA210_CLK_PLL_A
},
2254 { .con_id
= "pll_a_out0", .dt_id
= TEGRA210_CLK_PLL_A_OUT0
},
2255 { .con_id
= "pll_re_vco", .dt_id
= TEGRA210_CLK_PLL_RE_VCO
},
2256 { .con_id
= "pll_re_out", .dt_id
= TEGRA210_CLK_PLL_RE_OUT
},
2257 { .con_id
= "spdif_in_sync", .dt_id
= TEGRA210_CLK_SPDIF_IN_SYNC
},
2258 { .con_id
= "i2s0_sync", .dt_id
= TEGRA210_CLK_I2S0_SYNC
},
2259 { .con_id
= "i2s1_sync", .dt_id
= TEGRA210_CLK_I2S1_SYNC
},
2260 { .con_id
= "i2s2_sync", .dt_id
= TEGRA210_CLK_I2S2_SYNC
},
2261 { .con_id
= "i2s3_sync", .dt_id
= TEGRA210_CLK_I2S3_SYNC
},
2262 { .con_id
= "i2s4_sync", .dt_id
= TEGRA210_CLK_I2S4_SYNC
},
2263 { .con_id
= "vimclk_sync", .dt_id
= TEGRA210_CLK_VIMCLK_SYNC
},
2264 { .con_id
= "audio0", .dt_id
= TEGRA210_CLK_AUDIO0
},
2265 { .con_id
= "audio1", .dt_id
= TEGRA210_CLK_AUDIO1
},
2266 { .con_id
= "audio2", .dt_id
= TEGRA210_CLK_AUDIO2
},
2267 { .con_id
= "audio3", .dt_id
= TEGRA210_CLK_AUDIO3
},
2268 { .con_id
= "audio4", .dt_id
= TEGRA210_CLK_AUDIO4
},
2269 { .con_id
= "spdif", .dt_id
= TEGRA210_CLK_SPDIF
},
2270 { .con_id
= "spdif_2x", .dt_id
= TEGRA210_CLK_SPDIF_2X
},
2271 { .con_id
= "extern1", .dev_id
= "clk_out_1", .dt_id
= TEGRA210_CLK_EXTERN1
},
2272 { .con_id
= "extern2", .dev_id
= "clk_out_2", .dt_id
= TEGRA210_CLK_EXTERN2
},
2273 { .con_id
= "extern3", .dev_id
= "clk_out_3", .dt_id
= TEGRA210_CLK_EXTERN3
},
2274 { .con_id
= "blink", .dt_id
= TEGRA210_CLK_BLINK
},
2275 { .con_id
= "cclk_g", .dt_id
= TEGRA210_CLK_CCLK_G
},
2276 { .con_id
= "cclk_lp", .dt_id
= TEGRA210_CLK_CCLK_LP
},
2277 { .con_id
= "sclk", .dt_id
= TEGRA210_CLK_SCLK
},
2278 { .con_id
= "hclk", .dt_id
= TEGRA210_CLK_HCLK
},
2279 { .con_id
= "pclk", .dt_id
= TEGRA210_CLK_PCLK
},
2280 { .con_id
= "fuse", .dt_id
= TEGRA210_CLK_FUSE
},
2281 { .dev_id
= "rtc-tegra", .dt_id
= TEGRA210_CLK_RTC
},
2282 { .dev_id
= "timer", .dt_id
= TEGRA210_CLK_TIMER
},
2283 { .con_id
= "pll_c4_out0", .dt_id
= TEGRA210_CLK_PLL_C4_OUT0
},
2284 { .con_id
= "pll_c4_out1", .dt_id
= TEGRA210_CLK_PLL_C4_OUT1
},
2285 { .con_id
= "pll_c4_out2", .dt_id
= TEGRA210_CLK_PLL_C4_OUT2
},
2286 { .con_id
= "pll_c4_out3", .dt_id
= TEGRA210_CLK_PLL_C4_OUT3
},
2287 { .con_id
= "dpaux", .dt_id
= TEGRA210_CLK_DPAUX
},
2288 { .con_id
= "sor0", .dt_id
= TEGRA210_CLK_SOR0
},
2291 static struct tegra_audio_clk_info tegra210_audio_plls
[] = {
2292 { "pll_a", &pll_a_params
, tegra_clk_pll_a
, "pll_ref" },
2293 { "pll_a1", &pll_a1_params
, tegra_clk_pll_a1
, "pll_ref" },
2296 static struct clk
**clks
;
2298 static void tegra210_utmi_param_configure(void __iomem
*clk_base
)
2303 for (i
= 0; i
< ARRAY_SIZE(utmi_parameters
); i
++) {
2304 if (osc_freq
== utmi_parameters
[i
].osc_frequency
)
2308 if (i
>= ARRAY_SIZE(utmi_parameters
)) {
2309 pr_err("%s: Unexpected oscillator freq %lu\n", __func__
,
2314 reg
= readl_relaxed(clk_base
+ PLLU_HW_PWRDN_CFG0
);
2315 reg
|= PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE
|
2316 PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT
|
2317 PLLU_HW_PWRDN_CFG0_USE_LOCKDET
;
2318 reg
&= ~(PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL
|
2319 PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL
);
2320 writel_relaxed(reg
, clk_base
+ PLLU_HW_PWRDN_CFG0
);
2322 reg
= readl_relaxed(clk_base
+ PLLU_HW_PWRDN_CFG0
);
2323 reg
|= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE
;
2324 writel_relaxed(reg
, clk_base
+ PLLU_HW_PWRDN_CFG0
);
2327 reg
= readl_relaxed(clk_base
+ PLLU_BASE
);
2328 reg
&= ~PLLU_BASE_CLKENABLE_USB
;
2329 writel_relaxed(reg
, clk_base
+ PLLU_BASE
);
2331 reg
= readl_relaxed(clk_base
+ UTMIPLL_HW_PWRDN_CFG0
);
2332 reg
&= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE
;
2333 writel_relaxed(reg
, clk_base
+ UTMIPLL_HW_PWRDN_CFG0
);
2337 reg
= readl_relaxed(clk_base
+ UTMIP_PLL_CFG2
);
2339 /* Program UTMIP PLL stable and active counts */
2340 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
2341 reg
&= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
2342 reg
|= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters
[i
].stable_count
);
2344 reg
&= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
2346 reg
|= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters
[i
].
2347 active_delay_count
);
2348 writel_relaxed(reg
, clk_base
+ UTMIP_PLL_CFG2
);
2350 /* Program UTMIP PLL delay and oscillator frequency counts */
2351 reg
= readl_relaxed(clk_base
+ UTMIP_PLL_CFG1
);
2352 reg
&= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
2354 reg
|= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters
[i
].
2355 enable_delay_count
);
2357 reg
&= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
2358 reg
|= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters
[i
].
2361 reg
|= UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN
;
2362 writel_relaxed(reg
, clk_base
+ UTMIP_PLL_CFG1
);
2364 /* Remove power downs from UTMIP PLL control bits */
2365 reg
= readl_relaxed(clk_base
+ UTMIP_PLL_CFG1
);
2366 reg
&= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN
;
2367 reg
|= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP
;
2368 writel_relaxed(reg
, clk_base
+ UTMIP_PLL_CFG1
);
2371 /* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */
2372 reg
= readl_relaxed(clk_base
+ UTMIP_PLL_CFG2
);
2373 reg
|= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP
;
2374 reg
|= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP
;
2375 reg
|= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP
;
2376 reg
&= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN
;
2377 reg
&= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN
;
2378 reg
&= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN
;
2379 writel_relaxed(reg
, clk_base
+ UTMIP_PLL_CFG2
);
2381 /* Setup HW control of UTMIPLL */
2382 reg
= readl_relaxed(clk_base
+ UTMIP_PLL_CFG1
);
2383 reg
&= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN
;
2384 reg
&= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP
;
2385 writel_relaxed(reg
, clk_base
+ UTMIP_PLL_CFG1
);
2387 reg
= readl_relaxed(clk_base
+ UTMIPLL_HW_PWRDN_CFG0
);
2388 reg
|= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET
;
2389 reg
&= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL
;
2390 writel_relaxed(reg
, clk_base
+ UTMIPLL_HW_PWRDN_CFG0
);
2394 reg
= readl_relaxed(clk_base
+ XUSB_PLL_CFG0
);
2395 reg
&= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY
;
2396 writel_relaxed(reg
, clk_base
+ XUSB_PLL_CFG0
);
2400 /* Enable HW control UTMIPLL */
2401 reg
= readl_relaxed(clk_base
+ UTMIPLL_HW_PWRDN_CFG0
);
2402 reg
|= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE
;
2403 writel_relaxed(reg
, clk_base
+ UTMIPLL_HW_PWRDN_CFG0
);
2406 static __init
void tegra210_periph_clk_init(void __iomem
*clk_base
,
2407 void __iomem
*pmc_base
)
2412 clk
= clk_register_fixed_factor(NULL
, "xusb_ss_div2", "xusb_ss_src", 0,
2414 clks
[TEGRA210_CLK_XUSB_SS_DIV2
] = clk
;
2417 clk
= clk_register_gate(NULL
, "pll_d_dsi_out", "pll_d_out0", 0,
2418 clk_base
+ PLLD_MISC0
, 21, 0, &pll_d_lock
);
2419 clks
[TEGRA210_CLK_PLL_D_DSI_OUT
] = clk
;
2422 clk
= tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,
2424 periph_clk_enb_refcnt
);
2425 clks
[TEGRA210_CLK_DSIA
] = clk
;
2428 clk
= tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,
2430 periph_clk_enb_refcnt
);
2431 clks
[TEGRA210_CLK_DSIB
] = clk
;
2434 clk
= clk_register_mux(NULL
, "emc_mux", mux_pllmcp_clkm
,
2435 ARRAY_SIZE(mux_pllmcp_clkm
), 0,
2436 clk_base
+ CLK_SOURCE_EMC
,
2437 29, 3, 0, &emc_lock
);
2439 clk
= tegra_clk_register_mc("mc", "emc_mux", clk_base
+ CLK_SOURCE_EMC
,
2441 clks
[TEGRA210_CLK_MC
] = clk
;
2444 clk
= clk_register_gate(NULL
, "cml0", "pll_e", 0, clk_base
+ PLLE_AUX
,
2446 clk_register_clkdev(clk
, "cml0", NULL
);
2447 clks
[TEGRA210_CLK_CML0
] = clk
;
2450 clk
= clk_register_gate(NULL
, "cml1", "pll_e", 0, clk_base
+ PLLE_AUX
,
2452 clk_register_clkdev(clk
, "cml1", NULL
);
2453 clks
[TEGRA210_CLK_CML1
] = clk
;
2455 tegra_periph_clk_init(clk_base
, pmc_base
, tegra210_clks
, &pll_p_params
);
2458 static void __init
tegra210_pll_init(void __iomem
*clk_base
,
2465 clk
= tegra_clk_register_pllxc_tegra210("pll_c", "pll_ref", clk_base
,
2466 pmc
, 0, &pll_c_params
, NULL
);
2467 if (!WARN_ON(IS_ERR(clk
)))
2468 clk_register_clkdev(clk
, "pll_c", NULL
);
2469 clks
[TEGRA210_CLK_PLL_C
] = clk
;
2472 clk
= tegra_clk_register_divider("pll_c_out1_div", "pll_c",
2473 clk_base
+ PLLC_OUT
, 0, TEGRA_DIVIDER_ROUND_UP
,
2475 clk
= tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
2476 clk_base
+ PLLC_OUT
, 1, 0,
2477 CLK_SET_RATE_PARENT
, 0, NULL
);
2478 clk_register_clkdev(clk
, "pll_c_out1", NULL
);
2479 clks
[TEGRA210_CLK_PLL_C_OUT1
] = clk
;
2482 clk
= clk_register_fixed_factor(NULL
, "pll_c_ud", "pll_c",
2483 CLK_SET_RATE_PARENT
, 1, 1);
2484 clk_register_clkdev(clk
, "pll_c_ud", NULL
);
2485 clks
[TEGRA210_CLK_PLL_C_UD
] = clk
;
2488 clk
= tegra_clk_register_pllc_tegra210("pll_c2", "pll_ref", clk_base
,
2489 pmc
, 0, &pll_c2_params
, NULL
);
2490 clk_register_clkdev(clk
, "pll_c2", NULL
);
2491 clks
[TEGRA210_CLK_PLL_C2
] = clk
;
2494 clk
= tegra_clk_register_pllc_tegra210("pll_c3", "pll_ref", clk_base
,
2495 pmc
, 0, &pll_c3_params
, NULL
);
2496 clk_register_clkdev(clk
, "pll_c3", NULL
);
2497 clks
[TEGRA210_CLK_PLL_C3
] = clk
;
2500 clk
= tegra_clk_register_pllm("pll_m", "osc", clk_base
, pmc
,
2501 CLK_SET_RATE_GATE
, &pll_m_params
, NULL
);
2502 clk_register_clkdev(clk
, "pll_m", NULL
);
2503 clks
[TEGRA210_CLK_PLL_M
] = clk
;
2506 clk
= tegra_clk_register_pllmb("pll_mb", "osc", clk_base
, pmc
,
2507 CLK_SET_RATE_GATE
, &pll_mb_params
, NULL
);
2508 clk_register_clkdev(clk
, "pll_mb", NULL
);
2509 clks
[TEGRA210_CLK_PLL_MB
] = clk
;
2511 clk_register_clkdev(clk
, "pll_m_out1", NULL
);
2512 clks
[TEGRA210_CLK_PLL_M_OUT1
] = clk
;
2515 clk
= clk_register_fixed_factor(NULL
, "pll_m_ud", "pll_m",
2516 CLK_SET_RATE_PARENT
, 1, 1);
2517 clk_register_clkdev(clk
, "pll_m_ud", NULL
);
2518 clks
[TEGRA210_CLK_PLL_M_UD
] = clk
;
2521 val
= readl(clk_base
+ pll_u_vco_params
.base_reg
);
2522 val
&= ~BIT(24); /* disable PLLU_OVERRIDE */
2523 writel(val
, clk_base
+ pll_u_vco_params
.base_reg
);
2525 clk
= tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base
, pmc
,
2526 0, &pll_u_vco_params
, &pll_u_lock
, pll_ref_freq
);
2527 clk_register_clkdev(clk
, "pll_u_vco", NULL
);
2528 clks
[TEGRA210_CLK_PLL_U
] = clk
;
2531 clk
= clk_register_divider_table(NULL
, "pll_u_out", "pll_u_vco", 0,
2532 clk_base
+ PLLU_BASE
, 16, 4, 0,
2533 pll_vco_post_div_table
, NULL
);
2534 clk_register_clkdev(clk
, "pll_u_out", NULL
);
2535 clks
[TEGRA210_CLK_PLL_U_OUT
] = clk
;
2538 clk
= tegra_clk_register_divider("pll_u_out1_div", "pll_u_out",
2539 clk_base
+ PLLU_OUTA
, 0,
2540 TEGRA_DIVIDER_ROUND_UP
,
2541 8, 8, 1, &pll_u_lock
);
2542 clk
= tegra_clk_register_pll_out("pll_u_out1", "pll_u_out1_div",
2543 clk_base
+ PLLU_OUTA
, 1, 0,
2544 CLK_SET_RATE_PARENT
, 0, &pll_u_lock
);
2545 clk_register_clkdev(clk
, "pll_u_out1", NULL
);
2546 clks
[TEGRA210_CLK_PLL_U_OUT1
] = clk
;
2549 clk
= tegra_clk_register_divider("pll_u_out2_div", "pll_u_out",
2550 clk_base
+ PLLU_OUTA
, 0,
2551 TEGRA_DIVIDER_ROUND_UP
,
2552 24, 8, 1, &pll_u_lock
);
2553 clk
= tegra_clk_register_pll_out("pll_u_out2", "pll_u_out2_div",
2554 clk_base
+ PLLU_OUTA
, 17, 16,
2555 CLK_SET_RATE_PARENT
, 0, &pll_u_lock
);
2556 clk_register_clkdev(clk
, "pll_u_out2", NULL
);
2557 clks
[TEGRA210_CLK_PLL_U_OUT2
] = clk
;
2559 tegra210_utmi_param_configure(clk_base
);
2562 clk
= clk_register_gate(NULL
, "pll_u_480M", "pll_u_vco",
2563 CLK_SET_RATE_PARENT
, clk_base
+ PLLU_BASE
,
2564 22, 0, &pll_u_lock
);
2565 clk_register_clkdev(clk
, "pll_u_480M", NULL
);
2566 clks
[TEGRA210_CLK_PLL_U_480M
] = clk
;
2569 clk
= clk_register_gate(NULL
, "pll_u_60M", "pll_u_out2",
2570 CLK_SET_RATE_PARENT
, clk_base
+ PLLU_BASE
,
2572 clk_register_clkdev(clk
, "pll_u_60M", NULL
);
2573 clks
[TEGRA210_CLK_PLL_U_60M
] = clk
;
2576 clk
= clk_register_gate(NULL
, "pll_u_48M", "pll_u_out1",
2577 CLK_SET_RATE_PARENT
, clk_base
+ PLLU_BASE
,
2579 clk_register_clkdev(clk
, "pll_u_48M", NULL
);
2580 clks
[TEGRA210_CLK_PLL_U_48M
] = clk
;
2583 clk
= tegra_clk_register_pll("pll_d", "pll_ref", clk_base
, pmc
, 0,
2584 &pll_d_params
, &pll_d_lock
);
2585 clk_register_clkdev(clk
, "pll_d", NULL
);
2586 clks
[TEGRA210_CLK_PLL_D
] = clk
;
2589 clk
= clk_register_fixed_factor(NULL
, "pll_d_out0", "pll_d",
2590 CLK_SET_RATE_PARENT
, 1, 2);
2591 clk_register_clkdev(clk
, "pll_d_out0", NULL
);
2592 clks
[TEGRA210_CLK_PLL_D_OUT0
] = clk
;
2595 clk
= tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base
, pmc
,
2596 0, &pll_re_vco_params
, &pll_re_lock
, pll_ref_freq
);
2597 clk_register_clkdev(clk
, "pll_re_vco", NULL
);
2598 clks
[TEGRA210_CLK_PLL_RE_VCO
] = clk
;
2600 clk
= clk_register_divider_table(NULL
, "pll_re_out", "pll_re_vco", 0,
2601 clk_base
+ PLLRE_BASE
, 16, 5, 0,
2602 pll_vco_post_div_table
, &pll_re_lock
);
2603 clk_register_clkdev(clk
, "pll_re_out", NULL
);
2604 clks
[TEGRA210_CLK_PLL_RE_OUT
] = clk
;
2607 clk
= tegra_clk_register_plle_tegra210("pll_e", "pll_ref",
2608 clk_base
, 0, &pll_e_params
, NULL
);
2609 clk_register_clkdev(clk
, "pll_e", NULL
);
2610 clks
[TEGRA210_CLK_PLL_E
] = clk
;
2613 clk
= tegra_clk_register_pllre("pll_c4_vco", "pll_ref", clk_base
, pmc
,
2614 0, &pll_c4_vco_params
, NULL
, pll_ref_freq
);
2615 clk_register_clkdev(clk
, "pll_c4_vco", NULL
);
2616 clks
[TEGRA210_CLK_PLL_C4
] = clk
;
2619 clk
= clk_register_divider_table(NULL
, "pll_c4_out0", "pll_c4_vco", 0,
2620 clk_base
+ PLLC4_BASE
, 19, 4, 0,
2621 pll_vco_post_div_table
, NULL
);
2622 clk_register_clkdev(clk
, "pll_c4_out0", NULL
);
2623 clks
[TEGRA210_CLK_PLL_C4_OUT0
] = clk
;
2626 clk
= clk_register_fixed_factor(NULL
, "pll_c4_out1", "pll_c4_vco",
2627 CLK_SET_RATE_PARENT
, 1, 3);
2628 clk_register_clkdev(clk
, "pll_c4_out1", NULL
);
2629 clks
[TEGRA210_CLK_PLL_C4_OUT1
] = clk
;
2632 clk
= clk_register_fixed_factor(NULL
, "pll_c4_out2", "pll_c4_vco",
2633 CLK_SET_RATE_PARENT
, 1, 5);
2634 clk_register_clkdev(clk
, "pll_c4_out2", NULL
);
2635 clks
[TEGRA210_CLK_PLL_C4_OUT2
] = clk
;
2638 clk
= tegra_clk_register_divider("pll_c4_out3_div", "pll_c4_out0",
2639 clk_base
+ PLLC4_OUT
, 0, TEGRA_DIVIDER_ROUND_UP
,
2641 clk
= tegra_clk_register_pll_out("pll_c4_out3", "pll_c4_out3_div",
2642 clk_base
+ PLLC4_OUT
, 1, 0,
2643 CLK_SET_RATE_PARENT
, 0, NULL
);
2644 clk_register_clkdev(clk
, "pll_c4_out3", NULL
);
2645 clks
[TEGRA210_CLK_PLL_C4_OUT3
] = clk
;
2648 clk
= tegra_clk_register_pllss_tegra210("pll_dp", "pll_ref", clk_base
,
2649 0, &pll_dp_params
, NULL
);
2650 clk_register_clkdev(clk
, "pll_dp", NULL
);
2651 clks
[TEGRA210_CLK_PLL_DP
] = clk
;
2654 clk
= tegra_clk_register_pllss_tegra210("pll_d2", "pll_ref", clk_base
,
2655 0, &pll_d2_params
, NULL
);
2656 clk_register_clkdev(clk
, "pll_d2", NULL
);
2657 clks
[TEGRA210_CLK_PLL_D2
] = clk
;
2660 clk
= clk_register_fixed_factor(NULL
, "pll_d2_out0", "pll_d2",
2661 CLK_SET_RATE_PARENT
, 1, 1);
2662 clk_register_clkdev(clk
, "pll_d2_out0", NULL
);
2663 clks
[TEGRA210_CLK_PLL_D2_OUT0
] = clk
;
2666 clk
= clk_register_fixed_factor(NULL
, "pll_p_out2", "pll_p",
2667 CLK_SET_RATE_PARENT
, 1, 2);
2668 clk_register_clkdev(clk
, "pll_p_out2", NULL
);
2669 clks
[TEGRA210_CLK_PLL_P_OUT2
] = clk
;
2673 /* Tegra210 CPU clock and reset control functions */
2674 static void tegra210_wait_cpu_in_reset(u32 cpu
)
2679 reg
= readl(clk_base
+ CLK_RST_CONTROLLER_CPU_CMPLX_STATUS
);
2681 } while (!(reg
& (1 << cpu
))); /* check CPU been reset or not */
2684 static void tegra210_disable_cpu_clock(u32 cpu
)
2686 /* flow controller would take care in the power sequence. */
2689 #ifdef CONFIG_PM_SLEEP
2690 static void tegra210_cpu_clock_suspend(void)
2692 /* switch coresite to clk_m, save off original source */
2693 tegra210_cpu_clk_sctx
.clk_csite_src
=
2694 readl(clk_base
+ CLK_SOURCE_CSITE
);
2695 writel(3 << 30, clk_base
+ CLK_SOURCE_CSITE
);
2698 static void tegra210_cpu_clock_resume(void)
2700 writel(tegra210_cpu_clk_sctx
.clk_csite_src
,
2701 clk_base
+ CLK_SOURCE_CSITE
);
2705 static struct tegra_cpu_car_ops tegra210_cpu_car_ops
= {
2706 .wait_for_reset
= tegra210_wait_cpu_in_reset
,
2707 .disable_clock
= tegra210_disable_cpu_clock
,
2708 #ifdef CONFIG_PM_SLEEP
2709 .suspend
= tegra210_cpu_clock_suspend
,
2710 .resume
= tegra210_cpu_clock_resume
,
2714 static const struct of_device_id pmc_match
[] __initconst
= {
2715 { .compatible
= "nvidia,tegra210-pmc" },
2719 static struct tegra_clk_init_table init_table
[] __initdata
= {
2720 { TEGRA210_CLK_UARTA
, TEGRA210_CLK_PLL_P
, 408000000, 0 },
2721 { TEGRA210_CLK_UARTB
, TEGRA210_CLK_PLL_P
, 408000000, 0 },
2722 { TEGRA210_CLK_UARTC
, TEGRA210_CLK_PLL_P
, 408000000, 0 },
2723 { TEGRA210_CLK_UARTD
, TEGRA210_CLK_PLL_P
, 408000000, 0 },
2724 { TEGRA210_CLK_PLL_A
, TEGRA210_CLK_CLK_MAX
, 564480000, 1 },
2725 { TEGRA210_CLK_PLL_A_OUT0
, TEGRA210_CLK_CLK_MAX
, 11289600, 1 },
2726 { TEGRA210_CLK_EXTERN1
, TEGRA210_CLK_PLL_A_OUT0
, 0, 1 },
2727 { TEGRA210_CLK_CLK_OUT_1_MUX
, TEGRA210_CLK_EXTERN1
, 0, 1 },
2728 { TEGRA210_CLK_CLK_OUT_1
, TEGRA210_CLK_CLK_MAX
, 0, 1 },
2729 { TEGRA210_CLK_I2S0
, TEGRA210_CLK_PLL_A_OUT0
, 11289600, 0 },
2730 { TEGRA210_CLK_I2S1
, TEGRA210_CLK_PLL_A_OUT0
, 11289600, 0 },
2731 { TEGRA210_CLK_I2S2
, TEGRA210_CLK_PLL_A_OUT0
, 11289600, 0 },
2732 { TEGRA210_CLK_I2S3
, TEGRA210_CLK_PLL_A_OUT0
, 11289600, 0 },
2733 { TEGRA210_CLK_I2S4
, TEGRA210_CLK_PLL_A_OUT0
, 11289600, 0 },
2734 { TEGRA210_CLK_HOST1X
, TEGRA210_CLK_PLL_P
, 136000000, 1 },
2735 { TEGRA210_CLK_SCLK_MUX
, TEGRA210_CLK_PLL_P
, 0, 1 },
2736 { TEGRA210_CLK_SCLK
, TEGRA210_CLK_CLK_MAX
, 102000000, 1 },
2737 { TEGRA210_CLK_DFLL_SOC
, TEGRA210_CLK_PLL_P
, 51000000, 1 },
2738 { TEGRA210_CLK_DFLL_REF
, TEGRA210_CLK_PLL_P
, 51000000, 1 },
2739 { TEGRA210_CLK_SBC4
, TEGRA210_CLK_PLL_P
, 12000000, 1 },
2740 { TEGRA210_CLK_PLL_RE_VCO
, TEGRA210_CLK_CLK_MAX
, 672000000, 1 },
2741 { TEGRA210_CLK_PLL_U_OUT1
, TEGRA210_CLK_CLK_MAX
, 48000000, 1 },
2742 { TEGRA210_CLK_PLL_U_OUT2
, TEGRA210_CLK_CLK_MAX
, 60000000, 1 },
2743 { TEGRA210_CLK_XUSB_GATE
, TEGRA210_CLK_CLK_MAX
, 0, 1 },
2744 { TEGRA210_CLK_XUSB_SS_SRC
, TEGRA210_CLK_PLL_U_480M
, 120000000, 0 },
2745 { TEGRA210_CLK_XUSB_FS_SRC
, TEGRA210_CLK_PLL_U_48M
, 48000000, 0 },
2746 { TEGRA210_CLK_XUSB_HS_SRC
, TEGRA210_CLK_XUSB_SS_SRC
, 120000000, 0 },
2747 { TEGRA210_CLK_XUSB_SSP_SRC
, TEGRA210_CLK_XUSB_SS_SRC
, 120000000, 0 },
2748 { TEGRA210_CLK_XUSB_FALCON_SRC
, TEGRA210_CLK_PLL_P_OUT_XUSB
, 204000000, 0 },
2749 { TEGRA210_CLK_XUSB_HOST_SRC
, TEGRA210_CLK_PLL_P_OUT_XUSB
, 102000000, 0 },
2750 { TEGRA210_CLK_XUSB_DEV_SRC
, TEGRA210_CLK_PLL_P_OUT_XUSB
, 102000000, 0 },
2751 { TEGRA210_CLK_SATA
, TEGRA210_CLK_PLL_P
, 104000000, 0 },
2752 { TEGRA210_CLK_SATA_OOB
, TEGRA210_CLK_PLL_P
, 204000000, 0 },
2753 { TEGRA210_CLK_EMC
, TEGRA210_CLK_CLK_MAX
, 0, 1 },
2754 { TEGRA210_CLK_MSELECT
, TEGRA210_CLK_CLK_MAX
, 0, 1 },
2755 { TEGRA210_CLK_CSITE
, TEGRA210_CLK_CLK_MAX
, 0, 1 },
2756 { TEGRA210_CLK_TSENSOR
, TEGRA210_CLK_CLK_M
, 400000, 0 },
2757 { TEGRA210_CLK_I2C1
, TEGRA210_CLK_PLL_P
, 0, 0 },
2758 { TEGRA210_CLK_I2C2
, TEGRA210_CLK_PLL_P
, 0, 0 },
2759 { TEGRA210_CLK_I2C3
, TEGRA210_CLK_PLL_P
, 0, 0 },
2760 { TEGRA210_CLK_I2C4
, TEGRA210_CLK_PLL_P
, 0, 0 },
2761 { TEGRA210_CLK_I2C5
, TEGRA210_CLK_PLL_P
, 0, 0 },
2762 { TEGRA210_CLK_I2C6
, TEGRA210_CLK_PLL_P
, 0, 0 },
2763 { TEGRA210_CLK_PLL_DP
, TEGRA210_CLK_CLK_MAX
, 270000000, 0 },
2764 { TEGRA210_CLK_SOC_THERM
, TEGRA210_CLK_PLL_P
, 51000000, 0 },
2765 { TEGRA210_CLK_CCLK_G
, TEGRA210_CLK_CLK_MAX
, 0, 1 },
2766 /* This MUST be the last entry. */
2767 { TEGRA210_CLK_CLK_MAX
, TEGRA210_CLK_CLK_MAX
, 0, 0 },
2771 * tegra210_clock_apply_init_table - initialize clocks on Tegra210 SoCs
2773 * Program an initial clock rate and enable or disable clocks needed
2774 * by the rest of the kernel, for Tegra210 SoCs. It is intended to be
2775 * called by assigning a pointer to it to tegra_clk_apply_init_table -
2776 * this will be called as an arch_initcall. No return value.
2778 static void __init
tegra210_clock_apply_init_table(void)
2780 tegra_init_from_table(init_table
, clks
, TEGRA210_CLK_CLK_MAX
);
2784 * tegra210_clock_init - Tegra210-specific clock initialization
2785 * @np: struct device_node * of the DT node for the SoC CAR IP block
2787 * Register most SoC clocks for the Tegra210 system-on-chip. Intended
2788 * to be called by the OF init code when a DT node with the
2789 * "nvidia,tegra210-car" string is encountered, and declared with
2790 * CLK_OF_DECLARE. No return value.
2792 static void __init
tegra210_clock_init(struct device_node
*np
)
2794 struct device_node
*node
;
2795 u32 value
, clk_m_div
;
2797 clk_base
= of_iomap(np
, 0);
2799 pr_err("ioremap tegra210 CAR failed\n");
2803 node
= of_find_matching_node(NULL
, pmc_match
);
2805 pr_err("Failed to find pmc node\n");
2810 pmc_base
= of_iomap(node
, 0);
2812 pr_err("Can't map pmc registers\n");
2817 clks
= tegra_clk_init(clk_base
, TEGRA210_CLK_CLK_MAX
,
2818 TEGRA210_CAR_BANK_COUNT
);
2822 value
= clk_readl(clk_base
+ SPARE_REG0
) >> CLK_M_DIVISOR_SHIFT
;
2823 clk_m_div
= (value
& CLK_M_DIVISOR_MASK
) + 1;
2825 if (tegra_osc_clk_init(clk_base
, tegra210_clks
, tegra210_input_freq
,
2826 ARRAY_SIZE(tegra210_input_freq
), clk_m_div
,
2827 &osc_freq
, &pll_ref_freq
) < 0)
2830 tegra_fixed_clk_init(tegra210_clks
);
2831 tegra210_pll_init(clk_base
, pmc_base
);
2832 tegra210_periph_clk_init(clk_base
, pmc_base
);
2833 tegra_audio_clk_init(clk_base
, pmc_base
, tegra210_clks
,
2834 tegra210_audio_plls
,
2835 ARRAY_SIZE(tegra210_audio_plls
));
2836 tegra_pmc_clk_init(pmc_base
, tegra210_clks
);
2838 /* For Tegra210, PLLD is the only source for DSIA & DSIB */
2839 value
= clk_readl(clk_base
+ PLLD_BASE
);
2841 clk_writel(value
, clk_base
+ PLLD_BASE
);
2843 tegra_clk_apply_init_table
= tegra210_clock_apply_init_table
;
2845 tegra_super_clk_gen5_init(clk_base
, pmc_base
, tegra210_clks
,
2847 tegra_add_of_provider(np
);
2848 tegra_register_devclks(devclks
, ARRAY_SIZE(devclks
));
2850 tegra_cpu_car_ops
= &tegra210_cpu_car_ops
;
2852 CLK_OF_DECLARE(tegra210
, "nvidia,tegra210-car", tegra210_clock_init
);