2 * OMAP APLL clock support
4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * J Keerthy <j-keerthy@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk-provider.h>
19 #include <linux/module.h>
20 #include <linux/slab.h>
22 #include <linux/err.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
26 #include <linux/of_address.h>
27 #include <linux/clk/ti.h>
28 #include <linux/delay.h>
30 #define APLL_FORCE_LOCK 0x1
31 #define APLL_AUTO_IDLE 0x2
32 #define MAX_APLL_WAIT_TRIES 1000000
35 #define pr_fmt(fmt) "%s: " fmt, __func__
37 static int dra7_apll_enable(struct clk_hw
*hw
)
39 struct clk_hw_omap
*clk
= to_clk_hw_omap(hw
);
50 clk_name
= __clk_get_name(clk
->hw
.clk
);
52 state
<<= __ffs(ad
->idlest_mask
);
54 /* Check is already locked */
55 v
= ti_clk_ll_ops
->clk_readl(ad
->idlest_reg
);
57 if ((v
& ad
->idlest_mask
) == state
)
60 v
= ti_clk_ll_ops
->clk_readl(ad
->control_reg
);
61 v
&= ~ad
->enable_mask
;
62 v
|= APLL_FORCE_LOCK
<< __ffs(ad
->enable_mask
);
63 ti_clk_ll_ops
->clk_writel(v
, ad
->control_reg
);
65 state
<<= __ffs(ad
->idlest_mask
);
68 v
= ti_clk_ll_ops
->clk_readl(ad
->idlest_reg
);
69 if ((v
& ad
->idlest_mask
) == state
)
71 if (i
> MAX_APLL_WAIT_TRIES
)
77 if (i
== MAX_APLL_WAIT_TRIES
) {
78 pr_warn("clock: %s failed transition to '%s'\n",
79 clk_name
, (state
) ? "locked" : "bypassed");
81 pr_debug("clock: %s transition to '%s' in %d loops\n",
82 clk_name
, (state
) ? "locked" : "bypassed", i
);
90 static void dra7_apll_disable(struct clk_hw
*hw
)
92 struct clk_hw_omap
*clk
= to_clk_hw_omap(hw
);
99 state
<<= __ffs(ad
->idlest_mask
);
101 v
= ti_clk_ll_ops
->clk_readl(ad
->control_reg
);
102 v
&= ~ad
->enable_mask
;
103 v
|= APLL_AUTO_IDLE
<< __ffs(ad
->enable_mask
);
104 ti_clk_ll_ops
->clk_writel(v
, ad
->control_reg
);
107 static int dra7_apll_is_enabled(struct clk_hw
*hw
)
109 struct clk_hw_omap
*clk
= to_clk_hw_omap(hw
);
110 struct dpll_data
*ad
;
115 v
= ti_clk_ll_ops
->clk_readl(ad
->control_reg
);
116 v
&= ad
->enable_mask
;
118 v
>>= __ffs(ad
->enable_mask
);
120 return v
== APLL_AUTO_IDLE
? 0 : 1;
123 static u8
dra7_init_apll_parent(struct clk_hw
*hw
)
128 static const struct clk_ops apll_ck_ops
= {
129 .enable
= &dra7_apll_enable
,
130 .disable
= &dra7_apll_disable
,
131 .is_enabled
= &dra7_apll_is_enabled
,
132 .get_parent
= &dra7_init_apll_parent
,
135 static void __init
omap_clk_register_apll(struct clk_hw
*hw
,
136 struct device_node
*node
)
138 struct clk_hw_omap
*clk_hw
= to_clk_hw_omap(hw
);
139 struct dpll_data
*ad
= clk_hw
->dpll_data
;
142 ad
->clk_ref
= of_clk_get(node
, 0);
143 ad
->clk_bypass
= of_clk_get(node
, 1);
145 if (IS_ERR(ad
->clk_ref
) || IS_ERR(ad
->clk_bypass
)) {
146 pr_debug("clk-ref or clk-bypass for %s not ready, retry\n",
148 if (!ti_clk_retry_init(node
, hw
, omap_clk_register_apll
))
154 clk
= clk_register(NULL
, &clk_hw
->hw
);
156 of_clk_add_provider(node
, of_clk_src_simple_get
, clk
);
157 kfree(clk_hw
->hw
.init
->parent_names
);
158 kfree(clk_hw
->hw
.init
);
163 kfree(clk_hw
->dpll_data
);
164 kfree(clk_hw
->hw
.init
->parent_names
);
165 kfree(clk_hw
->hw
.init
);
169 static void __init
of_dra7_apll_setup(struct device_node
*node
)
171 struct dpll_data
*ad
= NULL
;
172 struct clk_hw_omap
*clk_hw
= NULL
;
173 struct clk_init_data
*init
= NULL
;
174 const char **parent_names
= NULL
;
177 ad
= kzalloc(sizeof(*ad
), GFP_KERNEL
);
178 clk_hw
= kzalloc(sizeof(*clk_hw
), GFP_KERNEL
);
179 init
= kzalloc(sizeof(*init
), GFP_KERNEL
);
180 if (!ad
|| !clk_hw
|| !init
)
183 clk_hw
->dpll_data
= ad
;
184 clk_hw
->hw
.init
= init
;
185 clk_hw
->flags
= MEMMAP_ADDRESSING
;
187 init
->name
= node
->name
;
188 init
->ops
= &apll_ck_ops
;
190 init
->num_parents
= of_clk_get_parent_count(node
);
191 if (init
->num_parents
< 1) {
192 pr_err("dra7 apll %s must have parent(s)\n", node
->name
);
196 parent_names
= kzalloc(sizeof(char *) * init
->num_parents
, GFP_KERNEL
);
200 for (i
= 0; i
< init
->num_parents
; i
++)
201 parent_names
[i
] = of_clk_get_parent_name(node
, i
);
203 init
->parent_names
= parent_names
;
205 ad
->control_reg
= ti_clk_get_reg_addr(node
, 0);
206 ad
->idlest_reg
= ti_clk_get_reg_addr(node
, 1);
208 if (!ad
->control_reg
|| !ad
->idlest_reg
)
211 ad
->idlest_mask
= 0x1;
212 ad
->enable_mask
= 0x3;
214 omap_clk_register_apll(&clk_hw
->hw
, node
);
223 CLK_OF_DECLARE(dra7_apll_clock
, "ti,dra7-apll-clock", of_dra7_apll_setup
);
225 #define OMAP2_EN_APLL_LOCKED 0x3
226 #define OMAP2_EN_APLL_STOPPED 0x0
228 static int omap2_apll_is_enabled(struct clk_hw
*hw
)
230 struct clk_hw_omap
*clk
= to_clk_hw_omap(hw
);
231 struct dpll_data
*ad
= clk
->dpll_data
;
234 v
= ti_clk_ll_ops
->clk_readl(ad
->control_reg
);
235 v
&= ad
->enable_mask
;
237 v
>>= __ffs(ad
->enable_mask
);
239 return v
== OMAP2_EN_APLL_LOCKED
? 1 : 0;
242 static unsigned long omap2_apll_recalc(struct clk_hw
*hw
,
243 unsigned long parent_rate
)
245 struct clk_hw_omap
*clk
= to_clk_hw_omap(hw
);
247 if (omap2_apll_is_enabled(hw
))
248 return clk
->fixed_rate
;
253 static int omap2_apll_enable(struct clk_hw
*hw
)
255 struct clk_hw_omap
*clk
= to_clk_hw_omap(hw
);
256 struct dpll_data
*ad
= clk
->dpll_data
;
260 v
= ti_clk_ll_ops
->clk_readl(ad
->control_reg
);
261 v
&= ~ad
->enable_mask
;
262 v
|= OMAP2_EN_APLL_LOCKED
<< __ffs(ad
->enable_mask
);
263 ti_clk_ll_ops
->clk_writel(v
, ad
->control_reg
);
266 v
= ti_clk_ll_ops
->clk_readl(ad
->idlest_reg
);
267 if (v
& ad
->idlest_mask
)
269 if (i
> MAX_APLL_WAIT_TRIES
)
275 if (i
== MAX_APLL_WAIT_TRIES
) {
276 pr_warn("%s failed to transition to locked\n",
277 __clk_get_name(clk
->hw
.clk
));
284 static void omap2_apll_disable(struct clk_hw
*hw
)
286 struct clk_hw_omap
*clk
= to_clk_hw_omap(hw
);
287 struct dpll_data
*ad
= clk
->dpll_data
;
290 v
= ti_clk_ll_ops
->clk_readl(ad
->control_reg
);
291 v
&= ~ad
->enable_mask
;
292 v
|= OMAP2_EN_APLL_STOPPED
<< __ffs(ad
->enable_mask
);
293 ti_clk_ll_ops
->clk_writel(v
, ad
->control_reg
);
296 static struct clk_ops omap2_apll_ops
= {
297 .enable
= &omap2_apll_enable
,
298 .disable
= &omap2_apll_disable
,
299 .is_enabled
= &omap2_apll_is_enabled
,
300 .recalc_rate
= &omap2_apll_recalc
,
303 static void omap2_apll_set_autoidle(struct clk_hw_omap
*clk
, u32 val
)
305 struct dpll_data
*ad
= clk
->dpll_data
;
308 v
= ti_clk_ll_ops
->clk_readl(ad
->autoidle_reg
);
309 v
&= ~ad
->autoidle_mask
;
310 v
|= val
<< __ffs(ad
->autoidle_mask
);
311 ti_clk_ll_ops
->clk_writel(v
, ad
->control_reg
);
314 #define OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP 0x3
315 #define OMAP2_APLL_AUTOIDLE_DISABLE 0x0
317 static void omap2_apll_allow_idle(struct clk_hw_omap
*clk
)
319 omap2_apll_set_autoidle(clk
, OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP
);
322 static void omap2_apll_deny_idle(struct clk_hw_omap
*clk
)
324 omap2_apll_set_autoidle(clk
, OMAP2_APLL_AUTOIDLE_DISABLE
);
327 static struct clk_hw_omap_ops omap2_apll_hwops
= {
328 .allow_idle
= &omap2_apll_allow_idle
,
329 .deny_idle
= &omap2_apll_deny_idle
,
332 static void __init
of_omap2_apll_setup(struct device_node
*node
)
334 struct dpll_data
*ad
= NULL
;
335 struct clk_hw_omap
*clk_hw
= NULL
;
336 struct clk_init_data
*init
= NULL
;
338 const char *parent_name
;
341 ad
= kzalloc(sizeof(*clk_hw
), GFP_KERNEL
);
342 clk_hw
= kzalloc(sizeof(*clk_hw
), GFP_KERNEL
);
343 init
= kzalloc(sizeof(*init
), GFP_KERNEL
);
345 if (!ad
|| !clk_hw
|| !init
)
348 clk_hw
->dpll_data
= ad
;
349 clk_hw
->hw
.init
= init
;
350 init
->ops
= &omap2_apll_ops
;
351 init
->name
= node
->name
;
352 clk_hw
->ops
= &omap2_apll_hwops
;
354 init
->num_parents
= of_clk_get_parent_count(node
);
355 if (init
->num_parents
!= 1) {
356 pr_err("%s must have one parent\n", node
->name
);
360 parent_name
= of_clk_get_parent_name(node
, 0);
361 init
->parent_names
= &parent_name
;
363 if (of_property_read_u32(node
, "ti,clock-frequency", &val
)) {
364 pr_err("%s missing clock-frequency\n", node
->name
);
367 clk_hw
->fixed_rate
= val
;
369 if (of_property_read_u32(node
, "ti,bit-shift", &val
)) {
370 pr_err("%s missing bit-shift\n", node
->name
);
374 clk_hw
->enable_bit
= val
;
375 ad
->enable_mask
= 0x3 << val
;
376 ad
->autoidle_mask
= 0x3 << val
;
378 if (of_property_read_u32(node
, "ti,idlest-shift", &val
)) {
379 pr_err("%s missing idlest-shift\n", node
->name
);
383 ad
->idlest_mask
= 1 << val
;
385 ad
->control_reg
= ti_clk_get_reg_addr(node
, 0);
386 ad
->autoidle_reg
= ti_clk_get_reg_addr(node
, 1);
387 ad
->idlest_reg
= ti_clk_get_reg_addr(node
, 2);
389 if (!ad
->control_reg
|| !ad
->autoidle_reg
|| !ad
->idlest_reg
)
392 clk
= clk_register(NULL
, &clk_hw
->hw
);
394 of_clk_add_provider(node
, of_clk_src_simple_get
, clk
);
403 CLK_OF_DECLARE(omap2_apll_clock
, "ti,omap2-apll-clock",
404 of_omap2_apll_setup
);