2 * OMAP3 Legacy clock data
4 * Copyright (C) 2014 Texas Instruments, Inc
5 * Tero Kristo (t-kristo@ti.com)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/kernel.h>
18 #include <linux/clk-provider.h>
19 #include <linux/clk/ti.h>
23 static struct ti_clk_fixed virt_12m_ck_data
= {
24 .frequency
= 12000000,
27 static struct ti_clk virt_12m_ck
= {
28 .name
= "virt_12m_ck",
30 .data
= &virt_12m_ck_data
,
33 static struct ti_clk_fixed virt_13m_ck_data
= {
34 .frequency
= 13000000,
37 static struct ti_clk virt_13m_ck
= {
38 .name
= "virt_13m_ck",
40 .data
= &virt_13m_ck_data
,
43 static struct ti_clk_fixed virt_19200000_ck_data
= {
44 .frequency
= 19200000,
47 static struct ti_clk virt_19200000_ck
= {
48 .name
= "virt_19200000_ck",
50 .data
= &virt_19200000_ck_data
,
53 static struct ti_clk_fixed virt_26000000_ck_data
= {
54 .frequency
= 26000000,
57 static struct ti_clk virt_26000000_ck
= {
58 .name
= "virt_26000000_ck",
60 .data
= &virt_26000000_ck_data
,
63 static struct ti_clk_fixed virt_38_4m_ck_data
= {
64 .frequency
= 38400000,
67 static struct ti_clk virt_38_4m_ck
= {
68 .name
= "virt_38_4m_ck",
70 .data
= &virt_38_4m_ck_data
,
73 static struct ti_clk_fixed virt_16_8m_ck_data
= {
74 .frequency
= 16800000,
77 static struct ti_clk virt_16_8m_ck
= {
78 .name
= "virt_16_8m_ck",
80 .data
= &virt_16_8m_ck_data
,
83 static const char *osc_sys_ck_parents
[] = {
92 static struct ti_clk_mux osc_sys_ck_data
= {
93 .num_parents
= ARRAY_SIZE(osc_sys_ck_parents
),
95 .module
= TI_CLKM_PRM
,
96 .parents
= osc_sys_ck_parents
,
99 static struct ti_clk osc_sys_ck
= {
100 .name
= "osc_sys_ck",
102 .data
= &osc_sys_ck_data
,
105 static struct ti_clk_divider sys_ck_data
= {
106 .parent
= "osc_sys_ck",
110 .module
= TI_CLKM_PRM
,
111 .flags
= CLKF_INDEX_STARTS_AT_ONE
,
114 static struct ti_clk sys_ck
= {
116 .type
= TI_CLK_DIVIDER
,
117 .data
= &sys_ck_data
,
120 static const char *dpll3_ck_parents
[] = {
125 static struct ti_clk_dpll dpll3_ck_data
= {
126 .num_parents
= ARRAY_SIZE(dpll3_ck_parents
),
127 .control_reg
= 0xd00,
129 .mult_div1_reg
= 0xd40,
130 .autoidle_reg
= 0xd30,
131 .module
= TI_CLKM_CM
,
132 .parents
= dpll3_ck_parents
,
134 .freqsel_mask
= 0xf0,
137 .auto_recal_bit
= 0x3,
141 .max_multiplier
= 0x7ff,
143 .mult_mask
= 0x7ff0000,
145 .autoidle_mask
= 0x7,
148 static struct ti_clk dpll3_ck
= {
150 .clkdm_name
= "dpll3_clkdm",
152 .data
= &dpll3_ck_data
,
155 static struct ti_clk_divider dpll3_m2_ck_data
= {
156 .parent
= "dpll3_ck",
160 .module
= TI_CLKM_CM
,
161 .flags
= CLKF_INDEX_STARTS_AT_ONE
,
164 static struct ti_clk dpll3_m2_ck
= {
165 .name
= "dpll3_m2_ck",
166 .type
= TI_CLK_DIVIDER
,
167 .data
= &dpll3_m2_ck_data
,
170 static struct ti_clk_fixed_factor core_ck_data
= {
171 .parent
= "dpll3_m2_ck",
176 static struct ti_clk core_ck
= {
178 .type
= TI_CLK_FIXED_FACTOR
,
179 .data
= &core_ck_data
,
182 static struct ti_clk_divider l3_ick_data
= {
186 .module
= TI_CLKM_CM
,
187 .flags
= CLKF_INDEX_STARTS_AT_ONE
,
190 static struct ti_clk l3_ick
= {
192 .type
= TI_CLK_DIVIDER
,
193 .data
= &l3_ick_data
,
196 static struct ti_clk_fixed_factor security_l3_ick_data
= {
202 static struct ti_clk security_l3_ick
= {
203 .name
= "security_l3_ick",
204 .type
= TI_CLK_FIXED_FACTOR
,
205 .data
= &security_l3_ick_data
,
208 static struct ti_clk_fixed_factor wkup_l4_ick_data
= {
214 static struct ti_clk wkup_l4_ick
= {
215 .name
= "wkup_l4_ick",
216 .type
= TI_CLK_FIXED_FACTOR
,
217 .data
= &wkup_l4_ick_data
,
220 static struct ti_clk_gate usim_ick_data
= {
221 .parent
= "wkup_l4_ick",
224 .module
= TI_CLKM_CM
,
225 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
228 static struct ti_clk usim_ick
= {
230 .clkdm_name
= "wkup_clkdm",
232 .data
= &usim_ick_data
,
235 static struct ti_clk_gate dss2_alwon_fck_data
= {
239 .module
= TI_CLKM_CM
,
242 static struct ti_clk dss2_alwon_fck
= {
243 .name
= "dss2_alwon_fck",
244 .clkdm_name
= "dss_clkdm",
246 .data
= &dss2_alwon_fck_data
,
249 static struct ti_clk_divider l4_ick_data
= {
254 .module
= TI_CLKM_CM
,
255 .flags
= CLKF_INDEX_STARTS_AT_ONE
,
258 static struct ti_clk l4_ick
= {
260 .type
= TI_CLK_DIVIDER
,
261 .data
= &l4_ick_data
,
264 static struct ti_clk_fixed_factor core_l4_ick_data
= {
270 static struct ti_clk core_l4_ick
= {
271 .name
= "core_l4_ick",
272 .type
= TI_CLK_FIXED_FACTOR
,
273 .data
= &core_l4_ick_data
,
276 static struct ti_clk_gate mmchs2_ick_data
= {
277 .parent
= "core_l4_ick",
280 .module
= TI_CLKM_CM
,
281 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
284 static struct ti_clk mmchs2_ick
= {
285 .name
= "mmchs2_ick",
286 .clkdm_name
= "core_l4_clkdm",
288 .data
= &mmchs2_ick_data
,
291 static const char *dpll4_ck_parents
[] = {
296 static struct ti_clk_dpll dpll4_ck_data
= {
297 .num_parents
= ARRAY_SIZE(dpll4_ck_parents
),
298 .control_reg
= 0xd00,
300 .mult_div1_reg
= 0xd44,
301 .autoidle_reg
= 0xd30,
302 .module
= TI_CLKM_CM
,
303 .parents
= dpll4_ck_parents
,
305 .freqsel_mask
= 0xf00000,
309 .auto_recal_bit
= 0x13,
313 .max_multiplier
= 0x7ff,
314 .enable_mask
= 0x70000,
315 .mult_mask
= 0x7ff00,
317 .autoidle_mask
= 0x38,
320 static struct ti_clk dpll4_ck
= {
322 .clkdm_name
= "dpll4_clkdm",
324 .data
= &dpll4_ck_data
,
327 static struct ti_clk_divider dpll4_m2_ck_data
= {
328 .parent
= "dpll4_ck",
331 .module
= TI_CLKM_CM
,
332 .flags
= CLKF_INDEX_STARTS_AT_ONE
,
335 static struct ti_clk dpll4_m2_ck
= {
336 .name
= "dpll4_m2_ck",
337 .type
= TI_CLK_DIVIDER
,
338 .data
= &dpll4_m2_ck_data
,
341 static struct ti_clk_fixed_factor dpll4_m2x2_mul_ck_data
= {
342 .parent
= "dpll4_m2_ck",
347 static struct ti_clk dpll4_m2x2_mul_ck
= {
348 .name
= "dpll4_m2x2_mul_ck",
349 .type
= TI_CLK_FIXED_FACTOR
,
350 .data
= &dpll4_m2x2_mul_ck_data
,
353 static struct ti_clk_gate dpll4_m2x2_ck_data
= {
354 .parent
= "dpll4_m2x2_mul_ck",
357 .module
= TI_CLKM_CM
,
358 .flags
= CLKF_SET_BIT_TO_DISABLE
,
361 static struct ti_clk dpll4_m2x2_ck
= {
362 .name
= "dpll4_m2x2_ck",
364 .data
= &dpll4_m2x2_ck_data
,
367 static struct ti_clk_fixed_factor omap_96m_alwon_fck_data
= {
368 .parent
= "dpll4_m2x2_ck",
373 static struct ti_clk omap_96m_alwon_fck
= {
374 .name
= "omap_96m_alwon_fck",
375 .type
= TI_CLK_FIXED_FACTOR
,
376 .data
= &omap_96m_alwon_fck_data
,
379 static struct ti_clk_fixed_factor cm_96m_fck_data
= {
380 .parent
= "omap_96m_alwon_fck",
385 static struct ti_clk cm_96m_fck
= {
386 .name
= "cm_96m_fck",
387 .type
= TI_CLK_FIXED_FACTOR
,
388 .data
= &cm_96m_fck_data
,
391 static const char *omap_96m_fck_parents
[] = {
396 static struct ti_clk_mux omap_96m_fck_data
= {
398 .num_parents
= ARRAY_SIZE(omap_96m_fck_parents
),
400 .module
= TI_CLKM_CM
,
401 .parents
= omap_96m_fck_parents
,
404 static struct ti_clk omap_96m_fck
= {
405 .name
= "omap_96m_fck",
407 .data
= &omap_96m_fck_data
,
410 static struct ti_clk_fixed_factor core_96m_fck_data
= {
411 .parent
= "omap_96m_fck",
416 static struct ti_clk core_96m_fck
= {
417 .name
= "core_96m_fck",
418 .type
= TI_CLK_FIXED_FACTOR
,
419 .data
= &core_96m_fck_data
,
422 static struct ti_clk_gate mspro_fck_data
= {
423 .parent
= "core_96m_fck",
426 .module
= TI_CLKM_CM
,
430 static struct ti_clk mspro_fck
= {
432 .clkdm_name
= "core_l4_clkdm",
434 .data
= &mspro_fck_data
,
437 static struct ti_clk_gate dss_ick_3430es2_data
= {
441 .module
= TI_CLKM_CM
,
442 .flags
= CLKF_DSS
| CLKF_OMAP3
| CLKF_INTERFACE
,
445 static struct ti_clk dss_ick_3430es2
= {
447 .clkdm_name
= "dss_clkdm",
449 .data
= &dss_ick_3430es2_data
,
452 static struct ti_clk_gate uart4_ick_am35xx_data
= {
453 .parent
= "core_l4_ick",
456 .module
= TI_CLKM_CM
,
457 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
460 static struct ti_clk uart4_ick_am35xx
= {
461 .name
= "uart4_ick_am35xx",
462 .clkdm_name
= "core_l4_clkdm",
464 .data
= &uart4_ick_am35xx_data
,
467 static struct ti_clk_fixed_factor security_l4_ick2_data
= {
473 static struct ti_clk security_l4_ick2
= {
474 .name
= "security_l4_ick2",
475 .type
= TI_CLK_FIXED_FACTOR
,
476 .data
= &security_l4_ick2_data
,
479 static struct ti_clk_gate aes1_ick_data
= {
480 .parent
= "security_l4_ick2",
483 .module
= TI_CLKM_CM
,
484 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
487 static struct ti_clk aes1_ick
= {
490 .data
= &aes1_ick_data
,
493 static const char *dpll5_ck_parents
[] = {
498 static struct ti_clk_dpll dpll5_ck_data
= {
499 .num_parents
= ARRAY_SIZE(dpll5_ck_parents
),
500 .control_reg
= 0xd04,
502 .mult_div1_reg
= 0xd4c,
503 .autoidle_reg
= 0xd34,
504 .module
= TI_CLKM_CM
,
505 .parents
= dpll5_ck_parents
,
506 .freqsel_mask
= 0xf0,
510 .auto_recal_bit
= 0x3,
513 .recal_en_bit
= 0x19,
514 .max_multiplier
= 0x7ff,
516 .mult_mask
= 0x7ff00,
517 .recal_st_bit
= 0x19,
518 .autoidle_mask
= 0x7,
521 static struct ti_clk dpll5_ck
= {
523 .clkdm_name
= "dpll5_clkdm",
525 .data
= &dpll5_ck_data
,
528 static struct ti_clk_divider dpll5_m2_ck_data
= {
529 .parent
= "dpll5_ck",
532 .module
= TI_CLKM_CM
,
533 .flags
= CLKF_INDEX_STARTS_AT_ONE
,
536 static struct ti_clk dpll5_m2_ck
= {
537 .name
= "dpll5_m2_ck",
538 .type
= TI_CLK_DIVIDER
,
539 .data
= &dpll5_m2_ck_data
,
542 static struct ti_clk_gate usbhost_120m_fck_data
= {
543 .parent
= "dpll5_m2_ck",
546 .module
= TI_CLKM_CM
,
549 static struct ti_clk usbhost_120m_fck
= {
550 .name
= "usbhost_120m_fck",
551 .clkdm_name
= "usbhost_clkdm",
553 .data
= &usbhost_120m_fck_data
,
556 static struct ti_clk_fixed_factor cm_96m_d2_fck_data
= {
557 .parent
= "cm_96m_fck",
562 static struct ti_clk cm_96m_d2_fck
= {
563 .name
= "cm_96m_d2_fck",
564 .type
= TI_CLK_FIXED_FACTOR
,
565 .data
= &cm_96m_d2_fck_data
,
568 static struct ti_clk_fixed sys_altclk_data
= {
572 static struct ti_clk sys_altclk
= {
573 .name
= "sys_altclk",
574 .type
= TI_CLK_FIXED
,
575 .data
= &sys_altclk_data
,
578 static const char *omap_48m_fck_parents
[] = {
583 static struct ti_clk_mux omap_48m_fck_data
= {
585 .num_parents
= ARRAY_SIZE(omap_48m_fck_parents
),
587 .module
= TI_CLKM_CM
,
588 .parents
= omap_48m_fck_parents
,
591 static struct ti_clk omap_48m_fck
= {
592 .name
= "omap_48m_fck",
594 .data
= &omap_48m_fck_data
,
597 static struct ti_clk_fixed_factor core_48m_fck_data
= {
598 .parent
= "omap_48m_fck",
603 static struct ti_clk core_48m_fck
= {
604 .name
= "core_48m_fck",
605 .type
= TI_CLK_FIXED_FACTOR
,
606 .data
= &core_48m_fck_data
,
609 static struct ti_clk_fixed mcbsp_clks_data
= {
613 static struct ti_clk mcbsp_clks
= {
614 .name
= "mcbsp_clks",
615 .type
= TI_CLK_FIXED
,
616 .data
= &mcbsp_clks_data
,
619 static struct ti_clk_gate mcbsp2_gate_fck_data
= {
620 .parent
= "mcbsp_clks",
623 .module
= TI_CLKM_CM
,
626 static struct ti_clk_fixed_factor per_96m_fck_data
= {
627 .parent
= "omap_96m_alwon_fck",
632 static struct ti_clk per_96m_fck
= {
633 .name
= "per_96m_fck",
634 .type
= TI_CLK_FIXED_FACTOR
,
635 .data
= &per_96m_fck_data
,
638 static const char *mcbsp2_mux_fck_parents
[] = {
643 static struct ti_clk_mux mcbsp2_mux_fck_data
= {
645 .num_parents
= ARRAY_SIZE(mcbsp2_mux_fck_parents
),
647 .module
= TI_CLKM_SCRM
,
648 .parents
= mcbsp2_mux_fck_parents
,
651 static struct ti_clk_composite mcbsp2_fck_data
= {
652 .mux
= &mcbsp2_mux_fck_data
,
653 .gate
= &mcbsp2_gate_fck_data
,
656 static struct ti_clk mcbsp2_fck
= {
657 .name
= "mcbsp2_fck",
658 .type
= TI_CLK_COMPOSITE
,
659 .data
= &mcbsp2_fck_data
,
662 static struct ti_clk_fixed_factor dpll3_m2x2_ck_data
= {
663 .parent
= "dpll3_m2_ck",
668 static struct ti_clk dpll3_m2x2_ck
= {
669 .name
= "dpll3_m2x2_ck",
670 .type
= TI_CLK_FIXED_FACTOR
,
671 .data
= &dpll3_m2x2_ck_data
,
674 static struct ti_clk_fixed_factor corex2_fck_data
= {
675 .parent
= "dpll3_m2x2_ck",
680 static struct ti_clk corex2_fck
= {
681 .name
= "corex2_fck",
682 .type
= TI_CLK_FIXED_FACTOR
,
683 .data
= &corex2_fck_data
,
686 static struct ti_clk_gate ssi_ssr_gate_fck_3430es1_data
= {
687 .parent
= "corex2_fck",
690 .module
= TI_CLKM_CM
,
691 .flags
= CLKF_NO_WAIT
,
694 static int ssi_ssr_div_fck_3430es1_divs
[] = {
706 static struct ti_clk_divider ssi_ssr_div_fck_3430es1_data
= {
707 .num_dividers
= ARRAY_SIZE(ssi_ssr_div_fck_3430es1_divs
),
708 .parent
= "corex2_fck",
710 .dividers
= ssi_ssr_div_fck_3430es1_divs
,
712 .module
= TI_CLKM_CM
,
715 static struct ti_clk_composite ssi_ssr_fck_3430es1_data
= {
716 .gate
= &ssi_ssr_gate_fck_3430es1_data
,
717 .divider
= &ssi_ssr_div_fck_3430es1_data
,
720 static struct ti_clk ssi_ssr_fck_3430es1
= {
721 .name
= "ssi_ssr_fck",
722 .type
= TI_CLK_COMPOSITE
,
723 .data
= &ssi_ssr_fck_3430es1_data
,
726 static struct ti_clk_fixed_factor ssi_sst_fck_3430es1_data
= {
727 .parent
= "ssi_ssr_fck",
732 static struct ti_clk ssi_sst_fck_3430es1
= {
733 .name
= "ssi_sst_fck",
734 .type
= TI_CLK_FIXED_FACTOR
,
735 .data
= &ssi_sst_fck_3430es1_data
,
738 static struct ti_clk_fixed omap_32k_fck_data
= {
742 static struct ti_clk omap_32k_fck
= {
743 .name
= "omap_32k_fck",
744 .type
= TI_CLK_FIXED
,
745 .data
= &omap_32k_fck_data
,
748 static struct ti_clk_fixed_factor per_32k_alwon_fck_data
= {
749 .parent
= "omap_32k_fck",
754 static struct ti_clk per_32k_alwon_fck
= {
755 .name
= "per_32k_alwon_fck",
756 .type
= TI_CLK_FIXED_FACTOR
,
757 .data
= &per_32k_alwon_fck_data
,
760 static struct ti_clk_gate gpio5_dbck_data
= {
761 .parent
= "per_32k_alwon_fck",
764 .module
= TI_CLKM_CM
,
767 static struct ti_clk gpio5_dbck
= {
768 .name
= "gpio5_dbck",
769 .clkdm_name
= "per_clkdm",
771 .data
= &gpio5_dbck_data
,
774 static struct ti_clk_gate gpt1_ick_data
= {
775 .parent
= "wkup_l4_ick",
778 .module
= TI_CLKM_CM
,
779 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
782 static struct ti_clk gpt1_ick
= {
784 .clkdm_name
= "wkup_clkdm",
786 .data
= &gpt1_ick_data
,
789 static struct ti_clk_gate mcspi3_fck_data
= {
790 .parent
= "core_48m_fck",
793 .module
= TI_CLKM_CM
,
797 static struct ti_clk mcspi3_fck
= {
798 .name
= "mcspi3_fck",
799 .clkdm_name
= "core_l4_clkdm",
801 .data
= &mcspi3_fck_data
,
804 static struct ti_clk_gate gpt2_gate_fck_data
= {
808 .module
= TI_CLKM_CM
,
811 static const char *gpt2_mux_fck_parents
[] = {
816 static struct ti_clk_mux gpt2_mux_fck_data
= {
817 .num_parents
= ARRAY_SIZE(gpt2_mux_fck_parents
),
819 .module
= TI_CLKM_CM
,
820 .parents
= gpt2_mux_fck_parents
,
823 static struct ti_clk_composite gpt2_fck_data
= {
824 .mux
= &gpt2_mux_fck_data
,
825 .gate
= &gpt2_gate_fck_data
,
828 static struct ti_clk gpt2_fck
= {
830 .type
= TI_CLK_COMPOSITE
,
831 .data
= &gpt2_fck_data
,
834 static struct ti_clk_gate gpt10_ick_data
= {
835 .parent
= "core_l4_ick",
838 .module
= TI_CLKM_CM
,
839 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
842 static struct ti_clk gpt10_ick
= {
844 .clkdm_name
= "core_l4_clkdm",
846 .data
= &gpt10_ick_data
,
849 static struct ti_clk_gate uart2_fck_data
= {
850 .parent
= "core_48m_fck",
853 .module
= TI_CLKM_CM
,
857 static struct ti_clk uart2_fck
= {
859 .clkdm_name
= "core_l4_clkdm",
861 .data
= &uart2_fck_data
,
864 static struct ti_clk_fixed_factor sr_l4_ick_data
= {
870 static struct ti_clk sr_l4_ick
= {
872 .type
= TI_CLK_FIXED_FACTOR
,
873 .data
= &sr_l4_ick_data
,
876 static struct ti_clk_fixed_factor omap_96m_d8_fck_data
= {
877 .parent
= "omap_96m_fck",
882 static struct ti_clk omap_96m_d8_fck
= {
883 .name
= "omap_96m_d8_fck",
884 .type
= TI_CLK_FIXED_FACTOR
,
885 .data
= &omap_96m_d8_fck_data
,
888 static struct ti_clk_divider dpll4_m5_ck_data
= {
889 .parent
= "dpll4_ck",
892 .module
= TI_CLKM_CM
,
893 .flags
= CLKF_INDEX_STARTS_AT_ONE
,
896 static struct ti_clk dpll4_m5_ck
= {
897 .name
= "dpll4_m5_ck",
898 .type
= TI_CLK_DIVIDER
,
899 .data
= &dpll4_m5_ck_data
,
902 static struct ti_clk_fixed_factor dpll4_m5x2_mul_ck_data
= {
903 .parent
= "dpll4_m5_ck",
906 .flags
= CLKF_SET_RATE_PARENT
,
909 static struct ti_clk dpll4_m5x2_mul_ck
= {
910 .name
= "dpll4_m5x2_mul_ck",
911 .type
= TI_CLK_FIXED_FACTOR
,
912 .data
= &dpll4_m5x2_mul_ck_data
,
915 static struct ti_clk_gate dpll4_m5x2_ck_data
= {
916 .parent
= "dpll4_m5x2_mul_ck",
919 .module
= TI_CLKM_CM
,
920 .flags
= CLKF_SET_BIT_TO_DISABLE
,
923 static struct ti_clk dpll4_m5x2_ck
= {
924 .name
= "dpll4_m5x2_ck",
926 .data
= &dpll4_m5x2_ck_data
,
929 static struct ti_clk_gate cam_mclk_data
= {
930 .parent
= "dpll4_m5x2_ck",
933 .module
= TI_CLKM_CM
,
934 .flags
= CLKF_SET_RATE_PARENT
,
937 static struct ti_clk cam_mclk
= {
940 .data
= &cam_mclk_data
,
943 static struct ti_clk_gate mcbsp3_gate_fck_data
= {
944 .parent
= "mcbsp_clks",
947 .module
= TI_CLKM_CM
,
950 static const char *mcbsp3_mux_fck_parents
[] = {
955 static struct ti_clk_mux mcbsp3_mux_fck_data
= {
956 .num_parents
= ARRAY_SIZE(mcbsp3_mux_fck_parents
),
958 .module
= TI_CLKM_SCRM
,
959 .parents
= mcbsp3_mux_fck_parents
,
962 static struct ti_clk_composite mcbsp3_fck_data
= {
963 .mux
= &mcbsp3_mux_fck_data
,
964 .gate
= &mcbsp3_gate_fck_data
,
967 static struct ti_clk mcbsp3_fck
= {
968 .name
= "mcbsp3_fck",
969 .type
= TI_CLK_COMPOSITE
,
970 .data
= &mcbsp3_fck_data
,
973 static struct ti_clk_gate csi2_96m_fck_data
= {
974 .parent
= "core_96m_fck",
977 .module
= TI_CLKM_CM
,
980 static struct ti_clk csi2_96m_fck
= {
981 .name
= "csi2_96m_fck",
982 .clkdm_name
= "cam_clkdm",
984 .data
= &csi2_96m_fck_data
,
987 static struct ti_clk_gate gpt9_gate_fck_data
= {
991 .module
= TI_CLKM_CM
,
994 static const char *gpt9_mux_fck_parents
[] = {
999 static struct ti_clk_mux gpt9_mux_fck_data
= {
1001 .num_parents
= ARRAY_SIZE(gpt9_mux_fck_parents
),
1003 .module
= TI_CLKM_CM
,
1004 .parents
= gpt9_mux_fck_parents
,
1007 static struct ti_clk_composite gpt9_fck_data
= {
1008 .mux
= &gpt9_mux_fck_data
,
1009 .gate
= &gpt9_gate_fck_data
,
1012 static struct ti_clk gpt9_fck
= {
1014 .type
= TI_CLK_COMPOSITE
,
1015 .data
= &gpt9_fck_data
,
1018 static struct ti_clk_divider dpll3_m3_ck_data
= {
1019 .parent
= "dpll3_ck",
1023 .module
= TI_CLKM_CM
,
1024 .flags
= CLKF_INDEX_STARTS_AT_ONE
,
1027 static struct ti_clk dpll3_m3_ck
= {
1028 .name
= "dpll3_m3_ck",
1029 .type
= TI_CLK_DIVIDER
,
1030 .data
= &dpll3_m3_ck_data
,
1033 static struct ti_clk_fixed_factor dpll3_m3x2_mul_ck_data
= {
1034 .parent
= "dpll3_m3_ck",
1039 static struct ti_clk dpll3_m3x2_mul_ck
= {
1040 .name
= "dpll3_m3x2_mul_ck",
1041 .type
= TI_CLK_FIXED_FACTOR
,
1042 .data
= &dpll3_m3x2_mul_ck_data
,
1045 static struct ti_clk_gate sr2_fck_data
= {
1049 .module
= TI_CLKM_CM
,
1053 static struct ti_clk sr2_fck
= {
1055 .clkdm_name
= "wkup_clkdm",
1056 .type
= TI_CLK_GATE
,
1057 .data
= &sr2_fck_data
,
1060 static struct ti_clk_fixed pclk_ck_data
= {
1061 .frequency
= 27000000,
1064 static struct ti_clk pclk_ck
= {
1066 .type
= TI_CLK_FIXED
,
1067 .data
= &pclk_ck_data
,
1070 static struct ti_clk_gate wdt2_ick_data
= {
1071 .parent
= "wkup_l4_ick",
1074 .module
= TI_CLKM_CM
,
1075 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
1078 static struct ti_clk wdt2_ick
= {
1080 .clkdm_name
= "wkup_clkdm",
1081 .type
= TI_CLK_GATE
,
1082 .data
= &wdt2_ick_data
,
1085 static struct ti_clk_fixed_factor core_l3_ick_data
= {
1091 static struct ti_clk core_l3_ick
= {
1092 .name
= "core_l3_ick",
1093 .type
= TI_CLK_FIXED_FACTOR
,
1094 .data
= &core_l3_ick_data
,
1097 static struct ti_clk_gate mcspi4_fck_data
= {
1098 .parent
= "core_48m_fck",
1101 .module
= TI_CLKM_CM
,
1105 static struct ti_clk mcspi4_fck
= {
1106 .name
= "mcspi4_fck",
1107 .clkdm_name
= "core_l4_clkdm",
1108 .type
= TI_CLK_GATE
,
1109 .data
= &mcspi4_fck_data
,
1112 static struct ti_clk_fixed_factor per_48m_fck_data
= {
1113 .parent
= "omap_48m_fck",
1118 static struct ti_clk per_48m_fck
= {
1119 .name
= "per_48m_fck",
1120 .type
= TI_CLK_FIXED_FACTOR
,
1121 .data
= &per_48m_fck_data
,
1124 static struct ti_clk_gate uart4_fck_data
= {
1125 .parent
= "per_48m_fck",
1128 .module
= TI_CLKM_CM
,
1132 static struct ti_clk uart4_fck
= {
1133 .name
= "uart4_fck",
1134 .clkdm_name
= "per_clkdm",
1135 .type
= TI_CLK_GATE
,
1136 .data
= &uart4_fck_data
,
1139 static struct ti_clk_fixed_factor omap_96m_d10_fck_data
= {
1140 .parent
= "omap_96m_fck",
1145 static struct ti_clk omap_96m_d10_fck
= {
1146 .name
= "omap_96m_d10_fck",
1147 .type
= TI_CLK_FIXED_FACTOR
,
1148 .data
= &omap_96m_d10_fck_data
,
1151 static struct ti_clk_gate usim_gate_fck_data
= {
1152 .parent
= "omap_96m_fck",
1155 .module
= TI_CLKM_CM
,
1158 static struct ti_clk_fixed_factor per_l4_ick_data
= {
1164 static struct ti_clk per_l4_ick
= {
1165 .name
= "per_l4_ick",
1166 .type
= TI_CLK_FIXED_FACTOR
,
1167 .data
= &per_l4_ick_data
,
1170 static struct ti_clk_gate gpt5_ick_data
= {
1171 .parent
= "per_l4_ick",
1174 .module
= TI_CLKM_CM
,
1175 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
1178 static struct ti_clk gpt5_ick
= {
1180 .clkdm_name
= "per_clkdm",
1181 .type
= TI_CLK_GATE
,
1182 .data
= &gpt5_ick_data
,
1185 static struct ti_clk_gate mcspi2_ick_data
= {
1186 .parent
= "core_l4_ick",
1189 .module
= TI_CLKM_CM
,
1190 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
1193 static struct ti_clk mcspi2_ick
= {
1194 .name
= "mcspi2_ick",
1195 .clkdm_name
= "core_l4_clkdm",
1196 .type
= TI_CLK_GATE
,
1197 .data
= &mcspi2_ick_data
,
1200 static struct ti_clk_fixed_factor ssi_l4_ick_data
= {
1206 static struct ti_clk ssi_l4_ick
= {
1207 .name
= "ssi_l4_ick",
1208 .clkdm_name
= "core_l4_clkdm",
1209 .type
= TI_CLK_FIXED_FACTOR
,
1210 .data
= &ssi_l4_ick_data
,
1213 static struct ti_clk_gate ssi_ick_3430es1_data
= {
1214 .parent
= "ssi_l4_ick",
1217 .module
= TI_CLKM_CM
,
1218 .flags
= CLKF_OMAP3
| CLKF_NO_WAIT
| CLKF_INTERFACE
,
1221 static struct ti_clk ssi_ick_3430es1
= {
1223 .clkdm_name
= "core_l4_clkdm",
1224 .type
= TI_CLK_GATE
,
1225 .data
= &ssi_ick_3430es1_data
,
1228 static struct ti_clk_gate i2c2_fck_data
= {
1229 .parent
= "core_96m_fck",
1232 .module
= TI_CLKM_CM
,
1236 static struct ti_clk i2c2_fck
= {
1238 .clkdm_name
= "core_l4_clkdm",
1239 .type
= TI_CLK_GATE
,
1240 .data
= &i2c2_fck_data
,
1243 static struct ti_clk_divider dpll1_fck_data
= {
1244 .parent
= "core_ck",
1248 .module
= TI_CLKM_CM
,
1249 .flags
= CLKF_INDEX_STARTS_AT_ONE
,
1252 static struct ti_clk dpll1_fck
= {
1253 .name
= "dpll1_fck",
1254 .type
= TI_CLK_DIVIDER
,
1255 .data
= &dpll1_fck_data
,
1258 static const char *dpll1_ck_parents
[] = {
1263 static struct ti_clk_dpll dpll1_ck_data
= {
1264 .num_parents
= ARRAY_SIZE(dpll1_ck_parents
),
1265 .control_reg
= 0x904,
1266 .idlest_reg
= 0x924,
1267 .mult_div1_reg
= 0x940,
1268 .autoidle_reg
= 0x934,
1269 .module
= TI_CLKM_CM
,
1270 .parents
= dpll1_ck_parents
,
1271 .freqsel_mask
= 0xf0,
1275 .auto_recal_bit
= 0x3,
1276 .max_divider
= 0x80,
1278 .recal_en_bit
= 0x7,
1279 .max_multiplier
= 0x7ff,
1281 .mult_mask
= 0x7ff00,
1282 .recal_st_bit
= 0x7,
1283 .autoidle_mask
= 0x7,
1286 static struct ti_clk dpll1_ck
= {
1288 .clkdm_name
= "dpll1_clkdm",
1289 .type
= TI_CLK_DPLL
,
1290 .data
= &dpll1_ck_data
,
1293 static struct ti_clk_fixed secure_32k_fck_data
= {
1297 static struct ti_clk secure_32k_fck
= {
1298 .name
= "secure_32k_fck",
1299 .type
= TI_CLK_FIXED
,
1300 .data
= &secure_32k_fck_data
,
1303 static struct ti_clk_gate gpio5_ick_data
= {
1304 .parent
= "per_l4_ick",
1307 .module
= TI_CLKM_CM
,
1308 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
1311 static struct ti_clk gpio5_ick
= {
1312 .name
= "gpio5_ick",
1313 .clkdm_name
= "per_clkdm",
1314 .type
= TI_CLK_GATE
,
1315 .data
= &gpio5_ick_data
,
1318 static struct ti_clk_divider dpll4_m4_ck_data
= {
1319 .parent
= "dpll4_ck",
1322 .module
= TI_CLKM_CM
,
1323 .flags
= CLKF_INDEX_STARTS_AT_ONE
,
1326 static struct ti_clk dpll4_m4_ck
= {
1327 .name
= "dpll4_m4_ck",
1328 .type
= TI_CLK_DIVIDER
,
1329 .data
= &dpll4_m4_ck_data
,
1332 static struct ti_clk_fixed_factor dpll4_m4x2_mul_ck_data
= {
1333 .parent
= "dpll4_m4_ck",
1336 .flags
= CLKF_SET_RATE_PARENT
,
1339 static struct ti_clk dpll4_m4x2_mul_ck
= {
1340 .name
= "dpll4_m4x2_mul_ck",
1341 .type
= TI_CLK_FIXED_FACTOR
,
1342 .data
= &dpll4_m4x2_mul_ck_data
,
1345 static struct ti_clk_gate dpll4_m4x2_ck_data
= {
1346 .parent
= "dpll4_m4x2_mul_ck",
1349 .module
= TI_CLKM_CM
,
1350 .flags
= CLKF_SET_RATE_PARENT
| CLKF_SET_BIT_TO_DISABLE
,
1353 static struct ti_clk dpll4_m4x2_ck
= {
1354 .name
= "dpll4_m4x2_ck",
1355 .type
= TI_CLK_GATE
,
1356 .data
= &dpll4_m4x2_ck_data
,
1359 static struct ti_clk_gate dss1_alwon_fck_3430es2_data
= {
1360 .parent
= "dpll4_m4x2_ck",
1363 .module
= TI_CLKM_CM
,
1364 .flags
= CLKF_DSS
| CLKF_SET_RATE_PARENT
,
1367 static struct ti_clk dss1_alwon_fck_3430es2
= {
1368 .name
= "dss1_alwon_fck",
1369 .clkdm_name
= "dss_clkdm",
1370 .type
= TI_CLK_GATE
,
1371 .data
= &dss1_alwon_fck_3430es2_data
,
1374 static struct ti_clk_gate uart3_ick_data
= {
1375 .parent
= "per_l4_ick",
1378 .module
= TI_CLKM_CM
,
1379 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
1382 static struct ti_clk uart3_ick
= {
1383 .name
= "uart3_ick",
1384 .clkdm_name
= "per_clkdm",
1385 .type
= TI_CLK_GATE
,
1386 .data
= &uart3_ick_data
,
1389 static struct ti_clk_divider dpll4_m3_ck_data
= {
1390 .parent
= "dpll4_ck",
1394 .module
= TI_CLKM_CM
,
1395 .flags
= CLKF_INDEX_STARTS_AT_ONE
,
1398 static struct ti_clk dpll4_m3_ck
= {
1399 .name
= "dpll4_m3_ck",
1400 .type
= TI_CLK_DIVIDER
,
1401 .data
= &dpll4_m3_ck_data
,
1404 static struct ti_clk_gate mcbsp3_ick_data
= {
1405 .parent
= "per_l4_ick",
1408 .module
= TI_CLKM_CM
,
1409 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
1412 static struct ti_clk mcbsp3_ick
= {
1413 .name
= "mcbsp3_ick",
1414 .clkdm_name
= "per_clkdm",
1415 .type
= TI_CLK_GATE
,
1416 .data
= &mcbsp3_ick_data
,
1419 static struct ti_clk_gate gpio3_dbck_data
= {
1420 .parent
= "per_32k_alwon_fck",
1423 .module
= TI_CLKM_CM
,
1426 static struct ti_clk gpio3_dbck
= {
1427 .name
= "gpio3_dbck",
1428 .clkdm_name
= "per_clkdm",
1429 .type
= TI_CLK_GATE
,
1430 .data
= &gpio3_dbck_data
,
1433 static struct ti_clk_gate fac_ick_data
= {
1434 .parent
= "core_l4_ick",
1437 .module
= TI_CLKM_CM
,
1438 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
1441 static struct ti_clk fac_ick
= {
1443 .clkdm_name
= "core_l4_clkdm",
1444 .type
= TI_CLK_GATE
,
1445 .data
= &fac_ick_data
,
1448 static struct ti_clk_gate clkout2_src_gate_ck_data
= {
1449 .parent
= "core_ck",
1452 .module
= TI_CLKM_CM
,
1453 .flags
= CLKF_NO_WAIT
,
1456 static struct ti_clk_fixed_factor dpll4_m3x2_mul_ck_data
= {
1457 .parent
= "dpll4_m3_ck",
1462 static struct ti_clk dpll4_m3x2_mul_ck
= {
1463 .name
= "dpll4_m3x2_mul_ck",
1464 .type
= TI_CLK_FIXED_FACTOR
,
1465 .data
= &dpll4_m3x2_mul_ck_data
,
1468 static struct ti_clk_gate dpll4_m3x2_ck_data
= {
1469 .parent
= "dpll4_m3x2_mul_ck",
1472 .module
= TI_CLKM_CM
,
1473 .flags
= CLKF_SET_BIT_TO_DISABLE
,
1476 static struct ti_clk dpll4_m3x2_ck
= {
1477 .name
= "dpll4_m3x2_ck",
1478 .type
= TI_CLK_GATE
,
1479 .data
= &dpll4_m3x2_ck_data
,
1482 static const char *omap_54m_fck_parents
[] = {
1487 static struct ti_clk_mux omap_54m_fck_data
= {
1489 .num_parents
= ARRAY_SIZE(omap_54m_fck_parents
),
1491 .module
= TI_CLKM_CM
,
1492 .parents
= omap_54m_fck_parents
,
1495 static struct ti_clk omap_54m_fck
= {
1496 .name
= "omap_54m_fck",
1498 .data
= &omap_54m_fck_data
,
1501 static const char *clkout2_src_mux_ck_parents
[] = {
1508 static struct ti_clk_mux clkout2_src_mux_ck_data
= {
1509 .num_parents
= ARRAY_SIZE(clkout2_src_mux_ck_parents
),
1511 .module
= TI_CLKM_CM
,
1512 .parents
= clkout2_src_mux_ck_parents
,
1515 static struct ti_clk_composite clkout2_src_ck_data
= {
1516 .mux
= &clkout2_src_mux_ck_data
,
1517 .gate
= &clkout2_src_gate_ck_data
,
1520 static struct ti_clk clkout2_src_ck
= {
1521 .name
= "clkout2_src_ck",
1522 .type
= TI_CLK_COMPOSITE
,
1523 .data
= &clkout2_src_ck_data
,
1526 static struct ti_clk_gate i2c1_fck_data
= {
1527 .parent
= "core_96m_fck",
1530 .module
= TI_CLKM_CM
,
1534 static struct ti_clk i2c1_fck
= {
1536 .clkdm_name
= "core_l4_clkdm",
1537 .type
= TI_CLK_GATE
,
1538 .data
= &i2c1_fck_data
,
1541 static struct ti_clk_gate wdt3_fck_data
= {
1542 .parent
= "per_32k_alwon_fck",
1545 .module
= TI_CLKM_CM
,
1549 static struct ti_clk wdt3_fck
= {
1551 .clkdm_name
= "per_clkdm",
1552 .type
= TI_CLK_GATE
,
1553 .data
= &wdt3_fck_data
,
1556 static struct ti_clk_gate gpt7_gate_fck_data
= {
1560 .module
= TI_CLKM_CM
,
1563 static const char *gpt7_mux_fck_parents
[] = {
1568 static struct ti_clk_mux gpt7_mux_fck_data
= {
1570 .num_parents
= ARRAY_SIZE(gpt7_mux_fck_parents
),
1572 .module
= TI_CLKM_CM
,
1573 .parents
= gpt7_mux_fck_parents
,
1576 static struct ti_clk_composite gpt7_fck_data
= {
1577 .mux
= &gpt7_mux_fck_data
,
1578 .gate
= &gpt7_gate_fck_data
,
1581 static struct ti_clk gpt7_fck
= {
1583 .type
= TI_CLK_COMPOSITE
,
1584 .data
= &gpt7_fck_data
,
1587 static struct ti_clk_gate usb_l4_gate_ick_data
= {
1591 .module
= TI_CLKM_CM
,
1592 .flags
= CLKF_INTERFACE
,
1595 static struct ti_clk_divider usb_l4_div_ick_data
= {
1600 .module
= TI_CLKM_CM
,
1601 .flags
= CLKF_INDEX_STARTS_AT_ONE
,
1604 static struct ti_clk_composite usb_l4_ick_data
= {
1605 .gate
= &usb_l4_gate_ick_data
,
1606 .divider
= &usb_l4_div_ick_data
,
1609 static struct ti_clk usb_l4_ick
= {
1610 .name
= "usb_l4_ick",
1611 .type
= TI_CLK_COMPOSITE
,
1612 .data
= &usb_l4_ick_data
,
1615 static struct ti_clk_gate uart4_ick_data
= {
1616 .parent
= "per_l4_ick",
1619 .module
= TI_CLKM_CM
,
1620 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
1623 static struct ti_clk uart4_ick
= {
1624 .name
= "uart4_ick",
1625 .clkdm_name
= "per_clkdm",
1626 .type
= TI_CLK_GATE
,
1627 .data
= &uart4_ick_data
,
1630 static struct ti_clk_fixed dummy_ck_data
= {
1634 static struct ti_clk dummy_ck
= {
1636 .type
= TI_CLK_FIXED
,
1637 .data
= &dummy_ck_data
,
1640 static const char *gpt3_mux_fck_parents
[] = {
1645 static struct ti_clk_mux gpt3_mux_fck_data
= {
1647 .num_parents
= ARRAY_SIZE(gpt3_mux_fck_parents
),
1649 .module
= TI_CLKM_CM
,
1650 .parents
= gpt3_mux_fck_parents
,
1653 static struct ti_clk_gate gpt9_ick_data
= {
1654 .parent
= "per_l4_ick",
1657 .module
= TI_CLKM_CM
,
1658 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
1661 static struct ti_clk gpt9_ick
= {
1663 .clkdm_name
= "per_clkdm",
1664 .type
= TI_CLK_GATE
,
1665 .data
= &gpt9_ick_data
,
1668 static struct ti_clk_gate gpt10_gate_fck_data
= {
1672 .module
= TI_CLKM_CM
,
1675 static struct ti_clk_gate dss_ick_3430es1_data
= {
1679 .module
= TI_CLKM_CM
,
1680 .flags
= CLKF_OMAP3
| CLKF_NO_WAIT
| CLKF_INTERFACE
,
1683 static struct ti_clk dss_ick_3430es1
= {
1685 .clkdm_name
= "dss_clkdm",
1686 .type
= TI_CLK_GATE
,
1687 .data
= &dss_ick_3430es1_data
,
1690 static struct ti_clk_gate gpt11_ick_data
= {
1691 .parent
= "core_l4_ick",
1694 .module
= TI_CLKM_CM
,
1695 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
1698 static struct ti_clk gpt11_ick
= {
1699 .name
= "gpt11_ick",
1700 .clkdm_name
= "core_l4_clkdm",
1701 .type
= TI_CLK_GATE
,
1702 .data
= &gpt11_ick_data
,
1705 static struct ti_clk_divider dpll2_fck_data
= {
1706 .parent
= "core_ck",
1710 .module
= TI_CLKM_CM
,
1711 .flags
= CLKF_INDEX_STARTS_AT_ONE
,
1714 static struct ti_clk dpll2_fck
= {
1715 .name
= "dpll2_fck",
1716 .type
= TI_CLK_DIVIDER
,
1717 .data
= &dpll2_fck_data
,
1720 static struct ti_clk_gate uart1_fck_data
= {
1721 .parent
= "core_48m_fck",
1724 .module
= TI_CLKM_CM
,
1728 static struct ti_clk uart1_fck
= {
1729 .name
= "uart1_fck",
1730 .clkdm_name
= "core_l4_clkdm",
1731 .type
= TI_CLK_GATE
,
1732 .data
= &uart1_fck_data
,
1735 static struct ti_clk_gate hsotgusb_ick_3430es1_data
= {
1736 .parent
= "core_l3_ick",
1739 .module
= TI_CLKM_CM
,
1740 .flags
= CLKF_OMAP3
| CLKF_NO_WAIT
| CLKF_INTERFACE
,
1743 static struct ti_clk hsotgusb_ick_3430es1
= {
1744 .name
= "hsotgusb_ick_3430es1",
1745 .clkdm_name
= "core_l3_clkdm",
1746 .type
= TI_CLK_GATE
,
1747 .data
= &hsotgusb_ick_3430es1_data
,
1750 static struct ti_clk_gate gpio2_ick_data
= {
1751 .parent
= "per_l4_ick",
1754 .module
= TI_CLKM_CM
,
1755 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
1758 static struct ti_clk gpio2_ick
= {
1759 .name
= "gpio2_ick",
1760 .clkdm_name
= "per_clkdm",
1761 .type
= TI_CLK_GATE
,
1762 .data
= &gpio2_ick_data
,
1765 static struct ti_clk_gate mmchs1_ick_data
= {
1766 .parent
= "core_l4_ick",
1769 .module
= TI_CLKM_CM
,
1770 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
1773 static struct ti_clk mmchs1_ick
= {
1774 .name
= "mmchs1_ick",
1775 .clkdm_name
= "core_l4_clkdm",
1776 .type
= TI_CLK_GATE
,
1777 .data
= &mmchs1_ick_data
,
1780 static struct ti_clk_gate modem_fck_data
= {
1784 .module
= TI_CLKM_CM
,
1785 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
1788 static struct ti_clk modem_fck
= {
1789 .name
= "modem_fck",
1790 .clkdm_name
= "d2d_clkdm",
1791 .type
= TI_CLK_GATE
,
1792 .data
= &modem_fck_data
,
1795 static struct ti_clk_gate mcbsp4_ick_data
= {
1796 .parent
= "per_l4_ick",
1799 .module
= TI_CLKM_CM
,
1800 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
1803 static struct ti_clk mcbsp4_ick
= {
1804 .name
= "mcbsp4_ick",
1805 .clkdm_name
= "per_clkdm",
1806 .type
= TI_CLK_GATE
,
1807 .data
= &mcbsp4_ick_data
,
1810 static struct ti_clk_gate gpio1_ick_data
= {
1811 .parent
= "wkup_l4_ick",
1814 .module
= TI_CLKM_CM
,
1815 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
1818 static struct ti_clk gpio1_ick
= {
1819 .name
= "gpio1_ick",
1820 .clkdm_name
= "wkup_clkdm",
1821 .type
= TI_CLK_GATE
,
1822 .data
= &gpio1_ick_data
,
1825 static const char *gpt6_mux_fck_parents
[] = {
1830 static struct ti_clk_mux gpt6_mux_fck_data
= {
1832 .num_parents
= ARRAY_SIZE(gpt6_mux_fck_parents
),
1834 .module
= TI_CLKM_CM
,
1835 .parents
= gpt6_mux_fck_parents
,
1838 static struct ti_clk_fixed_factor dpll1_x2_ck_data
= {
1839 .parent
= "dpll1_ck",
1844 static struct ti_clk dpll1_x2_ck
= {
1845 .name
= "dpll1_x2_ck",
1846 .type
= TI_CLK_FIXED_FACTOR
,
1847 .data
= &dpll1_x2_ck_data
,
1850 static struct ti_clk_divider dpll1_x2m2_ck_data
= {
1851 .parent
= "dpll1_x2_ck",
1854 .module
= TI_CLKM_CM
,
1855 .flags
= CLKF_INDEX_STARTS_AT_ONE
,
1858 static struct ti_clk dpll1_x2m2_ck
= {
1859 .name
= "dpll1_x2m2_ck",
1860 .type
= TI_CLK_DIVIDER
,
1861 .data
= &dpll1_x2m2_ck_data
,
1864 static struct ti_clk_fixed_factor mpu_ck_data
= {
1865 .parent
= "dpll1_x2m2_ck",
1870 static struct ti_clk mpu_ck
= {
1872 .type
= TI_CLK_FIXED_FACTOR
,
1873 .data
= &mpu_ck_data
,
1876 static struct ti_clk_divider arm_fck_data
= {
1880 .module
= TI_CLKM_CM
,
1883 static struct ti_clk arm_fck
= {
1885 .type
= TI_CLK_DIVIDER
,
1886 .data
= &arm_fck_data
,
1889 static struct ti_clk_fixed_factor core_d3_ck_data
= {
1890 .parent
= "core_ck",
1895 static struct ti_clk core_d3_ck
= {
1896 .name
= "core_d3_ck",
1897 .type
= TI_CLK_FIXED_FACTOR
,
1898 .data
= &core_d3_ck_data
,
1901 static struct ti_clk_gate gpt11_gate_fck_data
= {
1905 .module
= TI_CLKM_CM
,
1908 static const char *gpt11_mux_fck_parents
[] = {
1913 static struct ti_clk_mux gpt11_mux_fck_data
= {
1915 .num_parents
= ARRAY_SIZE(gpt11_mux_fck_parents
),
1917 .module
= TI_CLKM_CM
,
1918 .parents
= gpt11_mux_fck_parents
,
1921 static struct ti_clk_composite gpt11_fck_data
= {
1922 .mux
= &gpt11_mux_fck_data
,
1923 .gate
= &gpt11_gate_fck_data
,
1926 static struct ti_clk gpt11_fck
= {
1927 .name
= "gpt11_fck",
1928 .type
= TI_CLK_COMPOSITE
,
1929 .data
= &gpt11_fck_data
,
1932 static struct ti_clk_fixed_factor core_d6_ck_data
= {
1933 .parent
= "core_ck",
1938 static struct ti_clk core_d6_ck
= {
1939 .name
= "core_d6_ck",
1940 .type
= TI_CLK_FIXED_FACTOR
,
1941 .data
= &core_d6_ck_data
,
1944 static struct ti_clk_gate uart4_fck_am35xx_data
= {
1945 .parent
= "core_48m_fck",
1948 .module
= TI_CLKM_CM
,
1952 static struct ti_clk uart4_fck_am35xx
= {
1953 .name
= "uart4_fck_am35xx",
1954 .clkdm_name
= "core_l4_clkdm",
1955 .type
= TI_CLK_GATE
,
1956 .data
= &uart4_fck_am35xx_data
,
1959 static struct ti_clk_gate dpll3_m3x2_ck_data
= {
1960 .parent
= "dpll3_m3x2_mul_ck",
1963 .module
= TI_CLKM_CM
,
1964 .flags
= CLKF_SET_BIT_TO_DISABLE
,
1967 static struct ti_clk dpll3_m3x2_ck
= {
1968 .name
= "dpll3_m3x2_ck",
1969 .type
= TI_CLK_GATE
,
1970 .data
= &dpll3_m3x2_ck_data
,
1973 static struct ti_clk_fixed_factor emu_core_alwon_ck_data
= {
1974 .parent
= "dpll3_m3x2_ck",
1979 static struct ti_clk emu_core_alwon_ck
= {
1980 .name
= "emu_core_alwon_ck",
1981 .type
= TI_CLK_FIXED_FACTOR
,
1982 .data
= &emu_core_alwon_ck_data
,
1985 static struct ti_clk_divider dpll4_m6_ck_data
= {
1986 .parent
= "dpll4_ck",
1990 .module
= TI_CLKM_CM
,
1991 .flags
= CLKF_INDEX_STARTS_AT_ONE
,
1994 static struct ti_clk dpll4_m6_ck
= {
1995 .name
= "dpll4_m6_ck",
1996 .type
= TI_CLK_DIVIDER
,
1997 .data
= &dpll4_m6_ck_data
,
2000 static struct ti_clk_fixed_factor dpll4_m6x2_mul_ck_data
= {
2001 .parent
= "dpll4_m6_ck",
2006 static struct ti_clk dpll4_m6x2_mul_ck
= {
2007 .name
= "dpll4_m6x2_mul_ck",
2008 .type
= TI_CLK_FIXED_FACTOR
,
2009 .data
= &dpll4_m6x2_mul_ck_data
,
2012 static struct ti_clk_gate dpll4_m6x2_ck_data
= {
2013 .parent
= "dpll4_m6x2_mul_ck",
2016 .module
= TI_CLKM_CM
,
2017 .flags
= CLKF_SET_BIT_TO_DISABLE
,
2020 static struct ti_clk dpll4_m6x2_ck
= {
2021 .name
= "dpll4_m6x2_ck",
2022 .type
= TI_CLK_GATE
,
2023 .data
= &dpll4_m6x2_ck_data
,
2026 static struct ti_clk_fixed_factor emu_per_alwon_ck_data
= {
2027 .parent
= "dpll4_m6x2_ck",
2032 static struct ti_clk emu_per_alwon_ck
= {
2033 .name
= "emu_per_alwon_ck",
2034 .type
= TI_CLK_FIXED_FACTOR
,
2035 .data
= &emu_per_alwon_ck_data
,
2038 static struct ti_clk_fixed_factor emu_mpu_alwon_ck_data
= {
2044 static struct ti_clk emu_mpu_alwon_ck
= {
2045 .name
= "emu_mpu_alwon_ck",
2046 .type
= TI_CLK_FIXED_FACTOR
,
2047 .data
= &emu_mpu_alwon_ck_data
,
2050 static const char *emu_src_mux_ck_parents
[] = {
2052 "emu_core_alwon_ck",
2057 static struct ti_clk_mux emu_src_mux_ck_data
= {
2058 .num_parents
= ARRAY_SIZE(emu_src_mux_ck_parents
),
2060 .module
= TI_CLKM_CM
,
2061 .parents
= emu_src_mux_ck_parents
,
2064 static struct ti_clk emu_src_mux_ck
= {
2065 .name
= "emu_src_mux_ck",
2067 .data
= &emu_src_mux_ck_data
,
2070 static struct ti_clk_gate emu_src_ck_data
= {
2071 .parent
= "emu_src_mux_ck",
2072 .flags
= CLKF_CLKDM
,
2075 static struct ti_clk emu_src_ck
= {
2076 .name
= "emu_src_ck",
2077 .clkdm_name
= "emu_clkdm",
2078 .type
= TI_CLK_GATE
,
2079 .data
= &emu_src_ck_data
,
2082 static struct ti_clk_divider atclk_fck_data
= {
2083 .parent
= "emu_src_ck",
2087 .module
= TI_CLKM_CM
,
2088 .flags
= CLKF_INDEX_STARTS_AT_ONE
,
2091 static struct ti_clk atclk_fck
= {
2092 .name
= "atclk_fck",
2093 .type
= TI_CLK_DIVIDER
,
2094 .data
= &atclk_fck_data
,
2097 static struct ti_clk_gate ipss_ick_data
= {
2098 .parent
= "core_l3_ick",
2101 .module
= TI_CLKM_CM
,
2102 .flags
= CLKF_AM35XX
| CLKF_INTERFACE
,
2105 static struct ti_clk ipss_ick
= {
2107 .clkdm_name
= "core_l3_clkdm",
2108 .type
= TI_CLK_GATE
,
2109 .data
= &ipss_ick_data
,
2112 static struct ti_clk_gate emac_ick_data
= {
2113 .parent
= "ipss_ick",
2116 .module
= TI_CLKM_SCRM
,
2117 .flags
= CLKF_AM35XX
,
2120 static struct ti_clk emac_ick
= {
2122 .clkdm_name
= "core_l3_clkdm",
2123 .type
= TI_CLK_GATE
,
2124 .data
= &emac_ick_data
,
2127 static struct ti_clk_gate vpfe_ick_data
= {
2128 .parent
= "ipss_ick",
2131 .module
= TI_CLKM_SCRM
,
2132 .flags
= CLKF_AM35XX
,
2135 static struct ti_clk vpfe_ick
= {
2137 .clkdm_name
= "core_l3_clkdm",
2138 .type
= TI_CLK_GATE
,
2139 .data
= &vpfe_ick_data
,
2142 static const char *dpll2_ck_parents
[] = {
2147 static struct ti_clk_dpll dpll2_ck_data
= {
2148 .num_parents
= ARRAY_SIZE(dpll2_ck_parents
),
2151 .mult_div1_reg
= 0x40,
2152 .autoidle_reg
= 0x34,
2153 .module
= TI_CLKM_CM
,
2154 .parents
= dpll2_ck_parents
,
2155 .freqsel_mask
= 0xf0,
2159 .auto_recal_bit
= 0x3,
2160 .max_divider
= 0x80,
2162 .recal_en_bit
= 0x8,
2163 .max_multiplier
= 0x7ff,
2165 .mult_mask
= 0x7ff00,
2166 .recal_st_bit
= 0x8,
2167 .autoidle_mask
= 0x7,
2170 static struct ti_clk dpll2_ck
= {
2172 .clkdm_name
= "dpll2_clkdm",
2173 .type
= TI_CLK_DPLL
,
2174 .data
= &dpll2_ck_data
,
2177 static struct ti_clk_divider dpll2_m2_ck_data
= {
2178 .parent
= "dpll2_ck",
2181 .module
= TI_CLKM_CM
,
2182 .flags
= CLKF_INDEX_STARTS_AT_ONE
,
2185 static struct ti_clk dpll2_m2_ck
= {
2186 .name
= "dpll2_m2_ck",
2187 .type
= TI_CLK_DIVIDER
,
2188 .data
= &dpll2_m2_ck_data
,
2191 static const char *mcbsp4_mux_fck_parents
[] = {
2196 static struct ti_clk_mux mcbsp4_mux_fck_data
= {
2198 .num_parents
= ARRAY_SIZE(mcbsp4_mux_fck_parents
),
2200 .module
= TI_CLKM_SCRM
,
2201 .parents
= mcbsp4_mux_fck_parents
,
2204 static const char *mcbsp1_mux_fck_parents
[] = {
2209 static struct ti_clk_mux mcbsp1_mux_fck_data
= {
2211 .num_parents
= ARRAY_SIZE(mcbsp1_mux_fck_parents
),
2213 .module
= TI_CLKM_SCRM
,
2214 .parents
= mcbsp1_mux_fck_parents
,
2217 static struct ti_clk_gate gpt8_gate_fck_data
= {
2221 .module
= TI_CLKM_CM
,
2224 static struct ti_clk_gate gpt8_ick_data
= {
2225 .parent
= "per_l4_ick",
2228 .module
= TI_CLKM_CM
,
2229 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
2232 static struct ti_clk gpt8_ick
= {
2234 .clkdm_name
= "per_clkdm",
2235 .type
= TI_CLK_GATE
,
2236 .data
= &gpt8_ick_data
,
2239 static const char *gpt10_mux_fck_parents
[] = {
2244 static struct ti_clk_mux gpt10_mux_fck_data
= {
2246 .num_parents
= ARRAY_SIZE(gpt10_mux_fck_parents
),
2248 .module
= TI_CLKM_CM
,
2249 .parents
= gpt10_mux_fck_parents
,
2252 static struct ti_clk_gate mmchs3_ick_data
= {
2253 .parent
= "core_l4_ick",
2256 .module
= TI_CLKM_CM
,
2257 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
2260 static struct ti_clk mmchs3_ick
= {
2261 .name
= "mmchs3_ick",
2262 .clkdm_name
= "core_l4_clkdm",
2263 .type
= TI_CLK_GATE
,
2264 .data
= &mmchs3_ick_data
,
2267 static struct ti_clk_gate gpio3_ick_data
= {
2268 .parent
= "per_l4_ick",
2271 .module
= TI_CLKM_CM
,
2272 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
2275 static struct ti_clk gpio3_ick
= {
2276 .name
= "gpio3_ick",
2277 .clkdm_name
= "per_clkdm",
2278 .type
= TI_CLK_GATE
,
2279 .data
= &gpio3_ick_data
,
2282 static const char *traceclk_src_fck_parents
[] = {
2284 "emu_core_alwon_ck",
2289 static struct ti_clk_mux traceclk_src_fck_data
= {
2291 .num_parents
= ARRAY_SIZE(traceclk_src_fck_parents
),
2293 .module
= TI_CLKM_CM
,
2294 .parents
= traceclk_src_fck_parents
,
2297 static struct ti_clk traceclk_src_fck
= {
2298 .name
= "traceclk_src_fck",
2300 .data
= &traceclk_src_fck_data
,
2303 static struct ti_clk_divider traceclk_fck_data
= {
2304 .parent
= "traceclk_src_fck",
2308 .module
= TI_CLKM_CM
,
2309 .flags
= CLKF_INDEX_STARTS_AT_ONE
,
2312 static struct ti_clk traceclk_fck
= {
2313 .name
= "traceclk_fck",
2314 .type
= TI_CLK_DIVIDER
,
2315 .data
= &traceclk_fck_data
,
2318 static struct ti_clk_gate mcbsp5_gate_fck_data
= {
2319 .parent
= "mcbsp_clks",
2322 .module
= TI_CLKM_CM
,
2325 static struct ti_clk_gate sad2d_ick_data
= {
2329 .module
= TI_CLKM_CM
,
2330 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
2333 static struct ti_clk sad2d_ick
= {
2334 .name
= "sad2d_ick",
2335 .clkdm_name
= "d2d_clkdm",
2336 .type
= TI_CLK_GATE
,
2337 .data
= &sad2d_ick_data
,
2340 static const char *gpt1_mux_fck_parents
[] = {
2345 static struct ti_clk_mux gpt1_mux_fck_data
= {
2346 .num_parents
= ARRAY_SIZE(gpt1_mux_fck_parents
),
2348 .module
= TI_CLKM_CM
,
2349 .parents
= gpt1_mux_fck_parents
,
2352 static struct ti_clk_gate hecc_ck_data
= {
2356 .module
= TI_CLKM_SCRM
,
2357 .flags
= CLKF_AM35XX
,
2360 static struct ti_clk hecc_ck
= {
2362 .clkdm_name
= "core_l3_clkdm",
2363 .type
= TI_CLK_GATE
,
2364 .data
= &hecc_ck_data
,
2367 static struct ti_clk_gate gpt1_gate_fck_data
= {
2371 .module
= TI_CLKM_CM
,
2374 static struct ti_clk_composite gpt1_fck_data
= {
2375 .mux
= &gpt1_mux_fck_data
,
2376 .gate
= &gpt1_gate_fck_data
,
2379 static struct ti_clk gpt1_fck
= {
2381 .type
= TI_CLK_COMPOSITE
,
2382 .data
= &gpt1_fck_data
,
2385 static struct ti_clk_gate dpll4_m2x2_ck_omap36xx_data
= {
2386 .parent
= "dpll4_m2x2_mul_ck",
2389 .module
= TI_CLKM_CM
,
2390 .flags
= CLKF_HSDIV
| CLKF_SET_BIT_TO_DISABLE
,
2393 static struct ti_clk dpll4_m2x2_ck_omap36xx
= {
2394 .name
= "dpll4_m2x2_ck",
2395 .type
= TI_CLK_GATE
,
2396 .data
= &dpll4_m2x2_ck_omap36xx_data
,
2397 .patch
= &dpll4_m2x2_ck
,
2400 static struct ti_clk_divider gfx_l3_fck_data
= {
2404 .module
= TI_CLKM_CM
,
2405 .flags
= CLKF_INDEX_STARTS_AT_ONE
,
2408 static struct ti_clk gfx_l3_fck
= {
2409 .name
= "gfx_l3_fck",
2410 .type
= TI_CLK_DIVIDER
,
2411 .data
= &gfx_l3_fck_data
,
2414 static struct ti_clk_gate gfx_cg1_ck_data
= {
2415 .parent
= "gfx_l3_fck",
2418 .module
= TI_CLKM_CM
,
2422 static struct ti_clk gfx_cg1_ck
= {
2423 .name
= "gfx_cg1_ck",
2424 .clkdm_name
= "gfx_3430es1_clkdm",
2425 .type
= TI_CLK_GATE
,
2426 .data
= &gfx_cg1_ck_data
,
2429 static struct ti_clk_gate mailboxes_ick_data
= {
2430 .parent
= "core_l4_ick",
2433 .module
= TI_CLKM_CM
,
2434 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
2437 static struct ti_clk mailboxes_ick
= {
2438 .name
= "mailboxes_ick",
2439 .clkdm_name
= "core_l4_clkdm",
2440 .type
= TI_CLK_GATE
,
2441 .data
= &mailboxes_ick_data
,
2444 static struct ti_clk_gate sha11_ick_data
= {
2445 .parent
= "security_l4_ick2",
2448 .module
= TI_CLKM_CM
,
2449 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
2452 static struct ti_clk sha11_ick
= {
2453 .name
= "sha11_ick",
2454 .type
= TI_CLK_GATE
,
2455 .data
= &sha11_ick_data
,
2458 static struct ti_clk_gate hsotgusb_ick_am35xx_data
= {
2459 .parent
= "ipss_ick",
2462 .module
= TI_CLKM_SCRM
,
2463 .flags
= CLKF_AM35XX
,
2466 static struct ti_clk hsotgusb_ick_am35xx
= {
2467 .name
= "hsotgusb_ick_am35xx",
2468 .clkdm_name
= "core_l3_clkdm",
2469 .type
= TI_CLK_GATE
,
2470 .data
= &hsotgusb_ick_am35xx_data
,
2473 static struct ti_clk_gate mmchs3_fck_data
= {
2474 .parent
= "core_96m_fck",
2477 .module
= TI_CLKM_CM
,
2481 static struct ti_clk mmchs3_fck
= {
2482 .name
= "mmchs3_fck",
2483 .clkdm_name
= "core_l4_clkdm",
2484 .type
= TI_CLK_GATE
,
2485 .data
= &mmchs3_fck_data
,
2488 static struct ti_clk_divider pclk_fck_data
= {
2489 .parent
= "emu_src_ck",
2493 .module
= TI_CLKM_CM
,
2494 .flags
= CLKF_INDEX_STARTS_AT_ONE
,
2497 static struct ti_clk pclk_fck
= {
2499 .type
= TI_CLK_DIVIDER
,
2500 .data
= &pclk_fck_data
,
2503 static const char *dpll4_ck_omap36xx_parents
[] = {
2508 static struct ti_clk_dpll dpll4_ck_omap36xx_data
= {
2509 .num_parents
= ARRAY_SIZE(dpll4_ck_omap36xx_parents
),
2510 .control_reg
= 0xd00,
2511 .idlest_reg
= 0xd20,
2512 .mult_div1_reg
= 0xd44,
2513 .autoidle_reg
= 0xd30,
2514 .module
= TI_CLKM_CM
,
2515 .parents
= dpll4_ck_omap36xx_parents
,
2519 .auto_recal_bit
= 0x13,
2520 .max_divider
= 0x80,
2522 .recal_en_bit
= 0x6,
2523 .max_multiplier
= 0xfff,
2524 .enable_mask
= 0x70000,
2525 .mult_mask
= 0xfff00,
2526 .recal_st_bit
= 0x6,
2527 .autoidle_mask
= 0x38,
2528 .sddiv_mask
= 0xff000000,
2529 .dco_mask
= 0xe00000,
2530 .flags
= CLKF_PER
| CLKF_J_TYPE
,
2533 static struct ti_clk dpll4_ck_omap36xx
= {
2535 .type
= TI_CLK_DPLL
,
2536 .data
= &dpll4_ck_omap36xx_data
,
2540 static struct ti_clk_gate uart3_fck_data
= {
2541 .parent
= "per_48m_fck",
2544 .module
= TI_CLKM_CM
,
2548 static struct ti_clk uart3_fck
= {
2549 .name
= "uart3_fck",
2550 .clkdm_name
= "per_clkdm",
2551 .type
= TI_CLK_GATE
,
2552 .data
= &uart3_fck_data
,
2555 static struct ti_clk_fixed_factor wkup_32k_fck_data
= {
2556 .parent
= "omap_32k_fck",
2561 static struct ti_clk wkup_32k_fck
= {
2562 .name
= "wkup_32k_fck",
2563 .type
= TI_CLK_FIXED_FACTOR
,
2564 .data
= &wkup_32k_fck_data
,
2567 static struct ti_clk_gate sys_clkout1_data
= {
2568 .parent
= "osc_sys_ck",
2571 .module
= TI_CLKM_PRM
,
2574 static struct ti_clk sys_clkout1
= {
2575 .name
= "sys_clkout1",
2576 .type
= TI_CLK_GATE
,
2577 .data
= &sys_clkout1_data
,
2580 static struct ti_clk_fixed_factor gpmc_fck_data
= {
2581 .parent
= "core_l3_ick",
2586 static struct ti_clk gpmc_fck
= {
2588 .type
= TI_CLK_FIXED_FACTOR
,
2589 .data
= &gpmc_fck_data
,
2592 static struct ti_clk_fixed_factor dpll5_m2_d20_ck_data
= {
2593 .parent
= "dpll5_m2_ck",
2598 static struct ti_clk dpll5_m2_d20_ck
= {
2599 .name
= "dpll5_m2_d20_ck",
2600 .type
= TI_CLK_FIXED_FACTOR
,
2601 .data
= &dpll5_m2_d20_ck_data
,
2604 static struct ti_clk_gate dpll4_m5x2_ck_omap36xx_data
= {
2605 .parent
= "dpll4_m5x2_mul_ck",
2608 .module
= TI_CLKM_CM
,
2609 .flags
= CLKF_HSDIV
| CLKF_SET_RATE_PARENT
| CLKF_SET_BIT_TO_DISABLE
,
2612 static struct ti_clk dpll4_m5x2_ck_omap36xx
= {
2613 .name
= "dpll4_m5x2_ck",
2614 .type
= TI_CLK_GATE
,
2615 .data
= &dpll4_m5x2_ck_omap36xx_data
,
2616 .patch
= &dpll4_m5x2_ck
,
2619 static struct ti_clk_gate ssi_ssr_gate_fck_3430es2_data
= {
2620 .parent
= "corex2_fck",
2623 .module
= TI_CLKM_CM
,
2624 .flags
= CLKF_NO_WAIT
,
2627 static struct ti_clk_gate uart1_ick_data
= {
2628 .parent
= "core_l4_ick",
2631 .module
= TI_CLKM_CM
,
2632 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
2635 static struct ti_clk uart1_ick
= {
2636 .name
= "uart1_ick",
2637 .clkdm_name
= "core_l4_clkdm",
2638 .type
= TI_CLK_GATE
,
2639 .data
= &uart1_ick_data
,
2642 static struct ti_clk_gate iva2_ck_data
= {
2643 .parent
= "dpll2_m2_ck",
2646 .module
= TI_CLKM_CM
,
2650 static struct ti_clk iva2_ck
= {
2652 .clkdm_name
= "iva2_clkdm",
2653 .type
= TI_CLK_GATE
,
2654 .data
= &iva2_ck_data
,
2657 static struct ti_clk_gate pka_ick_data
= {
2658 .parent
= "security_l3_ick",
2661 .module
= TI_CLKM_CM
,
2662 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
2665 static struct ti_clk pka_ick
= {
2667 .type
= TI_CLK_GATE
,
2668 .data
= &pka_ick_data
,
2671 static struct ti_clk_gate gpt12_ick_data
= {
2672 .parent
= "wkup_l4_ick",
2675 .module
= TI_CLKM_CM
,
2676 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
2679 static struct ti_clk gpt12_ick
= {
2680 .name
= "gpt12_ick",
2681 .clkdm_name
= "wkup_clkdm",
2682 .type
= TI_CLK_GATE
,
2683 .data
= &gpt12_ick_data
,
2686 static const char *mcbsp5_mux_fck_parents
[] = {
2691 static struct ti_clk_mux mcbsp5_mux_fck_data
= {
2693 .num_parents
= ARRAY_SIZE(mcbsp5_mux_fck_parents
),
2695 .module
= TI_CLKM_SCRM
,
2696 .parents
= mcbsp5_mux_fck_parents
,
2699 static struct ti_clk_composite mcbsp5_fck_data
= {
2700 .mux
= &mcbsp5_mux_fck_data
,
2701 .gate
= &mcbsp5_gate_fck_data
,
2704 static struct ti_clk mcbsp5_fck
= {
2705 .name
= "mcbsp5_fck",
2706 .type
= TI_CLK_COMPOSITE
,
2707 .data
= &mcbsp5_fck_data
,
2710 static struct ti_clk_gate usbhost_48m_fck_data
= {
2711 .parent
= "omap_48m_fck",
2714 .module
= TI_CLKM_CM
,
2718 static struct ti_clk usbhost_48m_fck
= {
2719 .name
= "usbhost_48m_fck",
2720 .clkdm_name
= "usbhost_clkdm",
2721 .type
= TI_CLK_GATE
,
2722 .data
= &usbhost_48m_fck_data
,
2725 static struct ti_clk_gate des1_ick_data
= {
2726 .parent
= "security_l4_ick2",
2729 .module
= TI_CLKM_CM
,
2730 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
2733 static struct ti_clk des1_ick
= {
2735 .type
= TI_CLK_GATE
,
2736 .data
= &des1_ick_data
,
2739 static struct ti_clk_gate sgx_gate_fck_data
= {
2740 .parent
= "core_ck",
2743 .module
= TI_CLKM_CM
,
2746 static struct ti_clk_fixed_factor core_d4_ck_data
= {
2747 .parent
= "core_ck",
2752 static struct ti_clk core_d4_ck
= {
2753 .name
= "core_d4_ck",
2754 .type
= TI_CLK_FIXED_FACTOR
,
2755 .data
= &core_d4_ck_data
,
2758 static struct ti_clk_fixed_factor omap_192m_alwon_fck_data
= {
2759 .parent
= "dpll4_m2x2_ck",
2764 static struct ti_clk omap_192m_alwon_fck
= {
2765 .name
= "omap_192m_alwon_fck",
2766 .type
= TI_CLK_FIXED_FACTOR
,
2767 .data
= &omap_192m_alwon_fck_data
,
2770 static struct ti_clk_fixed_factor core_d2_ck_data
= {
2771 .parent
= "core_ck",
2776 static struct ti_clk core_d2_ck
= {
2777 .name
= "core_d2_ck",
2778 .type
= TI_CLK_FIXED_FACTOR
,
2779 .data
= &core_d2_ck_data
,
2782 static struct ti_clk_fixed_factor corex2_d3_fck_data
= {
2783 .parent
= "corex2_fck",
2788 static struct ti_clk corex2_d3_fck
= {
2789 .name
= "corex2_d3_fck",
2790 .type
= TI_CLK_FIXED_FACTOR
,
2791 .data
= &corex2_d3_fck_data
,
2794 static struct ti_clk_fixed_factor corex2_d5_fck_data
= {
2795 .parent
= "corex2_fck",
2800 static struct ti_clk corex2_d5_fck
= {
2801 .name
= "corex2_d5_fck",
2802 .type
= TI_CLK_FIXED_FACTOR
,
2803 .data
= &corex2_d5_fck_data
,
2806 static const char *sgx_mux_fck_parents
[] = {
2811 "omap_192m_alwon_fck",
2817 static struct ti_clk_mux sgx_mux_fck_data
= {
2818 .num_parents
= ARRAY_SIZE(sgx_mux_fck_parents
),
2820 .module
= TI_CLKM_CM
,
2821 .parents
= sgx_mux_fck_parents
,
2824 static struct ti_clk_composite sgx_fck_data
= {
2825 .mux
= &sgx_mux_fck_data
,
2826 .gate
= &sgx_gate_fck_data
,
2829 static struct ti_clk sgx_fck
= {
2831 .type
= TI_CLK_COMPOSITE
,
2832 .data
= &sgx_fck_data
,
2835 static struct ti_clk_gate mcspi1_fck_data
= {
2836 .parent
= "core_48m_fck",
2839 .module
= TI_CLKM_CM
,
2843 static struct ti_clk mcspi1_fck
= {
2844 .name
= "mcspi1_fck",
2845 .clkdm_name
= "core_l4_clkdm",
2846 .type
= TI_CLK_GATE
,
2847 .data
= &mcspi1_fck_data
,
2850 static struct ti_clk_gate mmchs2_fck_data
= {
2851 .parent
= "core_96m_fck",
2854 .module
= TI_CLKM_CM
,
2858 static struct ti_clk mmchs2_fck
= {
2859 .name
= "mmchs2_fck",
2860 .clkdm_name
= "core_l4_clkdm",
2861 .type
= TI_CLK_GATE
,
2862 .data
= &mmchs2_fck_data
,
2865 static struct ti_clk_gate mcspi2_fck_data
= {
2866 .parent
= "core_48m_fck",
2869 .module
= TI_CLKM_CM
,
2873 static struct ti_clk mcspi2_fck
= {
2874 .name
= "mcspi2_fck",
2875 .clkdm_name
= "core_l4_clkdm",
2876 .type
= TI_CLK_GATE
,
2877 .data
= &mcspi2_fck_data
,
2880 static struct ti_clk_gate vpfe_fck_data
= {
2881 .parent
= "pclk_ck",
2884 .module
= TI_CLKM_SCRM
,
2887 static struct ti_clk vpfe_fck
= {
2889 .type
= TI_CLK_GATE
,
2890 .data
= &vpfe_fck_data
,
2893 static struct ti_clk_gate gpt4_gate_fck_data
= {
2897 .module
= TI_CLKM_CM
,
2900 static struct ti_clk_gate mcbsp1_gate_fck_data
= {
2901 .parent
= "mcbsp_clks",
2904 .module
= TI_CLKM_CM
,
2907 static struct ti_clk_gate gpt5_gate_fck_data
= {
2911 .module
= TI_CLKM_CM
,
2914 static const char *gpt5_mux_fck_parents
[] = {
2919 static struct ti_clk_mux gpt5_mux_fck_data
= {
2921 .num_parents
= ARRAY_SIZE(gpt5_mux_fck_parents
),
2923 .module
= TI_CLKM_CM
,
2924 .parents
= gpt5_mux_fck_parents
,
2927 static struct ti_clk_composite gpt5_fck_data
= {
2928 .mux
= &gpt5_mux_fck_data
,
2929 .gate
= &gpt5_gate_fck_data
,
2932 static struct ti_clk gpt5_fck
= {
2934 .type
= TI_CLK_COMPOSITE
,
2935 .data
= &gpt5_fck_data
,
2938 static struct ti_clk_gate ts_fck_data
= {
2939 .parent
= "omap_32k_fck",
2942 .module
= TI_CLKM_CM
,
2945 static struct ti_clk ts_fck
= {
2947 .clkdm_name
= "core_l4_clkdm",
2948 .type
= TI_CLK_GATE
,
2949 .data
= &ts_fck_data
,
2952 static struct ti_clk_fixed_factor wdt1_fck_data
= {
2953 .parent
= "secure_32k_fck",
2958 static struct ti_clk wdt1_fck
= {
2960 .type
= TI_CLK_FIXED_FACTOR
,
2961 .data
= &wdt1_fck_data
,
2964 static struct ti_clk_gate dpll4_m6x2_ck_omap36xx_data
= {
2965 .parent
= "dpll4_m6x2_mul_ck",
2968 .module
= TI_CLKM_CM
,
2969 .flags
= CLKF_HSDIV
| CLKF_SET_BIT_TO_DISABLE
,
2972 static struct ti_clk dpll4_m6x2_ck_omap36xx
= {
2973 .name
= "dpll4_m6x2_ck",
2974 .type
= TI_CLK_GATE
,
2975 .data
= &dpll4_m6x2_ck_omap36xx_data
,
2976 .patch
= &dpll4_m6x2_ck
,
2979 static const char *gpt4_mux_fck_parents
[] = {
2984 static struct ti_clk_mux gpt4_mux_fck_data
= {
2986 .num_parents
= ARRAY_SIZE(gpt4_mux_fck_parents
),
2988 .module
= TI_CLKM_CM
,
2989 .parents
= gpt4_mux_fck_parents
,
2992 static struct ti_clk_gate usbhost_ick_data
= {
2996 .module
= TI_CLKM_CM
,
2997 .flags
= CLKF_DSS
| CLKF_OMAP3
| CLKF_INTERFACE
,
3000 static struct ti_clk usbhost_ick
= {
3001 .name
= "usbhost_ick",
3002 .clkdm_name
= "usbhost_clkdm",
3003 .type
= TI_CLK_GATE
,
3004 .data
= &usbhost_ick_data
,
3007 static struct ti_clk_gate mcbsp2_ick_data
= {
3008 .parent
= "per_l4_ick",
3011 .module
= TI_CLKM_CM
,
3012 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
3015 static struct ti_clk mcbsp2_ick
= {
3016 .name
= "mcbsp2_ick",
3017 .clkdm_name
= "per_clkdm",
3018 .type
= TI_CLK_GATE
,
3019 .data
= &mcbsp2_ick_data
,
3022 static struct ti_clk_gate omapctrl_ick_data
= {
3023 .parent
= "core_l4_ick",
3026 .module
= TI_CLKM_CM
,
3027 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
3030 static struct ti_clk omapctrl_ick
= {
3031 .name
= "omapctrl_ick",
3032 .clkdm_name
= "core_l4_clkdm",
3033 .type
= TI_CLK_GATE
,
3034 .data
= &omapctrl_ick_data
,
3037 static struct ti_clk_fixed_factor omap_96m_d4_fck_data
= {
3038 .parent
= "omap_96m_fck",
3043 static struct ti_clk omap_96m_d4_fck
= {
3044 .name
= "omap_96m_d4_fck",
3045 .type
= TI_CLK_FIXED_FACTOR
,
3046 .data
= &omap_96m_d4_fck_data
,
3049 static struct ti_clk_gate gpt6_ick_data
= {
3050 .parent
= "per_l4_ick",
3053 .module
= TI_CLKM_CM
,
3054 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
3057 static struct ti_clk gpt6_ick
= {
3059 .clkdm_name
= "per_clkdm",
3060 .type
= TI_CLK_GATE
,
3061 .data
= &gpt6_ick_data
,
3064 static struct ti_clk_gate dpll3_m3x2_ck_omap36xx_data
= {
3065 .parent
= "dpll3_m3x2_mul_ck",
3068 .module
= TI_CLKM_CM
,
3069 .flags
= CLKF_HSDIV
| CLKF_SET_BIT_TO_DISABLE
,
3072 static struct ti_clk dpll3_m3x2_ck_omap36xx
= {
3073 .name
= "dpll3_m3x2_ck",
3074 .type
= TI_CLK_GATE
,
3075 .data
= &dpll3_m3x2_ck_omap36xx_data
,
3076 .patch
= &dpll3_m3x2_ck
,
3079 static struct ti_clk_gate i2c3_ick_data
= {
3080 .parent
= "core_l4_ick",
3083 .module
= TI_CLKM_CM
,
3084 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
3087 static struct ti_clk i2c3_ick
= {
3089 .clkdm_name
= "core_l4_clkdm",
3090 .type
= TI_CLK_GATE
,
3091 .data
= &i2c3_ick_data
,
3094 static struct ti_clk_gate gpio6_ick_data
= {
3095 .parent
= "per_l4_ick",
3098 .module
= TI_CLKM_CM
,
3099 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
3102 static struct ti_clk gpio6_ick
= {
3103 .name
= "gpio6_ick",
3104 .clkdm_name
= "per_clkdm",
3105 .type
= TI_CLK_GATE
,
3106 .data
= &gpio6_ick_data
,
3109 static struct ti_clk_gate mspro_ick_data
= {
3110 .parent
= "core_l4_ick",
3113 .module
= TI_CLKM_CM
,
3114 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
3117 static struct ti_clk mspro_ick
= {
3118 .name
= "mspro_ick",
3119 .clkdm_name
= "core_l4_clkdm",
3120 .type
= TI_CLK_GATE
,
3121 .data
= &mspro_ick_data
,
3124 static struct ti_clk_composite mcbsp1_fck_data
= {
3125 .mux
= &mcbsp1_mux_fck_data
,
3126 .gate
= &mcbsp1_gate_fck_data
,
3129 static struct ti_clk mcbsp1_fck
= {
3130 .name
= "mcbsp1_fck",
3131 .type
= TI_CLK_COMPOSITE
,
3132 .data
= &mcbsp1_fck_data
,
3135 static struct ti_clk_gate gpt3_gate_fck_data
= {
3139 .module
= TI_CLKM_CM
,
3142 static struct ti_clk_fixed rmii_ck_data
= {
3143 .frequency
= 50000000,
3146 static struct ti_clk rmii_ck
= {
3148 .type
= TI_CLK_FIXED
,
3149 .data
= &rmii_ck_data
,
3152 static struct ti_clk_gate gpt6_gate_fck_data
= {
3156 .module
= TI_CLKM_CM
,
3159 static struct ti_clk_composite gpt6_fck_data
= {
3160 .mux
= &gpt6_mux_fck_data
,
3161 .gate
= &gpt6_gate_fck_data
,
3164 static struct ti_clk gpt6_fck
= {
3166 .type
= TI_CLK_COMPOSITE
,
3167 .data
= &gpt6_fck_data
,
3170 static struct ti_clk_fixed_factor dpll5_m2_d4_ck_data
= {
3171 .parent
= "dpll5_m2_ck",
3176 static struct ti_clk dpll5_m2_d4_ck
= {
3177 .name
= "dpll5_m2_d4_ck",
3178 .type
= TI_CLK_FIXED_FACTOR
,
3179 .data
= &dpll5_m2_d4_ck_data
,
3182 static struct ti_clk_fixed_factor sys_d2_ck_data
= {
3188 static struct ti_clk sys_d2_ck
= {
3189 .name
= "sys_d2_ck",
3190 .type
= TI_CLK_FIXED_FACTOR
,
3191 .data
= &sys_d2_ck_data
,
3194 static struct ti_clk_fixed_factor omap_96m_d2_fck_data
= {
3195 .parent
= "omap_96m_fck",
3200 static struct ti_clk omap_96m_d2_fck
= {
3201 .name
= "omap_96m_d2_fck",
3202 .type
= TI_CLK_FIXED_FACTOR
,
3203 .data
= &omap_96m_d2_fck_data
,
3206 static struct ti_clk_fixed_factor dpll5_m2_d8_ck_data
= {
3207 .parent
= "dpll5_m2_ck",
3212 static struct ti_clk dpll5_m2_d8_ck
= {
3213 .name
= "dpll5_m2_d8_ck",
3214 .type
= TI_CLK_FIXED_FACTOR
,
3215 .data
= &dpll5_m2_d8_ck_data
,
3218 static struct ti_clk_fixed_factor dpll5_m2_d16_ck_data
= {
3219 .parent
= "dpll5_m2_ck",
3224 static struct ti_clk dpll5_m2_d16_ck
= {
3225 .name
= "dpll5_m2_d16_ck",
3226 .type
= TI_CLK_FIXED_FACTOR
,
3227 .data
= &dpll5_m2_d16_ck_data
,
3230 static const char *usim_mux_fck_parents
[] = {
3243 static struct ti_clk_mux usim_mux_fck_data
= {
3245 .num_parents
= ARRAY_SIZE(usim_mux_fck_parents
),
3247 .module
= TI_CLKM_CM
,
3248 .parents
= usim_mux_fck_parents
,
3249 .flags
= CLKF_INDEX_STARTS_AT_ONE
,
3252 static struct ti_clk_composite usim_fck_data
= {
3253 .mux
= &usim_mux_fck_data
,
3254 .gate
= &usim_gate_fck_data
,
3257 static struct ti_clk usim_fck
= {
3259 .type
= TI_CLK_COMPOSITE
,
3260 .data
= &usim_fck_data
,
3263 static int ssi_ssr_div_fck_3430es2_divs
[] = {
3275 static struct ti_clk_divider ssi_ssr_div_fck_3430es2_data
= {
3276 .num_dividers
= ARRAY_SIZE(ssi_ssr_div_fck_3430es2_divs
),
3277 .parent
= "corex2_fck",
3279 .dividers
= ssi_ssr_div_fck_3430es2_divs
,
3281 .module
= TI_CLKM_CM
,
3284 static struct ti_clk_composite ssi_ssr_fck_3430es2_data
= {
3285 .gate
= &ssi_ssr_gate_fck_3430es2_data
,
3286 .divider
= &ssi_ssr_div_fck_3430es2_data
,
3289 static struct ti_clk ssi_ssr_fck_3430es2
= {
3290 .name
= "ssi_ssr_fck",
3291 .type
= TI_CLK_COMPOSITE
,
3292 .data
= &ssi_ssr_fck_3430es2_data
,
3295 static struct ti_clk_gate dss1_alwon_fck_3430es1_data
= {
3296 .parent
= "dpll4_m4x2_ck",
3299 .module
= TI_CLKM_CM
,
3300 .flags
= CLKF_SET_RATE_PARENT
,
3303 static struct ti_clk dss1_alwon_fck_3430es1
= {
3304 .name
= "dss1_alwon_fck",
3305 .clkdm_name
= "dss_clkdm",
3306 .type
= TI_CLK_GATE
,
3307 .data
= &dss1_alwon_fck_3430es1_data
,
3310 static struct ti_clk_gate gpt3_ick_data
= {
3311 .parent
= "per_l4_ick",
3314 .module
= TI_CLKM_CM
,
3315 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
3318 static struct ti_clk gpt3_ick
= {
3320 .clkdm_name
= "per_clkdm",
3321 .type
= TI_CLK_GATE
,
3322 .data
= &gpt3_ick_data
,
3325 static struct ti_clk_fixed_factor omap_12m_fck_data
= {
3326 .parent
= "omap_48m_fck",
3331 static struct ti_clk omap_12m_fck
= {
3332 .name
= "omap_12m_fck",
3333 .type
= TI_CLK_FIXED_FACTOR
,
3334 .data
= &omap_12m_fck_data
,
3337 static struct ti_clk_fixed_factor core_12m_fck_data
= {
3338 .parent
= "omap_12m_fck",
3343 static struct ti_clk core_12m_fck
= {
3344 .name
= "core_12m_fck",
3345 .type
= TI_CLK_FIXED_FACTOR
,
3346 .data
= &core_12m_fck_data
,
3349 static struct ti_clk_gate hdq_fck_data
= {
3350 .parent
= "core_12m_fck",
3353 .module
= TI_CLKM_CM
,
3357 static struct ti_clk hdq_fck
= {
3359 .clkdm_name
= "core_l4_clkdm",
3360 .type
= TI_CLK_GATE
,
3361 .data
= &hdq_fck_data
,
3364 static struct ti_clk_gate usbtll_fck_data
= {
3365 .parent
= "dpll5_m2_ck",
3368 .module
= TI_CLKM_CM
,
3372 static struct ti_clk usbtll_fck
= {
3373 .name
= "usbtll_fck",
3374 .clkdm_name
= "core_l4_clkdm",
3375 .type
= TI_CLK_GATE
,
3376 .data
= &usbtll_fck_data
,
3379 static struct ti_clk_gate hsotgusb_fck_am35xx_data
= {
3383 .module
= TI_CLKM_SCRM
,
3386 static struct ti_clk hsotgusb_fck_am35xx
= {
3387 .name
= "hsotgusb_fck_am35xx",
3388 .clkdm_name
= "core_l3_clkdm",
3389 .type
= TI_CLK_GATE
,
3390 .data
= &hsotgusb_fck_am35xx_data
,
3393 static struct ti_clk_gate hsotgusb_ick_3430es2_data
= {
3394 .parent
= "core_l3_ick",
3397 .module
= TI_CLKM_CM
,
3398 .flags
= CLKF_HSOTGUSB
| CLKF_OMAP3
| CLKF_INTERFACE
,
3401 static struct ti_clk hsotgusb_ick_3430es2
= {
3402 .name
= "hsotgusb_ick_3430es2",
3403 .clkdm_name
= "core_l3_clkdm",
3404 .type
= TI_CLK_GATE
,
3405 .data
= &hsotgusb_ick_3430es2_data
,
3408 static struct ti_clk_gate gfx_l3_ck_data
= {
3412 .module
= TI_CLKM_CM
,
3416 static struct ti_clk gfx_l3_ck
= {
3417 .name
= "gfx_l3_ck",
3418 .clkdm_name
= "gfx_3430es1_clkdm",
3419 .type
= TI_CLK_GATE
,
3420 .data
= &gfx_l3_ck_data
,
3423 static struct ti_clk_fixed_factor gfx_l3_ick_data
= {
3424 .parent
= "gfx_l3_ck",
3429 static struct ti_clk gfx_l3_ick
= {
3430 .name
= "gfx_l3_ick",
3431 .type
= TI_CLK_FIXED_FACTOR
,
3432 .data
= &gfx_l3_ick_data
,
3435 static struct ti_clk_gate mcbsp1_ick_data
= {
3436 .parent
= "core_l4_ick",
3439 .module
= TI_CLKM_CM
,
3440 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
3443 static struct ti_clk mcbsp1_ick
= {
3444 .name
= "mcbsp1_ick",
3445 .clkdm_name
= "core_l4_clkdm",
3446 .type
= TI_CLK_GATE
,
3447 .data
= &mcbsp1_ick_data
,
3450 static struct ti_clk_fixed_factor gpt12_fck_data
= {
3451 .parent
= "secure_32k_fck",
3456 static struct ti_clk gpt12_fck
= {
3457 .name
= "gpt12_fck",
3458 .type
= TI_CLK_FIXED_FACTOR
,
3459 .data
= &gpt12_fck_data
,
3462 static struct ti_clk_gate gfx_cg2_ck_data
= {
3463 .parent
= "gfx_l3_fck",
3466 .module
= TI_CLKM_CM
,
3470 static struct ti_clk gfx_cg2_ck
= {
3471 .name
= "gfx_cg2_ck",
3472 .clkdm_name
= "gfx_3430es1_clkdm",
3473 .type
= TI_CLK_GATE
,
3474 .data
= &gfx_cg2_ck_data
,
3477 static struct ti_clk_gate i2c2_ick_data
= {
3478 .parent
= "core_l4_ick",
3481 .module
= TI_CLKM_CM
,
3482 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
3485 static struct ti_clk i2c2_ick
= {
3487 .clkdm_name
= "core_l4_clkdm",
3488 .type
= TI_CLK_GATE
,
3489 .data
= &i2c2_ick_data
,
3492 static struct ti_clk_gate gpio4_dbck_data
= {
3493 .parent
= "per_32k_alwon_fck",
3496 .module
= TI_CLKM_CM
,
3499 static struct ti_clk gpio4_dbck
= {
3500 .name
= "gpio4_dbck",
3501 .clkdm_name
= "per_clkdm",
3502 .type
= TI_CLK_GATE
,
3503 .data
= &gpio4_dbck_data
,
3506 static struct ti_clk_gate i2c3_fck_data
= {
3507 .parent
= "core_96m_fck",
3510 .module
= TI_CLKM_CM
,
3514 static struct ti_clk i2c3_fck
= {
3516 .clkdm_name
= "core_l4_clkdm",
3517 .type
= TI_CLK_GATE
,
3518 .data
= &i2c3_fck_data
,
3521 static struct ti_clk_composite gpt3_fck_data
= {
3522 .mux
= &gpt3_mux_fck_data
,
3523 .gate
= &gpt3_gate_fck_data
,
3526 static struct ti_clk gpt3_fck
= {
3528 .type
= TI_CLK_COMPOSITE
,
3529 .data
= &gpt3_fck_data
,
3532 static struct ti_clk_gate i2c1_ick_data
= {
3533 .parent
= "core_l4_ick",
3536 .module
= TI_CLKM_CM
,
3537 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
3540 static struct ti_clk i2c1_ick
= {
3542 .clkdm_name
= "core_l4_clkdm",
3543 .type
= TI_CLK_GATE
,
3544 .data
= &i2c1_ick_data
,
3547 static struct ti_clk_gate omap_32ksync_ick_data
= {
3548 .parent
= "wkup_l4_ick",
3551 .module
= TI_CLKM_CM
,
3552 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
3555 static struct ti_clk omap_32ksync_ick
= {
3556 .name
= "omap_32ksync_ick",
3557 .clkdm_name
= "wkup_clkdm",
3558 .type
= TI_CLK_GATE
,
3559 .data
= &omap_32ksync_ick_data
,
3562 static struct ti_clk_gate aes2_ick_data
= {
3563 .parent
= "core_l4_ick",
3566 .module
= TI_CLKM_CM
,
3567 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
3570 static struct ti_clk aes2_ick
= {
3572 .clkdm_name
= "core_l4_clkdm",
3573 .type
= TI_CLK_GATE
,
3574 .data
= &aes2_ick_data
,
3577 static const char *gpt8_mux_fck_parents
[] = {
3582 static struct ti_clk_mux gpt8_mux_fck_data
= {
3584 .num_parents
= ARRAY_SIZE(gpt8_mux_fck_parents
),
3586 .module
= TI_CLKM_CM
,
3587 .parents
= gpt8_mux_fck_parents
,
3590 static struct ti_clk_composite gpt8_fck_data
= {
3591 .mux
= &gpt8_mux_fck_data
,
3592 .gate
= &gpt8_gate_fck_data
,
3595 static struct ti_clk gpt8_fck
= {
3597 .type
= TI_CLK_COMPOSITE
,
3598 .data
= &gpt8_fck_data
,
3601 static struct ti_clk_gate mcbsp4_gate_fck_data
= {
3602 .parent
= "mcbsp_clks",
3605 .module
= TI_CLKM_CM
,
3608 static struct ti_clk_composite mcbsp4_fck_data
= {
3609 .mux
= &mcbsp4_mux_fck_data
,
3610 .gate
= &mcbsp4_gate_fck_data
,
3613 static struct ti_clk mcbsp4_fck
= {
3614 .name
= "mcbsp4_fck",
3615 .type
= TI_CLK_COMPOSITE
,
3616 .data
= &mcbsp4_fck_data
,
3619 static struct ti_clk_gate gpio2_dbck_data
= {
3620 .parent
= "per_32k_alwon_fck",
3623 .module
= TI_CLKM_CM
,
3626 static struct ti_clk gpio2_dbck
= {
3627 .name
= "gpio2_dbck",
3628 .clkdm_name
= "per_clkdm",
3629 .type
= TI_CLK_GATE
,
3630 .data
= &gpio2_dbck_data
,
3633 static struct ti_clk_gate usbtll_ick_data
= {
3634 .parent
= "core_l4_ick",
3637 .module
= TI_CLKM_CM
,
3638 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
3641 static struct ti_clk usbtll_ick
= {
3642 .name
= "usbtll_ick",
3643 .clkdm_name
= "core_l4_clkdm",
3644 .type
= TI_CLK_GATE
,
3645 .data
= &usbtll_ick_data
,
3648 static struct ti_clk_gate mcspi4_ick_data
= {
3649 .parent
= "core_l4_ick",
3652 .module
= TI_CLKM_CM
,
3653 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
3656 static struct ti_clk mcspi4_ick
= {
3657 .name
= "mcspi4_ick",
3658 .clkdm_name
= "core_l4_clkdm",
3659 .type
= TI_CLK_GATE
,
3660 .data
= &mcspi4_ick_data
,
3663 static struct ti_clk_gate dss_96m_fck_data
= {
3664 .parent
= "omap_96m_fck",
3667 .module
= TI_CLKM_CM
,
3670 static struct ti_clk dss_96m_fck
= {
3671 .name
= "dss_96m_fck",
3672 .clkdm_name
= "dss_clkdm",
3673 .type
= TI_CLK_GATE
,
3674 .data
= &dss_96m_fck_data
,
3677 static struct ti_clk_divider rm_ick_data
= {
3682 .module
= TI_CLKM_CM
,
3683 .flags
= CLKF_INDEX_STARTS_AT_ONE
,
3686 static struct ti_clk rm_ick
= {
3688 .type
= TI_CLK_DIVIDER
,
3689 .data
= &rm_ick_data
,
3692 static struct ti_clk_gate hdq_ick_data
= {
3693 .parent
= "core_l4_ick",
3696 .module
= TI_CLKM_CM
,
3697 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
3700 static struct ti_clk hdq_ick
= {
3702 .clkdm_name
= "core_l4_clkdm",
3703 .type
= TI_CLK_GATE
,
3704 .data
= &hdq_ick_data
,
3707 static struct ti_clk_fixed_factor dpll3_x2_ck_data
= {
3708 .parent
= "dpll3_ck",
3713 static struct ti_clk dpll3_x2_ck
= {
3714 .name
= "dpll3_x2_ck",
3715 .type
= TI_CLK_FIXED_FACTOR
,
3716 .data
= &dpll3_x2_ck_data
,
3719 static struct ti_clk_gate mad2d_ick_data
= {
3723 .module
= TI_CLKM_CM
,
3724 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
3727 static struct ti_clk mad2d_ick
= {
3728 .name
= "mad2d_ick",
3729 .clkdm_name
= "d2d_clkdm",
3730 .type
= TI_CLK_GATE
,
3731 .data
= &mad2d_ick_data
,
3734 static struct ti_clk_gate fshostusb_fck_data
= {
3735 .parent
= "core_48m_fck",
3738 .module
= TI_CLKM_CM
,
3742 static struct ti_clk fshostusb_fck
= {
3743 .name
= "fshostusb_fck",
3744 .clkdm_name
= "core_l4_clkdm",
3745 .type
= TI_CLK_GATE
,
3746 .data
= &fshostusb_fck_data
,
3749 static struct ti_clk_gate sr1_fck_data
= {
3753 .module
= TI_CLKM_CM
,
3757 static struct ti_clk sr1_fck
= {
3759 .clkdm_name
= "wkup_clkdm",
3760 .type
= TI_CLK_GATE
,
3761 .data
= &sr1_fck_data
,
3764 static struct ti_clk_gate des2_ick_data
= {
3765 .parent
= "core_l4_ick",
3768 .module
= TI_CLKM_CM
,
3769 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
3772 static struct ti_clk des2_ick
= {
3774 .clkdm_name
= "core_l4_clkdm",
3775 .type
= TI_CLK_GATE
,
3776 .data
= &des2_ick_data
,
3779 static struct ti_clk_gate sdrc_ick_data
= {
3780 .parent
= "core_l3_ick",
3783 .module
= TI_CLKM_CM
,
3787 static struct ti_clk sdrc_ick
= {
3789 .clkdm_name
= "core_l3_clkdm",
3790 .type
= TI_CLK_GATE
,
3791 .data
= &sdrc_ick_data
,
3794 static struct ti_clk_composite gpt4_fck_data
= {
3795 .mux
= &gpt4_mux_fck_data
,
3796 .gate
= &gpt4_gate_fck_data
,
3799 static struct ti_clk gpt4_fck
= {
3801 .type
= TI_CLK_COMPOSITE
,
3802 .data
= &gpt4_fck_data
,
3805 static struct ti_clk_gate dpll4_m3x2_ck_omap36xx_data
= {
3806 .parent
= "dpll4_m3x2_mul_ck",
3809 .module
= TI_CLKM_CM
,
3810 .flags
= CLKF_HSDIV
| CLKF_SET_BIT_TO_DISABLE
,
3813 static struct ti_clk dpll4_m3x2_ck_omap36xx
= {
3814 .name
= "dpll4_m3x2_ck",
3815 .type
= TI_CLK_GATE
,
3816 .data
= &dpll4_m3x2_ck_omap36xx_data
,
3817 .patch
= &dpll4_m3x2_ck
,
3820 static struct ti_clk_gate cpefuse_fck_data
= {
3824 .module
= TI_CLKM_CM
,
3827 static struct ti_clk cpefuse_fck
= {
3828 .name
= "cpefuse_fck",
3829 .clkdm_name
= "core_l4_clkdm",
3830 .type
= TI_CLK_GATE
,
3831 .data
= &cpefuse_fck_data
,
3834 static struct ti_clk_gate mcspi3_ick_data
= {
3835 .parent
= "core_l4_ick",
3838 .module
= TI_CLKM_CM
,
3839 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
3842 static struct ti_clk mcspi3_ick
= {
3843 .name
= "mcspi3_ick",
3844 .clkdm_name
= "core_l4_clkdm",
3845 .type
= TI_CLK_GATE
,
3846 .data
= &mcspi3_ick_data
,
3849 static struct ti_clk_fixed_factor ssi_sst_fck_3430es2_data
= {
3850 .parent
= "ssi_ssr_fck",
3855 static struct ti_clk ssi_sst_fck_3430es2
= {
3856 .name
= "ssi_sst_fck",
3857 .type
= TI_CLK_FIXED_FACTOR
,
3858 .data
= &ssi_sst_fck_3430es2_data
,
3861 static struct ti_clk_gate gpio1_dbck_data
= {
3862 .parent
= "wkup_32k_fck",
3865 .module
= TI_CLKM_CM
,
3868 static struct ti_clk gpio1_dbck
= {
3869 .name
= "gpio1_dbck",
3870 .clkdm_name
= "wkup_clkdm",
3871 .type
= TI_CLK_GATE
,
3872 .data
= &gpio1_dbck_data
,
3875 static struct ti_clk_gate gpt4_ick_data
= {
3876 .parent
= "per_l4_ick",
3879 .module
= TI_CLKM_CM
,
3880 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
3883 static struct ti_clk gpt4_ick
= {
3885 .clkdm_name
= "per_clkdm",
3886 .type
= TI_CLK_GATE
,
3887 .data
= &gpt4_ick_data
,
3890 static struct ti_clk_gate gpt2_ick_data
= {
3891 .parent
= "per_l4_ick",
3894 .module
= TI_CLKM_CM
,
3895 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
3898 static struct ti_clk gpt2_ick
= {
3900 .clkdm_name
= "per_clkdm",
3901 .type
= TI_CLK_GATE
,
3902 .data
= &gpt2_ick_data
,
3905 static struct ti_clk_gate mmchs1_fck_data
= {
3906 .parent
= "core_96m_fck",
3909 .module
= TI_CLKM_CM
,
3913 static struct ti_clk mmchs1_fck
= {
3914 .name
= "mmchs1_fck",
3915 .clkdm_name
= "core_l4_clkdm",
3916 .type
= TI_CLK_GATE
,
3917 .data
= &mmchs1_fck_data
,
3920 static struct ti_clk_fixed dummy_apb_pclk_data
= {
3924 static struct ti_clk dummy_apb_pclk
= {
3925 .name
= "dummy_apb_pclk",
3926 .type
= TI_CLK_FIXED
,
3927 .data
= &dummy_apb_pclk_data
,
3930 static struct ti_clk_gate gpio6_dbck_data
= {
3931 .parent
= "per_32k_alwon_fck",
3934 .module
= TI_CLKM_CM
,
3937 static struct ti_clk gpio6_dbck
= {
3938 .name
= "gpio6_dbck",
3939 .clkdm_name
= "per_clkdm",
3940 .type
= TI_CLK_GATE
,
3941 .data
= &gpio6_dbck_data
,
3944 static struct ti_clk_gate uart2_ick_data
= {
3945 .parent
= "core_l4_ick",
3948 .module
= TI_CLKM_CM
,
3949 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
3952 static struct ti_clk uart2_ick
= {
3953 .name
= "uart2_ick",
3954 .clkdm_name
= "core_l4_clkdm",
3955 .type
= TI_CLK_GATE
,
3956 .data
= &uart2_ick_data
,
3959 static struct ti_clk_fixed_factor dpll4_x2_ck_data
= {
3960 .parent
= "dpll4_ck",
3965 static struct ti_clk dpll4_x2_ck
= {
3966 .name
= "dpll4_x2_ck",
3967 .type
= TI_CLK_FIXED_FACTOR
,
3968 .data
= &dpll4_x2_ck_data
,
3971 static struct ti_clk_gate gpt7_ick_data
= {
3972 .parent
= "per_l4_ick",
3975 .module
= TI_CLKM_CM
,
3976 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
3979 static struct ti_clk gpt7_ick
= {
3981 .clkdm_name
= "per_clkdm",
3982 .type
= TI_CLK_GATE
,
3983 .data
= &gpt7_ick_data
,
3986 static struct ti_clk_gate dss_tv_fck_data
= {
3987 .parent
= "omap_54m_fck",
3990 .module
= TI_CLKM_CM
,
3993 static struct ti_clk dss_tv_fck
= {
3994 .name
= "dss_tv_fck",
3995 .clkdm_name
= "dss_clkdm",
3996 .type
= TI_CLK_GATE
,
3997 .data
= &dss_tv_fck_data
,
4000 static struct ti_clk_gate mcbsp5_ick_data
= {
4001 .parent
= "core_l4_ick",
4004 .module
= TI_CLKM_CM
,
4005 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
4008 static struct ti_clk mcbsp5_ick
= {
4009 .name
= "mcbsp5_ick",
4010 .clkdm_name
= "core_l4_clkdm",
4011 .type
= TI_CLK_GATE
,
4012 .data
= &mcbsp5_ick_data
,
4015 static struct ti_clk_gate mcspi1_ick_data
= {
4016 .parent
= "core_l4_ick",
4019 .module
= TI_CLKM_CM
,
4020 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
4023 static struct ti_clk mcspi1_ick
= {
4024 .name
= "mcspi1_ick",
4025 .clkdm_name
= "core_l4_clkdm",
4026 .type
= TI_CLK_GATE
,
4027 .data
= &mcspi1_ick_data
,
4030 static struct ti_clk_gate d2d_26m_fck_data
= {
4034 .module
= TI_CLKM_CM
,
4038 static struct ti_clk d2d_26m_fck
= {
4039 .name
= "d2d_26m_fck",
4040 .clkdm_name
= "d2d_clkdm",
4041 .type
= TI_CLK_GATE
,
4042 .data
= &d2d_26m_fck_data
,
4045 static struct ti_clk_gate wdt3_ick_data
= {
4046 .parent
= "per_l4_ick",
4049 .module
= TI_CLKM_CM
,
4050 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
4053 static struct ti_clk wdt3_ick
= {
4055 .clkdm_name
= "per_clkdm",
4056 .type
= TI_CLK_GATE
,
4057 .data
= &wdt3_ick_data
,
4060 static struct ti_clk_divider pclkx2_fck_data
= {
4061 .parent
= "emu_src_ck",
4065 .module
= TI_CLKM_CM
,
4066 .flags
= CLKF_INDEX_STARTS_AT_ONE
,
4069 static struct ti_clk pclkx2_fck
= {
4070 .name
= "pclkx2_fck",
4071 .type
= TI_CLK_DIVIDER
,
4072 .data
= &pclkx2_fck_data
,
4075 static struct ti_clk_gate sha12_ick_data
= {
4076 .parent
= "core_l4_ick",
4079 .module
= TI_CLKM_CM
,
4080 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
4083 static struct ti_clk sha12_ick
= {
4084 .name
= "sha12_ick",
4085 .clkdm_name
= "core_l4_clkdm",
4086 .type
= TI_CLK_GATE
,
4087 .data
= &sha12_ick_data
,
4090 static struct ti_clk_gate emac_fck_data
= {
4091 .parent
= "rmii_ck",
4094 .module
= TI_CLKM_SCRM
,
4097 static struct ti_clk emac_fck
= {
4099 .type
= TI_CLK_GATE
,
4100 .data
= &emac_fck_data
,
4103 static struct ti_clk_composite gpt10_fck_data
= {
4104 .mux
= &gpt10_mux_fck_data
,
4105 .gate
= &gpt10_gate_fck_data
,
4108 static struct ti_clk gpt10_fck
= {
4109 .name
= "gpt10_fck",
4110 .type
= TI_CLK_COMPOSITE
,
4111 .data
= &gpt10_fck_data
,
4114 static struct ti_clk_gate wdt2_fck_data
= {
4115 .parent
= "wkup_32k_fck",
4118 .module
= TI_CLKM_CM
,
4122 static struct ti_clk wdt2_fck
= {
4124 .clkdm_name
= "wkup_clkdm",
4125 .type
= TI_CLK_GATE
,
4126 .data
= &wdt2_fck_data
,
4129 static struct ti_clk_gate cam_ick_data
= {
4133 .module
= TI_CLKM_CM
,
4134 .flags
= CLKF_OMAP3
| CLKF_NO_WAIT
| CLKF_INTERFACE
,
4137 static struct ti_clk cam_ick
= {
4139 .clkdm_name
= "cam_clkdm",
4140 .type
= TI_CLK_GATE
,
4141 .data
= &cam_ick_data
,
4144 static struct ti_clk_gate ssi_ick_3430es2_data
= {
4145 .parent
= "ssi_l4_ick",
4148 .module
= TI_CLKM_CM
,
4149 .flags
= CLKF_SSI
| CLKF_OMAP3
| CLKF_INTERFACE
,
4152 static struct ti_clk ssi_ick_3430es2
= {
4154 .clkdm_name
= "core_l4_clkdm",
4155 .type
= TI_CLK_GATE
,
4156 .data
= &ssi_ick_3430es2_data
,
4159 static struct ti_clk_gate gpio4_ick_data
= {
4160 .parent
= "per_l4_ick",
4163 .module
= TI_CLKM_CM
,
4164 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
4167 static struct ti_clk gpio4_ick
= {
4168 .name
= "gpio4_ick",
4169 .clkdm_name
= "per_clkdm",
4170 .type
= TI_CLK_GATE
,
4171 .data
= &gpio4_ick_data
,
4174 static struct ti_clk_gate wdt1_ick_data
= {
4175 .parent
= "wkup_l4_ick",
4178 .module
= TI_CLKM_CM
,
4179 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
4182 static struct ti_clk wdt1_ick
= {
4184 .clkdm_name
= "wkup_clkdm",
4185 .type
= TI_CLK_GATE
,
4186 .data
= &wdt1_ick_data
,
4189 static struct ti_clk_gate rng_ick_data
= {
4190 .parent
= "security_l4_ick2",
4193 .module
= TI_CLKM_CM
,
4194 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
4197 static struct ti_clk rng_ick
= {
4199 .type
= TI_CLK_GATE
,
4200 .data
= &rng_ick_data
,
4203 static struct ti_clk_gate icr_ick_data
= {
4204 .parent
= "core_l4_ick",
4207 .module
= TI_CLKM_CM
,
4208 .flags
= CLKF_OMAP3
| CLKF_INTERFACE
,
4211 static struct ti_clk icr_ick
= {
4213 .clkdm_name
= "core_l4_clkdm",
4214 .type
= TI_CLK_GATE
,
4215 .data
= &icr_ick_data
,
4218 static struct ti_clk_gate sgx_ick_data
= {
4222 .module
= TI_CLKM_CM
,
4226 static struct ti_clk sgx_ick
= {
4228 .clkdm_name
= "sgx_clkdm",
4229 .type
= TI_CLK_GATE
,
4230 .data
= &sgx_ick_data
,
4233 static struct ti_clk_divider sys_clkout2_data
= {
4234 .parent
= "clkout2_src_ck",
4238 .module
= TI_CLKM_CM
,
4239 .flags
= CLKF_INDEX_POWER_OF_TWO
,
4242 static struct ti_clk sys_clkout2
= {
4243 .name
= "sys_clkout2",
4244 .type
= TI_CLK_DIVIDER
,
4245 .data
= &sys_clkout2_data
,
4248 static struct ti_clk_alias omap34xx_omap36xx_clks
[] = {
4249 CLK(NULL
, "security_l4_ick2", &security_l4_ick2
),
4250 CLK(NULL
, "aes1_ick", &aes1_ick
),
4251 CLK("omap_rng", "ick", &rng_ick
),
4252 CLK("omap3-rom-rng", "ick", &rng_ick
),
4253 CLK(NULL
, "sha11_ick", &sha11_ick
),
4254 CLK(NULL
, "des1_ick", &des1_ick
),
4255 CLK(NULL
, "cam_mclk", &cam_mclk
),
4256 CLK(NULL
, "cam_ick", &cam_ick
),
4257 CLK(NULL
, "csi2_96m_fck", &csi2_96m_fck
),
4258 CLK(NULL
, "security_l3_ick", &security_l3_ick
),
4259 CLK(NULL
, "pka_ick", &pka_ick
),
4260 CLK(NULL
, "icr_ick", &icr_ick
),
4261 CLK(NULL
, "des2_ick", &des2_ick
),
4262 CLK(NULL
, "mspro_ick", &mspro_ick
),
4263 CLK(NULL
, "mailboxes_ick", &mailboxes_ick
),
4264 CLK(NULL
, "ssi_l4_ick", &ssi_l4_ick
),
4265 CLK(NULL
, "sr1_fck", &sr1_fck
),
4266 CLK(NULL
, "sr2_fck", &sr2_fck
),
4267 CLK(NULL
, "sr_l4_ick", &sr_l4_ick
),
4268 CLK(NULL
, "dpll2_fck", &dpll2_fck
),
4269 CLK(NULL
, "dpll2_ck", &dpll2_ck
),
4270 CLK(NULL
, "dpll2_m2_ck", &dpll2_m2_ck
),
4271 CLK(NULL
, "iva2_ck", &iva2_ck
),
4272 CLK(NULL
, "modem_fck", &modem_fck
),
4273 CLK(NULL
, "sad2d_ick", &sad2d_ick
),
4274 CLK(NULL
, "mad2d_ick", &mad2d_ick
),
4275 CLK(NULL
, "mspro_fck", &mspro_fck
),
4279 static struct ti_clk_alias omap36xx_omap3430es2plus_clks
[] = {
4280 CLK(NULL
, "ssi_ssr_fck", &ssi_ssr_fck_3430es2
),
4281 CLK(NULL
, "ssi_sst_fck", &ssi_sst_fck_3430es2
),
4282 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2
),
4283 CLK(NULL
, "hsotgusb_ick", &hsotgusb_ick_3430es2
),
4284 CLK(NULL
, "ssi_ick", &ssi_ick_3430es2
),
4285 CLK(NULL
, "sys_d2_ck", &sys_d2_ck
),
4286 CLK(NULL
, "omap_96m_d2_fck", &omap_96m_d2_fck
),
4287 CLK(NULL
, "omap_96m_d4_fck", &omap_96m_d4_fck
),
4288 CLK(NULL
, "omap_96m_d8_fck", &omap_96m_d8_fck
),
4289 CLK(NULL
, "omap_96m_d10_fck", &omap_96m_d10_fck
),
4290 CLK(NULL
, "dpll5_m2_d4_ck", &dpll5_m2_d4_ck
),
4291 CLK(NULL
, "dpll5_m2_d8_ck", &dpll5_m2_d8_ck
),
4292 CLK(NULL
, "dpll5_m2_d16_ck", &dpll5_m2_d16_ck
),
4293 CLK(NULL
, "dpll5_m2_d20_ck", &dpll5_m2_d20_ck
),
4294 CLK(NULL
, "usim_fck", &usim_fck
),
4295 CLK(NULL
, "usim_ick", &usim_ick
),
4299 static struct ti_clk_alias omap3xxx_clks
[] = {
4300 CLK(NULL
, "apb_pclk", &dummy_apb_pclk
),
4301 CLK(NULL
, "omap_32k_fck", &omap_32k_fck
),
4302 CLK(NULL
, "virt_12m_ck", &virt_12m_ck
),
4303 CLK(NULL
, "virt_13m_ck", &virt_13m_ck
),
4304 CLK(NULL
, "virt_19200000_ck", &virt_19200000_ck
),
4305 CLK(NULL
, "virt_26000000_ck", &virt_26000000_ck
),
4306 CLK(NULL
, "virt_38_4m_ck", &virt_38_4m_ck
),
4307 CLK(NULL
, "virt_16_8m_ck", &virt_16_8m_ck
),
4308 CLK(NULL
, "osc_sys_ck", &osc_sys_ck
),
4309 CLK("twl", "fck", &osc_sys_ck
),
4310 CLK(NULL
, "sys_ck", &sys_ck
),
4311 CLK(NULL
, "timer_sys_ck", &sys_ck
),
4312 CLK(NULL
, "dpll4_ck", &dpll4_ck
),
4313 CLK(NULL
, "dpll4_m2_ck", &dpll4_m2_ck
),
4314 CLK(NULL
, "dpll4_m2x2_mul_ck", &dpll4_m2x2_mul_ck
),
4315 CLK(NULL
, "dpll4_m2x2_ck", &dpll4_m2x2_ck
),
4316 CLK(NULL
, "omap_96m_alwon_fck", &omap_96m_alwon_fck
),
4317 CLK(NULL
, "dpll3_ck", &dpll3_ck
),
4318 CLK(NULL
, "dpll3_m3_ck", &dpll3_m3_ck
),
4319 CLK(NULL
, "dpll3_m3x2_mul_ck", &dpll3_m3x2_mul_ck
),
4320 CLK(NULL
, "dpll3_m3x2_ck", &dpll3_m3x2_ck
),
4321 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck
),
4322 CLK(NULL
, "sys_altclk", &sys_altclk
),
4323 CLK(NULL
, "sys_clkout1", &sys_clkout1
),
4324 CLK(NULL
, "dpll3_m2_ck", &dpll3_m2_ck
),
4325 CLK(NULL
, "core_ck", &core_ck
),
4326 CLK(NULL
, "dpll1_fck", &dpll1_fck
),
4327 CLK(NULL
, "dpll1_ck", &dpll1_ck
),
4328 CLK(NULL
, "cpufreq_ck", &dpll1_ck
),
4329 CLK(NULL
, "dpll1_x2_ck", &dpll1_x2_ck
),
4330 CLK(NULL
, "dpll1_x2m2_ck", &dpll1_x2m2_ck
),
4331 CLK(NULL
, "dpll3_x2_ck", &dpll3_x2_ck
),
4332 CLK(NULL
, "dpll3_m2x2_ck", &dpll3_m2x2_ck
),
4333 CLK(NULL
, "dpll4_x2_ck", &dpll4_x2_ck
),
4334 CLK(NULL
, "cm_96m_fck", &cm_96m_fck
),
4335 CLK(NULL
, "omap_96m_fck", &omap_96m_fck
),
4336 CLK(NULL
, "dpll4_m3_ck", &dpll4_m3_ck
),
4337 CLK(NULL
, "dpll4_m3x2_mul_ck", &dpll4_m3x2_mul_ck
),
4338 CLK(NULL
, "dpll4_m3x2_ck", &dpll4_m3x2_ck
),
4339 CLK(NULL
, "omap_54m_fck", &omap_54m_fck
),
4340 CLK(NULL
, "cm_96m_d2_fck", &cm_96m_d2_fck
),
4341 CLK(NULL
, "omap_48m_fck", &omap_48m_fck
),
4342 CLK(NULL
, "omap_12m_fck", &omap_12m_fck
),
4343 CLK(NULL
, "dpll4_m4_ck", &dpll4_m4_ck
),
4344 CLK(NULL
, "dpll4_m4x2_mul_ck", &dpll4_m4x2_mul_ck
),
4345 CLK(NULL
, "dpll4_m4x2_ck", &dpll4_m4x2_ck
),
4346 CLK(NULL
, "dpll4_m5_ck", &dpll4_m5_ck
),
4347 CLK(NULL
, "dpll4_m5x2_mul_ck", &dpll4_m5x2_mul_ck
),
4348 CLK(NULL
, "dpll4_m5x2_ck", &dpll4_m5x2_ck
),
4349 CLK(NULL
, "dpll4_m6_ck", &dpll4_m6_ck
),
4350 CLK(NULL
, "dpll4_m6x2_mul_ck", &dpll4_m6x2_mul_ck
),
4351 CLK(NULL
, "dpll4_m6x2_ck", &dpll4_m6x2_ck
),
4352 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck
),
4353 CLK(NULL
, "clkout2_src_ck", &clkout2_src_ck
),
4354 CLK(NULL
, "sys_clkout2", &sys_clkout2
),
4355 CLK(NULL
, "corex2_fck", &corex2_fck
),
4356 CLK(NULL
, "mpu_ck", &mpu_ck
),
4357 CLK(NULL
, "arm_fck", &arm_fck
),
4358 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck
),
4359 CLK(NULL
, "l3_ick", &l3_ick
),
4360 CLK(NULL
, "l4_ick", &l4_ick
),
4361 CLK(NULL
, "rm_ick", &rm_ick
),
4362 CLK(NULL
, "timer_32k_ck", &omap_32k_fck
),
4363 CLK(NULL
, "gpt10_fck", &gpt10_fck
),
4364 CLK(NULL
, "gpt11_fck", &gpt11_fck
),
4365 CLK(NULL
, "core_96m_fck", &core_96m_fck
),
4366 CLK(NULL
, "mmchs2_fck", &mmchs2_fck
),
4367 CLK(NULL
, "mmchs1_fck", &mmchs1_fck
),
4368 CLK(NULL
, "i2c3_fck", &i2c3_fck
),
4369 CLK(NULL
, "i2c2_fck", &i2c2_fck
),
4370 CLK(NULL
, "i2c1_fck", &i2c1_fck
),
4371 CLK(NULL
, "core_48m_fck", &core_48m_fck
),
4372 CLK(NULL
, "mcspi4_fck", &mcspi4_fck
),
4373 CLK(NULL
, "mcspi3_fck", &mcspi3_fck
),
4374 CLK(NULL
, "mcspi2_fck", &mcspi2_fck
),
4375 CLK(NULL
, "mcspi1_fck", &mcspi1_fck
),
4376 CLK(NULL
, "uart2_fck", &uart2_fck
),
4377 CLK(NULL
, "uart1_fck", &uart1_fck
),
4378 CLK(NULL
, "core_12m_fck", &core_12m_fck
),
4379 CLK("omap_hdq.0", "fck", &hdq_fck
),
4380 CLK(NULL
, "hdq_fck", &hdq_fck
),
4381 CLK(NULL
, "core_l3_ick", &core_l3_ick
),
4382 CLK(NULL
, "sdrc_ick", &sdrc_ick
),
4383 CLK(NULL
, "gpmc_fck", &gpmc_fck
),
4384 CLK(NULL
, "core_l4_ick", &core_l4_ick
),
4385 CLK("omap_hsmmc.1", "ick", &mmchs2_ick
),
4386 CLK("omap_hsmmc.0", "ick", &mmchs1_ick
),
4387 CLK(NULL
, "mmchs2_ick", &mmchs2_ick
),
4388 CLK(NULL
, "mmchs1_ick", &mmchs1_ick
),
4389 CLK("omap_hdq.0", "ick", &hdq_ick
),
4390 CLK(NULL
, "hdq_ick", &hdq_ick
),
4391 CLK("omap2_mcspi.4", "ick", &mcspi4_ick
),
4392 CLK("omap2_mcspi.3", "ick", &mcspi3_ick
),
4393 CLK("omap2_mcspi.2", "ick", &mcspi2_ick
),
4394 CLK("omap2_mcspi.1", "ick", &mcspi1_ick
),
4395 CLK(NULL
, "mcspi4_ick", &mcspi4_ick
),
4396 CLK(NULL
, "mcspi3_ick", &mcspi3_ick
),
4397 CLK(NULL
, "mcspi2_ick", &mcspi2_ick
),
4398 CLK(NULL
, "mcspi1_ick", &mcspi1_ick
),
4399 CLK("omap_i2c.3", "ick", &i2c3_ick
),
4400 CLK("omap_i2c.2", "ick", &i2c2_ick
),
4401 CLK("omap_i2c.1", "ick", &i2c1_ick
),
4402 CLK(NULL
, "i2c3_ick", &i2c3_ick
),
4403 CLK(NULL
, "i2c2_ick", &i2c2_ick
),
4404 CLK(NULL
, "i2c1_ick", &i2c1_ick
),
4405 CLK(NULL
, "uart2_ick", &uart2_ick
),
4406 CLK(NULL
, "uart1_ick", &uart1_ick
),
4407 CLK(NULL
, "gpt11_ick", &gpt11_ick
),
4408 CLK(NULL
, "gpt10_ick", &gpt10_ick
),
4409 CLK(NULL
, "mcbsp5_ick", &mcbsp5_ick
),
4410 CLK(NULL
, "mcbsp1_ick", &mcbsp1_ick
),
4411 CLK(NULL
, "omapctrl_ick", &omapctrl_ick
),
4412 CLK(NULL
, "dss_tv_fck", &dss_tv_fck
),
4413 CLK(NULL
, "dss_96m_fck", &dss_96m_fck
),
4414 CLK(NULL
, "dss2_alwon_fck", &dss2_alwon_fck
),
4415 CLK(NULL
, "init_60m_fclk", &dummy_ck
),
4416 CLK(NULL
, "gpt1_fck", &gpt1_fck
),
4417 CLK(NULL
, "aes2_ick", &aes2_ick
),
4418 CLK(NULL
, "wkup_32k_fck", &wkup_32k_fck
),
4419 CLK(NULL
, "gpio1_dbck", &gpio1_dbck
),
4420 CLK(NULL
, "sha12_ick", &sha12_ick
),
4421 CLK(NULL
, "wdt2_fck", &wdt2_fck
),
4422 CLK(NULL
, "wkup_l4_ick", &wkup_l4_ick
),
4423 CLK("omap_wdt", "ick", &wdt2_ick
),
4424 CLK(NULL
, "wdt2_ick", &wdt2_ick
),
4425 CLK(NULL
, "wdt1_ick", &wdt1_ick
),
4426 CLK(NULL
, "gpio1_ick", &gpio1_ick
),
4427 CLK(NULL
, "omap_32ksync_ick", &omap_32ksync_ick
),
4428 CLK(NULL
, "gpt12_ick", &gpt12_ick
),
4429 CLK(NULL
, "gpt1_ick", &gpt1_ick
),
4430 CLK(NULL
, "per_96m_fck", &per_96m_fck
),
4431 CLK(NULL
, "per_48m_fck", &per_48m_fck
),
4432 CLK(NULL
, "uart3_fck", &uart3_fck
),
4433 CLK(NULL
, "gpt2_fck", &gpt2_fck
),
4434 CLK(NULL
, "gpt3_fck", &gpt3_fck
),
4435 CLK(NULL
, "gpt4_fck", &gpt4_fck
),
4436 CLK(NULL
, "gpt5_fck", &gpt5_fck
),
4437 CLK(NULL
, "gpt6_fck", &gpt6_fck
),
4438 CLK(NULL
, "gpt7_fck", &gpt7_fck
),
4439 CLK(NULL
, "gpt8_fck", &gpt8_fck
),
4440 CLK(NULL
, "gpt9_fck", &gpt9_fck
),
4441 CLK(NULL
, "per_32k_alwon_fck", &per_32k_alwon_fck
),
4442 CLK(NULL
, "gpio6_dbck", &gpio6_dbck
),
4443 CLK(NULL
, "gpio5_dbck", &gpio5_dbck
),
4444 CLK(NULL
, "gpio4_dbck", &gpio4_dbck
),
4445 CLK(NULL
, "gpio3_dbck", &gpio3_dbck
),
4446 CLK(NULL
, "gpio2_dbck", &gpio2_dbck
),
4447 CLK(NULL
, "wdt3_fck", &wdt3_fck
),
4448 CLK(NULL
, "per_l4_ick", &per_l4_ick
),
4449 CLK(NULL
, "gpio6_ick", &gpio6_ick
),
4450 CLK(NULL
, "gpio5_ick", &gpio5_ick
),
4451 CLK(NULL
, "gpio4_ick", &gpio4_ick
),
4452 CLK(NULL
, "gpio3_ick", &gpio3_ick
),
4453 CLK(NULL
, "gpio2_ick", &gpio2_ick
),
4454 CLK(NULL
, "wdt3_ick", &wdt3_ick
),
4455 CLK(NULL
, "uart3_ick", &uart3_ick
),
4456 CLK(NULL
, "uart4_ick", &uart4_ick
),
4457 CLK(NULL
, "gpt9_ick", &gpt9_ick
),
4458 CLK(NULL
, "gpt8_ick", &gpt8_ick
),
4459 CLK(NULL
, "gpt7_ick", &gpt7_ick
),
4460 CLK(NULL
, "gpt6_ick", &gpt6_ick
),
4461 CLK(NULL
, "gpt5_ick", &gpt5_ick
),
4462 CLK(NULL
, "gpt4_ick", &gpt4_ick
),
4463 CLK(NULL
, "gpt3_ick", &gpt3_ick
),
4464 CLK(NULL
, "gpt2_ick", &gpt2_ick
),
4465 CLK(NULL
, "mcbsp_clks", &mcbsp_clks
),
4466 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick
),
4467 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick
),
4468 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick
),
4469 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick
),
4470 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick
),
4471 CLK(NULL
, "mcbsp1_ick", &mcbsp1_ick
),
4472 CLK(NULL
, "mcbsp2_ick", &mcbsp2_ick
),
4473 CLK(NULL
, "mcbsp3_ick", &mcbsp3_ick
),
4474 CLK(NULL
, "mcbsp4_ick", &mcbsp4_ick
),
4475 CLK(NULL
, "mcbsp5_ick", &mcbsp5_ick
),
4476 CLK(NULL
, "mcbsp1_fck", &mcbsp1_fck
),
4477 CLK(NULL
, "mcbsp2_fck", &mcbsp2_fck
),
4478 CLK(NULL
, "mcbsp3_fck", &mcbsp3_fck
),
4479 CLK(NULL
, "mcbsp4_fck", &mcbsp4_fck
),
4480 CLK(NULL
, "mcbsp5_fck", &mcbsp5_fck
),
4481 CLK(NULL
, "emu_src_mux_ck", &emu_src_mux_ck
),
4482 CLK("etb", "emu_src_ck", &emu_src_ck
),
4483 CLK(NULL
, "emu_src_mux_ck", &emu_src_mux_ck
),
4484 CLK(NULL
, "emu_src_ck", &emu_src_ck
),
4485 CLK(NULL
, "pclk_fck", &pclk_fck
),
4486 CLK(NULL
, "pclkx2_fck", &pclkx2_fck
),
4487 CLK(NULL
, "atclk_fck", &atclk_fck
),
4488 CLK(NULL
, "traceclk_src_fck", &traceclk_src_fck
),
4489 CLK(NULL
, "traceclk_fck", &traceclk_fck
),
4490 CLK(NULL
, "secure_32k_fck", &secure_32k_fck
),
4491 CLK(NULL
, "gpt12_fck", &gpt12_fck
),
4492 CLK(NULL
, "wdt1_fck", &wdt1_fck
),
4496 static struct ti_clk_alias omap36xx_am35xx_omap3430es2plus_clks
[] = {
4497 CLK(NULL
, "dpll5_ck", &dpll5_ck
),
4498 CLK(NULL
, "dpll5_m2_ck", &dpll5_m2_ck
),
4499 CLK(NULL
, "core_d3_ck", &core_d3_ck
),
4500 CLK(NULL
, "core_d4_ck", &core_d4_ck
),
4501 CLK(NULL
, "core_d6_ck", &core_d6_ck
),
4502 CLK(NULL
, "omap_192m_alwon_fck", &omap_192m_alwon_fck
),
4503 CLK(NULL
, "core_d2_ck", &core_d2_ck
),
4504 CLK(NULL
, "corex2_d3_fck", &corex2_d3_fck
),
4505 CLK(NULL
, "corex2_d5_fck", &corex2_d5_fck
),
4506 CLK(NULL
, "sgx_fck", &sgx_fck
),
4507 CLK(NULL
, "sgx_ick", &sgx_ick
),
4508 CLK(NULL
, "cpefuse_fck", &cpefuse_fck
),
4509 CLK(NULL
, "ts_fck", &ts_fck
),
4510 CLK(NULL
, "usbtll_fck", &usbtll_fck
),
4511 CLK(NULL
, "usbtll_ick", &usbtll_ick
),
4512 CLK("omap_hsmmc.2", "ick", &mmchs3_ick
),
4513 CLK(NULL
, "mmchs3_ick", &mmchs3_ick
),
4514 CLK(NULL
, "mmchs3_fck", &mmchs3_fck
),
4515 CLK(NULL
, "dss1_alwon_fck", &dss1_alwon_fck_3430es2
),
4516 CLK("omapdss_dss", "ick", &dss_ick_3430es2
),
4517 CLK(NULL
, "dss_ick", &dss_ick_3430es2
),
4518 CLK(NULL
, "usbhost_120m_fck", &usbhost_120m_fck
),
4519 CLK(NULL
, "usbhost_48m_fck", &usbhost_48m_fck
),
4520 CLK(NULL
, "usbhost_ick", &usbhost_ick
),
4524 static struct ti_clk_alias omap3430es1_clks
[] = {
4525 CLK(NULL
, "gfx_l3_ck", &gfx_l3_ck
),
4526 CLK(NULL
, "gfx_l3_fck", &gfx_l3_fck
),
4527 CLK(NULL
, "gfx_l3_ick", &gfx_l3_ick
),
4528 CLK(NULL
, "gfx_cg1_ck", &gfx_cg1_ck
),
4529 CLK(NULL
, "gfx_cg2_ck", &gfx_cg2_ck
),
4530 CLK(NULL
, "d2d_26m_fck", &d2d_26m_fck
),
4531 CLK(NULL
, "fshostusb_fck", &fshostusb_fck
),
4532 CLK(NULL
, "ssi_ssr_fck", &ssi_ssr_fck_3430es1
),
4533 CLK(NULL
, "ssi_sst_fck", &ssi_sst_fck_3430es1
),
4534 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1
),
4535 CLK(NULL
, "hsotgusb_ick", &hsotgusb_ick_3430es1
),
4536 CLK(NULL
, "fac_ick", &fac_ick
),
4537 CLK(NULL
, "ssi_ick", &ssi_ick_3430es1
),
4538 CLK(NULL
, "usb_l4_ick", &usb_l4_ick
),
4539 CLK(NULL
, "dss1_alwon_fck", &dss1_alwon_fck_3430es1
),
4540 CLK("omapdss_dss", "ick", &dss_ick_3430es1
),
4541 CLK(NULL
, "dss_ick", &dss_ick_3430es1
),
4545 static struct ti_clk_alias omap36xx_clks
[] = {
4546 CLK(NULL
, "uart4_fck", &uart4_fck
),
4550 static struct ti_clk_alias am35xx_clks
[] = {
4551 CLK(NULL
, "ipss_ick", &ipss_ick
),
4552 CLK(NULL
, "rmii_ck", &rmii_ck
),
4553 CLK(NULL
, "pclk_ck", &pclk_ck
),
4554 CLK(NULL
, "emac_ick", &emac_ick
),
4555 CLK(NULL
, "emac_fck", &emac_fck
),
4556 CLK("davinci_emac.0", NULL
, &emac_ick
),
4557 CLK("davinci_mdio.0", NULL
, &emac_fck
),
4558 CLK("vpfe-capture", "master", &vpfe_ick
),
4559 CLK("vpfe-capture", "slave", &vpfe_fck
),
4560 CLK(NULL
, "hsotgusb_ick", &hsotgusb_ick_am35xx
),
4561 CLK(NULL
, "hsotgusb_fck", &hsotgusb_fck_am35xx
),
4562 CLK(NULL
, "hecc_ck", &hecc_ck
),
4563 CLK(NULL
, "uart4_ick", &uart4_ick_am35xx
),
4564 CLK(NULL
, "uart4_fck", &uart4_fck_am35xx
),
4568 static struct ti_clk
*omap36xx_clk_patches
[] = {
4569 &dpll4_m3x2_ck_omap36xx
,
4570 &dpll3_m3x2_ck_omap36xx
,
4571 &dpll4_m6x2_ck_omap36xx
,
4572 &dpll4_m2x2_ck_omap36xx
,
4573 &dpll4_m5x2_ck_omap36xx
,
4578 static const char *enable_init_clks
[] = {
4584 static void __init
omap3_clk_legacy_common_init(void)
4586 omap2_clk_disable_autoidle_all();
4588 omap2_clk_enable_init_clocks(enable_init_clks
,
4589 ARRAY_SIZE(enable_init_clks
));
4591 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
4592 (clk_get_rate(osc_sys_ck
.clk
) / 1000000),
4593 (clk_get_rate(osc_sys_ck
.clk
) / 100000) % 10,
4594 (clk_get_rate(core_ck
.clk
) / 1000000),
4595 (clk_get_rate(arm_fck
.clk
) / 1000000));
4598 int __init
omap3430es1_clk_legacy_init(void)
4602 r
= ti_clk_register_legacy_clks(omap3430es1_clks
);
4603 r
|= ti_clk_register_legacy_clks(omap34xx_omap36xx_clks
);
4604 r
|= ti_clk_register_legacy_clks(omap3xxx_clks
);
4606 omap3_clk_legacy_common_init();
4611 int __init
omap3430_clk_legacy_init(void)
4615 r
= ti_clk_register_legacy_clks(omap34xx_omap36xx_clks
);
4616 r
|= ti_clk_register_legacy_clks(omap36xx_omap3430es2plus_clks
);
4617 r
|= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks
);
4618 r
|= ti_clk_register_legacy_clks(omap3xxx_clks
);
4620 omap3_clk_legacy_common_init();
4621 omap3_clk_lock_dpll5();
4626 int __init
omap36xx_clk_legacy_init(void)
4630 ti_clk_patch_legacy_clks(omap36xx_clk_patches
);
4631 r
= ti_clk_register_legacy_clks(omap36xx_clks
);
4632 r
|= ti_clk_register_legacy_clks(omap36xx_omap3430es2plus_clks
);
4633 r
|= ti_clk_register_legacy_clks(omap34xx_omap36xx_clks
);
4634 r
|= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks
);
4635 r
|= ti_clk_register_legacy_clks(omap3xxx_clks
);
4637 omap3_clk_legacy_common_init();
4638 omap3_clk_lock_dpll5();
4643 int __init
am35xx_clk_legacy_init(void)
4647 r
= ti_clk_register_legacy_clks(am35xx_clks
);
4648 r
|= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks
);
4649 r
|= ti_clk_register_legacy_clks(omap3xxx_clks
);
4651 omap3_clk_legacy_common_init();
4652 omap3_clk_lock_dpll5();