drivers/clk/ti/divider.c

   1 /*
   2  * TI Divider Clock
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * Tero Kristo <t-kristo@ti.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13  * kind, whether express or implied; without even the implied warranty
  14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/clk-provider.h>
  19 #include <linux/slab.h>
  20 #include <linux/err.h>
  21 #include <linux/of.h>
  22 #include <linux/of_address.h>
  23 #include <linux/clk/ti.h>
  24 #include "clock.h"
  25
  26 #undef pr_fmt
  27 #define pr_fmt(fmt) "%s: " fmt, __func__
  28
  29 static unsigned int _get_table_div(const struct clk_div_table *table,
  30                                    unsigned int val)
  31 {
  32         const struct clk_div_table *clkt;
  33
  34         for (clkt = table; clkt->div; clkt++)
  35                 if (clkt->val == val)
  36                         return clkt->div;
  37         return 0;
  38 }
  39
  40 static void _setup_mask(struct clk_omap_divider *divider)
  41 {
  42         u16 mask;
  43         u32 max_val;
  44         const struct clk_div_table *clkt;
  45
  46         if (divider->table) {
  47                 max_val = 0;
  48
  49                 for (clkt = divider->table; clkt->div; clkt++)
  50                         if (clkt->val > max_val)
  51                                 max_val = clkt->val;
  52         } else {
  53                 max_val = divider->max;
  54
  55                 if (!(divider->flags & CLK_DIVIDER_ONE_BASED) &&
  56                     !(divider->flags & CLK_DIVIDER_POWER_OF_TWO))
  57                         max_val--;
  58         }
  59
  60         if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
  61                 mask = fls(max_val) - 1;
  62         else
  63                 mask = max_val;
  64
  65         divider->mask = (1 << fls(mask)) - 1;
  66 }
  67
  68 static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val)
  69 {
  70         if (divider->flags & CLK_DIVIDER_ONE_BASED)
  71                 return val;
  72         if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
  73                 return 1 << val;
  74         if (divider->table)
  75                 return _get_table_div(divider->table, val);
  76         return val + 1;
  77 }
  78
  79 static unsigned int _get_table_val(const struct clk_div_table *table,
  80                                    unsigned int div)
  81 {
  82         const struct clk_div_table *clkt;
  83
  84         for (clkt = table; clkt->div; clkt++)
  85                 if (clkt->div == div)
  86                         return clkt->val;
  87         return 0;
  88 }
  89
  90 static unsigned int _get_val(struct clk_omap_divider *divider, u8 div)
  91 {
  92         if (divider->flags & CLK_DIVIDER_ONE_BASED)
  93                 return div;
  94         if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
  95                 return __ffs(div);
  96         if (divider->table)
  97                 return  _get_table_val(divider->table, div);
  98         return div - 1;
  99 }
 100
 101 static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw,
 102                                                 unsigned long parent_rate)
 103 {
 104         struct clk_omap_divider *divider = to_clk_omap_divider(hw);
 105         unsigned int div, val;
 106
 107         val = ti_clk_ll_ops->clk_readl(&divider->reg) >> divider->shift;
 108         val &= divider->mask;
 109
 110         div = _get_div(divider, val);
 111         if (!div) {
 112                 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
 113                      "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
 114                      clk_hw_get_name(hw));
 115                 return parent_rate;
 116         }
 117
 118         return DIV_ROUND_UP(parent_rate, div);
 119 }
 120
 121 /*
 122  * The reverse of DIV_ROUND_UP: The maximum number which
 123  * divided by m is r
 124  */
 125 #define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
 126
 127 static bool _is_valid_table_div(const struct clk_div_table *table,
 128                                 unsigned int div)
 129 {
 130         const struct clk_div_table *clkt;
 131
 132         for (clkt = table; clkt->div; clkt++)
 133                 if (clkt->div == div)
 134                         return true;
 135         return false;
 136 }
 137
 138 static bool _is_valid_div(struct clk_omap_divider *divider, unsigned int div)
 139 {
 140         if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
 141                 return is_power_of_2(div);
 142         if (divider->table)
 143                 return _is_valid_table_div(divider->table, div);
 144         return true;
 145 }
 146
 147 static int _div_round_up(const struct clk_div_table *table,
 148                          unsigned long parent_rate, unsigned long rate)
 149 {
 150         const struct clk_div_table *clkt;
 151         int up = INT_MAX;
 152         int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
 153
 154         for (clkt = table; clkt->div; clkt++) {
 155                 if (clkt->div == div)
 156                         return clkt->div;
 157                 else if (clkt->div < div)
 158                         continue;
 159
 160                 if ((clkt->div - div) < (up - div))
 161                         up = clkt->div;
 162         }
 163
 164         return up;
 165 }
 166
 167 static int _div_round(const struct clk_div_table *table,
 168                       unsigned long parent_rate, unsigned long rate)
 169 {
 170         if (!table)
 171                 return DIV_ROUND_UP(parent_rate, rate);
 172
 173         return _div_round_up(table, parent_rate, rate);
 174 }
 175
 176 static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
 177                                   unsigned long *best_parent_rate)
 178 {
 179         struct clk_omap_divider *divider = to_clk_omap_divider(hw);
 180         int i, bestdiv = 0;
 181         unsigned long parent_rate, best = 0, now, maxdiv;
 182         unsigned long parent_rate_saved = *best_parent_rate;
 183
 184         if (!rate)
 185                 rate = 1;
 186
 187         maxdiv = divider->max;
 188
 189         if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
 190                 parent_rate = *best_parent_rate;
 191                 bestdiv = _div_round(divider->table, parent_rate, rate);
 192                 bestdiv = bestdiv == 0 ? 1 : bestdiv;
 193                 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
 194                 return bestdiv;
 195         }
 196
 197         /*
 198          * The maximum divider we can use without overflowing
 199          * unsigned long in rate * i below
 200          */
 201         maxdiv = min(ULONG_MAX / rate, maxdiv);
 202
 203         for (i = 1; i <= maxdiv; i++) {
 204                 if (!_is_valid_div(divider, i))
 205                         continue;
 206                 if (rate * i == parent_rate_saved) {
 207                         /*
 208                          * It's the most ideal case if the requested rate can be
 209                          * divided from parent clock without needing to change
 210                          * parent rate, so return the divider immediately.
 211                          */
 212                         *best_parent_rate = parent_rate_saved;
 213                         return i;
 214                 }
 215                 parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
 216                                 MULT_ROUND_UP(rate, i));
 217                 now = DIV_ROUND_UP(parent_rate, i);
 218                 if (now <= rate && now > best) {
 219                         bestdiv = i;
 220                         best = now;
 221                         *best_parent_rate = parent_rate;
 222                 }
 223         }
 224
 225         if (!bestdiv) {
 226                 bestdiv = divider->max;
 227                 *best_parent_rate =
 228                         clk_hw_round_rate(clk_hw_get_parent(hw), 1);
 229         }
 230
 231         return bestdiv;
 232 }
 233
 234 static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
 235                                       unsigned long *prate)
 236 {
 237         int div;
 238         div = ti_clk_divider_bestdiv(hw, rate, prate);
 239
 240         return DIV_ROUND_UP(*prate, div);
 241 }
 242
 243 static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
 244                                    unsigned long parent_rate)
 245 {
 246         struct clk_omap_divider *divider;
 247         unsigned int div, value;
 248         u32 val;
 249
 250         if (!hw || !rate)
 251                 return -EINVAL;
 252
 253         divider = to_clk_omap_divider(hw);
 254
 255         div = DIV_ROUND_UP(parent_rate, rate);
 256
 257         if (div > divider->max)
 258                 div = divider->max;
 259         if (div < divider->min)
 260                 div = divider->min;
 261
 262         value = _get_val(divider, div);
 263
 264         val = ti_clk_ll_ops->clk_readl(&divider->reg);
 265         val &= ~(divider->mask << divider->shift);
 266         val |= value << divider->shift;
 267         ti_clk_ll_ops->clk_writel(val, &divider->reg);
 268
 269         ti_clk_latch(&divider->reg, divider->latch);
 270
 271         return 0;
 272 }
 273
 274 /**
 275  * clk_divider_save_context - Save the divider value
 276  * @hw: pointer  struct clk_hw
 277  *
 278  * Save the divider value
 279  */
 280 static int clk_divider_save_context(struct clk_hw *hw)
 281 {
 282         struct clk_omap_divider *divider = to_clk_omap_divider(hw);
 283         u32 val;
 284
 285         val = ti_clk_ll_ops->clk_readl(&divider->reg) >> divider->shift;
 286         divider->context = val & divider->mask;
 287
 288         return 0;
 289 }
 290
 291 /**
 292  * clk_divider_restore_context - restore the saved the divider value
 293  * @hw: pointer  struct clk_hw
 294  *
 295  * Restore the saved the divider value
 296  */
 297 static void clk_divider_restore_context(struct clk_hw *hw)
 298 {
 299         struct clk_omap_divider *divider = to_clk_omap_divider(hw);
 300         u32 val;
 301
 302         val = ti_clk_ll_ops->clk_readl(&divider->reg);
 303         val &= ~(divider->mask << divider->shift);
 304         val |= divider->context << divider->shift;
 305         ti_clk_ll_ops->clk_writel(val, &divider->reg);
 306 }
 307
 308 const struct clk_ops ti_clk_divider_ops = {
 309         .recalc_rate = ti_clk_divider_recalc_rate,
 310         .round_rate = ti_clk_divider_round_rate,
 311         .set_rate = ti_clk_divider_set_rate,
 312         .save_context = clk_divider_save_context,
 313         .restore_context = clk_divider_restore_context,
 314 };
 315
 316 static struct clk *_register_divider(struct device_node *node,
 317                                      u32 flags,
 318                                      struct clk_omap_divider *div)
 319 {
 320         struct clk *clk;
 321         struct clk_init_data init;
 322         const char *parent_name;
 323
 324         parent_name = of_clk_get_parent_name(node, 0);
 325
 326         init.name = node->name;
 327         init.ops = &ti_clk_divider_ops;
 328         init.flags = flags;
 329         init.parent_names = (parent_name ? &parent_name : NULL);
 330         init.num_parents = (parent_name ? 1 : 0);
 331
 332         div->hw.init = &init;
 333
 334         /* register the clock */
 335         clk = ti_clk_register(NULL, &div->hw, node->name);
 336
 337         if (IS_ERR(clk))
 338                 kfree(div);
 339
 340         return clk;
 341 }
 342
 343 int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
 344                               u8 flags, struct clk_omap_divider *divider)
 345 {
 346         int valid_div = 0;
 347         int i;
 348         struct clk_div_table *tmp;
 349         u16 min_div = 0;
 350
 351         if (!div_table) {
 352                 divider->min = 1;
 353                 divider->max = max_div;
 354                 _setup_mask(divider);
 355                 return 0;
 356         }
 357
 358         i = 0;
 359
 360         while (!num_dividers || i < num_dividers) {
 361                 if (div_table[i] == -1)
 362                         break;
 363                 if (div_table[i])
 364                         valid_div++;
 365                 i++;
 366         }
 367
 368         num_dividers = i;
 369
 370         tmp = kcalloc(valid_div + 1, sizeof(*tmp), GFP_KERNEL);
 371         if (!tmp)
 372                 return -ENOMEM;
 373
 374         valid_div = 0;
 375
 376         for (i = 0; i < num_dividers; i++)
 377                 if (div_table[i] > 0) {
 378                         tmp[valid_div].div = div_table[i];
 379                         tmp[valid_div].val = i;
 380                         valid_div++;
 381                         if (div_table[i] > max_div)
 382                                 max_div = div_table[i];
 383                         if (!min_div || div_table[i] < min_div)
 384                                 min_div = div_table[i];
 385                 }
 386
 387         divider->min = min_div;
 388         divider->max = max_div;
 389         divider->table = tmp;
 390         _setup_mask(divider);
 391
 392         return 0;
 393 }
 394
 395 static int __init ti_clk_get_div_table(struct device_node *node,
 396                                        struct clk_omap_divider *div)
 397 {
 398         struct clk_div_table *table;
 399         const __be32 *divspec;
 400         u32 val;
 401         u32 num_div;
 402         u32 valid_div;
 403         int i;
 404
 405         divspec = of_get_property(node, "ti,dividers", &num_div);
 406
 407         if (!divspec)
 408                 return 0;
 409
 410         num_div /= 4;
 411
 412         valid_div = 0;
 413
 414         /* Determine required size for divider table */
 415         for (i = 0; i < num_div; i++) {
 416                 of_property_read_u32_index(node, "ti,dividers", i, &val);
 417                 if (val)
 418                         valid_div++;
 419         }
 420
 421         if (!valid_div) {
 422                 pr_err("no valid dividers for %pOFn table\n", node);
 423                 return -EINVAL;
 424         }
 425
 426         table = kcalloc(valid_div + 1, sizeof(*table), GFP_KERNEL);
 427         if (!table)
 428                 return -ENOMEM;
 429
 430         valid_div = 0;
 431
 432         for (i = 0; i < num_div; i++) {
 433                 of_property_read_u32_index(node, "ti,dividers", i, &val);
 434                 if (val) {
 435                         table[valid_div].div = val;
 436                         table[valid_div].val = i;
 437                         valid_div++;
 438                 }
 439         }
 440
 441         div->table = table;
 442
 443         return 0;
 444 }
 445
 446 static int _populate_divider_min_max(struct device_node *node,
 447                                      struct clk_omap_divider *divider)
 448 {
 449         u32 min_div = 0;
 450         u32 max_div = 0;
 451         u32 val;
 452         const struct clk_div_table *clkt;
 453
 454         if (!divider->table) {
 455                 /* Clk divider table not provided, determine min/max divs */
 456                 if (of_property_read_u32(node, "ti,min-div", &min_div))
 457                         min_div = 1;
 458
 459                 if (of_property_read_u32(node, "ti,max-div", &max_div)) {
 460                         pr_err("no max-div for %pOFn!\n", node);
 461                         return -EINVAL;
 462                 }
 463         } else {
 464
 465                 for (clkt = divider->table; clkt->div; clkt++) {
 466                         val = clkt->div;
 467                         if (val > max_div)
 468                                 max_div = val;
 469                         if (!min_div || val < min_div)
 470                                 min_div = val;
 471                 }
 472         }
 473
 474         divider->min = min_div;
 475         divider->max = max_div;
 476         _setup_mask(divider);
 477
 478         return 0;
 479 }
 480
 481 static int __init ti_clk_divider_populate(struct device_node *node,
 482                                           struct clk_omap_divider *div,
 483                                           u32 *flags)
 484 {
 485         u32 val;
 486         int ret;
 487
 488         ret = ti_clk_get_reg_addr(node, 0, &div->reg);
 489         if (ret)
 490                 return ret;
 491
 492         if (!of_property_read_u32(node, "ti,bit-shift", &val))
 493                 div->shift = val;
 494         else
 495                 div->shift = 0;
 496
 497         if (!of_property_read_u32(node, "ti,latch-bit", &val))
 498                 div->latch = val;
 499         else
 500                 div->latch = -EINVAL;
 501
 502         *flags = 0;
 503         div->flags = 0;
 504
 505         if (of_property_read_bool(node, "ti,index-starts-at-one"))
 506                 div->flags |= CLK_DIVIDER_ONE_BASED;
 507
 508         if (of_property_read_bool(node, "ti,index-power-of-two"))
 509                 div->flags |= CLK_DIVIDER_POWER_OF_TWO;
 510
 511         if (of_property_read_bool(node, "ti,set-rate-parent"))
 512                 *flags |= CLK_SET_RATE_PARENT;
 513
 514         ret = ti_clk_get_div_table(node, div);
 515         if (ret)
 516                 return ret;
 517
 518         return _populate_divider_min_max(node, div);
 519 }
 520
 521 /**
 522  * of_ti_divider_clk_setup - Setup function for simple div rate clock
 523  * @node: device node for this clock
 524  *
 525  * Sets up a basic divider clock.
 526  */
 527 static void __init of_ti_divider_clk_setup(struct device_node *node)
 528 {
 529         struct clk *clk;
 530         u32 flags = 0;
 531         struct clk_omap_divider *div;
 532
 533         div = kzalloc(sizeof(*div), GFP_KERNEL);
 534         if (!div)
 535                 return;
 536
 537         if (ti_clk_divider_populate(node, div, &flags))
 538                 goto cleanup;
 539
 540         clk = _register_divider(node, flags, div);
 541         if (!IS_ERR(clk)) {
 542                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
 543                 of_ti_clk_autoidle_setup(node);
 544                 return;
 545         }
 546
 547 cleanup:
 548         kfree(div->table);
 549         kfree(div);
 550 }
 551 CLK_OF_DECLARE(divider_clk, "ti,divider-clock", of_ti_divider_clk_setup);
 552
 553 static void __init of_ti_composite_divider_clk_setup(struct device_node *node)
 554 {
 555         struct clk_omap_divider *div;
 556         u32 tmp;
 557
 558         div = kzalloc(sizeof(*div), GFP_KERNEL);
 559         if (!div)
 560                 return;
 561
 562         if (ti_clk_divider_populate(node, div, &tmp))
 563                 goto cleanup;
 564
 565         if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER))
 566                 return;
 567
 568 cleanup:
 569         kfree(div->table);
 570         kfree(div);
 571 }
 572 CLK_OF_DECLARE(ti_composite_divider_clk, "ti,composite-divider-clock",
 573                of_ti_composite_divider_clk_setup);