4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * Tero Kristo <t-kristo@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk-provider.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
22 #include <linux/of_address.h>
23 #include <linux/clk/ti.h>
27 #define pr_fmt(fmt) "%s: " fmt, __func__
29 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
31 #define div_mask(d) ((1 << ((d)->width)) - 1)
33 static unsigned int _get_table_maxdiv(const struct clk_div_table
*table
)
35 unsigned int maxdiv
= 0;
36 const struct clk_div_table
*clkt
;
38 for (clkt
= table
; clkt
->div
; clkt
++)
39 if (clkt
->div
> maxdiv
)
44 static unsigned int _get_maxdiv(struct clk_divider
*divider
)
46 if (divider
->flags
& CLK_DIVIDER_ONE_BASED
)
47 return div_mask(divider
);
48 if (divider
->flags
& CLK_DIVIDER_POWER_OF_TWO
)
49 return 1 << div_mask(divider
);
51 return _get_table_maxdiv(divider
->table
);
52 return div_mask(divider
) + 1;
55 static unsigned int _get_table_div(const struct clk_div_table
*table
,
58 const struct clk_div_table
*clkt
;
60 for (clkt
= table
; clkt
->div
; clkt
++)
66 static unsigned int _get_div(struct clk_divider
*divider
, unsigned int val
)
68 if (divider
->flags
& CLK_DIVIDER_ONE_BASED
)
70 if (divider
->flags
& CLK_DIVIDER_POWER_OF_TWO
)
73 return _get_table_div(divider
->table
, val
);
77 static unsigned int _get_table_val(const struct clk_div_table
*table
,
80 const struct clk_div_table
*clkt
;
82 for (clkt
= table
; clkt
->div
; clkt
++)
88 static unsigned int _get_val(struct clk_divider
*divider
, u8 div
)
90 if (divider
->flags
& CLK_DIVIDER_ONE_BASED
)
92 if (divider
->flags
& CLK_DIVIDER_POWER_OF_TWO
)
95 return _get_table_val(divider
->table
, div
);
99 static unsigned long ti_clk_divider_recalc_rate(struct clk_hw
*hw
,
100 unsigned long parent_rate
)
102 struct clk_divider
*divider
= to_clk_divider(hw
);
103 unsigned int div
, val
;
105 val
= ti_clk_ll_ops
->clk_readl(divider
->reg
) >> divider
->shift
;
106 val
&= div_mask(divider
);
108 div
= _get_div(divider
, val
);
110 WARN(!(divider
->flags
& CLK_DIVIDER_ALLOW_ZERO
),
111 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
112 clk_hw_get_name(hw
));
116 return DIV_ROUND_UP(parent_rate
, div
);
120 * The reverse of DIV_ROUND_UP: The maximum number which
123 #define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
125 static bool _is_valid_table_div(const struct clk_div_table
*table
,
128 const struct clk_div_table
*clkt
;
130 for (clkt
= table
; clkt
->div
; clkt
++)
131 if (clkt
->div
== div
)
136 static bool _is_valid_div(struct clk_divider
*divider
, unsigned int div
)
138 if (divider
->flags
& CLK_DIVIDER_POWER_OF_TWO
)
139 return is_power_of_2(div
);
141 return _is_valid_table_div(divider
->table
, div
);
145 static int ti_clk_divider_bestdiv(struct clk_hw
*hw
, unsigned long rate
,
146 unsigned long *best_parent_rate
)
148 struct clk_divider
*divider
= to_clk_divider(hw
);
150 unsigned long parent_rate
, best
= 0, now
, maxdiv
;
151 unsigned long parent_rate_saved
= *best_parent_rate
;
156 maxdiv
= _get_maxdiv(divider
);
158 if (!(clk_hw_get_flags(hw
) & CLK_SET_RATE_PARENT
)) {
159 parent_rate
= *best_parent_rate
;
160 bestdiv
= DIV_ROUND_UP(parent_rate
, rate
);
161 bestdiv
= bestdiv
== 0 ? 1 : bestdiv
;
162 bestdiv
= bestdiv
> maxdiv
? maxdiv
: bestdiv
;
167 * The maximum divider we can use without overflowing
168 * unsigned long in rate * i below
170 maxdiv
= min(ULONG_MAX
/ rate
, maxdiv
);
172 for (i
= 1; i
<= maxdiv
; i
++) {
173 if (!_is_valid_div(divider
, i
))
175 if (rate
* i
== parent_rate_saved
) {
177 * It's the most ideal case if the requested rate can be
178 * divided from parent clock without needing to change
179 * parent rate, so return the divider immediately.
181 *best_parent_rate
= parent_rate_saved
;
184 parent_rate
= clk_hw_round_rate(clk_hw_get_parent(hw
),
185 MULT_ROUND_UP(rate
, i
));
186 now
= DIV_ROUND_UP(parent_rate
, i
);
187 if (now
<= rate
&& now
> best
) {
190 *best_parent_rate
= parent_rate
;
195 bestdiv
= _get_maxdiv(divider
);
197 clk_hw_round_rate(clk_hw_get_parent(hw
), 1);
203 static long ti_clk_divider_round_rate(struct clk_hw
*hw
, unsigned long rate
,
204 unsigned long *prate
)
207 div
= ti_clk_divider_bestdiv(hw
, rate
, prate
);
209 return DIV_ROUND_UP(*prate
, div
);
212 static int ti_clk_divider_set_rate(struct clk_hw
*hw
, unsigned long rate
,
213 unsigned long parent_rate
)
215 struct clk_divider
*divider
;
216 unsigned int div
, value
;
217 unsigned long flags
= 0;
223 divider
= to_clk_divider(hw
);
225 div
= DIV_ROUND_UP(parent_rate
, rate
);
226 value
= _get_val(divider
, div
);
228 if (value
> div_mask(divider
))
229 value
= div_mask(divider
);
232 spin_lock_irqsave(divider
->lock
, flags
);
234 if (divider
->flags
& CLK_DIVIDER_HIWORD_MASK
) {
235 val
= div_mask(divider
) << (divider
->shift
+ 16);
237 val
= ti_clk_ll_ops
->clk_readl(divider
->reg
);
238 val
&= ~(div_mask(divider
) << divider
->shift
);
240 val
|= value
<< divider
->shift
;
241 ti_clk_ll_ops
->clk_writel(val
, divider
->reg
);
244 spin_unlock_irqrestore(divider
->lock
, flags
);
249 const struct clk_ops ti_clk_divider_ops
= {
250 .recalc_rate
= ti_clk_divider_recalc_rate
,
251 .round_rate
= ti_clk_divider_round_rate
,
252 .set_rate
= ti_clk_divider_set_rate
,
255 static struct clk
*_register_divider(struct device
*dev
, const char *name
,
256 const char *parent_name
,
257 unsigned long flags
, void __iomem
*reg
,
258 u8 shift
, u8 width
, u8 clk_divider_flags
,
259 const struct clk_div_table
*table
,
262 struct clk_divider
*div
;
264 struct clk_init_data init
;
266 if (clk_divider_flags
& CLK_DIVIDER_HIWORD_MASK
) {
267 if (width
+ shift
> 16) {
268 pr_warn("divider value exceeds LOWORD field\n");
269 return ERR_PTR(-EINVAL
);
273 /* allocate the divider */
274 div
= kzalloc(sizeof(*div
), GFP_KERNEL
);
276 pr_err("%s: could not allocate divider clk\n", __func__
);
277 return ERR_PTR(-ENOMEM
);
281 init
.ops
= &ti_clk_divider_ops
;
282 init
.flags
= flags
| CLK_IS_BASIC
;
283 init
.parent_names
= (parent_name
? &parent_name
: NULL
);
284 init
.num_parents
= (parent_name
? 1 : 0);
286 /* struct clk_divider assignments */
290 div
->flags
= clk_divider_flags
;
292 div
->hw
.init
= &init
;
295 /* register the clock */
296 clk
= clk_register(dev
, &div
->hw
);
304 static struct clk_div_table
*
305 _get_div_table_from_setup(struct ti_clk_divider
*setup
, u8
*width
)
308 struct clk_div_table
*table
;
314 if (!setup
->num_dividers
) {
315 /* Clk divider table not provided, determine min/max divs */
316 flags
= setup
->flags
;
318 if (flags
& CLKF_INDEX_STARTS_AT_ONE
)
325 while (div
< setup
->max_div
) {
326 if (flags
& CLKF_INDEX_POWER_OF_TWO
)
338 for (i
= 0; i
< setup
->num_dividers
; i
++)
339 if (setup
->dividers
[i
])
342 table
= kzalloc(sizeof(*table
) * (valid_div
+ 1), GFP_KERNEL
);
344 return ERR_PTR(-ENOMEM
);
349 for (i
= 0; i
< setup
->num_dividers
; i
++)
350 if (setup
->dividers
[i
]) {
351 table
[valid_div
].div
= setup
->dividers
[i
];
352 table
[valid_div
].val
= i
;
357 *width
= fls(*width
);
362 struct clk_hw
*ti_clk_build_component_div(struct ti_clk_divider
*setup
)
364 struct clk_divider
*div
;
365 struct clk_omap_reg
*reg
;
370 div
= kzalloc(sizeof(*div
), GFP_KERNEL
);
372 return ERR_PTR(-ENOMEM
);
374 reg
= (struct clk_omap_reg
*)&div
->reg
;
375 reg
->index
= setup
->module
;
376 reg
->offset
= setup
->reg
;
378 if (setup
->flags
& CLKF_INDEX_STARTS_AT_ONE
)
379 div
->flags
|= CLK_DIVIDER_ONE_BASED
;
381 if (setup
->flags
& CLKF_INDEX_POWER_OF_TWO
)
382 div
->flags
|= CLK_DIVIDER_POWER_OF_TWO
;
384 div
->table
= _get_div_table_from_setup(setup
, &div
->width
);
386 div
->shift
= setup
->bit_shift
;
391 struct clk
*ti_clk_register_divider(struct ti_clk
*setup
)
393 struct ti_clk_divider
*div
;
394 struct clk_omap_reg
*reg_setup
;
399 struct clk_div_table
*table
;
404 reg_setup
= (struct clk_omap_reg
*)®
;
406 reg_setup
->index
= div
->module
;
407 reg_setup
->offset
= div
->reg
;
409 if (div
->flags
& CLKF_INDEX_STARTS_AT_ONE
)
410 div_flags
|= CLK_DIVIDER_ONE_BASED
;
412 if (div
->flags
& CLKF_INDEX_POWER_OF_TWO
)
413 div_flags
|= CLK_DIVIDER_POWER_OF_TWO
;
415 if (div
->flags
& CLKF_SET_RATE_PARENT
)
416 flags
|= CLK_SET_RATE_PARENT
;
418 table
= _get_div_table_from_setup(div
, &width
);
420 return (struct clk
*)table
;
422 clk
= _register_divider(NULL
, setup
->name
, div
->parent
,
423 flags
, (void __iomem
*)reg
, div
->bit_shift
,
424 width
, div_flags
, table
, NULL
);
432 static struct clk_div_table
*
433 __init
ti_clk_get_div_table(struct device_node
*node
)
435 struct clk_div_table
*table
;
436 const __be32
*divspec
;
442 divspec
= of_get_property(node
, "ti,dividers", &num_div
);
451 /* Determine required size for divider table */
452 for (i
= 0; i
< num_div
; i
++) {
453 of_property_read_u32_index(node
, "ti,dividers", i
, &val
);
459 pr_err("no valid dividers for %s table\n", node
->name
);
460 return ERR_PTR(-EINVAL
);
463 table
= kzalloc(sizeof(*table
) * (valid_div
+ 1), GFP_KERNEL
);
466 return ERR_PTR(-ENOMEM
);
470 for (i
= 0; i
< num_div
; i
++) {
471 of_property_read_u32_index(node
, "ti,dividers", i
, &val
);
473 table
[valid_div
].div
= val
;
474 table
[valid_div
].val
= i
;
482 static int _get_divider_width(struct device_node
*node
,
483 const struct clk_div_table
*table
,
492 /* Clk divider table not provided, determine min/max divs */
493 if (of_property_read_u32(node
, "ti,min-div", &min_div
))
496 if (of_property_read_u32(node
, "ti,max-div", &max_div
)) {
497 pr_err("no max-div for %s!\n", node
->name
);
501 /* Determine bit width for the field */
502 if (flags
& CLK_DIVIDER_ONE_BASED
)
507 while (div
< max_div
) {
508 if (flags
& CLK_DIVIDER_POWER_OF_TWO
)
517 while (table
[div
].div
) {
518 val
= table
[div
].val
;
526 static int __init
ti_clk_divider_populate(struct device_node
*node
,
527 void __iomem
**reg
, const struct clk_div_table
**table
,
528 u32
*flags
, u8
*div_flags
, u8
*width
, u8
*shift
)
532 *reg
= ti_clk_get_reg_addr(node
, 0);
534 return PTR_ERR(*reg
);
536 if (!of_property_read_u32(node
, "ti,bit-shift", &val
))
544 if (of_property_read_bool(node
, "ti,index-starts-at-one"))
545 *div_flags
|= CLK_DIVIDER_ONE_BASED
;
547 if (of_property_read_bool(node
, "ti,index-power-of-two"))
548 *div_flags
|= CLK_DIVIDER_POWER_OF_TWO
;
550 if (of_property_read_bool(node
, "ti,set-rate-parent"))
551 *flags
|= CLK_SET_RATE_PARENT
;
553 *table
= ti_clk_get_div_table(node
);
556 return PTR_ERR(*table
);
558 *width
= _get_divider_width(node
, *table
, *div_flags
);
564 * of_ti_divider_clk_setup - Setup function for simple div rate clock
565 * @node: device node for this clock
567 * Sets up a basic divider clock.
569 static void __init
of_ti_divider_clk_setup(struct device_node
*node
)
572 const char *parent_name
;
574 u8 clk_divider_flags
= 0;
577 const struct clk_div_table
*table
= NULL
;
580 parent_name
= of_clk_get_parent_name(node
, 0);
582 if (ti_clk_divider_populate(node
, ®
, &table
, &flags
,
583 &clk_divider_flags
, &width
, &shift
))
586 clk
= _register_divider(NULL
, node
->name
, parent_name
, flags
, reg
,
587 shift
, width
, clk_divider_flags
, table
,
591 of_clk_add_provider(node
, of_clk_src_simple_get
, clk
);
592 of_ti_clk_autoidle_setup(node
);
599 CLK_OF_DECLARE(divider_clk
, "ti,divider-clock", of_ti_divider_clk_setup
);
601 static void __init
of_ti_composite_divider_clk_setup(struct device_node
*node
)
603 struct clk_divider
*div
;
606 div
= kzalloc(sizeof(*div
), GFP_KERNEL
);
610 if (ti_clk_divider_populate(node
, &div
->reg
, &div
->table
, &val
,
611 &div
->flags
, &div
->width
, &div
->shift
) < 0)
614 if (!ti_clk_add_component(node
, &div
->hw
, CLK_COMPONENT_TYPE_DIVIDER
))
621 CLK_OF_DECLARE(ti_composite_divider_clk
, "ti,composite-divider-clock",
622 of_ti_composite_divider_clk_setup
);