4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * Tero Kristo <t-kristo@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk-provider.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
22 #include <linux/of_address.h>
23 #include <linux/clk/ti.h>
27 #define pr_fmt(fmt) "%s: " fmt, __func__
29 #define div_mask(d) ((1 << ((d)->width)) - 1)
31 static unsigned int _get_table_maxdiv(const struct clk_div_table
*table
)
33 unsigned int maxdiv
= 0;
34 const struct clk_div_table
*clkt
;
36 for (clkt
= table
; clkt
->div
; clkt
++)
37 if (clkt
->div
> maxdiv
)
42 static unsigned int _get_maxdiv(struct clk_omap_divider
*divider
)
44 if (divider
->flags
& CLK_DIVIDER_ONE_BASED
)
45 return div_mask(divider
);
46 if (divider
->flags
& CLK_DIVIDER_POWER_OF_TWO
)
47 return 1 << div_mask(divider
);
49 return _get_table_maxdiv(divider
->table
);
50 return div_mask(divider
) + 1;
53 static unsigned int _get_table_div(const struct clk_div_table
*table
,
56 const struct clk_div_table
*clkt
;
58 for (clkt
= table
; clkt
->div
; clkt
++)
64 static unsigned int _get_div(struct clk_omap_divider
*divider
, unsigned int val
)
66 if (divider
->flags
& CLK_DIVIDER_ONE_BASED
)
68 if (divider
->flags
& CLK_DIVIDER_POWER_OF_TWO
)
71 return _get_table_div(divider
->table
, val
);
75 static unsigned int _get_table_val(const struct clk_div_table
*table
,
78 const struct clk_div_table
*clkt
;
80 for (clkt
= table
; clkt
->div
; clkt
++)
86 static unsigned int _get_val(struct clk_omap_divider
*divider
, u8 div
)
88 if (divider
->flags
& CLK_DIVIDER_ONE_BASED
)
90 if (divider
->flags
& CLK_DIVIDER_POWER_OF_TWO
)
93 return _get_table_val(divider
->table
, div
);
97 static unsigned long ti_clk_divider_recalc_rate(struct clk_hw
*hw
,
98 unsigned long parent_rate
)
100 struct clk_omap_divider
*divider
= to_clk_omap_divider(hw
);
101 unsigned int div
, val
;
103 val
= ti_clk_ll_ops
->clk_readl(÷r
->reg
) >> divider
->shift
;
104 val
&= div_mask(divider
);
106 div
= _get_div(divider
, val
);
108 WARN(!(divider
->flags
& CLK_DIVIDER_ALLOW_ZERO
),
109 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
110 clk_hw_get_name(hw
));
114 return DIV_ROUND_UP(parent_rate
, div
);
118 * The reverse of DIV_ROUND_UP: The maximum number which
121 #define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
123 static bool _is_valid_table_div(const struct clk_div_table
*table
,
126 const struct clk_div_table
*clkt
;
128 for (clkt
= table
; clkt
->div
; clkt
++)
129 if (clkt
->div
== div
)
134 static bool _is_valid_div(struct clk_omap_divider
*divider
, unsigned int div
)
136 if (divider
->flags
& CLK_DIVIDER_POWER_OF_TWO
)
137 return is_power_of_2(div
);
139 return _is_valid_table_div(divider
->table
, div
);
143 static int _div_round_up(const struct clk_div_table
*table
,
144 unsigned long parent_rate
, unsigned long rate
)
146 const struct clk_div_table
*clkt
;
148 int div
= DIV_ROUND_UP_ULL((u64
)parent_rate
, rate
);
150 for (clkt
= table
; clkt
->div
; clkt
++) {
151 if (clkt
->div
== div
)
153 else if (clkt
->div
< div
)
156 if ((clkt
->div
- div
) < (up
- div
))
163 static int _div_round(const struct clk_div_table
*table
,
164 unsigned long parent_rate
, unsigned long rate
)
167 return DIV_ROUND_UP(parent_rate
, rate
);
169 return _div_round_up(table
, parent_rate
, rate
);
172 static int ti_clk_divider_bestdiv(struct clk_hw
*hw
, unsigned long rate
,
173 unsigned long *best_parent_rate
)
175 struct clk_omap_divider
*divider
= to_clk_omap_divider(hw
);
177 unsigned long parent_rate
, best
= 0, now
, maxdiv
;
178 unsigned long parent_rate_saved
= *best_parent_rate
;
183 maxdiv
= _get_maxdiv(divider
);
185 if (!(clk_hw_get_flags(hw
) & CLK_SET_RATE_PARENT
)) {
186 parent_rate
= *best_parent_rate
;
187 bestdiv
= _div_round(divider
->table
, parent_rate
, rate
);
188 bestdiv
= bestdiv
== 0 ? 1 : bestdiv
;
189 bestdiv
= bestdiv
> maxdiv
? maxdiv
: bestdiv
;
194 * The maximum divider we can use without overflowing
195 * unsigned long in rate * i below
197 maxdiv
= min(ULONG_MAX
/ rate
, maxdiv
);
199 for (i
= 1; i
<= maxdiv
; i
++) {
200 if (!_is_valid_div(divider
, i
))
202 if (rate
* i
== parent_rate_saved
) {
204 * It's the most ideal case if the requested rate can be
205 * divided from parent clock without needing to change
206 * parent rate, so return the divider immediately.
208 *best_parent_rate
= parent_rate_saved
;
211 parent_rate
= clk_hw_round_rate(clk_hw_get_parent(hw
),
212 MULT_ROUND_UP(rate
, i
));
213 now
= DIV_ROUND_UP(parent_rate
, i
);
214 if (now
<= rate
&& now
> best
) {
217 *best_parent_rate
= parent_rate
;
222 bestdiv
= _get_maxdiv(divider
);
224 clk_hw_round_rate(clk_hw_get_parent(hw
), 1);
230 static long ti_clk_divider_round_rate(struct clk_hw
*hw
, unsigned long rate
,
231 unsigned long *prate
)
234 div
= ti_clk_divider_bestdiv(hw
, rate
, prate
);
236 return DIV_ROUND_UP(*prate
, div
);
239 static int ti_clk_divider_set_rate(struct clk_hw
*hw
, unsigned long rate
,
240 unsigned long parent_rate
)
242 struct clk_omap_divider
*divider
;
243 unsigned int div
, value
;
249 divider
= to_clk_omap_divider(hw
);
251 div
= DIV_ROUND_UP(parent_rate
, rate
);
252 value
= _get_val(divider
, div
);
254 if (value
> div_mask(divider
))
255 value
= div_mask(divider
);
257 if (divider
->flags
& CLK_DIVIDER_HIWORD_MASK
) {
258 val
= div_mask(divider
) << (divider
->shift
+ 16);
260 val
= ti_clk_ll_ops
->clk_readl(÷r
->reg
);
261 val
&= ~(div_mask(divider
) << divider
->shift
);
263 val
|= value
<< divider
->shift
;
264 ti_clk_ll_ops
->clk_writel(val
, ÷r
->reg
);
266 ti_clk_latch(÷r
->reg
, divider
->latch
);
272 * clk_divider_save_context - Save the divider value
273 * @hw: pointer struct clk_hw
275 * Save the divider value
277 static int clk_divider_save_context(struct clk_hw
*hw
)
279 struct clk_omap_divider
*divider
= to_clk_omap_divider(hw
);
282 val
= ti_clk_ll_ops
->clk_readl(÷r
->reg
) >> divider
->shift
;
283 divider
->context
= val
& div_mask(divider
);
289 * clk_divider_restore_context - restore the saved the divider value
290 * @hw: pointer struct clk_hw
292 * Restore the saved the divider value
294 static void clk_divider_restore_context(struct clk_hw
*hw
)
296 struct clk_omap_divider
*divider
= to_clk_omap_divider(hw
);
299 val
= ti_clk_ll_ops
->clk_readl(÷r
->reg
);
300 val
&= ~(div_mask(divider
) << divider
->shift
);
301 val
|= divider
->context
<< divider
->shift
;
302 ti_clk_ll_ops
->clk_writel(val
, ÷r
->reg
);
305 const struct clk_ops ti_clk_divider_ops
= {
306 .recalc_rate
= ti_clk_divider_recalc_rate
,
307 .round_rate
= ti_clk_divider_round_rate
,
308 .set_rate
= ti_clk_divider_set_rate
,
309 .save_context
= clk_divider_save_context
,
310 .restore_context
= clk_divider_restore_context
,
313 static struct clk
*_register_divider(struct device
*dev
, const char *name
,
314 const char *parent_name
,
316 struct clk_omap_reg
*reg
,
317 u8 shift
, u8 width
, s8 latch
,
318 u8 clk_divider_flags
,
319 const struct clk_div_table
*table
)
321 struct clk_omap_divider
*div
;
323 struct clk_init_data init
;
325 if (clk_divider_flags
& CLK_DIVIDER_HIWORD_MASK
) {
326 if (width
+ shift
> 16) {
327 pr_warn("divider value exceeds LOWORD field\n");
328 return ERR_PTR(-EINVAL
);
332 /* allocate the divider */
333 div
= kzalloc(sizeof(*div
), GFP_KERNEL
);
335 return ERR_PTR(-ENOMEM
);
338 init
.ops
= &ti_clk_divider_ops
;
339 init
.flags
= flags
| CLK_IS_BASIC
;
340 init
.parent_names
= (parent_name
? &parent_name
: NULL
);
341 init
.num_parents
= (parent_name
? 1 : 0);
343 /* struct clk_divider assignments */
344 memcpy(&div
->reg
, reg
, sizeof(*reg
));
348 div
->flags
= clk_divider_flags
;
349 div
->hw
.init
= &init
;
352 /* register the clock */
353 clk
= ti_clk_register(dev
, &div
->hw
, name
);
361 int ti_clk_parse_divider_data(int *div_table
, int num_dividers
, int max_div
,
363 const struct clk_div_table
**table
)
369 struct clk_div_table
*tmp
;
372 if (flags
& CLKF_INDEX_STARTS_AT_ONE
)
379 while (div
< max_div
) {
380 if (flags
& CLKF_INDEX_POWER_OF_TWO
)
395 while (!num_dividers
|| i
< num_dividers
) {
396 if (div_table
[i
] == -1)
405 tmp
= kcalloc(valid_div
+ 1, sizeof(*tmp
), GFP_KERNEL
);
407 *table
= ERR_PTR(-ENOMEM
);
414 for (i
= 0; i
< num_dividers
; i
++)
415 if (div_table
[i
] > 0) {
416 tmp
[valid_div
].div
= div_table
[i
];
417 tmp
[valid_div
].val
= i
;
422 *width
= fls(*width
);
428 static const struct clk_div_table
*
429 _get_div_table_from_setup(struct ti_clk_divider
*setup
, u8
*width
)
431 const struct clk_div_table
*table
= NULL
;
433 ti_clk_parse_divider_data(setup
->dividers
, setup
->num_dividers
,
434 setup
->max_div
, setup
->flags
, width
,
440 struct clk_hw
*ti_clk_build_component_div(struct ti_clk_divider
*setup
)
442 struct clk_omap_divider
*div
;
443 struct clk_omap_reg
*reg
;
449 div
= kzalloc(sizeof(*div
), GFP_KERNEL
);
451 return ERR_PTR(-ENOMEM
);
453 reg
= (struct clk_omap_reg
*)&div
->reg
;
454 reg
->index
= setup
->module
;
455 reg
->offset
= setup
->reg
;
457 if (setup
->flags
& CLKF_INDEX_STARTS_AT_ONE
)
458 div
->flags
|= CLK_DIVIDER_ONE_BASED
;
460 if (setup
->flags
& CLKF_INDEX_POWER_OF_TWO
)
461 div
->flags
|= CLK_DIVIDER_POWER_OF_TWO
;
463 div
->table
= _get_div_table_from_setup(setup
, &div
->width
);
464 if (IS_ERR(div
->table
)) {
465 ret
= PTR_ERR(div
->table
);
471 div
->shift
= setup
->bit_shift
;
472 div
->latch
= -EINVAL
;
477 struct clk
*ti_clk_register_divider(struct ti_clk
*setup
)
479 struct ti_clk_divider
*div
= setup
->data
;
480 struct clk_omap_reg reg
= {
481 .index
= div
->module
,
487 const struct clk_div_table
*table
;
490 if (div
->flags
& CLKF_INDEX_STARTS_AT_ONE
)
491 div_flags
|= CLK_DIVIDER_ONE_BASED
;
493 if (div
->flags
& CLKF_INDEX_POWER_OF_TWO
)
494 div_flags
|= CLK_DIVIDER_POWER_OF_TWO
;
496 if (div
->flags
& CLKF_SET_RATE_PARENT
)
497 flags
|= CLK_SET_RATE_PARENT
;
499 table
= _get_div_table_from_setup(div
, &width
);
501 return (struct clk
*)table
;
503 clk
= _register_divider(NULL
, setup
->name
, div
->parent
,
504 flags
, ®
, div
->bit_shift
,
505 width
, -EINVAL
, div_flags
, table
);
513 static struct clk_div_table
*
514 __init
ti_clk_get_div_table(struct device_node
*node
)
516 struct clk_div_table
*table
;
517 const __be32
*divspec
;
523 divspec
= of_get_property(node
, "ti,dividers", &num_div
);
532 /* Determine required size for divider table */
533 for (i
= 0; i
< num_div
; i
++) {
534 of_property_read_u32_index(node
, "ti,dividers", i
, &val
);
540 pr_err("no valid dividers for %pOFn table\n", node
);
541 return ERR_PTR(-EINVAL
);
544 table
= kcalloc(valid_div
+ 1, sizeof(*table
), GFP_KERNEL
);
547 return ERR_PTR(-ENOMEM
);
551 for (i
= 0; i
< num_div
; i
++) {
552 of_property_read_u32_index(node
, "ti,dividers", i
, &val
);
554 table
[valid_div
].div
= val
;
555 table
[valid_div
].val
= i
;
563 static int _get_divider_width(struct device_node
*node
,
564 const struct clk_div_table
*table
,
573 /* Clk divider table not provided, determine min/max divs */
574 if (of_property_read_u32(node
, "ti,min-div", &min_div
))
577 if (of_property_read_u32(node
, "ti,max-div", &max_div
)) {
578 pr_err("no max-div for %pOFn!\n", node
);
582 /* Determine bit width for the field */
583 if (flags
& CLK_DIVIDER_ONE_BASED
)
588 while (div
< max_div
) {
589 if (flags
& CLK_DIVIDER_POWER_OF_TWO
)
598 while (table
[div
].div
) {
599 val
= table
[div
].val
;
607 static int __init
ti_clk_divider_populate(struct device_node
*node
,
608 struct clk_omap_reg
*reg
, const struct clk_div_table
**table
,
609 u32
*flags
, u8
*div_flags
, u8
*width
, u8
*shift
, s8
*latch
)
614 ret
= ti_clk_get_reg_addr(node
, 0, reg
);
618 if (!of_property_read_u32(node
, "ti,bit-shift", &val
))
624 if (!of_property_read_u32(node
, "ti,latch-bit", &val
))
633 if (of_property_read_bool(node
, "ti,index-starts-at-one"))
634 *div_flags
|= CLK_DIVIDER_ONE_BASED
;
636 if (of_property_read_bool(node
, "ti,index-power-of-two"))
637 *div_flags
|= CLK_DIVIDER_POWER_OF_TWO
;
639 if (of_property_read_bool(node
, "ti,set-rate-parent"))
640 *flags
|= CLK_SET_RATE_PARENT
;
642 *table
= ti_clk_get_div_table(node
);
645 return PTR_ERR(*table
);
647 *width
= _get_divider_width(node
, *table
, *div_flags
);
653 * of_ti_divider_clk_setup - Setup function for simple div rate clock
654 * @node: device node for this clock
656 * Sets up a basic divider clock.
658 static void __init
of_ti_divider_clk_setup(struct device_node
*node
)
661 const char *parent_name
;
662 struct clk_omap_reg reg
;
663 u8 clk_divider_flags
= 0;
667 const struct clk_div_table
*table
= NULL
;
670 parent_name
= of_clk_get_parent_name(node
, 0);
672 if (ti_clk_divider_populate(node
, ®
, &table
, &flags
,
673 &clk_divider_flags
, &width
, &shift
, &latch
))
676 clk
= _register_divider(NULL
, node
->name
, parent_name
, flags
, ®
,
677 shift
, width
, latch
, clk_divider_flags
, table
);
680 of_clk_add_provider(node
, of_clk_src_simple_get
, clk
);
681 of_ti_clk_autoidle_setup(node
);
688 CLK_OF_DECLARE(divider_clk
, "ti,divider-clock", of_ti_divider_clk_setup
);
690 static void __init
of_ti_composite_divider_clk_setup(struct device_node
*node
)
692 struct clk_omap_divider
*div
;
695 div
= kzalloc(sizeof(*div
), GFP_KERNEL
);
699 if (ti_clk_divider_populate(node
, &div
->reg
, &div
->table
, &val
,
700 &div
->flags
, &div
->width
, &div
->shift
,
704 if (!ti_clk_add_component(node
, &div
->hw
, CLK_COMPONENT_TYPE_DIVIDER
))
711 CLK_OF_DECLARE(ti_composite_divider_clk
, "ti,composite-divider-clock",
712 of_ti_composite_divider_clk_setup
);