drivers/clk/ti/mux.c

   1 /*
   2  * TI Multiplexer Clock
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * Tero Kristo <t-kristo@ti.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13  * kind, whether express or implied; without even the implied warranty
  14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/clk-provider.h>
  19 #include <linux/slab.h>
  20 #include <linux/err.h>
  21 #include <linux/of.h>
  22 #include <linux/of_address.h>
  23 #include <linux/clk/ti.h>
  24 #include "clock.h"
  25
  26 #undef pr_fmt
  27 #define pr_fmt(fmt) "%s: " fmt, __func__
  28
  29 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
  30
  31 static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
  32 {
  33         struct clk_mux *mux = to_clk_mux(hw);
  34         int num_parents = clk_hw_get_num_parents(hw);
  35         u32 val;
  36
  37         /*
  38          * FIXME need a mux-specific flag to determine if val is bitwise or
  39          * numeric. e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges
  40          * from 0x1 to 0x7 (index starts at one)
  41          * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
  42          * val = 0x4 really means "bit 2, index starts at bit 0"
  43          */
  44         val = ti_clk_ll_ops->clk_readl(mux->reg) >> mux->shift;
  45         val &= mux->mask;
  46
  47         if (mux->table) {
  48                 int i;
  49
  50                 for (i = 0; i < num_parents; i++)
  51                         if (mux->table[i] == val)
  52                                 return i;
  53                 return -EINVAL;
  54         }
  55
  56         if (val && (mux->flags & CLK_MUX_INDEX_BIT))
  57                 val = ffs(val) - 1;
  58
  59         if (val && (mux->flags & CLK_MUX_INDEX_ONE))
  60                 val--;
  61
  62         if (val >= num_parents)
  63                 return -EINVAL;
  64
  65         return val;
  66 }
  67
  68 static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
  69 {
  70         struct clk_mux *mux = to_clk_mux(hw);
  71         u32 val;
  72         unsigned long flags = 0;
  73
  74         if (mux->table) {
  75                 index = mux->table[index];
  76         } else {
  77                 if (mux->flags & CLK_MUX_INDEX_BIT)
  78                         index = (1 << ffs(index));
  79
  80                 if (mux->flags & CLK_MUX_INDEX_ONE)
  81                         index++;
  82         }
  83
  84         if (mux->lock)
  85                 spin_lock_irqsave(mux->lock, flags);
  86
  87         if (mux->flags & CLK_MUX_HIWORD_MASK) {
  88                 val = mux->mask << (mux->shift + 16);
  89         } else {
  90                 val = ti_clk_ll_ops->clk_readl(mux->reg);
  91                 val &= ~(mux->mask << mux->shift);
  92         }
  93         val |= index << mux->shift;
  94         ti_clk_ll_ops->clk_writel(val, mux->reg);
  95
  96         if (mux->lock)
  97                 spin_unlock_irqrestore(mux->lock, flags);
  98
  99         return 0;
 100 }
 101
 102 const struct clk_ops ti_clk_mux_ops = {
 103         .get_parent = ti_clk_mux_get_parent,
 104         .set_parent = ti_clk_mux_set_parent,
 105         .determine_rate = __clk_mux_determine_rate,
 106 };
 107
 108 static struct clk *_register_mux(struct device *dev, const char *name,
 109                                  const char **parent_names, u8 num_parents,
 110                                  unsigned long flags, void __iomem *reg,
 111                                  u8 shift, u32 mask, u8 clk_mux_flags,
 112                                  u32 *table, spinlock_t *lock)
 113 {
 114         struct clk_mux *mux;
 115         struct clk *clk;
 116         struct clk_init_data init;
 117
 118         /* allocate the mux */
 119         mux = kzalloc(sizeof(*mux), GFP_KERNEL);
 120         if (!mux) {
 121                 pr_err("%s: could not allocate mux clk\n", __func__);
 122                 return ERR_PTR(-ENOMEM);
 123         }
 124
 125         init.name = name;
 126         init.ops = &ti_clk_mux_ops;
 127         init.flags = flags | CLK_IS_BASIC;
 128         init.parent_names = parent_names;
 129         init.num_parents = num_parents;
 130
 131         /* struct clk_mux assignments */
 132         mux->reg = reg;
 133         mux->shift = shift;
 134         mux->mask = mask;
 135         mux->flags = clk_mux_flags;
 136         mux->lock = lock;
 137         mux->table = table;
 138         mux->hw.init = &init;
 139
 140         clk = clk_register(dev, &mux->hw);
 141
 142         if (IS_ERR(clk))
 143                 kfree(mux);
 144
 145         return clk;
 146 }
 147
 148 struct clk *ti_clk_register_mux(struct ti_clk *setup)
 149 {
 150         struct ti_clk_mux *mux;
 151         u32 flags;
 152         u8 mux_flags = 0;
 153         struct clk_omap_reg *reg_setup;
 154         u32 reg;
 155         u32 mask;
 156
 157         reg_setup = (struct clk_omap_reg *)&reg;
 158
 159         mux = setup->data;
 160         flags = CLK_SET_RATE_NO_REPARENT;
 161
 162         mask = mux->num_parents;
 163         if (!(mux->flags & CLKF_INDEX_STARTS_AT_ONE))
 164                 mask--;
 165
 166         mask = (1 << fls(mask)) - 1;
 167         reg_setup->index = mux->module;
 168         reg_setup->offset = mux->reg;
 169
 170         if (mux->flags & CLKF_INDEX_STARTS_AT_ONE)
 171                 mux_flags |= CLK_MUX_INDEX_ONE;
 172
 173         if (mux->flags & CLKF_SET_RATE_PARENT)
 174                 flags |= CLK_SET_RATE_PARENT;
 175
 176         return _register_mux(NULL, setup->name, mux->parents, mux->num_parents,
 177                              flags, (void __iomem *)reg, mux->bit_shift, mask,
 178                              mux_flags, NULL, NULL);
 179 }
 180
 181 /**
 182  * of_mux_clk_setup - Setup function for simple mux rate clock
 183  * @node: DT node for the clock
 184  *
 185  * Sets up a basic clock multiplexer.
 186  */
 187 static void of_mux_clk_setup(struct device_node *node)
 188 {
 189         struct clk *clk;
 190         void __iomem *reg;
 191         int num_parents;
 192         const char **parent_names;
 193         u8 clk_mux_flags = 0;
 194         u32 mask = 0;
 195         u32 shift = 0;
 196         u32 flags = CLK_SET_RATE_NO_REPARENT;
 197
 198         num_parents = of_clk_get_parent_count(node);
 199         if (num_parents < 2) {
 200                 pr_err("mux-clock %s must have parents\n", node->name);
 201                 return;
 202         }
 203         parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
 204         if (!parent_names)
 205                 goto cleanup;
 206
 207         of_clk_parent_fill(node, parent_names, num_parents);
 208
 209         reg = ti_clk_get_reg_addr(node, 0);
 210
 211         if (IS_ERR(reg))
 212                 goto cleanup;
 213
 214         of_property_read_u32(node, "ti,bit-shift", &shift);
 215
 216         if (of_property_read_bool(node, "ti,index-starts-at-one"))
 217                 clk_mux_flags |= CLK_MUX_INDEX_ONE;
 218
 219         if (of_property_read_bool(node, "ti,set-rate-parent"))
 220                 flags |= CLK_SET_RATE_PARENT;
 221
 222         /* Generate bit-mask based on parent info */
 223         mask = num_parents;
 224         if (!(clk_mux_flags & CLK_MUX_INDEX_ONE))
 225                 mask--;
 226
 227         mask = (1 << fls(mask)) - 1;
 228
 229         clk = _register_mux(NULL, node->name, parent_names, num_parents,
 230                             flags, reg, shift, mask, clk_mux_flags, NULL,
 231                             NULL);
 232
 233         if (!IS_ERR(clk))
 234                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
 235
 236 cleanup:
 237         kfree(parent_names);
 238 }
 239 CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup);
 240
 241 struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup)
 242 {
 243         struct clk_mux *mux;
 244         struct clk_omap_reg *reg;
 245         int num_parents;
 246
 247         if (!setup)
 248                 return NULL;
 249
 250         mux = kzalloc(sizeof(*mux), GFP_KERNEL);
 251         if (!mux)
 252                 return ERR_PTR(-ENOMEM);
 253
 254         reg = (struct clk_omap_reg *)&mux->reg;
 255
 256         mux->shift = setup->bit_shift;
 257
 258         reg->index = setup->module;
 259         reg->offset = setup->reg;
 260
 261         if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
 262                 mux->flags |= CLK_MUX_INDEX_ONE;
 263
 264         num_parents = setup->num_parents;
 265
 266         mux->mask = num_parents - 1;
 267         mux->mask = (1 << fls(mux->mask)) - 1;
 268
 269         return &mux->hw;
 270 }
 271
 272 static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
 273 {
 274         struct clk_mux *mux;
 275         int num_parents;
 276         u32 val;
 277
 278         mux = kzalloc(sizeof(*mux), GFP_KERNEL);
 279         if (!mux)
 280                 return;
 281
 282         mux->reg = ti_clk_get_reg_addr(node, 0);
 283
 284         if (IS_ERR(mux->reg))
 285                 goto cleanup;
 286
 287         if (!of_property_read_u32(node, "ti,bit-shift", &val))
 288                 mux->shift = val;
 289
 290         if (of_property_read_bool(node, "ti,index-starts-at-one"))
 291                 mux->flags |= CLK_MUX_INDEX_ONE;
 292
 293         num_parents = of_clk_get_parent_count(node);
 294
 295         if (num_parents < 2) {
 296                 pr_err("%s must have parents\n", node->name);
 297                 goto cleanup;
 298         }
 299
 300         mux->mask = num_parents - 1;
 301         mux->mask = (1 << fls(mux->mask)) - 1;
 302
 303         if (!ti_clk_add_component(node, &mux->hw, CLK_COMPONENT_TYPE_MUX))
 304                 return;
 305
 306 cleanup:
 307         kfree(mux);
 308 }
 309 CLK_OF_DECLARE(ti_composite_mux_clk_setup, "ti,composite-mux-clock",
 310                of_ti_composite_mux_clk_setup);