2 * Zynq clock controller
4 * Copyright (C) 2012 - 2013 Xilinx
6 * Sören Brinkmann <soren.brinkmann@xilinx.com>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License v2 as published by
10 * the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/clk/zynq.h>
22 #include <linux/clk-provider.h>
24 #include <linux/of_address.h>
25 #include <linux/slab.h>
26 #include <linux/string.h>
29 static void __iomem
*zynq_clkc_base
;
31 #define SLCR_ARMPLL_CTRL (zynq_clkc_base + 0x00)
32 #define SLCR_DDRPLL_CTRL (zynq_clkc_base + 0x04)
33 #define SLCR_IOPLL_CTRL (zynq_clkc_base + 0x08)
34 #define SLCR_PLL_STATUS (zynq_clkc_base + 0x0c)
35 #define SLCR_ARM_CLK_CTRL (zynq_clkc_base + 0x20)
36 #define SLCR_DDR_CLK_CTRL (zynq_clkc_base + 0x24)
37 #define SLCR_DCI_CLK_CTRL (zynq_clkc_base + 0x28)
38 #define SLCR_APER_CLK_CTRL (zynq_clkc_base + 0x2c)
39 #define SLCR_GEM0_CLK_CTRL (zynq_clkc_base + 0x40)
40 #define SLCR_GEM1_CLK_CTRL (zynq_clkc_base + 0x44)
41 #define SLCR_SMC_CLK_CTRL (zynq_clkc_base + 0x48)
42 #define SLCR_LQSPI_CLK_CTRL (zynq_clkc_base + 0x4c)
43 #define SLCR_SDIO_CLK_CTRL (zynq_clkc_base + 0x50)
44 #define SLCR_UART_CLK_CTRL (zynq_clkc_base + 0x54)
45 #define SLCR_SPI_CLK_CTRL (zynq_clkc_base + 0x58)
46 #define SLCR_CAN_CLK_CTRL (zynq_clkc_base + 0x5c)
47 #define SLCR_CAN_MIOCLK_CTRL (zynq_clkc_base + 0x60)
48 #define SLCR_DBG_CLK_CTRL (zynq_clkc_base + 0x64)
49 #define SLCR_PCAP_CLK_CTRL (zynq_clkc_base + 0x68)
50 #define SLCR_FPGA0_CLK_CTRL (zynq_clkc_base + 0x70)
51 #define SLCR_621_TRUE (zynq_clkc_base + 0xc4)
52 #define SLCR_SWDT_CLK_SEL (zynq_clkc_base + 0x204)
54 #define NUM_MIO_PINS 54
56 #define DBG_CLK_CTRL_CLKACT_TRC BIT(0)
57 #define DBG_CLK_CTRL_CPU_1XCLKACT BIT(1)
60 armpll
, ddrpll
, iopll
,
61 cpu_6or4x
, cpu_3or2x
, cpu_2x
, cpu_1x
,
63 lqspi
, smc
, pcap
, gem0
, gem1
, fclk0
, fclk1
, fclk2
, fclk3
, can0
, can1
,
64 sdio0
, sdio1
, uart0
, uart1
, spi0
, spi1
, dma
,
65 usb0_aper
, usb1_aper
, gem0_aper
, gem1_aper
,
66 sdio0_aper
, sdio1_aper
, spi0_aper
, spi1_aper
, can0_aper
, can1_aper
,
67 i2c0_aper
, i2c1_aper
, uart0_aper
, uart1_aper
, gpio_aper
, lqspi_aper
,
68 smc_aper
, swdt
, dbg_trc
, dbg_apb
, clk_max
};
70 static struct clk
*ps_clk
;
71 static struct clk
*clks
[clk_max
];
72 static struct clk_onecell_data clk_data
;
74 static DEFINE_SPINLOCK(armpll_lock
);
75 static DEFINE_SPINLOCK(ddrpll_lock
);
76 static DEFINE_SPINLOCK(iopll_lock
);
77 static DEFINE_SPINLOCK(armclk_lock
);
78 static DEFINE_SPINLOCK(swdtclk_lock
);
79 static DEFINE_SPINLOCK(ddrclk_lock
);
80 static DEFINE_SPINLOCK(dciclk_lock
);
81 static DEFINE_SPINLOCK(gem0clk_lock
);
82 static DEFINE_SPINLOCK(gem1clk_lock
);
83 static DEFINE_SPINLOCK(canclk_lock
);
84 static DEFINE_SPINLOCK(canmioclk_lock
);
85 static DEFINE_SPINLOCK(dbgclk_lock
);
86 static DEFINE_SPINLOCK(aperclk_lock
);
88 static const char dummy_nm
[] __initconst
= "dummy_name";
90 static const char *armpll_parents
[] __initdata
= {"armpll_int", "ps_clk"};
91 static const char *ddrpll_parents
[] __initdata
= {"ddrpll_int", "ps_clk"};
92 static const char *iopll_parents
[] __initdata
= {"iopll_int", "ps_clk"};
93 static const char *gem0_mux_parents
[] __initdata
= {"gem0_div1", dummy_nm
};
94 static const char *gem1_mux_parents
[] __initdata
= {"gem1_div1", dummy_nm
};
95 static const char *can0_mio_mux2_parents
[] __initdata
= {"can0_gate",
97 static const char *can1_mio_mux2_parents
[] __initdata
= {"can1_gate",
99 static const char *dbg_emio_mux_parents
[] __initdata
= {"dbg_div",
102 static const char *dbgtrc_emio_input_names
[] __initdata
= {"trace_emio_clk"};
103 static const char *gem0_emio_input_names
[] __initdata
= {"gem0_emio_clk"};
104 static const char *gem1_emio_input_names
[] __initdata
= {"gem1_emio_clk"};
105 static const char *swdt_ext_clk_input_names
[] __initdata
= {"swdt_ext_clk"};
107 static void __init
zynq_clk_register_fclk(enum zynq_clk fclk
,
108 const char *clk_name
, void __iomem
*fclk_ctrl_reg
,
109 const char **parents
, int enable
)
116 spinlock_t
*fclk_lock
;
117 spinlock_t
*fclk_gate_lock
;
118 void __iomem
*fclk_gate_reg
= fclk_ctrl_reg
+ 8;
120 fclk_lock
= kmalloc(sizeof(*fclk_lock
), GFP_KERNEL
);
123 fclk_gate_lock
= kmalloc(sizeof(*fclk_gate_lock
), GFP_KERNEL
);
125 goto err_fclk_gate_lock
;
126 spin_lock_init(fclk_lock
);
127 spin_lock_init(fclk_gate_lock
);
129 mux_name
= kasprintf(GFP_KERNEL
, "%s_mux", clk_name
);
132 div0_name
= kasprintf(GFP_KERNEL
, "%s_div0", clk_name
);
135 div1_name
= kasprintf(GFP_KERNEL
, "%s_div1", clk_name
);
139 clk
= clk_register_mux(NULL
, mux_name
, parents
, 4,
140 CLK_SET_RATE_NO_REPARENT
, fclk_ctrl_reg
, 4, 2, 0,
143 clk
= clk_register_divider(NULL
, div0_name
, mux_name
,
144 0, fclk_ctrl_reg
, 8, 6, CLK_DIVIDER_ONE_BASED
|
145 CLK_DIVIDER_ALLOW_ZERO
, fclk_lock
);
147 clk
= clk_register_divider(NULL
, div1_name
, div0_name
,
148 CLK_SET_RATE_PARENT
, fclk_ctrl_reg
, 20, 6,
149 CLK_DIVIDER_ONE_BASED
| CLK_DIVIDER_ALLOW_ZERO
,
152 clks
[fclk
] = clk_register_gate(NULL
, clk_name
,
153 div1_name
, CLK_SET_RATE_PARENT
, fclk_gate_reg
,
154 0, CLK_GATE_SET_TO_DISABLE
, fclk_gate_lock
);
155 enable_reg
= clk_readl(fclk_gate_reg
) & 1;
156 if (enable
&& !enable_reg
) {
157 if (clk_prepare_enable(clks
[fclk
]))
158 pr_warn("%s: FCLK%u enable failed\n", __func__
,
172 kfree(fclk_gate_lock
);
176 clks
[fclk
] = ERR_PTR(-ENOMEM
);
179 static void __init
zynq_clk_register_periph_clk(enum zynq_clk clk0
,
180 enum zynq_clk clk1
, const char *clk_name0
,
181 const char *clk_name1
, void __iomem
*clk_ctrl
,
182 const char **parents
, unsigned int two_gates
)
189 lock
= kmalloc(sizeof(*lock
), GFP_KERNEL
);
192 spin_lock_init(lock
);
194 mux_name
= kasprintf(GFP_KERNEL
, "%s_mux", clk_name0
);
195 div_name
= kasprintf(GFP_KERNEL
, "%s_div", clk_name0
);
197 clk
= clk_register_mux(NULL
, mux_name
, parents
, 4,
198 CLK_SET_RATE_NO_REPARENT
, clk_ctrl
, 4, 2, 0, lock
);
200 clk
= clk_register_divider(NULL
, div_name
, mux_name
, 0, clk_ctrl
, 8, 6,
201 CLK_DIVIDER_ONE_BASED
| CLK_DIVIDER_ALLOW_ZERO
, lock
);
203 clks
[clk0
] = clk_register_gate(NULL
, clk_name0
, div_name
,
204 CLK_SET_RATE_PARENT
, clk_ctrl
, 0, 0, lock
);
206 clks
[clk1
] = clk_register_gate(NULL
, clk_name1
, div_name
,
207 CLK_SET_RATE_PARENT
, clk_ctrl
, 1, 0, lock
);
215 clks
[clk0
] = ERR_PTR(-ENOMEM
);
217 clks
[clk1
] = ERR_PTR(-ENOMEM
);
220 static void __init
zynq_clk_setup(struct device_node
*np
)
227 unsigned int fclk_enable
= 0;
228 const char *clk_output_name
[clk_max
];
229 const char *cpu_parents
[4];
230 const char *periph_parents
[4];
231 const char *swdt_ext_clk_mux_parents
[2];
232 const char *can_mio_mux_parents
[NUM_MIO_PINS
];
234 pr_info("Zynq clock init\n");
236 /* get clock output names from DT */
237 for (i
= 0; i
< clk_max
; i
++) {
238 if (of_property_read_string_index(np
, "clock-output-names",
239 i
, &clk_output_name
[i
])) {
240 pr_err("%s: clock output name not in DT\n", __func__
);
244 cpu_parents
[0] = clk_output_name
[armpll
];
245 cpu_parents
[1] = clk_output_name
[armpll
];
246 cpu_parents
[2] = clk_output_name
[ddrpll
];
247 cpu_parents
[3] = clk_output_name
[iopll
];
248 periph_parents
[0] = clk_output_name
[iopll
];
249 periph_parents
[1] = clk_output_name
[iopll
];
250 periph_parents
[2] = clk_output_name
[armpll
];
251 periph_parents
[3] = clk_output_name
[ddrpll
];
253 of_property_read_u32(np
, "fclk-enable", &fclk_enable
);
256 ret
= of_property_read_u32(np
, "ps-clk-frequency", &tmp
);
258 pr_warn("ps_clk frequency not specified, using 33 MHz.\n");
261 ps_clk
= clk_register_fixed_rate(NULL
, "ps_clk", NULL
, CLK_IS_ROOT
,
265 clk
= clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL
,
266 SLCR_PLL_STATUS
, 0, &armpll_lock
);
267 clks
[armpll
] = clk_register_mux(NULL
, clk_output_name
[armpll
],
268 armpll_parents
, 2, CLK_SET_RATE_NO_REPARENT
,
269 SLCR_ARMPLL_CTRL
, 4, 1, 0, &armpll_lock
);
271 clk
= clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL
,
272 SLCR_PLL_STATUS
, 1, &ddrpll_lock
);
273 clks
[ddrpll
] = clk_register_mux(NULL
, clk_output_name
[ddrpll
],
274 ddrpll_parents
, 2, CLK_SET_RATE_NO_REPARENT
,
275 SLCR_DDRPLL_CTRL
, 4, 1, 0, &ddrpll_lock
);
277 clk
= clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL
,
278 SLCR_PLL_STATUS
, 2, &iopll_lock
);
279 clks
[iopll
] = clk_register_mux(NULL
, clk_output_name
[iopll
],
280 iopll_parents
, 2, CLK_SET_RATE_NO_REPARENT
,
281 SLCR_IOPLL_CTRL
, 4, 1, 0, &iopll_lock
);
284 tmp
= clk_readl(SLCR_621_TRUE
) & 1;
285 clk
= clk_register_mux(NULL
, "cpu_mux", cpu_parents
, 4,
286 CLK_SET_RATE_NO_REPARENT
, SLCR_ARM_CLK_CTRL
, 4, 2, 0,
288 clk
= clk_register_divider(NULL
, "cpu_div", "cpu_mux", 0,
289 SLCR_ARM_CLK_CTRL
, 8, 6, CLK_DIVIDER_ONE_BASED
|
290 CLK_DIVIDER_ALLOW_ZERO
, &armclk_lock
);
292 clks
[cpu_6or4x
] = clk_register_gate(NULL
, clk_output_name
[cpu_6or4x
],
293 "cpu_div", CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
294 SLCR_ARM_CLK_CTRL
, 24, 0, &armclk_lock
);
296 clk
= clk_register_fixed_factor(NULL
, "cpu_3or2x_div", "cpu_div", 0,
298 clks
[cpu_3or2x
] = clk_register_gate(NULL
, clk_output_name
[cpu_3or2x
],
299 "cpu_3or2x_div", CLK_IGNORE_UNUSED
,
300 SLCR_ARM_CLK_CTRL
, 25, 0, &armclk_lock
);
302 clk
= clk_register_fixed_factor(NULL
, "cpu_2x_div", "cpu_div", 0, 1,
304 clks
[cpu_2x
] = clk_register_gate(NULL
, clk_output_name
[cpu_2x
],
305 "cpu_2x_div", CLK_IGNORE_UNUSED
, SLCR_ARM_CLK_CTRL
,
306 26, 0, &armclk_lock
);
308 clk
= clk_register_fixed_factor(NULL
, "cpu_1x_div", "cpu_div", 0, 1,
310 clks
[cpu_1x
] = clk_register_gate(NULL
, clk_output_name
[cpu_1x
],
311 "cpu_1x_div", CLK_IGNORE_UNUSED
, SLCR_ARM_CLK_CTRL
, 27,
315 swdt_ext_clk_mux_parents
[0] = clk_output_name
[cpu_1x
];
316 for (i
= 0; i
< ARRAY_SIZE(swdt_ext_clk_input_names
); i
++) {
317 int idx
= of_property_match_string(np
, "clock-names",
318 swdt_ext_clk_input_names
[i
]);
320 swdt_ext_clk_mux_parents
[i
+ 1] =
321 of_clk_get_parent_name(np
, idx
);
323 swdt_ext_clk_mux_parents
[i
+ 1] = dummy_nm
;
325 clks
[swdt
] = clk_register_mux(NULL
, clk_output_name
[swdt
],
326 swdt_ext_clk_mux_parents
, 2, CLK_SET_RATE_PARENT
|
327 CLK_SET_RATE_NO_REPARENT
, SLCR_SWDT_CLK_SEL
, 0, 1, 0,
331 clk
= clk_register_divider(NULL
, "ddr2x_div", "ddrpll", 0,
332 SLCR_DDR_CLK_CTRL
, 26, 6, CLK_DIVIDER_ONE_BASED
|
333 CLK_DIVIDER_ALLOW_ZERO
, &ddrclk_lock
);
334 clks
[ddr2x
] = clk_register_gate(NULL
, clk_output_name
[ddr2x
],
335 "ddr2x_div", 0, SLCR_DDR_CLK_CTRL
, 1, 0, &ddrclk_lock
);
336 clk_prepare_enable(clks
[ddr2x
]);
337 clk
= clk_register_divider(NULL
, "ddr3x_div", "ddrpll", 0,
338 SLCR_DDR_CLK_CTRL
, 20, 6, CLK_DIVIDER_ONE_BASED
|
339 CLK_DIVIDER_ALLOW_ZERO
, &ddrclk_lock
);
340 clks
[ddr3x
] = clk_register_gate(NULL
, clk_output_name
[ddr3x
],
341 "ddr3x_div", 0, SLCR_DDR_CLK_CTRL
, 0, 0, &ddrclk_lock
);
342 clk_prepare_enable(clks
[ddr3x
]);
344 clk
= clk_register_divider(NULL
, "dci_div0", "ddrpll", 0,
345 SLCR_DCI_CLK_CTRL
, 8, 6, CLK_DIVIDER_ONE_BASED
|
346 CLK_DIVIDER_ALLOW_ZERO
, &dciclk_lock
);
347 clk
= clk_register_divider(NULL
, "dci_div1", "dci_div0",
348 CLK_SET_RATE_PARENT
, SLCR_DCI_CLK_CTRL
, 20, 6,
349 CLK_DIVIDER_ONE_BASED
| CLK_DIVIDER_ALLOW_ZERO
,
351 clks
[dci
] = clk_register_gate(NULL
, clk_output_name
[dci
], "dci_div1",
352 CLK_SET_RATE_PARENT
, SLCR_DCI_CLK_CTRL
, 0, 0,
354 clk_prepare_enable(clks
[dci
]);
356 /* Peripheral clocks */
357 for (i
= fclk0
; i
<= fclk3
; i
++) {
358 int enable
= !!(fclk_enable
& BIT(i
- fclk0
));
359 zynq_clk_register_fclk(i
, clk_output_name
[i
],
360 SLCR_FPGA0_CLK_CTRL
+ 0x10 * (i
- fclk0
),
361 periph_parents
, enable
);
364 zynq_clk_register_periph_clk(lqspi
, 0, clk_output_name
[lqspi
], NULL
,
365 SLCR_LQSPI_CLK_CTRL
, periph_parents
, 0);
367 zynq_clk_register_periph_clk(smc
, 0, clk_output_name
[smc
], NULL
,
368 SLCR_SMC_CLK_CTRL
, periph_parents
, 0);
370 zynq_clk_register_periph_clk(pcap
, 0, clk_output_name
[pcap
], NULL
,
371 SLCR_PCAP_CLK_CTRL
, periph_parents
, 0);
373 zynq_clk_register_periph_clk(sdio0
, sdio1
, clk_output_name
[sdio0
],
374 clk_output_name
[sdio1
], SLCR_SDIO_CLK_CTRL
,
377 zynq_clk_register_periph_clk(uart0
, uart1
, clk_output_name
[uart0
],
378 clk_output_name
[uart1
], SLCR_UART_CLK_CTRL
,
381 zynq_clk_register_periph_clk(spi0
, spi1
, clk_output_name
[spi0
],
382 clk_output_name
[spi1
], SLCR_SPI_CLK_CTRL
,
385 for (i
= 0; i
< ARRAY_SIZE(gem0_emio_input_names
); i
++) {
386 int idx
= of_property_match_string(np
, "clock-names",
387 gem0_emio_input_names
[i
]);
389 gem0_mux_parents
[i
+ 1] = of_clk_get_parent_name(np
,
392 clk
= clk_register_mux(NULL
, "gem0_mux", periph_parents
, 4,
393 CLK_SET_RATE_NO_REPARENT
, SLCR_GEM0_CLK_CTRL
, 4, 2, 0,
395 clk
= clk_register_divider(NULL
, "gem0_div0", "gem0_mux", 0,
396 SLCR_GEM0_CLK_CTRL
, 8, 6, CLK_DIVIDER_ONE_BASED
|
397 CLK_DIVIDER_ALLOW_ZERO
, &gem0clk_lock
);
398 clk
= clk_register_divider(NULL
, "gem0_div1", "gem0_div0",
399 CLK_SET_RATE_PARENT
, SLCR_GEM0_CLK_CTRL
, 20, 6,
400 CLK_DIVIDER_ONE_BASED
| CLK_DIVIDER_ALLOW_ZERO
,
402 clk
= clk_register_mux(NULL
, "gem0_emio_mux", gem0_mux_parents
, 2,
403 CLK_SET_RATE_PARENT
| CLK_SET_RATE_NO_REPARENT
,
404 SLCR_GEM0_CLK_CTRL
, 6, 1, 0,
406 clks
[gem0
] = clk_register_gate(NULL
, clk_output_name
[gem0
],
407 "gem0_emio_mux", CLK_SET_RATE_PARENT
,
408 SLCR_GEM0_CLK_CTRL
, 0, 0, &gem0clk_lock
);
410 for (i
= 0; i
< ARRAY_SIZE(gem1_emio_input_names
); i
++) {
411 int idx
= of_property_match_string(np
, "clock-names",
412 gem1_emio_input_names
[i
]);
414 gem1_mux_parents
[i
+ 1] = of_clk_get_parent_name(np
,
417 clk
= clk_register_mux(NULL
, "gem1_mux", periph_parents
, 4,
418 CLK_SET_RATE_NO_REPARENT
, SLCR_GEM1_CLK_CTRL
, 4, 2, 0,
420 clk
= clk_register_divider(NULL
, "gem1_div0", "gem1_mux", 0,
421 SLCR_GEM1_CLK_CTRL
, 8, 6, CLK_DIVIDER_ONE_BASED
|
422 CLK_DIVIDER_ALLOW_ZERO
, &gem1clk_lock
);
423 clk
= clk_register_divider(NULL
, "gem1_div1", "gem1_div0",
424 CLK_SET_RATE_PARENT
, SLCR_GEM1_CLK_CTRL
, 20, 6,
425 CLK_DIVIDER_ONE_BASED
| CLK_DIVIDER_ALLOW_ZERO
,
427 clk
= clk_register_mux(NULL
, "gem1_emio_mux", gem1_mux_parents
, 2,
428 CLK_SET_RATE_PARENT
| CLK_SET_RATE_NO_REPARENT
,
429 SLCR_GEM1_CLK_CTRL
, 6, 1, 0,
431 clks
[gem1
] = clk_register_gate(NULL
, clk_output_name
[gem1
],
432 "gem1_emio_mux", CLK_SET_RATE_PARENT
,
433 SLCR_GEM1_CLK_CTRL
, 0, 0, &gem1clk_lock
);
435 tmp
= strlen("mio_clk_00x");
436 clk_name
= kmalloc(tmp
, GFP_KERNEL
);
437 for (i
= 0; i
< NUM_MIO_PINS
; i
++) {
440 snprintf(clk_name
, tmp
, "mio_clk_%2.2d", i
);
441 idx
= of_property_match_string(np
, "clock-names", clk_name
);
443 can_mio_mux_parents
[i
] = of_clk_get_parent_name(np
,
446 can_mio_mux_parents
[i
] = dummy_nm
;
449 clk
= clk_register_mux(NULL
, "can_mux", periph_parents
, 4,
450 CLK_SET_RATE_NO_REPARENT
, SLCR_CAN_CLK_CTRL
, 4, 2, 0,
452 clk
= clk_register_divider(NULL
, "can_div0", "can_mux", 0,
453 SLCR_CAN_CLK_CTRL
, 8, 6, CLK_DIVIDER_ONE_BASED
|
454 CLK_DIVIDER_ALLOW_ZERO
, &canclk_lock
);
455 clk
= clk_register_divider(NULL
, "can_div1", "can_div0",
456 CLK_SET_RATE_PARENT
, SLCR_CAN_CLK_CTRL
, 20, 6,
457 CLK_DIVIDER_ONE_BASED
| CLK_DIVIDER_ALLOW_ZERO
,
459 clk
= clk_register_gate(NULL
, "can0_gate", "can_div1",
460 CLK_SET_RATE_PARENT
, SLCR_CAN_CLK_CTRL
, 0, 0,
462 clk
= clk_register_gate(NULL
, "can1_gate", "can_div1",
463 CLK_SET_RATE_PARENT
, SLCR_CAN_CLK_CTRL
, 1, 0,
465 clk
= clk_register_mux(NULL
, "can0_mio_mux",
466 can_mio_mux_parents
, 54, CLK_SET_RATE_PARENT
|
467 CLK_SET_RATE_NO_REPARENT
, SLCR_CAN_MIOCLK_CTRL
, 0, 6, 0,
469 clk
= clk_register_mux(NULL
, "can1_mio_mux",
470 can_mio_mux_parents
, 54, CLK_SET_RATE_PARENT
|
471 CLK_SET_RATE_NO_REPARENT
, SLCR_CAN_MIOCLK_CTRL
, 16, 6,
473 clks
[can0
] = clk_register_mux(NULL
, clk_output_name
[can0
],
474 can0_mio_mux2_parents
, 2, CLK_SET_RATE_PARENT
|
475 CLK_SET_RATE_NO_REPARENT
, SLCR_CAN_MIOCLK_CTRL
, 6, 1, 0,
477 clks
[can1
] = clk_register_mux(NULL
, clk_output_name
[can1
],
478 can1_mio_mux2_parents
, 2, CLK_SET_RATE_PARENT
|
479 CLK_SET_RATE_NO_REPARENT
, SLCR_CAN_MIOCLK_CTRL
, 22, 1,
482 for (i
= 0; i
< ARRAY_SIZE(dbgtrc_emio_input_names
); i
++) {
483 int idx
= of_property_match_string(np
, "clock-names",
484 dbgtrc_emio_input_names
[i
]);
486 dbg_emio_mux_parents
[i
+ 1] = of_clk_get_parent_name(np
,
489 clk
= clk_register_mux(NULL
, "dbg_mux", periph_parents
, 4,
490 CLK_SET_RATE_NO_REPARENT
, SLCR_DBG_CLK_CTRL
, 4, 2, 0,
492 clk
= clk_register_divider(NULL
, "dbg_div", "dbg_mux", 0,
493 SLCR_DBG_CLK_CTRL
, 8, 6, CLK_DIVIDER_ONE_BASED
|
494 CLK_DIVIDER_ALLOW_ZERO
, &dbgclk_lock
);
495 clk
= clk_register_mux(NULL
, "dbg_emio_mux", dbg_emio_mux_parents
, 2,
496 CLK_SET_RATE_NO_REPARENT
, SLCR_DBG_CLK_CTRL
, 6, 1, 0,
498 clks
[dbg_trc
] = clk_register_gate(NULL
, clk_output_name
[dbg_trc
],
499 "dbg_emio_mux", CLK_SET_RATE_PARENT
, SLCR_DBG_CLK_CTRL
,
501 clks
[dbg_apb
] = clk_register_gate(NULL
, clk_output_name
[dbg_apb
],
502 clk_output_name
[cpu_1x
], 0, SLCR_DBG_CLK_CTRL
, 1, 0,
505 /* leave debug clocks in the state the bootloader set them up to */
506 tmp
= clk_readl(SLCR_DBG_CLK_CTRL
);
507 if (tmp
& DBG_CLK_CTRL_CLKACT_TRC
)
508 if (clk_prepare_enable(clks
[dbg_trc
]))
509 pr_warn("%s: trace clk enable failed\n", __func__
);
510 if (tmp
& DBG_CLK_CTRL_CPU_1XCLKACT
)
511 if (clk_prepare_enable(clks
[dbg_apb
]))
512 pr_warn("%s: debug APB clk enable failed\n", __func__
);
514 /* One gated clock for all APER clocks. */
515 clks
[dma
] = clk_register_gate(NULL
, clk_output_name
[dma
],
516 clk_output_name
[cpu_2x
], 0, SLCR_APER_CLK_CTRL
, 0, 0,
518 clks
[usb0_aper
] = clk_register_gate(NULL
, clk_output_name
[usb0_aper
],
519 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 2, 0,
521 clks
[usb1_aper
] = clk_register_gate(NULL
, clk_output_name
[usb1_aper
],
522 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 3, 0,
524 clks
[gem0_aper
] = clk_register_gate(NULL
, clk_output_name
[gem0_aper
],
525 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 6, 0,
527 clks
[gem1_aper
] = clk_register_gate(NULL
, clk_output_name
[gem1_aper
],
528 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 7, 0,
530 clks
[sdio0_aper
] = clk_register_gate(NULL
, clk_output_name
[sdio0_aper
],
531 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 10, 0,
533 clks
[sdio1_aper
] = clk_register_gate(NULL
, clk_output_name
[sdio1_aper
],
534 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 11, 0,
536 clks
[spi0_aper
] = clk_register_gate(NULL
, clk_output_name
[spi0_aper
],
537 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 14, 0,
539 clks
[spi1_aper
] = clk_register_gate(NULL
, clk_output_name
[spi1_aper
],
540 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 15, 0,
542 clks
[can0_aper
] = clk_register_gate(NULL
, clk_output_name
[can0_aper
],
543 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 16, 0,
545 clks
[can1_aper
] = clk_register_gate(NULL
, clk_output_name
[can1_aper
],
546 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 17, 0,
548 clks
[i2c0_aper
] = clk_register_gate(NULL
, clk_output_name
[i2c0_aper
],
549 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 18, 0,
551 clks
[i2c1_aper
] = clk_register_gate(NULL
, clk_output_name
[i2c1_aper
],
552 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 19, 0,
554 clks
[uart0_aper
] = clk_register_gate(NULL
, clk_output_name
[uart0_aper
],
555 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 20, 0,
557 clks
[uart1_aper
] = clk_register_gate(NULL
, clk_output_name
[uart1_aper
],
558 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 21, 0,
560 clks
[gpio_aper
] = clk_register_gate(NULL
, clk_output_name
[gpio_aper
],
561 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 22, 0,
563 clks
[lqspi_aper
] = clk_register_gate(NULL
, clk_output_name
[lqspi_aper
],
564 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 23, 0,
566 clks
[smc_aper
] = clk_register_gate(NULL
, clk_output_name
[smc_aper
],
567 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 24, 0,
570 for (i
= 0; i
< ARRAY_SIZE(clks
); i
++) {
571 if (IS_ERR(clks
[i
])) {
572 pr_err("Zynq clk %d: register failed with %ld\n",
573 i
, PTR_ERR(clks
[i
]));
578 clk_data
.clks
= clks
;
579 clk_data
.clk_num
= ARRAY_SIZE(clks
);
580 of_clk_add_provider(np
, of_clk_src_onecell_get
, &clk_data
);
583 CLK_OF_DECLARE(zynq_clkc
, "xlnx,ps7-clkc", zynq_clk_setup
);
585 void __init
zynq_clock_init(void)
587 struct device_node
*np
;
588 struct device_node
*slcr
;
591 np
= of_find_compatible_node(NULL
, NULL
, "xlnx,ps7-clkc");
593 pr_err("%s: clkc node not found\n", __func__
);
597 if (of_address_to_resource(np
, 0, &res
)) {
598 pr_err("%s: failed to get resource\n", np
->name
);
602 slcr
= of_get_parent(np
);
605 zynq_clkc_base
= (__force
void __iomem
*)slcr
->data
+ res
.start
;
607 pr_err("%s: Unable to get I/O memory\n", np
->name
);
612 pr_info("%s: clkc starts at %p\n", __func__
, zynq_clkc_base
);