1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC clock controller
5 * Copyright (C) 2016-2018 Xilinx
7 * Based on drivers/clk/zynq/clkc.c
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/module.h>
14 #include <linux/of_platform.h>
15 #include <linux/slab.h>
16 #include <linux/string.h>
18 #include "clk-zynqmp.h"
20 #define MAX_PARENT 100
22 #define MAX_NAME_LEN 50
24 #define CLK_TYPE_SHIFT 2
26 #define PM_API_PAYLOAD_LEN 3
28 #define NA_PARENT 0xFFFFFFFF
29 #define DUMMY_PARENT 0xFFFFFFFE
31 #define CLK_TYPE_FIELD_LEN 4
32 #define CLK_TOPOLOGY_NODE_OFFSET 16
33 #define NODES_PER_RESP 3
35 #define CLK_TYPE_FIELD_MASK 0xF
36 #define CLK_FLAG_FIELD_MASK GENMASK(21, 8)
37 #define CLK_TYPE_FLAG_FIELD_MASK GENMASK(31, 24)
39 #define CLK_PARENTS_ID_LEN 16
40 #define CLK_PARENTS_ID_MASK 0xFFFF
42 /* Flags for parents */
43 #define PARENT_CLK_SELF 0
44 #define PARENT_CLK_NODE1 1
45 #define PARENT_CLK_NODE2 2
46 #define PARENT_CLK_NODE3 3
47 #define PARENT_CLK_NODE4 4
48 #define PARENT_CLK_EXTERNAL 5
50 #define END_OF_CLK_NAME "END_OF_CLK"
51 #define END_OF_TOPOLOGY_NODE 1
52 #define END_OF_PARENTS 1
53 #define RESERVED_CLK_NAME ""
55 #define CLK_VALID_MASK 0x1
63 * struct clock_parent - Clock parent
65 * @id: Parent clock ID
69 char name
[MAX_NAME_LEN
];
75 * struct zynqmp_clock - Clock
76 * @clk_name: Clock name
77 * @valid: Validity flag of clock
78 * @type: Clock type (Output/External)
79 * @node: Clock topology nodes
80 * @num_nodes: Number of nodes present in topology
81 * @parent: Parent of clock
82 * @num_parents: Number of parents of clock
85 char clk_name
[MAX_NAME_LEN
];
88 struct clock_topology node
[MAX_NODES
];
90 struct clock_parent parent
[MAX_PARENT
];
94 static const char clk_type_postfix
[][10] = {
98 [TYPE_DIV1
] = "_div1",
99 [TYPE_DIV2
] = "_div2",
100 [TYPE_FIXEDFACTOR
] = "_ff",
104 static struct clk_hw
*(* const clk_topology
[]) (const char *name
, u32 clk_id
,
105 const char * const *parents
,
107 const struct clock_topology
*nodes
)
109 [TYPE_INVALID
] = NULL
,
110 [TYPE_MUX
] = zynqmp_clk_register_mux
,
111 [TYPE_PLL
] = zynqmp_clk_register_pll
,
112 [TYPE_FIXEDFACTOR
] = zynqmp_clk_register_fixed_factor
,
113 [TYPE_DIV1
] = zynqmp_clk_register_divider
,
114 [TYPE_DIV2
] = zynqmp_clk_register_divider
,
115 [TYPE_GATE
] = zynqmp_clk_register_gate
118 static struct zynqmp_clock
*clock
;
119 static struct clk_hw_onecell_data
*zynqmp_data
;
120 static unsigned int clock_max_idx
;
121 static const struct zynqmp_eemi_ops
*eemi_ops
;
124 * zynqmp_is_valid_clock() - Check whether clock is valid or not
125 * @clk_id: Clock index
127 * Return: 1 if clock is valid, 0 if clock is invalid else error code
129 static inline int zynqmp_is_valid_clock(u32 clk_id
)
131 if (clk_id
>= clock_max_idx
)
134 return clock
[clk_id
].valid
;
138 * zynqmp_get_clock_name() - Get name of clock from Clock index
139 * @clk_id: Clock index
140 * @clk_name: Name of clock
142 * Return: 0 on success else error code
144 static int zynqmp_get_clock_name(u32 clk_id
, char *clk_name
)
148 ret
= zynqmp_is_valid_clock(clk_id
);
150 strncpy(clk_name
, clock
[clk_id
].clk_name
, MAX_NAME_LEN
);
154 return ret
== 0 ? -EINVAL
: ret
;
158 * zynqmp_get_clock_type() - Get type of clock
159 * @clk_id: Clock index
160 * @type: Clock type: CLK_TYPE_OUTPUT or CLK_TYPE_EXTERNAL
162 * Return: 0 on success else error code
164 static int zynqmp_get_clock_type(u32 clk_id
, u32
*type
)
168 ret
= zynqmp_is_valid_clock(clk_id
);
170 *type
= clock
[clk_id
].type
;
174 return ret
== 0 ? -EINVAL
: ret
;
178 * zynqmp_pm_clock_get_num_clocks() - Get number of clocks in system
179 * @nclocks: Number of clocks in system/board.
181 * Call firmware API to get number of clocks.
183 * Return: 0 on success else error code.
185 static int zynqmp_pm_clock_get_num_clocks(u32
*nclocks
)
187 struct zynqmp_pm_query_data qdata
= {0};
188 u32 ret_payload
[PAYLOAD_ARG_CNT
];
191 qdata
.qid
= PM_QID_CLOCK_GET_NUM_CLOCKS
;
193 ret
= eemi_ops
->query_data(qdata
, ret_payload
);
194 *nclocks
= ret_payload
[1];
200 * zynqmp_pm_clock_get_name() - Get the name of clock for given id
201 * @clock_id: ID of the clock to be queried
202 * @name: Name of given clock
204 * This function is used to get name of clock specified by given
207 * Return: Returns 0, in case of error name would be 0
209 static int zynqmp_pm_clock_get_name(u32 clock_id
, char *name
)
211 struct zynqmp_pm_query_data qdata
= {0};
212 u32 ret_payload
[PAYLOAD_ARG_CNT
];
214 qdata
.qid
= PM_QID_CLOCK_GET_NAME
;
215 qdata
.arg1
= clock_id
;
217 eemi_ops
->query_data(qdata
, ret_payload
);
218 memcpy(name
, ret_payload
, CLK_GET_NAME_RESP_LEN
);
224 * zynqmp_pm_clock_get_topology() - Get the topology of clock for given id
225 * @clock_id: ID of the clock to be queried
226 * @index: Node index of clock topology
227 * @topology: Buffer to store nodes in topology and flags
229 * This function is used to get topology information for the clock
230 * specified by given clock ID.
232 * This API will return 3 node of topology with a single response. To get
233 * other nodes, master should call same API in loop with new
234 * index till error is returned. E.g First call should have
235 * index 0 which will return nodes 0,1 and 2. Next call, index
236 * should be 3 which will return nodes 3,4 and 5 and so on.
238 * Return: 0 on success else error+reason
240 static int zynqmp_pm_clock_get_topology(u32 clock_id
, u32 index
, u32
*topology
)
242 struct zynqmp_pm_query_data qdata
= {0};
243 u32 ret_payload
[PAYLOAD_ARG_CNT
];
246 qdata
.qid
= PM_QID_CLOCK_GET_TOPOLOGY
;
247 qdata
.arg1
= clock_id
;
250 ret
= eemi_ops
->query_data(qdata
, ret_payload
);
251 memcpy(topology
, &ret_payload
[1], CLK_GET_TOPOLOGY_RESP_WORDS
* 4);
257 * zynqmp_clk_register_fixed_factor() - Register fixed factor with the
259 * @name: Name of this clock
261 * @parents: Name of this clock's parents
262 * @num_parents: Number of parents
263 * @nodes: Clock topology node
265 * Return: clock hardware to the registered clock
267 struct clk_hw
*zynqmp_clk_register_fixed_factor(const char *name
, u32 clk_id
,
268 const char * const *parents
,
270 const struct clock_topology
*nodes
)
274 struct zynqmp_pm_query_data qdata
= {0};
275 u32 ret_payload
[PAYLOAD_ARG_CNT
];
278 qdata
.qid
= PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS
;
281 ret
= eemi_ops
->query_data(qdata
, ret_payload
);
285 mult
= ret_payload
[1];
286 div
= ret_payload
[2];
288 hw
= clk_hw_register_fixed_factor(NULL
, name
,
297 * zynqmp_pm_clock_get_parents() - Get the first 3 parents of clock for given id
298 * @clock_id: Clock ID
299 * @index: Parent index
300 * @parents: 3 parents of the given clock
302 * This function is used to get 3 parents for the clock specified by
305 * This API will return 3 parents with a single response. To get
306 * other parents, master should call same API in loop with new
307 * parent index till error is returned. E.g First call should have
308 * index 0 which will return parents 0,1 and 2. Next call, index
309 * should be 3 which will return parent 3,4 and 5 and so on.
311 * Return: 0 on success else error+reason
313 static int zynqmp_pm_clock_get_parents(u32 clock_id
, u32 index
, u32
*parents
)
315 struct zynqmp_pm_query_data qdata
= {0};
316 u32 ret_payload
[PAYLOAD_ARG_CNT
];
319 qdata
.qid
= PM_QID_CLOCK_GET_PARENTS
;
320 qdata
.arg1
= clock_id
;
323 ret
= eemi_ops
->query_data(qdata
, ret_payload
);
324 memcpy(parents
, &ret_payload
[1], CLK_GET_PARENTS_RESP_WORDS
* 4);
330 * zynqmp_pm_clock_get_attributes() - Get the attributes of clock for given id
331 * @clock_id: Clock ID
332 * @attr: Clock attributes
334 * This function is used to get clock's attributes(e.g. valid, clock type, etc).
336 * Return: 0 on success else error+reason
338 static int zynqmp_pm_clock_get_attributes(u32 clock_id
, u32
*attr
)
340 struct zynqmp_pm_query_data qdata
= {0};
341 u32 ret_payload
[PAYLOAD_ARG_CNT
];
344 qdata
.qid
= PM_QID_CLOCK_GET_ATTRIBUTES
;
345 qdata
.arg1
= clock_id
;
347 ret
= eemi_ops
->query_data(qdata
, ret_payload
);
348 memcpy(attr
, &ret_payload
[1], CLK_GET_ATTR_RESP_WORDS
* 4);
354 * __zynqmp_clock_get_topology() - Get topology data of clock from firmware
356 * @topology: Clock topology
357 * @data: Clock topology data received from firmware
358 * @nnodes: Number of nodes
360 * Return: 0 on success else error+reason
362 static int __zynqmp_clock_get_topology(struct clock_topology
*topology
,
363 u32
*data
, u32
*nnodes
)
367 for (i
= 0; i
< PM_API_PAYLOAD_LEN
; i
++) {
368 if (!(data
[i
] & CLK_TYPE_FIELD_MASK
))
369 return END_OF_TOPOLOGY_NODE
;
370 topology
[*nnodes
].type
= data
[i
] & CLK_TYPE_FIELD_MASK
;
371 topology
[*nnodes
].flag
= FIELD_GET(CLK_FLAG_FIELD_MASK
,
373 topology
[*nnodes
].type_flag
=
374 FIELD_GET(CLK_TYPE_FLAG_FIELD_MASK
, data
[i
]);
382 * zynqmp_clock_get_topology() - Get topology of clock from firmware using
384 * @clk_id: Clock index
385 * @topology: Clock topology
386 * @num_nodes: Number of nodes
388 * Return: 0 on success else error+reason
390 static int zynqmp_clock_get_topology(u32 clk_id
,
391 struct clock_topology
*topology
,
395 u32 pm_resp
[PM_API_PAYLOAD_LEN
] = {0};
398 for (j
= 0; j
<= MAX_NODES
; j
+= 3) {
399 ret
= zynqmp_pm_clock_get_topology(clk_id
, j
, pm_resp
);
402 ret
= __zynqmp_clock_get_topology(topology
, pm_resp
, num_nodes
);
403 if (ret
== END_OF_TOPOLOGY_NODE
)
411 * __zynqmp_clock_get_topology() - Get parents info of clock from firmware
413 * @parents: Clock parents
414 * @data: Clock parents data received from firmware
415 * @nparent: Number of parent
417 * Return: 0 on success else error+reason
419 static int __zynqmp_clock_get_parents(struct clock_parent
*parents
, u32
*data
,
423 struct clock_parent
*parent
;
425 for (i
= 0; i
< PM_API_PAYLOAD_LEN
; i
++) {
426 if (data
[i
] == NA_PARENT
)
427 return END_OF_PARENTS
;
429 parent
= &parents
[i
];
430 parent
->id
= data
[i
] & CLK_PARENTS_ID_MASK
;
431 if (data
[i
] == DUMMY_PARENT
) {
432 strcpy(parent
->name
, "dummy_name");
435 parent
->flag
= data
[i
] >> CLK_PARENTS_ID_LEN
;
436 if (zynqmp_get_clock_name(parent
->id
, parent
->name
))
446 * zynqmp_clock_get_parents() - Get parents info from firmware using PM_API
447 * @clk_id: Clock index
448 * @parents: Clock parents
449 * @num_parents: Total number of parents
451 * Return: 0 on success else error+reason
453 static int zynqmp_clock_get_parents(u32 clk_id
, struct clock_parent
*parents
,
457 u32 pm_resp
[PM_API_PAYLOAD_LEN
] = {0};
461 /* Get parents from firmware */
462 ret
= zynqmp_pm_clock_get_parents(clk_id
, j
, pm_resp
);
466 ret
= __zynqmp_clock_get_parents(&parents
[j
], pm_resp
,
468 if (ret
== END_OF_PARENTS
)
470 j
+= PM_API_PAYLOAD_LEN
;
471 } while (*num_parents
<= MAX_PARENT
);
477 * zynqmp_get_parent_list() - Create list of parents name
479 * @clk_id: Clock index
480 * @parent_list: List of parent's name
481 * @num_parents: Total number of parents
483 * Return: 0 on success else error+reason
485 static int zynqmp_get_parent_list(struct device_node
*np
, u32 clk_id
,
486 const char **parent_list
, u32
*num_parents
)
489 u32 total_parents
= clock
[clk_id
].num_parents
;
490 struct clock_topology
*clk_nodes
;
491 struct clock_parent
*parents
;
493 clk_nodes
= clock
[clk_id
].node
;
494 parents
= clock
[clk_id
].parent
;
496 for (i
= 0; i
< total_parents
; i
++) {
497 if (!parents
[i
].flag
) {
498 parent_list
[i
] = parents
[i
].name
;
499 } else if (parents
[i
].flag
== PARENT_CLK_EXTERNAL
) {
500 ret
= of_property_match_string(np
, "clock-names",
503 strcpy(parents
[i
].name
, "dummy_name");
504 parent_list
[i
] = parents
[i
].name
;
506 strcat(parents
[i
].name
,
507 clk_type_postfix
[clk_nodes
[parents
[i
].flag
- 1].
509 parent_list
[i
] = parents
[i
].name
;
513 *num_parents
= total_parents
;
518 * zynqmp_register_clk_topology() - Register clock topology
519 * @clk_id: Clock index
520 * @clk_name: Clock Name
521 * @num_parents: Total number of parents
522 * @parent_names: List of parents name
524 * Return: Returns either clock hardware or error+reason
526 static struct clk_hw
*zynqmp_register_clk_topology(int clk_id
, char *clk_name
,
528 const char **parent_names
)
532 char *clk_out
= NULL
;
533 struct clock_topology
*nodes
;
534 struct clk_hw
*hw
= NULL
;
536 nodes
= clock
[clk_id
].node
;
537 num_nodes
= clock
[clk_id
].num_nodes
;
539 for (j
= 0; j
< num_nodes
; j
++) {
541 * Clock name received from firmware is output clock name.
542 * Intermediate clock names are postfixed with type of clock.
544 if (j
!= (num_nodes
- 1)) {
545 clk_out
= kasprintf(GFP_KERNEL
, "%s%s", clk_name
,
546 clk_type_postfix
[nodes
[j
].type
]);
548 clk_out
= kasprintf(GFP_KERNEL
, "%s", clk_name
);
551 if (!clk_topology
[nodes
[j
].type
])
554 hw
= (*clk_topology
[nodes
[j
].type
])(clk_out
, clk_id
,
559 pr_warn_once("%s() %s register fail with %ld\n",
560 __func__
, clk_name
, PTR_ERR(hw
));
562 parent_names
[0] = clk_out
;
569 * zynqmp_register_clocks() - Register clocks
572 * Return: 0 on success else error code
574 static int zynqmp_register_clocks(struct device_node
*np
)
577 u32 i
, total_parents
= 0, type
= 0;
578 const char *parent_names
[MAX_PARENT
];
580 for (i
= 0; i
< clock_max_idx
; i
++) {
581 char clk_name
[MAX_NAME_LEN
];
583 /* get clock name, continue to next clock if name not found */
584 if (zynqmp_get_clock_name(i
, clk_name
))
587 /* Check if clock is valid and output clock.
588 * Do not register invalid or external clock.
590 ret
= zynqmp_get_clock_type(i
, &type
);
591 if (ret
|| type
!= CLK_TYPE_OUTPUT
)
594 /* Get parents of clock*/
595 if (zynqmp_get_parent_list(np
, i
, parent_names
,
597 WARN_ONCE(1, "No parents found for %s\n",
602 zynqmp_data
->hws
[i
] =
603 zynqmp_register_clk_topology(i
, clk_name
,
608 for (i
= 0; i
< clock_max_idx
; i
++) {
609 if (IS_ERR(zynqmp_data
->hws
[i
])) {
610 pr_err("Zynq Ultrascale+ MPSoC clk %s: register failed with %ld\n",
611 clock
[i
].clk_name
, PTR_ERR(zynqmp_data
->hws
[i
]));
619 * zynqmp_get_clock_info() - Get clock information from firmware using PM_API
621 static void zynqmp_get_clock_info(void)
626 for (i
= 0; i
< clock_max_idx
; i
++) {
627 zynqmp_pm_clock_get_name(i
, clock
[i
].clk_name
);
628 if (!strcmp(clock
[i
].clk_name
, RESERVED_CLK_NAME
))
631 ret
= zynqmp_pm_clock_get_attributes(i
, &attr
);
635 clock
[i
].valid
= attr
& CLK_VALID_MASK
;
636 clock
[i
].type
= attr
>> CLK_TYPE_SHIFT
? CLK_TYPE_EXTERNAL
:
640 /* Get topology of all clock */
641 for (i
= 0; i
< clock_max_idx
; i
++) {
642 ret
= zynqmp_get_clock_type(i
, &type
);
643 if (ret
|| type
!= CLK_TYPE_OUTPUT
)
646 ret
= zynqmp_clock_get_topology(i
, clock
[i
].node
,
647 &clock
[i
].num_nodes
);
651 ret
= zynqmp_clock_get_parents(i
, clock
[i
].parent
,
652 &clock
[i
].num_parents
);
659 * zynqmp_clk_setup() - Setup the clock framework and register clocks
662 * Return: 0 on success else error code
664 static int zynqmp_clk_setup(struct device_node
*np
)
668 ret
= zynqmp_pm_clock_get_num_clocks(&clock_max_idx
);
672 zynqmp_data
= kzalloc(struct_size(zynqmp_data
, hws
, clock_max_idx
),
677 clock
= kcalloc(clock_max_idx
, sizeof(*clock
), GFP_KERNEL
);
683 zynqmp_get_clock_info();
684 zynqmp_register_clocks(np
);
686 zynqmp_data
->num
= clock_max_idx
;
687 of_clk_add_hw_provider(np
, of_clk_hw_onecell_get
, zynqmp_data
);
692 static int zynqmp_clock_probe(struct platform_device
*pdev
)
695 struct device
*dev
= &pdev
->dev
;
697 eemi_ops
= zynqmp_pm_get_eemi_ops();
701 ret
= zynqmp_clk_setup(dev
->of_node
);
706 static const struct of_device_id zynqmp_clock_of_match
[] = {
707 {.compatible
= "xlnx,zynqmp-clk"},
710 MODULE_DEVICE_TABLE(of
, zynqmp_clock_of_match
);
712 static struct platform_driver zynqmp_clock_driver
= {
714 .name
= "zynqmp_clock",
715 .of_match_table
= zynqmp_clock_of_match
,
717 .probe
= zynqmp_clock_probe
,
719 module_platform_driver(zynqmp_clock_driver
);