2 * linux/drivers/clocksource/arm_arch_timer.c
4 * Copyright (C) 2011 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #define pr_fmt(fmt) "arm_arch_timer: " fmt
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/device.h>
17 #include <linux/smp.h>
18 #include <linux/cpu.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/clockchips.h>
21 #include <linux/clocksource.h>
22 #include <linux/interrupt.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_address.h>
26 #include <linux/slab.h>
27 #include <linux/sched/clock.h>
28 #include <linux/sched_clock.h>
29 #include <linux/acpi.h>
31 #include <asm/arch_timer.h>
34 #include <clocksource/arm_arch_timer.h>
37 #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
39 #define CNTACR(n) (0x40 + ((n) * 4))
40 #define CNTACR_RPCT BIT(0)
41 #define CNTACR_RVCT BIT(1)
42 #define CNTACR_RFRQ BIT(2)
43 #define CNTACR_RVOFF BIT(3)
44 #define CNTACR_RWVT BIT(4)
45 #define CNTACR_RWPT BIT(5)
47 #define CNTVCT_LO 0x08
48 #define CNTVCT_HI 0x0c
50 #define CNTP_TVAL 0x28
52 #define CNTV_TVAL 0x38
55 #define ARCH_CP15_TIMER BIT(0)
56 #define ARCH_MEM_TIMER BIT(1)
57 static unsigned arch_timers_present __initdata
;
59 static void __iomem
*arch_counter_base
;
63 struct clock_event_device evt
;
66 #define to_arch_timer(e) container_of(e, struct arch_timer, evt)
68 static u32 arch_timer_rate
;
78 static int arch_timer_ppi
[MAX_TIMER_PPI
];
80 static struct clock_event_device __percpu
*arch_timer_evt
;
82 static enum ppi_nr arch_timer_uses_ppi
= VIRT_PPI
;
83 static bool arch_timer_c3stop
;
84 static bool arch_timer_mem_use_virtual
;
85 static bool arch_counter_suspend_stop
;
87 static bool evtstrm_enable
= IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM
);
89 static int __init
early_evtstrm_cfg(char *buf
)
91 return strtobool(buf
, &evtstrm_enable
);
93 early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg
);
96 * Architected system timer support.
99 #ifdef CONFIG_FSL_ERRATUM_A008585
101 * The number of retries is an arbitrary value well beyond the highest number
102 * of iterations the loop has been observed to take.
104 #define __fsl_a008585_read_reg(reg) ({ \
106 int _retries = 200; \
109 _old = read_sysreg(reg); \
110 _new = read_sysreg(reg); \
112 } while (unlikely(_old != _new) && _retries); \
114 WARN_ON_ONCE(!_retries); \
118 static u32 notrace
fsl_a008585_read_cntp_tval_el0(void)
120 return __fsl_a008585_read_reg(cntp_tval_el0
);
123 static u32 notrace
fsl_a008585_read_cntv_tval_el0(void)
125 return __fsl_a008585_read_reg(cntv_tval_el0
);
128 static u64 notrace
fsl_a008585_read_cntvct_el0(void)
130 return __fsl_a008585_read_reg(cntvct_el0
);
134 #ifdef CONFIG_HISILICON_ERRATUM_161010101
136 * Verify whether the value of the second read is larger than the first by
137 * less than 32 is the only way to confirm the value is correct, so clear the
138 * lower 5 bits to check whether the difference is greater than 32 or not.
139 * Theoretically the erratum should not occur more than twice in succession
140 * when reading the system counter, but it is possible that some interrupts
141 * may lead to more than twice read errors, triggering the warning, so setting
142 * the number of retries far beyond the number of iterations the loop has been
145 #define __hisi_161010101_read_reg(reg) ({ \
150 _old = read_sysreg(reg); \
151 _new = read_sysreg(reg); \
153 } while (unlikely((_new - _old) >> 5) && _retries); \
155 WARN_ON_ONCE(!_retries); \
159 static u32 notrace
hisi_161010101_read_cntp_tval_el0(void)
161 return __hisi_161010101_read_reg(cntp_tval_el0
);
164 static u32 notrace
hisi_161010101_read_cntv_tval_el0(void)
166 return __hisi_161010101_read_reg(cntv_tval_el0
);
169 static u64 notrace
hisi_161010101_read_cntvct_el0(void)
171 return __hisi_161010101_read_reg(cntvct_el0
);
175 #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
176 const struct arch_timer_erratum_workaround
*timer_unstable_counter_workaround
= NULL
;
177 EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround
);
179 DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled
);
180 EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled
);
182 static const struct arch_timer_erratum_workaround ool_workarounds
[] = {
183 #ifdef CONFIG_FSL_ERRATUM_A008585
185 .match_type
= ate_match_dt
,
186 .id
= "fsl,erratum-a008585",
187 .desc
= "Freescale erratum a005858",
188 .read_cntp_tval_el0
= fsl_a008585_read_cntp_tval_el0
,
189 .read_cntv_tval_el0
= fsl_a008585_read_cntv_tval_el0
,
190 .read_cntvct_el0
= fsl_a008585_read_cntvct_el0
,
193 #ifdef CONFIG_HISILICON_ERRATUM_161010101
195 .match_type
= ate_match_dt
,
196 .id
= "hisilicon,erratum-161010101",
197 .desc
= "HiSilicon erratum 161010101",
198 .read_cntp_tval_el0
= hisi_161010101_read_cntp_tval_el0
,
199 .read_cntv_tval_el0
= hisi_161010101_read_cntv_tval_el0
,
200 .read_cntvct_el0
= hisi_161010101_read_cntvct_el0
,
205 typedef bool (*ate_match_fn_t
)(const struct arch_timer_erratum_workaround
*,
209 bool arch_timer_check_dt_erratum(const struct arch_timer_erratum_workaround
*wa
,
212 const struct device_node
*np
= arg
;
214 return of_property_read_bool(np
, wa
->id
);
218 bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround
*wa
,
221 return this_cpu_has_cap((uintptr_t)wa
->id
);
224 static const struct arch_timer_erratum_workaround
*
225 arch_timer_iterate_errata(enum arch_timer_erratum_match_type type
,
226 ate_match_fn_t match_fn
,
231 for (i
= 0; i
< ARRAY_SIZE(ool_workarounds
); i
++) {
232 if (ool_workarounds
[i
].match_type
!= type
)
235 if (match_fn(&ool_workarounds
[i
], arg
))
236 return &ool_workarounds
[i
];
243 void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround
*wa
)
245 timer_unstable_counter_workaround
= wa
;
246 static_branch_enable(&arch_timer_read_ool_enabled
);
249 static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type type
,
252 const struct arch_timer_erratum_workaround
*wa
;
253 ate_match_fn_t match_fn
= NULL
;
258 match_fn
= arch_timer_check_dt_erratum
;
260 case ate_match_local_cap_id
:
261 match_fn
= arch_timer_check_local_cap_erratum
;
269 wa
= arch_timer_iterate_errata(type
, match_fn
, arg
);
273 if (needs_unstable_timer_counter_workaround()) {
274 if (wa
!= timer_unstable_counter_workaround
)
275 pr_warn("Can't enable workaround for %s (clashes with %s\n)",
277 timer_unstable_counter_workaround
->desc
);
281 arch_timer_enable_workaround(wa
);
282 pr_info("Enabling %s workaround for %s\n",
283 local
? "local" : "global", wa
->desc
);
287 #define arch_timer_check_ool_workaround(t,a) do { } while(0)
288 #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
290 static __always_inline
291 void arch_timer_reg_write(int access
, enum arch_timer_reg reg
, u32 val
,
292 struct clock_event_device
*clk
)
294 if (access
== ARCH_TIMER_MEM_PHYS_ACCESS
) {
295 struct arch_timer
*timer
= to_arch_timer(clk
);
297 case ARCH_TIMER_REG_CTRL
:
298 writel_relaxed(val
, timer
->base
+ CNTP_CTL
);
300 case ARCH_TIMER_REG_TVAL
:
301 writel_relaxed(val
, timer
->base
+ CNTP_TVAL
);
304 } else if (access
== ARCH_TIMER_MEM_VIRT_ACCESS
) {
305 struct arch_timer
*timer
= to_arch_timer(clk
);
307 case ARCH_TIMER_REG_CTRL
:
308 writel_relaxed(val
, timer
->base
+ CNTV_CTL
);
310 case ARCH_TIMER_REG_TVAL
:
311 writel_relaxed(val
, timer
->base
+ CNTV_TVAL
);
315 arch_timer_reg_write_cp15(access
, reg
, val
);
319 static __always_inline
320 u32
arch_timer_reg_read(int access
, enum arch_timer_reg reg
,
321 struct clock_event_device
*clk
)
325 if (access
== ARCH_TIMER_MEM_PHYS_ACCESS
) {
326 struct arch_timer
*timer
= to_arch_timer(clk
);
328 case ARCH_TIMER_REG_CTRL
:
329 val
= readl_relaxed(timer
->base
+ CNTP_CTL
);
331 case ARCH_TIMER_REG_TVAL
:
332 val
= readl_relaxed(timer
->base
+ CNTP_TVAL
);
335 } else if (access
== ARCH_TIMER_MEM_VIRT_ACCESS
) {
336 struct arch_timer
*timer
= to_arch_timer(clk
);
338 case ARCH_TIMER_REG_CTRL
:
339 val
= readl_relaxed(timer
->base
+ CNTV_CTL
);
341 case ARCH_TIMER_REG_TVAL
:
342 val
= readl_relaxed(timer
->base
+ CNTV_TVAL
);
346 val
= arch_timer_reg_read_cp15(access
, reg
);
352 static __always_inline irqreturn_t
timer_handler(const int access
,
353 struct clock_event_device
*evt
)
357 ctrl
= arch_timer_reg_read(access
, ARCH_TIMER_REG_CTRL
, evt
);
358 if (ctrl
& ARCH_TIMER_CTRL_IT_STAT
) {
359 ctrl
|= ARCH_TIMER_CTRL_IT_MASK
;
360 arch_timer_reg_write(access
, ARCH_TIMER_REG_CTRL
, ctrl
, evt
);
361 evt
->event_handler(evt
);
368 static irqreturn_t
arch_timer_handler_virt(int irq
, void *dev_id
)
370 struct clock_event_device
*evt
= dev_id
;
372 return timer_handler(ARCH_TIMER_VIRT_ACCESS
, evt
);
375 static irqreturn_t
arch_timer_handler_phys(int irq
, void *dev_id
)
377 struct clock_event_device
*evt
= dev_id
;
379 return timer_handler(ARCH_TIMER_PHYS_ACCESS
, evt
);
382 static irqreturn_t
arch_timer_handler_phys_mem(int irq
, void *dev_id
)
384 struct clock_event_device
*evt
= dev_id
;
386 return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS
, evt
);
389 static irqreturn_t
arch_timer_handler_virt_mem(int irq
, void *dev_id
)
391 struct clock_event_device
*evt
= dev_id
;
393 return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS
, evt
);
396 static __always_inline
int timer_shutdown(const int access
,
397 struct clock_event_device
*clk
)
401 ctrl
= arch_timer_reg_read(access
, ARCH_TIMER_REG_CTRL
, clk
);
402 ctrl
&= ~ARCH_TIMER_CTRL_ENABLE
;
403 arch_timer_reg_write(access
, ARCH_TIMER_REG_CTRL
, ctrl
, clk
);
408 static int arch_timer_shutdown_virt(struct clock_event_device
*clk
)
410 return timer_shutdown(ARCH_TIMER_VIRT_ACCESS
, clk
);
413 static int arch_timer_shutdown_phys(struct clock_event_device
*clk
)
415 return timer_shutdown(ARCH_TIMER_PHYS_ACCESS
, clk
);
418 static int arch_timer_shutdown_virt_mem(struct clock_event_device
*clk
)
420 return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS
, clk
);
423 static int arch_timer_shutdown_phys_mem(struct clock_event_device
*clk
)
425 return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS
, clk
);
428 static __always_inline
void set_next_event(const int access
, unsigned long evt
,
429 struct clock_event_device
*clk
)
432 ctrl
= arch_timer_reg_read(access
, ARCH_TIMER_REG_CTRL
, clk
);
433 ctrl
|= ARCH_TIMER_CTRL_ENABLE
;
434 ctrl
&= ~ARCH_TIMER_CTRL_IT_MASK
;
435 arch_timer_reg_write(access
, ARCH_TIMER_REG_TVAL
, evt
, clk
);
436 arch_timer_reg_write(access
, ARCH_TIMER_REG_CTRL
, ctrl
, clk
);
439 #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
440 static __always_inline
void erratum_set_next_event_generic(const int access
,
441 unsigned long evt
, struct clock_event_device
*clk
)
444 u64 cval
= evt
+ arch_counter_get_cntvct();
446 ctrl
= arch_timer_reg_read(access
, ARCH_TIMER_REG_CTRL
, clk
);
447 ctrl
|= ARCH_TIMER_CTRL_ENABLE
;
448 ctrl
&= ~ARCH_TIMER_CTRL_IT_MASK
;
450 if (access
== ARCH_TIMER_PHYS_ACCESS
)
451 write_sysreg(cval
, cntp_cval_el0
);
452 else if (access
== ARCH_TIMER_VIRT_ACCESS
)
453 write_sysreg(cval
, cntv_cval_el0
);
455 arch_timer_reg_write(access
, ARCH_TIMER_REG_CTRL
, ctrl
, clk
);
458 static int erratum_set_next_event_virt(unsigned long evt
,
459 struct clock_event_device
*clk
)
461 erratum_set_next_event_generic(ARCH_TIMER_VIRT_ACCESS
, evt
, clk
);
465 static int erratum_set_next_event_phys(unsigned long evt
,
466 struct clock_event_device
*clk
)
468 erratum_set_next_event_generic(ARCH_TIMER_PHYS_ACCESS
, evt
, clk
);
471 #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
473 static int arch_timer_set_next_event_virt(unsigned long evt
,
474 struct clock_event_device
*clk
)
476 set_next_event(ARCH_TIMER_VIRT_ACCESS
, evt
, clk
);
480 static int arch_timer_set_next_event_phys(unsigned long evt
,
481 struct clock_event_device
*clk
)
483 set_next_event(ARCH_TIMER_PHYS_ACCESS
, evt
, clk
);
487 static int arch_timer_set_next_event_virt_mem(unsigned long evt
,
488 struct clock_event_device
*clk
)
490 set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS
, evt
, clk
);
494 static int arch_timer_set_next_event_phys_mem(unsigned long evt
,
495 struct clock_event_device
*clk
)
497 set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS
, evt
, clk
);
501 static void erratum_workaround_set_sne(struct clock_event_device
*clk
)
503 #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
504 if (!static_branch_unlikely(&arch_timer_read_ool_enabled
))
507 if (arch_timer_uses_ppi
== VIRT_PPI
)
508 clk
->set_next_event
= erratum_set_next_event_virt
;
510 clk
->set_next_event
= erratum_set_next_event_phys
;
514 static void __arch_timer_setup(unsigned type
,
515 struct clock_event_device
*clk
)
517 clk
->features
= CLOCK_EVT_FEAT_ONESHOT
;
519 if (type
== ARCH_CP15_TIMER
) {
520 if (arch_timer_c3stop
)
521 clk
->features
|= CLOCK_EVT_FEAT_C3STOP
;
522 clk
->name
= "arch_sys_timer";
524 clk
->cpumask
= cpumask_of(smp_processor_id());
525 clk
->irq
= arch_timer_ppi
[arch_timer_uses_ppi
];
526 switch (arch_timer_uses_ppi
) {
528 clk
->set_state_shutdown
= arch_timer_shutdown_virt
;
529 clk
->set_state_oneshot_stopped
= arch_timer_shutdown_virt
;
530 clk
->set_next_event
= arch_timer_set_next_event_virt
;
532 case PHYS_SECURE_PPI
:
533 case PHYS_NONSECURE_PPI
:
535 clk
->set_state_shutdown
= arch_timer_shutdown_phys
;
536 clk
->set_state_oneshot_stopped
= arch_timer_shutdown_phys
;
537 clk
->set_next_event
= arch_timer_set_next_event_phys
;
543 arch_timer_check_ool_workaround(ate_match_local_cap_id
, NULL
);
545 erratum_workaround_set_sne(clk
);
547 clk
->features
|= CLOCK_EVT_FEAT_DYNIRQ
;
548 clk
->name
= "arch_mem_timer";
550 clk
->cpumask
= cpu_all_mask
;
551 if (arch_timer_mem_use_virtual
) {
552 clk
->set_state_shutdown
= arch_timer_shutdown_virt_mem
;
553 clk
->set_state_oneshot_stopped
= arch_timer_shutdown_virt_mem
;
554 clk
->set_next_event
=
555 arch_timer_set_next_event_virt_mem
;
557 clk
->set_state_shutdown
= arch_timer_shutdown_phys_mem
;
558 clk
->set_state_oneshot_stopped
= arch_timer_shutdown_phys_mem
;
559 clk
->set_next_event
=
560 arch_timer_set_next_event_phys_mem
;
564 clk
->set_state_shutdown(clk
);
566 clockevents_config_and_register(clk
, arch_timer_rate
, 0xf, 0x7fffffff);
569 static void arch_timer_evtstrm_enable(int divider
)
571 u32 cntkctl
= arch_timer_get_cntkctl();
573 cntkctl
&= ~ARCH_TIMER_EVT_TRIGGER_MASK
;
574 /* Set the divider and enable virtual event stream */
575 cntkctl
|= (divider
<< ARCH_TIMER_EVT_TRIGGER_SHIFT
)
576 | ARCH_TIMER_VIRT_EVT_EN
;
577 arch_timer_set_cntkctl(cntkctl
);
578 elf_hwcap
|= HWCAP_EVTSTRM
;
580 compat_elf_hwcap
|= COMPAT_HWCAP_EVTSTRM
;
584 static void arch_timer_configure_evtstream(void)
586 int evt_stream_div
, pos
;
588 /* Find the closest power of two to the divisor */
589 evt_stream_div
= arch_timer_rate
/ ARCH_TIMER_EVT_STREAM_FREQ
;
590 pos
= fls(evt_stream_div
);
591 if (pos
> 1 && !(evt_stream_div
& (1 << (pos
- 2))))
593 /* enable event stream */
594 arch_timer_evtstrm_enable(min(pos
, 15));
597 static void arch_counter_set_user_access(void)
599 u32 cntkctl
= arch_timer_get_cntkctl();
601 /* Disable user access to the timers and the physical counter */
602 /* Also disable virtual event stream */
603 cntkctl
&= ~(ARCH_TIMER_USR_PT_ACCESS_EN
604 | ARCH_TIMER_USR_VT_ACCESS_EN
605 | ARCH_TIMER_VIRT_EVT_EN
606 | ARCH_TIMER_USR_PCT_ACCESS_EN
);
608 /* Enable user access to the virtual counter */
609 cntkctl
|= ARCH_TIMER_USR_VCT_ACCESS_EN
;
611 arch_timer_set_cntkctl(cntkctl
);
614 static bool arch_timer_has_nonsecure_ppi(void)
616 return (arch_timer_uses_ppi
== PHYS_SECURE_PPI
&&
617 arch_timer_ppi
[PHYS_NONSECURE_PPI
]);
620 static u32
check_ppi_trigger(int irq
)
622 u32 flags
= irq_get_trigger_type(irq
);
624 if (flags
!= IRQF_TRIGGER_HIGH
&& flags
!= IRQF_TRIGGER_LOW
) {
625 pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq
);
626 pr_warn("WARNING: Please fix your firmware\n");
627 flags
= IRQF_TRIGGER_LOW
;
633 static int arch_timer_starting_cpu(unsigned int cpu
)
635 struct clock_event_device
*clk
= this_cpu_ptr(arch_timer_evt
);
638 __arch_timer_setup(ARCH_CP15_TIMER
, clk
);
640 flags
= check_ppi_trigger(arch_timer_ppi
[arch_timer_uses_ppi
]);
641 enable_percpu_irq(arch_timer_ppi
[arch_timer_uses_ppi
], flags
);
643 if (arch_timer_has_nonsecure_ppi()) {
644 flags
= check_ppi_trigger(arch_timer_ppi
[PHYS_NONSECURE_PPI
]);
645 enable_percpu_irq(arch_timer_ppi
[PHYS_NONSECURE_PPI
], flags
);
648 arch_counter_set_user_access();
650 arch_timer_configure_evtstream();
656 arch_timer_detect_rate(void __iomem
*cntbase
, struct device_node
*np
)
658 /* Who has more than one independent system counter? */
663 * Try to determine the frequency from the device tree or CNTFRQ,
664 * if ACPI is enabled, get the frequency from CNTFRQ ONLY.
666 if (!acpi_disabled
||
667 of_property_read_u32(np
, "clock-frequency", &arch_timer_rate
)) {
669 arch_timer_rate
= readl_relaxed(cntbase
+ CNTFRQ
);
671 arch_timer_rate
= arch_timer_get_cntfrq();
674 /* Check the timer frequency. */
675 if (arch_timer_rate
== 0)
676 pr_warn("Architected timer frequency not available\n");
679 static void arch_timer_banner(unsigned type
)
681 pr_info("Architected %s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
682 type
& ARCH_CP15_TIMER
? "cp15" : "",
683 type
== (ARCH_CP15_TIMER
| ARCH_MEM_TIMER
) ? " and " : "",
684 type
& ARCH_MEM_TIMER
? "mmio" : "",
685 (unsigned long)arch_timer_rate
/ 1000000,
686 (unsigned long)(arch_timer_rate
/ 10000) % 100,
687 type
& ARCH_CP15_TIMER
?
688 (arch_timer_uses_ppi
== VIRT_PPI
) ? "virt" : "phys" :
690 type
== (ARCH_CP15_TIMER
| ARCH_MEM_TIMER
) ? "/" : "",
691 type
& ARCH_MEM_TIMER
?
692 arch_timer_mem_use_virtual
? "virt" : "phys" :
696 u32
arch_timer_get_rate(void)
698 return arch_timer_rate
;
701 static u64
arch_counter_get_cntvct_mem(void)
703 u32 vct_lo
, vct_hi
, tmp_hi
;
706 vct_hi
= readl_relaxed(arch_counter_base
+ CNTVCT_HI
);
707 vct_lo
= readl_relaxed(arch_counter_base
+ CNTVCT_LO
);
708 tmp_hi
= readl_relaxed(arch_counter_base
+ CNTVCT_HI
);
709 } while (vct_hi
!= tmp_hi
);
711 return ((u64
) vct_hi
<< 32) | vct_lo
;
715 * Default to cp15 based access because arm64 uses this function for
716 * sched_clock() before DT is probed and the cp15 method is guaranteed
717 * to exist on arm64. arm doesn't use this before DT is probed so even
718 * if we don't have the cp15 accessors we won't have a problem.
720 u64 (*arch_timer_read_counter
)(void) = arch_counter_get_cntvct
;
722 static u64
arch_counter_read(struct clocksource
*cs
)
724 return arch_timer_read_counter();
727 static u64
arch_counter_read_cc(const struct cyclecounter
*cc
)
729 return arch_timer_read_counter();
732 static struct clocksource clocksource_counter
= {
733 .name
= "arch_sys_counter",
735 .read
= arch_counter_read
,
736 .mask
= CLOCKSOURCE_MASK(56),
737 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
740 static struct cyclecounter cyclecounter __ro_after_init
= {
741 .read
= arch_counter_read_cc
,
742 .mask
= CLOCKSOURCE_MASK(56),
745 static struct arch_timer_kvm_info arch_timer_kvm_info
;
747 struct arch_timer_kvm_info
*arch_timer_get_kvm_info(void)
749 return &arch_timer_kvm_info
;
752 static void __init
arch_counter_register(unsigned type
)
756 /* Register the CP15 based counter if we have one */
757 if (type
& ARCH_CP15_TIMER
) {
758 if (IS_ENABLED(CONFIG_ARM64
) || arch_timer_uses_ppi
== VIRT_PPI
)
759 arch_timer_read_counter
= arch_counter_get_cntvct
;
761 arch_timer_read_counter
= arch_counter_get_cntpct
;
763 clocksource_counter
.archdata
.vdso_direct
= true;
765 #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
767 * Don't use the vdso fastpath if errata require using
768 * the out-of-line counter accessor.
770 if (static_branch_unlikely(&arch_timer_read_ool_enabled
))
771 clocksource_counter
.archdata
.vdso_direct
= false;
774 arch_timer_read_counter
= arch_counter_get_cntvct_mem
;
777 if (!arch_counter_suspend_stop
)
778 clocksource_counter
.flags
|= CLOCK_SOURCE_SUSPEND_NONSTOP
;
779 start_count
= arch_timer_read_counter();
780 clocksource_register_hz(&clocksource_counter
, arch_timer_rate
);
781 cyclecounter
.mult
= clocksource_counter
.mult
;
782 cyclecounter
.shift
= clocksource_counter
.shift
;
783 timecounter_init(&arch_timer_kvm_info
.timecounter
,
784 &cyclecounter
, start_count
);
786 /* 56 bits minimum, so we assume worst case rollover */
787 sched_clock_register(arch_timer_read_counter
, 56, arch_timer_rate
);
790 static void arch_timer_stop(struct clock_event_device
*clk
)
792 pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
793 clk
->irq
, smp_processor_id());
795 disable_percpu_irq(arch_timer_ppi
[arch_timer_uses_ppi
]);
796 if (arch_timer_has_nonsecure_ppi())
797 disable_percpu_irq(arch_timer_ppi
[PHYS_NONSECURE_PPI
]);
799 clk
->set_state_shutdown(clk
);
802 static int arch_timer_dying_cpu(unsigned int cpu
)
804 struct clock_event_device
*clk
= this_cpu_ptr(arch_timer_evt
);
806 arch_timer_stop(clk
);
811 static unsigned int saved_cntkctl
;
812 static int arch_timer_cpu_pm_notify(struct notifier_block
*self
,
813 unsigned long action
, void *hcpu
)
815 if (action
== CPU_PM_ENTER
)
816 saved_cntkctl
= arch_timer_get_cntkctl();
817 else if (action
== CPU_PM_ENTER_FAILED
|| action
== CPU_PM_EXIT
)
818 arch_timer_set_cntkctl(saved_cntkctl
);
822 static struct notifier_block arch_timer_cpu_pm_notifier
= {
823 .notifier_call
= arch_timer_cpu_pm_notify
,
826 static int __init
arch_timer_cpu_pm_init(void)
828 return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier
);
831 static void __init
arch_timer_cpu_pm_deinit(void)
833 WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier
));
837 static int __init
arch_timer_cpu_pm_init(void)
842 static void __init
arch_timer_cpu_pm_deinit(void)
847 static int __init
arch_timer_register(void)
852 arch_timer_evt
= alloc_percpu(struct clock_event_device
);
853 if (!arch_timer_evt
) {
858 ppi
= arch_timer_ppi
[arch_timer_uses_ppi
];
859 switch (arch_timer_uses_ppi
) {
861 err
= request_percpu_irq(ppi
, arch_timer_handler_virt
,
862 "arch_timer", arch_timer_evt
);
864 case PHYS_SECURE_PPI
:
865 case PHYS_NONSECURE_PPI
:
866 err
= request_percpu_irq(ppi
, arch_timer_handler_phys
,
867 "arch_timer", arch_timer_evt
);
868 if (!err
&& arch_timer_ppi
[PHYS_NONSECURE_PPI
]) {
869 ppi
= arch_timer_ppi
[PHYS_NONSECURE_PPI
];
870 err
= request_percpu_irq(ppi
, arch_timer_handler_phys
,
871 "arch_timer", arch_timer_evt
);
873 free_percpu_irq(arch_timer_ppi
[PHYS_SECURE_PPI
],
878 err
= request_percpu_irq(ppi
, arch_timer_handler_phys
,
879 "arch_timer", arch_timer_evt
);
886 pr_err("arch_timer: can't register interrupt %d (%d)\n",
891 err
= arch_timer_cpu_pm_init();
893 goto out_unreg_notify
;
896 /* Register and immediately configure the timer on the boot CPU */
897 err
= cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING
,
898 "clockevents/arm/arch_timer:starting",
899 arch_timer_starting_cpu
, arch_timer_dying_cpu
);
901 goto out_unreg_cpupm
;
905 arch_timer_cpu_pm_deinit();
908 free_percpu_irq(arch_timer_ppi
[arch_timer_uses_ppi
], arch_timer_evt
);
909 if (arch_timer_has_nonsecure_ppi())
910 free_percpu_irq(arch_timer_ppi
[PHYS_NONSECURE_PPI
],
914 free_percpu(arch_timer_evt
);
919 static int __init
arch_timer_mem_register(void __iomem
*base
, unsigned int irq
)
923 struct arch_timer
*t
;
925 t
= kzalloc(sizeof(*t
), GFP_KERNEL
);
931 __arch_timer_setup(ARCH_MEM_TIMER
, &t
->evt
);
933 if (arch_timer_mem_use_virtual
)
934 func
= arch_timer_handler_virt_mem
;
936 func
= arch_timer_handler_phys_mem
;
938 ret
= request_irq(irq
, func
, IRQF_TIMER
, "arch_mem_timer", &t
->evt
);
940 pr_err("arch_timer: Failed to request mem timer irq\n");
947 static const struct of_device_id arch_timer_of_match
[] __initconst
= {
948 { .compatible
= "arm,armv7-timer", },
949 { .compatible
= "arm,armv8-timer", },
953 static const struct of_device_id arch_timer_mem_of_match
[] __initconst
= {
954 { .compatible
= "arm,armv7-timer-mem", },
959 arch_timer_needs_probing(int type
, const struct of_device_id
*matches
)
961 struct device_node
*dn
;
962 bool needs_probing
= false;
964 dn
= of_find_matching_node(NULL
, matches
);
965 if (dn
&& of_device_is_available(dn
) && !(arch_timers_present
& type
))
966 needs_probing
= true;
969 return needs_probing
;
972 static int __init
arch_timer_common_init(void)
974 unsigned mask
= ARCH_CP15_TIMER
| ARCH_MEM_TIMER
;
976 /* Wait until both nodes are probed if we have two timers */
977 if ((arch_timers_present
& mask
) != mask
) {
978 if (arch_timer_needs_probing(ARCH_MEM_TIMER
, arch_timer_mem_of_match
))
980 if (arch_timer_needs_probing(ARCH_CP15_TIMER
, arch_timer_of_match
))
984 arch_timer_banner(arch_timers_present
);
985 arch_counter_register(arch_timers_present
);
986 return arch_timer_arch_init();
989 static int __init
arch_timer_init(void)
993 * If HYP mode is available, we know that the physical timer
994 * has been configured to be accessible from PL1. Use it, so
995 * that a guest can use the virtual timer instead.
997 * If no interrupt provided for virtual timer, we'll have to
998 * stick to the physical timer. It'd better be accessible...
1000 * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE
1001 * accesses to CNTP_*_EL1 registers are silently redirected to
1002 * their CNTHP_*_EL2 counterparts, and use a different PPI
1005 if (is_hyp_mode_available() || !arch_timer_ppi
[VIRT_PPI
]) {
1008 if (is_kernel_in_hyp_mode()) {
1009 arch_timer_uses_ppi
= HYP_PPI
;
1010 has_ppi
= !!arch_timer_ppi
[HYP_PPI
];
1012 arch_timer_uses_ppi
= PHYS_SECURE_PPI
;
1013 has_ppi
= (!!arch_timer_ppi
[PHYS_SECURE_PPI
] ||
1014 !!arch_timer_ppi
[PHYS_NONSECURE_PPI
]);
1018 pr_warn("arch_timer: No interrupt available, giving up\n");
1023 ret
= arch_timer_register();
1027 ret
= arch_timer_common_init();
1031 arch_timer_kvm_info
.virtual_irq
= arch_timer_ppi
[VIRT_PPI
];
1036 static int __init
arch_timer_of_init(struct device_node
*np
)
1040 if (arch_timers_present
& ARCH_CP15_TIMER
) {
1041 pr_warn("arch_timer: multiple nodes in dt, skipping\n");
1045 arch_timers_present
|= ARCH_CP15_TIMER
;
1046 for (i
= PHYS_SECURE_PPI
; i
< MAX_TIMER_PPI
; i
++)
1047 arch_timer_ppi
[i
] = irq_of_parse_and_map(np
, i
);
1049 arch_timer_detect_rate(NULL
, np
);
1051 arch_timer_c3stop
= !of_property_read_bool(np
, "always-on");
1053 /* Check for globally applicable workarounds */
1054 arch_timer_check_ool_workaround(ate_match_dt
, np
);
1057 * If we cannot rely on firmware initializing the timer registers then
1058 * we should use the physical timers instead.
1060 if (IS_ENABLED(CONFIG_ARM
) &&
1061 of_property_read_bool(np
, "arm,cpu-registers-not-fw-configured"))
1062 arch_timer_uses_ppi
= PHYS_SECURE_PPI
;
1064 /* On some systems, the counter stops ticking when in suspend. */
1065 arch_counter_suspend_stop
= of_property_read_bool(np
,
1066 "arm,no-tick-in-suspend");
1068 return arch_timer_init();
1070 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer
, "arm,armv7-timer", arch_timer_of_init
);
1071 CLOCKSOURCE_OF_DECLARE(armv8_arch_timer
, "arm,armv8-timer", arch_timer_of_init
);
1073 static int __init
arch_timer_mem_init(struct device_node
*np
)
1075 struct device_node
*frame
, *best_frame
= NULL
;
1076 void __iomem
*cntctlbase
, *base
;
1077 unsigned int irq
, ret
= -EINVAL
;
1080 arch_timers_present
|= ARCH_MEM_TIMER
;
1081 cntctlbase
= of_iomap(np
, 0);
1083 pr_err("arch_timer: Can't find CNTCTLBase\n");
1087 cnttidr
= readl_relaxed(cntctlbase
+ CNTTIDR
);
1090 * Try to find a virtual capable frame. Otherwise fall back to a
1091 * physical capable frame.
1093 for_each_available_child_of_node(np
, frame
) {
1097 if (of_property_read_u32(frame
, "frame-number", &n
)) {
1098 pr_err("arch_timer: Missing frame-number\n");
1103 /* Try enabling everything, and see what sticks */
1104 cntacr
= CNTACR_RFRQ
| CNTACR_RWPT
| CNTACR_RPCT
|
1105 CNTACR_RWVT
| CNTACR_RVOFF
| CNTACR_RVCT
;
1106 writel_relaxed(cntacr
, cntctlbase
+ CNTACR(n
));
1107 cntacr
= readl_relaxed(cntctlbase
+ CNTACR(n
));
1109 if ((cnttidr
& CNTTIDR_VIRT(n
)) &&
1110 !(~cntacr
& (CNTACR_RWVT
| CNTACR_RVCT
))) {
1111 of_node_put(best_frame
);
1113 arch_timer_mem_use_virtual
= true;
1117 if (~cntacr
& (CNTACR_RWPT
| CNTACR_RPCT
))
1120 of_node_put(best_frame
);
1121 best_frame
= of_node_get(frame
);
1125 base
= arch_counter_base
= of_io_request_and_map(best_frame
, 0,
1128 pr_err("arch_timer: Can't map frame's registers\n");
1132 if (arch_timer_mem_use_virtual
)
1133 irq
= irq_of_parse_and_map(best_frame
, 1);
1135 irq
= irq_of_parse_and_map(best_frame
, 0);
1139 pr_err("arch_timer: Frame missing %s irq",
1140 arch_timer_mem_use_virtual
? "virt" : "phys");
1144 arch_timer_detect_rate(base
, np
);
1145 ret
= arch_timer_mem_register(base
, irq
);
1149 return arch_timer_common_init();
1151 iounmap(cntctlbase
);
1152 of_node_put(best_frame
);
1155 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem
, "arm,armv7-timer-mem",
1156 arch_timer_mem_init
);
1159 static int __init
map_generic_timer_interrupt(u32 interrupt
, u32 flags
)
1161 int trigger
, polarity
;
1166 trigger
= (flags
& ACPI_GTDT_INTERRUPT_MODE
) ? ACPI_EDGE_SENSITIVE
1167 : ACPI_LEVEL_SENSITIVE
;
1169 polarity
= (flags
& ACPI_GTDT_INTERRUPT_POLARITY
) ? ACPI_ACTIVE_LOW
1172 return acpi_register_gsi(NULL
, interrupt
, trigger
, polarity
);
1175 /* Initialize per-processor generic timer */
1176 static int __init
arch_timer_acpi_init(struct acpi_table_header
*table
)
1178 struct acpi_table_gtdt
*gtdt
;
1180 if (arch_timers_present
& ARCH_CP15_TIMER
) {
1181 pr_warn("arch_timer: already initialized, skipping\n");
1185 gtdt
= container_of(table
, struct acpi_table_gtdt
, header
);
1187 arch_timers_present
|= ARCH_CP15_TIMER
;
1189 arch_timer_ppi
[PHYS_SECURE_PPI
] =
1190 map_generic_timer_interrupt(gtdt
->secure_el1_interrupt
,
1191 gtdt
->secure_el1_flags
);
1193 arch_timer_ppi
[PHYS_NONSECURE_PPI
] =
1194 map_generic_timer_interrupt(gtdt
->non_secure_el1_interrupt
,
1195 gtdt
->non_secure_el1_flags
);
1197 arch_timer_ppi
[VIRT_PPI
] =
1198 map_generic_timer_interrupt(gtdt
->virtual_timer_interrupt
,
1199 gtdt
->virtual_timer_flags
);
1201 arch_timer_ppi
[HYP_PPI
] =
1202 map_generic_timer_interrupt(gtdt
->non_secure_el2_interrupt
,
1203 gtdt
->non_secure_el2_flags
);
1205 /* Get the frequency from CNTFRQ */
1206 arch_timer_detect_rate(NULL
, NULL
);
1208 /* Always-on capability */
1209 arch_timer_c3stop
= !(gtdt
->non_secure_el1_flags
& ACPI_GTDT_ALWAYS_ON
);
1214 CLOCKSOURCE_ACPI_DECLARE(arch_timer
, ACPI_SIG_GTDT
, arch_timer_acpi_init
);