2 * linux/drivers/clocksource/arm_arch_timer.c
4 * Copyright (C) 2011 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #define pr_fmt(fmt) "arm_arch_timer: " fmt
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/device.h>
17 #include <linux/smp.h>
18 #include <linux/cpu.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/clockchips.h>
21 #include <linux/clocksource.h>
22 #include <linux/interrupt.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_address.h>
26 #include <linux/slab.h>
27 #include <linux/sched_clock.h>
28 #include <linux/acpi.h>
30 #include <asm/arch_timer.h>
33 #include <clocksource/arm_arch_timer.h>
36 #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
38 #define CNTACR(n) (0x40 + ((n) * 4))
39 #define CNTACR_RPCT BIT(0)
40 #define CNTACR_RVCT BIT(1)
41 #define CNTACR_RFRQ BIT(2)
42 #define CNTACR_RVOFF BIT(3)
43 #define CNTACR_RWVT BIT(4)
44 #define CNTACR_RWPT BIT(5)
46 #define CNTVCT_LO 0x08
47 #define CNTVCT_HI 0x0c
49 #define CNTP_TVAL 0x28
51 #define CNTV_TVAL 0x38
54 #define ARCH_CP15_TIMER BIT(0)
55 #define ARCH_MEM_TIMER BIT(1)
56 static unsigned arch_timers_present __initdata
;
58 static void __iomem
*arch_counter_base
;
62 struct clock_event_device evt
;
65 #define to_arch_timer(e) container_of(e, struct arch_timer, evt)
67 static u32 arch_timer_rate
;
77 static int arch_timer_ppi
[MAX_TIMER_PPI
];
79 static struct clock_event_device __percpu
*arch_timer_evt
;
81 static enum ppi_nr arch_timer_uses_ppi
= VIRT_PPI
;
82 static bool arch_timer_c3stop
;
83 static bool arch_timer_mem_use_virtual
;
84 static bool arch_counter_suspend_stop
;
86 static bool evtstrm_enable
= IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM
);
88 static int __init
early_evtstrm_cfg(char *buf
)
90 return strtobool(buf
, &evtstrm_enable
);
92 early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg
);
95 * Architected system timer support.
98 #ifdef CONFIG_FSL_ERRATUM_A008585
100 * The number of retries is an arbitrary value well beyond the highest number
101 * of iterations the loop has been observed to take.
103 #define __fsl_a008585_read_reg(reg) ({ \
105 int _retries = 200; \
108 _old = read_sysreg(reg); \
109 _new = read_sysreg(reg); \
111 } while (unlikely(_old != _new) && _retries); \
113 WARN_ON_ONCE(!_retries); \
117 static u32 notrace
fsl_a008585_read_cntp_tval_el0(void)
119 return __fsl_a008585_read_reg(cntp_tval_el0
);
122 static u32 notrace
fsl_a008585_read_cntv_tval_el0(void)
124 return __fsl_a008585_read_reg(cntv_tval_el0
);
127 static u64 notrace
fsl_a008585_read_cntvct_el0(void)
129 return __fsl_a008585_read_reg(cntvct_el0
);
133 #ifdef CONFIG_HISILICON_ERRATUM_161010101
135 * Verify whether the value of the second read is larger than the first by
136 * less than 32 is the only way to confirm the value is correct, so clear the
137 * lower 5 bits to check whether the difference is greater than 32 or not.
138 * Theoretically the erratum should not occur more than twice in succession
139 * when reading the system counter, but it is possible that some interrupts
140 * may lead to more than twice read errors, triggering the warning, so setting
141 * the number of retries far beyond the number of iterations the loop has been
144 #define __hisi_161010101_read_reg(reg) ({ \
149 _old = read_sysreg(reg); \
150 _new = read_sysreg(reg); \
152 } while (unlikely((_new - _old) >> 5) && _retries); \
154 WARN_ON_ONCE(!_retries); \
158 static u32 notrace
hisi_161010101_read_cntp_tval_el0(void)
160 return __hisi_161010101_read_reg(cntp_tval_el0
);
163 static u32 notrace
hisi_161010101_read_cntv_tval_el0(void)
165 return __hisi_161010101_read_reg(cntv_tval_el0
);
168 static u64 notrace
hisi_161010101_read_cntvct_el0(void)
170 return __hisi_161010101_read_reg(cntvct_el0
);
174 #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
175 const struct arch_timer_erratum_workaround
*timer_unstable_counter_workaround
= NULL
;
176 EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround
);
178 DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled
);
179 EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled
);
181 static const struct arch_timer_erratum_workaround ool_workarounds
[] = {
182 #ifdef CONFIG_FSL_ERRATUM_A008585
184 .match_type
= ate_match_dt
,
185 .id
= "fsl,erratum-a008585",
186 .desc
= "Freescale erratum a005858",
187 .read_cntp_tval_el0
= fsl_a008585_read_cntp_tval_el0
,
188 .read_cntv_tval_el0
= fsl_a008585_read_cntv_tval_el0
,
189 .read_cntvct_el0
= fsl_a008585_read_cntvct_el0
,
192 #ifdef CONFIG_HISILICON_ERRATUM_161010101
194 .match_type
= ate_match_dt
,
195 .id
= "hisilicon,erratum-161010101",
196 .desc
= "HiSilicon erratum 161010101",
197 .read_cntp_tval_el0
= hisi_161010101_read_cntp_tval_el0
,
198 .read_cntv_tval_el0
= hisi_161010101_read_cntv_tval_el0
,
199 .read_cntvct_el0
= hisi_161010101_read_cntvct_el0
,
204 typedef bool (*ate_match_fn_t
)(const struct arch_timer_erratum_workaround
*,
208 bool arch_timer_check_dt_erratum(const struct arch_timer_erratum_workaround
*wa
,
211 const struct device_node
*np
= arg
;
213 return of_property_read_bool(np
, wa
->id
);
217 bool arch_timer_check_global_cap_erratum(const struct arch_timer_erratum_workaround
*wa
,
220 return cpus_have_cap((uintptr_t)wa
->id
);
224 bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround
*wa
,
227 return this_cpu_has_cap((uintptr_t)wa
->id
);
230 static const struct arch_timer_erratum_workaround
*
231 arch_timer_iterate_errata(enum arch_timer_erratum_match_type type
,
232 ate_match_fn_t match_fn
,
237 for (i
= 0; i
< ARRAY_SIZE(ool_workarounds
); i
++) {
238 if (ool_workarounds
[i
].match_type
!= type
)
241 if (match_fn(&ool_workarounds
[i
], arg
))
242 return &ool_workarounds
[i
];
249 void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround
*wa
)
251 timer_unstable_counter_workaround
= wa
;
252 static_branch_enable(&arch_timer_read_ool_enabled
);
255 static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type type
,
258 const struct arch_timer_erratum_workaround
*wa
;
259 ate_match_fn_t match_fn
= NULL
;
264 match_fn
= arch_timer_check_dt_erratum
;
266 case ate_match_global_cap_id
:
267 match_fn
= arch_timer_check_global_cap_erratum
;
269 case ate_match_local_cap_id
:
270 match_fn
= arch_timer_check_local_cap_erratum
;
275 wa
= arch_timer_iterate_errata(type
, match_fn
, arg
);
279 if (static_branch_unlikely(&arch_timer_read_ool_enabled
)) {
280 if (wa
!= timer_unstable_counter_workaround
)
281 pr_warn("Can't enable workaround for %s (clashes with %s\n)",
283 timer_unstable_counter_workaround
->desc
);
287 arch_timer_enable_workaround(wa
);
288 pr_info("Enabling %s workaround for %s\n",
289 local
? "local" : "global", wa
->desc
);
293 #define arch_timer_check_ool_workaround(t,a) do { } while(0)
294 #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
296 static __always_inline
297 void arch_timer_reg_write(int access
, enum arch_timer_reg reg
, u32 val
,
298 struct clock_event_device
*clk
)
300 if (access
== ARCH_TIMER_MEM_PHYS_ACCESS
) {
301 struct arch_timer
*timer
= to_arch_timer(clk
);
303 case ARCH_TIMER_REG_CTRL
:
304 writel_relaxed(val
, timer
->base
+ CNTP_CTL
);
306 case ARCH_TIMER_REG_TVAL
:
307 writel_relaxed(val
, timer
->base
+ CNTP_TVAL
);
310 } else if (access
== ARCH_TIMER_MEM_VIRT_ACCESS
) {
311 struct arch_timer
*timer
= to_arch_timer(clk
);
313 case ARCH_TIMER_REG_CTRL
:
314 writel_relaxed(val
, timer
->base
+ CNTV_CTL
);
316 case ARCH_TIMER_REG_TVAL
:
317 writel_relaxed(val
, timer
->base
+ CNTV_TVAL
);
321 arch_timer_reg_write_cp15(access
, reg
, val
);
325 static __always_inline
326 u32
arch_timer_reg_read(int access
, enum arch_timer_reg reg
,
327 struct clock_event_device
*clk
)
331 if (access
== ARCH_TIMER_MEM_PHYS_ACCESS
) {
332 struct arch_timer
*timer
= to_arch_timer(clk
);
334 case ARCH_TIMER_REG_CTRL
:
335 val
= readl_relaxed(timer
->base
+ CNTP_CTL
);
337 case ARCH_TIMER_REG_TVAL
:
338 val
= readl_relaxed(timer
->base
+ CNTP_TVAL
);
341 } else if (access
== ARCH_TIMER_MEM_VIRT_ACCESS
) {
342 struct arch_timer
*timer
= to_arch_timer(clk
);
344 case ARCH_TIMER_REG_CTRL
:
345 val
= readl_relaxed(timer
->base
+ CNTV_CTL
);
347 case ARCH_TIMER_REG_TVAL
:
348 val
= readl_relaxed(timer
->base
+ CNTV_TVAL
);
352 val
= arch_timer_reg_read_cp15(access
, reg
);
358 static __always_inline irqreturn_t
timer_handler(const int access
,
359 struct clock_event_device
*evt
)
363 ctrl
= arch_timer_reg_read(access
, ARCH_TIMER_REG_CTRL
, evt
);
364 if (ctrl
& ARCH_TIMER_CTRL_IT_STAT
) {
365 ctrl
|= ARCH_TIMER_CTRL_IT_MASK
;
366 arch_timer_reg_write(access
, ARCH_TIMER_REG_CTRL
, ctrl
, evt
);
367 evt
->event_handler(evt
);
374 static irqreturn_t
arch_timer_handler_virt(int irq
, void *dev_id
)
376 struct clock_event_device
*evt
= dev_id
;
378 return timer_handler(ARCH_TIMER_VIRT_ACCESS
, evt
);
381 static irqreturn_t
arch_timer_handler_phys(int irq
, void *dev_id
)
383 struct clock_event_device
*evt
= dev_id
;
385 return timer_handler(ARCH_TIMER_PHYS_ACCESS
, evt
);
388 static irqreturn_t
arch_timer_handler_phys_mem(int irq
, void *dev_id
)
390 struct clock_event_device
*evt
= dev_id
;
392 return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS
, evt
);
395 static irqreturn_t
arch_timer_handler_virt_mem(int irq
, void *dev_id
)
397 struct clock_event_device
*evt
= dev_id
;
399 return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS
, evt
);
402 static __always_inline
int timer_shutdown(const int access
,
403 struct clock_event_device
*clk
)
407 ctrl
= arch_timer_reg_read(access
, ARCH_TIMER_REG_CTRL
, clk
);
408 ctrl
&= ~ARCH_TIMER_CTRL_ENABLE
;
409 arch_timer_reg_write(access
, ARCH_TIMER_REG_CTRL
, ctrl
, clk
);
414 static int arch_timer_shutdown_virt(struct clock_event_device
*clk
)
416 return timer_shutdown(ARCH_TIMER_VIRT_ACCESS
, clk
);
419 static int arch_timer_shutdown_phys(struct clock_event_device
*clk
)
421 return timer_shutdown(ARCH_TIMER_PHYS_ACCESS
, clk
);
424 static int arch_timer_shutdown_virt_mem(struct clock_event_device
*clk
)
426 return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS
, clk
);
429 static int arch_timer_shutdown_phys_mem(struct clock_event_device
*clk
)
431 return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS
, clk
);
434 static __always_inline
void set_next_event(const int access
, unsigned long evt
,
435 struct clock_event_device
*clk
)
438 ctrl
= arch_timer_reg_read(access
, ARCH_TIMER_REG_CTRL
, clk
);
439 ctrl
|= ARCH_TIMER_CTRL_ENABLE
;
440 ctrl
&= ~ARCH_TIMER_CTRL_IT_MASK
;
441 arch_timer_reg_write(access
, ARCH_TIMER_REG_TVAL
, evt
, clk
);
442 arch_timer_reg_write(access
, ARCH_TIMER_REG_CTRL
, ctrl
, clk
);
445 #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
446 static __always_inline
void erratum_set_next_event_generic(const int access
,
447 unsigned long evt
, struct clock_event_device
*clk
)
450 u64 cval
= evt
+ arch_counter_get_cntvct();
452 ctrl
= arch_timer_reg_read(access
, ARCH_TIMER_REG_CTRL
, clk
);
453 ctrl
|= ARCH_TIMER_CTRL_ENABLE
;
454 ctrl
&= ~ARCH_TIMER_CTRL_IT_MASK
;
456 if (access
== ARCH_TIMER_PHYS_ACCESS
)
457 write_sysreg(cval
, cntp_cval_el0
);
458 else if (access
== ARCH_TIMER_VIRT_ACCESS
)
459 write_sysreg(cval
, cntv_cval_el0
);
461 arch_timer_reg_write(access
, ARCH_TIMER_REG_CTRL
, ctrl
, clk
);
464 static int erratum_set_next_event_virt(unsigned long evt
,
465 struct clock_event_device
*clk
)
467 erratum_set_next_event_generic(ARCH_TIMER_VIRT_ACCESS
, evt
, clk
);
471 static int erratum_set_next_event_phys(unsigned long evt
,
472 struct clock_event_device
*clk
)
474 erratum_set_next_event_generic(ARCH_TIMER_PHYS_ACCESS
, evt
, clk
);
477 #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
479 static int arch_timer_set_next_event_virt(unsigned long evt
,
480 struct clock_event_device
*clk
)
482 set_next_event(ARCH_TIMER_VIRT_ACCESS
, evt
, clk
);
486 static int arch_timer_set_next_event_phys(unsigned long evt
,
487 struct clock_event_device
*clk
)
489 set_next_event(ARCH_TIMER_PHYS_ACCESS
, evt
, clk
);
493 static int arch_timer_set_next_event_virt_mem(unsigned long evt
,
494 struct clock_event_device
*clk
)
496 set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS
, evt
, clk
);
500 static int arch_timer_set_next_event_phys_mem(unsigned long evt
,
501 struct clock_event_device
*clk
)
503 set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS
, evt
, clk
);
507 static void erratum_workaround_set_sne(struct clock_event_device
*clk
)
509 #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
510 if (!static_branch_unlikely(&arch_timer_read_ool_enabled
))
513 if (arch_timer_uses_ppi
== VIRT_PPI
)
514 clk
->set_next_event
= erratum_set_next_event_virt
;
516 clk
->set_next_event
= erratum_set_next_event_phys
;
520 static void __arch_timer_setup(unsigned type
,
521 struct clock_event_device
*clk
)
523 clk
->features
= CLOCK_EVT_FEAT_ONESHOT
;
525 if (type
== ARCH_CP15_TIMER
) {
526 if (arch_timer_c3stop
)
527 clk
->features
|= CLOCK_EVT_FEAT_C3STOP
;
528 clk
->name
= "arch_sys_timer";
530 clk
->cpumask
= cpumask_of(smp_processor_id());
531 clk
->irq
= arch_timer_ppi
[arch_timer_uses_ppi
];
532 switch (arch_timer_uses_ppi
) {
534 clk
->set_state_shutdown
= arch_timer_shutdown_virt
;
535 clk
->set_state_oneshot_stopped
= arch_timer_shutdown_virt
;
536 clk
->set_next_event
= arch_timer_set_next_event_virt
;
538 case PHYS_SECURE_PPI
:
539 case PHYS_NONSECURE_PPI
:
541 clk
->set_state_shutdown
= arch_timer_shutdown_phys
;
542 clk
->set_state_oneshot_stopped
= arch_timer_shutdown_phys
;
543 clk
->set_next_event
= arch_timer_set_next_event_phys
;
549 arch_timer_check_ool_workaround(ate_match_local_cap_id
, NULL
);
551 erratum_workaround_set_sne(clk
);
553 clk
->features
|= CLOCK_EVT_FEAT_DYNIRQ
;
554 clk
->name
= "arch_mem_timer";
556 clk
->cpumask
= cpu_all_mask
;
557 if (arch_timer_mem_use_virtual
) {
558 clk
->set_state_shutdown
= arch_timer_shutdown_virt_mem
;
559 clk
->set_state_oneshot_stopped
= arch_timer_shutdown_virt_mem
;
560 clk
->set_next_event
=
561 arch_timer_set_next_event_virt_mem
;
563 clk
->set_state_shutdown
= arch_timer_shutdown_phys_mem
;
564 clk
->set_state_oneshot_stopped
= arch_timer_shutdown_phys_mem
;
565 clk
->set_next_event
=
566 arch_timer_set_next_event_phys_mem
;
570 clk
->set_state_shutdown(clk
);
572 clockevents_config_and_register(clk
, arch_timer_rate
, 0xf, 0x7fffffff);
575 static void arch_timer_evtstrm_enable(int divider
)
577 u32 cntkctl
= arch_timer_get_cntkctl();
579 cntkctl
&= ~ARCH_TIMER_EVT_TRIGGER_MASK
;
580 /* Set the divider and enable virtual event stream */
581 cntkctl
|= (divider
<< ARCH_TIMER_EVT_TRIGGER_SHIFT
)
582 | ARCH_TIMER_VIRT_EVT_EN
;
583 arch_timer_set_cntkctl(cntkctl
);
584 elf_hwcap
|= HWCAP_EVTSTRM
;
586 compat_elf_hwcap
|= COMPAT_HWCAP_EVTSTRM
;
590 static void arch_timer_configure_evtstream(void)
592 int evt_stream_div
, pos
;
594 /* Find the closest power of two to the divisor */
595 evt_stream_div
= arch_timer_rate
/ ARCH_TIMER_EVT_STREAM_FREQ
;
596 pos
= fls(evt_stream_div
);
597 if (pos
> 1 && !(evt_stream_div
& (1 << (pos
- 2))))
599 /* enable event stream */
600 arch_timer_evtstrm_enable(min(pos
, 15));
603 static void arch_counter_set_user_access(void)
605 u32 cntkctl
= arch_timer_get_cntkctl();
607 /* Disable user access to the timers and the physical counter */
608 /* Also disable virtual event stream */
609 cntkctl
&= ~(ARCH_TIMER_USR_PT_ACCESS_EN
610 | ARCH_TIMER_USR_VT_ACCESS_EN
611 | ARCH_TIMER_VIRT_EVT_EN
612 | ARCH_TIMER_USR_PCT_ACCESS_EN
);
614 /* Enable user access to the virtual counter */
615 cntkctl
|= ARCH_TIMER_USR_VCT_ACCESS_EN
;
617 arch_timer_set_cntkctl(cntkctl
);
620 static bool arch_timer_has_nonsecure_ppi(void)
622 return (arch_timer_uses_ppi
== PHYS_SECURE_PPI
&&
623 arch_timer_ppi
[PHYS_NONSECURE_PPI
]);
626 static u32
check_ppi_trigger(int irq
)
628 u32 flags
= irq_get_trigger_type(irq
);
630 if (flags
!= IRQF_TRIGGER_HIGH
&& flags
!= IRQF_TRIGGER_LOW
) {
631 pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq
);
632 pr_warn("WARNING: Please fix your firmware\n");
633 flags
= IRQF_TRIGGER_LOW
;
639 static int arch_timer_starting_cpu(unsigned int cpu
)
641 struct clock_event_device
*clk
= this_cpu_ptr(arch_timer_evt
);
644 __arch_timer_setup(ARCH_CP15_TIMER
, clk
);
646 flags
= check_ppi_trigger(arch_timer_ppi
[arch_timer_uses_ppi
]);
647 enable_percpu_irq(arch_timer_ppi
[arch_timer_uses_ppi
], flags
);
649 if (arch_timer_has_nonsecure_ppi()) {
650 flags
= check_ppi_trigger(arch_timer_ppi
[PHYS_NONSECURE_PPI
]);
651 enable_percpu_irq(arch_timer_ppi
[PHYS_NONSECURE_PPI
], flags
);
654 arch_counter_set_user_access();
656 arch_timer_configure_evtstream();
662 arch_timer_detect_rate(void __iomem
*cntbase
, struct device_node
*np
)
664 /* Who has more than one independent system counter? */
669 * Try to determine the frequency from the device tree or CNTFRQ,
670 * if ACPI is enabled, get the frequency from CNTFRQ ONLY.
672 if (!acpi_disabled
||
673 of_property_read_u32(np
, "clock-frequency", &arch_timer_rate
)) {
675 arch_timer_rate
= readl_relaxed(cntbase
+ CNTFRQ
);
677 arch_timer_rate
= arch_timer_get_cntfrq();
680 /* Check the timer frequency. */
681 if (arch_timer_rate
== 0)
682 pr_warn("Architected timer frequency not available\n");
685 static void arch_timer_banner(unsigned type
)
687 pr_info("Architected %s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
688 type
& ARCH_CP15_TIMER
? "cp15" : "",
689 type
== (ARCH_CP15_TIMER
| ARCH_MEM_TIMER
) ? " and " : "",
690 type
& ARCH_MEM_TIMER
? "mmio" : "",
691 (unsigned long)arch_timer_rate
/ 1000000,
692 (unsigned long)(arch_timer_rate
/ 10000) % 100,
693 type
& ARCH_CP15_TIMER
?
694 (arch_timer_uses_ppi
== VIRT_PPI
) ? "virt" : "phys" :
696 type
== (ARCH_CP15_TIMER
| ARCH_MEM_TIMER
) ? "/" : "",
697 type
& ARCH_MEM_TIMER
?
698 arch_timer_mem_use_virtual
? "virt" : "phys" :
702 u32
arch_timer_get_rate(void)
704 return arch_timer_rate
;
707 static u64
arch_counter_get_cntvct_mem(void)
709 u32 vct_lo
, vct_hi
, tmp_hi
;
712 vct_hi
= readl_relaxed(arch_counter_base
+ CNTVCT_HI
);
713 vct_lo
= readl_relaxed(arch_counter_base
+ CNTVCT_LO
);
714 tmp_hi
= readl_relaxed(arch_counter_base
+ CNTVCT_HI
);
715 } while (vct_hi
!= tmp_hi
);
717 return ((u64
) vct_hi
<< 32) | vct_lo
;
721 * Default to cp15 based access because arm64 uses this function for
722 * sched_clock() before DT is probed and the cp15 method is guaranteed
723 * to exist on arm64. arm doesn't use this before DT is probed so even
724 * if we don't have the cp15 accessors we won't have a problem.
726 u64 (*arch_timer_read_counter
)(void) = arch_counter_get_cntvct
;
728 static u64
arch_counter_read(struct clocksource
*cs
)
730 return arch_timer_read_counter();
733 static u64
arch_counter_read_cc(const struct cyclecounter
*cc
)
735 return arch_timer_read_counter();
738 static struct clocksource clocksource_counter
= {
739 .name
= "arch_sys_counter",
741 .read
= arch_counter_read
,
742 .mask
= CLOCKSOURCE_MASK(56),
743 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
746 static struct cyclecounter cyclecounter
= {
747 .read
= arch_counter_read_cc
,
748 .mask
= CLOCKSOURCE_MASK(56),
751 static struct arch_timer_kvm_info arch_timer_kvm_info
;
753 struct arch_timer_kvm_info
*arch_timer_get_kvm_info(void)
755 return &arch_timer_kvm_info
;
758 static void __init
arch_counter_register(unsigned type
)
762 /* Register the CP15 based counter if we have one */
763 if (type
& ARCH_CP15_TIMER
) {
764 if (IS_ENABLED(CONFIG_ARM64
) || arch_timer_uses_ppi
== VIRT_PPI
)
765 arch_timer_read_counter
= arch_counter_get_cntvct
;
767 arch_timer_read_counter
= arch_counter_get_cntpct
;
769 clocksource_counter
.archdata
.vdso_direct
= true;
771 #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
773 * Don't use the vdso fastpath if errata require using
774 * the out-of-line counter accessor.
776 if (static_branch_unlikely(&arch_timer_read_ool_enabled
))
777 clocksource_counter
.archdata
.vdso_direct
= false;
780 arch_timer_read_counter
= arch_counter_get_cntvct_mem
;
783 if (!arch_counter_suspend_stop
)
784 clocksource_counter
.flags
|= CLOCK_SOURCE_SUSPEND_NONSTOP
;
785 start_count
= arch_timer_read_counter();
786 clocksource_register_hz(&clocksource_counter
, arch_timer_rate
);
787 cyclecounter
.mult
= clocksource_counter
.mult
;
788 cyclecounter
.shift
= clocksource_counter
.shift
;
789 timecounter_init(&arch_timer_kvm_info
.timecounter
,
790 &cyclecounter
, start_count
);
792 /* 56 bits minimum, so we assume worst case rollover */
793 sched_clock_register(arch_timer_read_counter
, 56, arch_timer_rate
);
796 static void arch_timer_stop(struct clock_event_device
*clk
)
798 pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
799 clk
->irq
, smp_processor_id());
801 disable_percpu_irq(arch_timer_ppi
[arch_timer_uses_ppi
]);
802 if (arch_timer_has_nonsecure_ppi())
803 disable_percpu_irq(arch_timer_ppi
[PHYS_NONSECURE_PPI
]);
805 clk
->set_state_shutdown(clk
);
808 static int arch_timer_dying_cpu(unsigned int cpu
)
810 struct clock_event_device
*clk
= this_cpu_ptr(arch_timer_evt
);
812 arch_timer_stop(clk
);
817 static unsigned int saved_cntkctl
;
818 static int arch_timer_cpu_pm_notify(struct notifier_block
*self
,
819 unsigned long action
, void *hcpu
)
821 if (action
== CPU_PM_ENTER
)
822 saved_cntkctl
= arch_timer_get_cntkctl();
823 else if (action
== CPU_PM_ENTER_FAILED
|| action
== CPU_PM_EXIT
)
824 arch_timer_set_cntkctl(saved_cntkctl
);
828 static struct notifier_block arch_timer_cpu_pm_notifier
= {
829 .notifier_call
= arch_timer_cpu_pm_notify
,
832 static int __init
arch_timer_cpu_pm_init(void)
834 return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier
);
837 static void __init
arch_timer_cpu_pm_deinit(void)
839 WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier
));
843 static int __init
arch_timer_cpu_pm_init(void)
848 static void __init
arch_timer_cpu_pm_deinit(void)
853 static int __init
arch_timer_register(void)
858 arch_timer_evt
= alloc_percpu(struct clock_event_device
);
859 if (!arch_timer_evt
) {
864 ppi
= arch_timer_ppi
[arch_timer_uses_ppi
];
865 switch (arch_timer_uses_ppi
) {
867 err
= request_percpu_irq(ppi
, arch_timer_handler_virt
,
868 "arch_timer", arch_timer_evt
);
870 case PHYS_SECURE_PPI
:
871 case PHYS_NONSECURE_PPI
:
872 err
= request_percpu_irq(ppi
, arch_timer_handler_phys
,
873 "arch_timer", arch_timer_evt
);
874 if (!err
&& arch_timer_ppi
[PHYS_NONSECURE_PPI
]) {
875 ppi
= arch_timer_ppi
[PHYS_NONSECURE_PPI
];
876 err
= request_percpu_irq(ppi
, arch_timer_handler_phys
,
877 "arch_timer", arch_timer_evt
);
879 free_percpu_irq(arch_timer_ppi
[PHYS_SECURE_PPI
],
884 err
= request_percpu_irq(ppi
, arch_timer_handler_phys
,
885 "arch_timer", arch_timer_evt
);
892 pr_err("arch_timer: can't register interrupt %d (%d)\n",
897 err
= arch_timer_cpu_pm_init();
899 goto out_unreg_notify
;
902 /* Register and immediately configure the timer on the boot CPU */
903 err
= cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING
,
904 "clockevents/arm/arch_timer:starting",
905 arch_timer_starting_cpu
, arch_timer_dying_cpu
);
907 goto out_unreg_cpupm
;
911 arch_timer_cpu_pm_deinit();
914 free_percpu_irq(arch_timer_ppi
[arch_timer_uses_ppi
], arch_timer_evt
);
915 if (arch_timer_has_nonsecure_ppi())
916 free_percpu_irq(arch_timer_ppi
[PHYS_NONSECURE_PPI
],
920 free_percpu(arch_timer_evt
);
925 static int __init
arch_timer_mem_register(void __iomem
*base
, unsigned int irq
)
929 struct arch_timer
*t
;
931 t
= kzalloc(sizeof(*t
), GFP_KERNEL
);
937 __arch_timer_setup(ARCH_MEM_TIMER
, &t
->evt
);
939 if (arch_timer_mem_use_virtual
)
940 func
= arch_timer_handler_virt_mem
;
942 func
= arch_timer_handler_phys_mem
;
944 ret
= request_irq(irq
, func
, IRQF_TIMER
, "arch_mem_timer", &t
->evt
);
946 pr_err("arch_timer: Failed to request mem timer irq\n");
953 static const struct of_device_id arch_timer_of_match
[] __initconst
= {
954 { .compatible
= "arm,armv7-timer", },
955 { .compatible
= "arm,armv8-timer", },
959 static const struct of_device_id arch_timer_mem_of_match
[] __initconst
= {
960 { .compatible
= "arm,armv7-timer-mem", },
965 arch_timer_needs_probing(int type
, const struct of_device_id
*matches
)
967 struct device_node
*dn
;
968 bool needs_probing
= false;
970 dn
= of_find_matching_node(NULL
, matches
);
971 if (dn
&& of_device_is_available(dn
) && !(arch_timers_present
& type
))
972 needs_probing
= true;
975 return needs_probing
;
978 static int __init
arch_timer_common_init(void)
980 unsigned mask
= ARCH_CP15_TIMER
| ARCH_MEM_TIMER
;
982 /* Wait until both nodes are probed if we have two timers */
983 if ((arch_timers_present
& mask
) != mask
) {
984 if (arch_timer_needs_probing(ARCH_MEM_TIMER
, arch_timer_mem_of_match
))
986 if (arch_timer_needs_probing(ARCH_CP15_TIMER
, arch_timer_of_match
))
990 arch_timer_banner(arch_timers_present
);
991 arch_counter_register(arch_timers_present
);
992 return arch_timer_arch_init();
995 static int __init
arch_timer_init(void)
999 * If HYP mode is available, we know that the physical timer
1000 * has been configured to be accessible from PL1. Use it, so
1001 * that a guest can use the virtual timer instead.
1003 * If no interrupt provided for virtual timer, we'll have to
1004 * stick to the physical timer. It'd better be accessible...
1006 * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE
1007 * accesses to CNTP_*_EL1 registers are silently redirected to
1008 * their CNTHP_*_EL2 counterparts, and use a different PPI
1011 if (is_hyp_mode_available() || !arch_timer_ppi
[VIRT_PPI
]) {
1014 if (is_kernel_in_hyp_mode()) {
1015 arch_timer_uses_ppi
= HYP_PPI
;
1016 has_ppi
= !!arch_timer_ppi
[HYP_PPI
];
1018 arch_timer_uses_ppi
= PHYS_SECURE_PPI
;
1019 has_ppi
= (!!arch_timer_ppi
[PHYS_SECURE_PPI
] ||
1020 !!arch_timer_ppi
[PHYS_NONSECURE_PPI
]);
1024 pr_warn("arch_timer: No interrupt available, giving up\n");
1029 ret
= arch_timer_register();
1033 ret
= arch_timer_common_init();
1037 arch_timer_kvm_info
.virtual_irq
= arch_timer_ppi
[VIRT_PPI
];
1042 static int __init
arch_timer_of_init(struct device_node
*np
)
1046 if (arch_timers_present
& ARCH_CP15_TIMER
) {
1047 pr_warn("arch_timer: multiple nodes in dt, skipping\n");
1051 arch_timers_present
|= ARCH_CP15_TIMER
;
1052 for (i
= PHYS_SECURE_PPI
; i
< MAX_TIMER_PPI
; i
++)
1053 arch_timer_ppi
[i
] = irq_of_parse_and_map(np
, i
);
1055 arch_timer_detect_rate(NULL
, np
);
1057 arch_timer_c3stop
= !of_property_read_bool(np
, "always-on");
1059 /* Check for globally applicable workarounds */
1060 arch_timer_check_ool_workaround(ate_match_dt
, np
);
1061 arch_timer_check_ool_workaround(ate_match_global_cap_id
, NULL
);
1064 * If we cannot rely on firmware initializing the timer registers then
1065 * we should use the physical timers instead.
1067 if (IS_ENABLED(CONFIG_ARM
) &&
1068 of_property_read_bool(np
, "arm,cpu-registers-not-fw-configured"))
1069 arch_timer_uses_ppi
= PHYS_SECURE_PPI
;
1071 /* On some systems, the counter stops ticking when in suspend. */
1072 arch_counter_suspend_stop
= of_property_read_bool(np
,
1073 "arm,no-tick-in-suspend");
1075 return arch_timer_init();
1077 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer
, "arm,armv7-timer", arch_timer_of_init
);
1078 CLOCKSOURCE_OF_DECLARE(armv8_arch_timer
, "arm,armv8-timer", arch_timer_of_init
);
1080 static int __init
arch_timer_mem_init(struct device_node
*np
)
1082 struct device_node
*frame
, *best_frame
= NULL
;
1083 void __iomem
*cntctlbase
, *base
;
1084 unsigned int irq
, ret
= -EINVAL
;
1087 arch_timers_present
|= ARCH_MEM_TIMER
;
1088 cntctlbase
= of_iomap(np
, 0);
1090 pr_err("arch_timer: Can't find CNTCTLBase\n");
1094 cnttidr
= readl_relaxed(cntctlbase
+ CNTTIDR
);
1097 * Try to find a virtual capable frame. Otherwise fall back to a
1098 * physical capable frame.
1100 for_each_available_child_of_node(np
, frame
) {
1104 if (of_property_read_u32(frame
, "frame-number", &n
)) {
1105 pr_err("arch_timer: Missing frame-number\n");
1110 /* Try enabling everything, and see what sticks */
1111 cntacr
= CNTACR_RFRQ
| CNTACR_RWPT
| CNTACR_RPCT
|
1112 CNTACR_RWVT
| CNTACR_RVOFF
| CNTACR_RVCT
;
1113 writel_relaxed(cntacr
, cntctlbase
+ CNTACR(n
));
1114 cntacr
= readl_relaxed(cntctlbase
+ CNTACR(n
));
1116 if ((cnttidr
& CNTTIDR_VIRT(n
)) &&
1117 !(~cntacr
& (CNTACR_RWVT
| CNTACR_RVCT
))) {
1118 of_node_put(best_frame
);
1120 arch_timer_mem_use_virtual
= true;
1124 if (~cntacr
& (CNTACR_RWPT
| CNTACR_RPCT
))
1127 of_node_put(best_frame
);
1128 best_frame
= of_node_get(frame
);
1132 base
= arch_counter_base
= of_io_request_and_map(best_frame
, 0,
1135 pr_err("arch_timer: Can't map frame's registers\n");
1139 if (arch_timer_mem_use_virtual
)
1140 irq
= irq_of_parse_and_map(best_frame
, 1);
1142 irq
= irq_of_parse_and_map(best_frame
, 0);
1146 pr_err("arch_timer: Frame missing %s irq",
1147 arch_timer_mem_use_virtual
? "virt" : "phys");
1151 arch_timer_detect_rate(base
, np
);
1152 ret
= arch_timer_mem_register(base
, irq
);
1156 return arch_timer_common_init();
1158 iounmap(cntctlbase
);
1159 of_node_put(best_frame
);
1162 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem
, "arm,armv7-timer-mem",
1163 arch_timer_mem_init
);
1166 static int __init
map_generic_timer_interrupt(u32 interrupt
, u32 flags
)
1168 int trigger
, polarity
;
1173 trigger
= (flags
& ACPI_GTDT_INTERRUPT_MODE
) ? ACPI_EDGE_SENSITIVE
1174 : ACPI_LEVEL_SENSITIVE
;
1176 polarity
= (flags
& ACPI_GTDT_INTERRUPT_POLARITY
) ? ACPI_ACTIVE_LOW
1179 return acpi_register_gsi(NULL
, interrupt
, trigger
, polarity
);
1182 /* Initialize per-processor generic timer */
1183 static int __init
arch_timer_acpi_init(struct acpi_table_header
*table
)
1185 struct acpi_table_gtdt
*gtdt
;
1187 if (arch_timers_present
& ARCH_CP15_TIMER
) {
1188 pr_warn("arch_timer: already initialized, skipping\n");
1192 gtdt
= container_of(table
, struct acpi_table_gtdt
, header
);
1194 arch_timers_present
|= ARCH_CP15_TIMER
;
1196 arch_timer_ppi
[PHYS_SECURE_PPI
] =
1197 map_generic_timer_interrupt(gtdt
->secure_el1_interrupt
,
1198 gtdt
->secure_el1_flags
);
1200 arch_timer_ppi
[PHYS_NONSECURE_PPI
] =
1201 map_generic_timer_interrupt(gtdt
->non_secure_el1_interrupt
,
1202 gtdt
->non_secure_el1_flags
);
1204 arch_timer_ppi
[VIRT_PPI
] =
1205 map_generic_timer_interrupt(gtdt
->virtual_timer_interrupt
,
1206 gtdt
->virtual_timer_flags
);
1208 arch_timer_ppi
[HYP_PPI
] =
1209 map_generic_timer_interrupt(gtdt
->non_secure_el2_interrupt
,
1210 gtdt
->non_secure_el2_flags
);
1212 /* Get the frequency from CNTFRQ */
1213 arch_timer_detect_rate(NULL
, NULL
);
1215 /* Always-on capability */
1216 arch_timer_c3stop
= !(gtdt
->non_secure_el1_flags
& ACPI_GTDT_ALWAYS_ON
);
1218 /* Check for globally applicable workarounds */
1219 arch_timer_check_ool_workaround(ate_match_global_cap_id
, NULL
);
1224 CLOCKSOURCE_ACPI_DECLARE(arch_timer
, ACPI_SIG_GTDT
, arch_timer_acpi_init
);