2 * linux/drivers/clocksource/arm_arch_timer.c
4 * Copyright (C) 2011 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #define pr_fmt(fmt) "arm_arch_timer: " fmt
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/device.h>
17 #include <linux/smp.h>
18 #include <linux/cpu.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/clockchips.h>
21 #include <linux/clocksource.h>
22 #include <linux/interrupt.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_address.h>
26 #include <linux/slab.h>
27 #include <linux/sched_clock.h>
28 #include <linux/acpi.h>
30 #include <asm/arch_timer.h>
33 #include <clocksource/arm_arch_timer.h>
36 #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
38 #define CNTACR(n) (0x40 + ((n) * 4))
39 #define CNTACR_RPCT BIT(0)
40 #define CNTACR_RVCT BIT(1)
41 #define CNTACR_RFRQ BIT(2)
42 #define CNTACR_RVOFF BIT(3)
43 #define CNTACR_RWVT BIT(4)
44 #define CNTACR_RWPT BIT(5)
46 #define CNTVCT_LO 0x08
47 #define CNTVCT_HI 0x0c
49 #define CNTP_TVAL 0x28
51 #define CNTV_TVAL 0x38
54 #define ARCH_CP15_TIMER BIT(0)
55 #define ARCH_MEM_TIMER BIT(1)
56 static unsigned arch_timers_present __initdata
;
58 static void __iomem
*arch_counter_base
;
62 struct clock_event_device evt
;
65 #define to_arch_timer(e) container_of(e, struct arch_timer, evt)
67 static u32 arch_timer_rate
;
77 static int arch_timer_ppi
[MAX_TIMER_PPI
];
79 static struct clock_event_device __percpu
*arch_timer_evt
;
81 static enum ppi_nr arch_timer_uses_ppi
= VIRT_PPI
;
82 static bool arch_timer_c3stop
;
83 static bool arch_timer_mem_use_virtual
;
84 static bool arch_counter_suspend_stop
;
86 static bool evtstrm_enable
= IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM
);
88 static int __init
early_evtstrm_cfg(char *buf
)
90 return strtobool(buf
, &evtstrm_enable
);
92 early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg
);
95 * Architected system timer support.
98 static __always_inline
99 void arch_timer_reg_write(int access
, enum arch_timer_reg reg
, u32 val
,
100 struct clock_event_device
*clk
)
102 if (access
== ARCH_TIMER_MEM_PHYS_ACCESS
) {
103 struct arch_timer
*timer
= to_arch_timer(clk
);
105 case ARCH_TIMER_REG_CTRL
:
106 writel_relaxed(val
, timer
->base
+ CNTP_CTL
);
108 case ARCH_TIMER_REG_TVAL
:
109 writel_relaxed(val
, timer
->base
+ CNTP_TVAL
);
112 } else if (access
== ARCH_TIMER_MEM_VIRT_ACCESS
) {
113 struct arch_timer
*timer
= to_arch_timer(clk
);
115 case ARCH_TIMER_REG_CTRL
:
116 writel_relaxed(val
, timer
->base
+ CNTV_CTL
);
118 case ARCH_TIMER_REG_TVAL
:
119 writel_relaxed(val
, timer
->base
+ CNTV_TVAL
);
123 arch_timer_reg_write_cp15(access
, reg
, val
);
127 static __always_inline
128 u32
arch_timer_reg_read(int access
, enum arch_timer_reg reg
,
129 struct clock_event_device
*clk
)
133 if (access
== ARCH_TIMER_MEM_PHYS_ACCESS
) {
134 struct arch_timer
*timer
= to_arch_timer(clk
);
136 case ARCH_TIMER_REG_CTRL
:
137 val
= readl_relaxed(timer
->base
+ CNTP_CTL
);
139 case ARCH_TIMER_REG_TVAL
:
140 val
= readl_relaxed(timer
->base
+ CNTP_TVAL
);
143 } else if (access
== ARCH_TIMER_MEM_VIRT_ACCESS
) {
144 struct arch_timer
*timer
= to_arch_timer(clk
);
146 case ARCH_TIMER_REG_CTRL
:
147 val
= readl_relaxed(timer
->base
+ CNTV_CTL
);
149 case ARCH_TIMER_REG_TVAL
:
150 val
= readl_relaxed(timer
->base
+ CNTV_TVAL
);
154 val
= arch_timer_reg_read_cp15(access
, reg
);
161 * Default to cp15 based access because arm64 uses this function for
162 * sched_clock() before DT is probed and the cp15 method is guaranteed
163 * to exist on arm64. arm doesn't use this before DT is probed so even
164 * if we don't have the cp15 accessors we won't have a problem.
166 u64 (*arch_timer_read_counter
)(void) = arch_counter_get_cntvct
;
168 static u64
arch_counter_read(struct clocksource
*cs
)
170 return arch_timer_read_counter();
173 static u64
arch_counter_read_cc(const struct cyclecounter
*cc
)
175 return arch_timer_read_counter();
178 static struct clocksource clocksource_counter
= {
179 .name
= "arch_sys_counter",
181 .read
= arch_counter_read
,
182 .mask
= CLOCKSOURCE_MASK(56),
183 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
186 static struct cyclecounter cyclecounter
= {
187 .read
= arch_counter_read_cc
,
188 .mask
= CLOCKSOURCE_MASK(56),
191 #ifdef CONFIG_FSL_ERRATUM_A008585
193 * The number of retries is an arbitrary value well beyond the highest number
194 * of iterations the loop has been observed to take.
196 #define __fsl_a008585_read_reg(reg) ({ \
198 int _retries = 200; \
201 _old = read_sysreg(reg); \
202 _new = read_sysreg(reg); \
204 } while (unlikely(_old != _new) && _retries); \
206 WARN_ON_ONCE(!_retries); \
210 static u32 notrace
fsl_a008585_read_cntp_tval_el0(void)
212 return __fsl_a008585_read_reg(cntp_tval_el0
);
215 static u32 notrace
fsl_a008585_read_cntv_tval_el0(void)
217 return __fsl_a008585_read_reg(cntv_tval_el0
);
220 static u64 notrace
fsl_a008585_read_cntvct_el0(void)
222 return __fsl_a008585_read_reg(cntvct_el0
);
226 #ifdef CONFIG_HISILICON_ERRATUM_161010101
228 * Verify whether the value of the second read is larger than the first by
229 * less than 32 is the only way to confirm the value is correct, so clear the
230 * lower 5 bits to check whether the difference is greater than 32 or not.
231 * Theoretically the erratum should not occur more than twice in succession
232 * when reading the system counter, but it is possible that some interrupts
233 * may lead to more than twice read errors, triggering the warning, so setting
234 * the number of retries far beyond the number of iterations the loop has been
237 #define __hisi_161010101_read_reg(reg) ({ \
242 _old = read_sysreg(reg); \
243 _new = read_sysreg(reg); \
245 } while (unlikely((_new - _old) >> 5) && _retries); \
247 WARN_ON_ONCE(!_retries); \
251 static u32 notrace
hisi_161010101_read_cntp_tval_el0(void)
253 return __hisi_161010101_read_reg(cntp_tval_el0
);
256 static u32 notrace
hisi_161010101_read_cntv_tval_el0(void)
258 return __hisi_161010101_read_reg(cntv_tval_el0
);
261 static u64 notrace
hisi_161010101_read_cntvct_el0(void)
263 return __hisi_161010101_read_reg(cntvct_el0
);
267 #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
268 DEFINE_PER_CPU(const struct arch_timer_erratum_workaround
*,
269 timer_unstable_counter_workaround
);
270 EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround
);
272 DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled
);
273 EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled
);
275 static void erratum_set_next_event_tval_generic(const int access
, unsigned long evt
,
276 struct clock_event_device
*clk
)
279 u64 cval
= evt
+ arch_counter_get_cntvct();
281 ctrl
= arch_timer_reg_read(access
, ARCH_TIMER_REG_CTRL
, clk
);
282 ctrl
|= ARCH_TIMER_CTRL_ENABLE
;
283 ctrl
&= ~ARCH_TIMER_CTRL_IT_MASK
;
285 if (access
== ARCH_TIMER_PHYS_ACCESS
)
286 write_sysreg(cval
, cntp_cval_el0
);
288 write_sysreg(cval
, cntv_cval_el0
);
290 arch_timer_reg_write(access
, ARCH_TIMER_REG_CTRL
, ctrl
, clk
);
293 static int erratum_set_next_event_tval_virt(unsigned long evt
,
294 struct clock_event_device
*clk
)
296 erratum_set_next_event_tval_generic(ARCH_TIMER_VIRT_ACCESS
, evt
, clk
);
300 static int erratum_set_next_event_tval_phys(unsigned long evt
,
301 struct clock_event_device
*clk
)
303 erratum_set_next_event_tval_generic(ARCH_TIMER_PHYS_ACCESS
, evt
, clk
);
307 static const struct arch_timer_erratum_workaround ool_workarounds
[] = {
308 #ifdef CONFIG_FSL_ERRATUM_A008585
310 .match_type
= ate_match_dt
,
311 .id
= "fsl,erratum-a008585",
312 .desc
= "Freescale erratum a005858",
313 .read_cntp_tval_el0
= fsl_a008585_read_cntp_tval_el0
,
314 .read_cntv_tval_el0
= fsl_a008585_read_cntv_tval_el0
,
315 .read_cntvct_el0
= fsl_a008585_read_cntvct_el0
,
316 .set_next_event_phys
= erratum_set_next_event_tval_phys
,
317 .set_next_event_virt
= erratum_set_next_event_tval_virt
,
320 #ifdef CONFIG_HISILICON_ERRATUM_161010101
322 .match_type
= ate_match_dt
,
323 .id
= "hisilicon,erratum-161010101",
324 .desc
= "HiSilicon erratum 161010101",
325 .read_cntp_tval_el0
= hisi_161010101_read_cntp_tval_el0
,
326 .read_cntv_tval_el0
= hisi_161010101_read_cntv_tval_el0
,
327 .read_cntvct_el0
= hisi_161010101_read_cntvct_el0
,
328 .set_next_event_phys
= erratum_set_next_event_tval_phys
,
329 .set_next_event_virt
= erratum_set_next_event_tval_virt
,
334 typedef bool (*ate_match_fn_t
)(const struct arch_timer_erratum_workaround
*,
338 bool arch_timer_check_dt_erratum(const struct arch_timer_erratum_workaround
*wa
,
341 const struct device_node
*np
= arg
;
343 return of_property_read_bool(np
, wa
->id
);
347 bool arch_timer_check_global_cap_erratum(const struct arch_timer_erratum_workaround
*wa
,
350 return cpus_have_cap((uintptr_t)wa
->id
);
354 bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround
*wa
,
357 return this_cpu_has_cap((uintptr_t)wa
->id
);
360 static const struct arch_timer_erratum_workaround
*
361 arch_timer_iterate_errata(enum arch_timer_erratum_match_type type
,
362 ate_match_fn_t match_fn
,
367 for (i
= 0; i
< ARRAY_SIZE(ool_workarounds
); i
++) {
368 if (ool_workarounds
[i
].match_type
!= type
)
371 if (match_fn(&ool_workarounds
[i
], arg
))
372 return &ool_workarounds
[i
];
379 void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround
*wa
,
385 __this_cpu_write(timer_unstable_counter_workaround
, wa
);
387 for_each_possible_cpu(i
)
388 per_cpu(timer_unstable_counter_workaround
, i
) = wa
;
391 static_branch_enable(&arch_timer_read_ool_enabled
);
394 static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type type
,
397 const struct arch_timer_erratum_workaround
*wa
;
398 ate_match_fn_t match_fn
= NULL
;
403 match_fn
= arch_timer_check_dt_erratum
;
405 case ate_match_global_cap_id
:
406 match_fn
= arch_timer_check_global_cap_erratum
;
408 case ate_match_local_cap_id
:
409 match_fn
= arch_timer_check_local_cap_erratum
;
414 wa
= arch_timer_iterate_errata(type
, match_fn
, arg
);
418 if (static_branch_unlikely(&arch_timer_read_ool_enabled
)) {
419 const struct arch_timer_erratum_workaround
*__wa
;
420 __wa
= __this_cpu_read(timer_unstable_counter_workaround
);
421 if (__wa
&& wa
!= __wa
)
422 pr_warn("Can't enable workaround for %s (clashes with %s\n)",
423 wa
->desc
, __wa
->desc
);
429 arch_timer_enable_workaround(wa
, local
);
430 pr_info("Enabling %s workaround for %s\n",
431 local
? "local" : "global", wa
->desc
);
434 #define erratum_handler(fn, r, ...) \
437 if (needs_unstable_timer_counter_workaround()) { \
438 const struct arch_timer_erratum_workaround *__wa; \
439 __wa = __this_cpu_read(timer_unstable_counter_workaround); \
440 if (__wa && __wa->fn) { \
441 r = __wa->fn(__VA_ARGS__); \
453 #define arch_timer_check_ool_workaround(t,a) do { } while(0)
454 #define erratum_set_next_event_tval_virt(...) ({BUG(); 0;})
455 #define erratum_set_next_event_tval_phys(...) ({BUG(); 0;})
456 #define erratum_handler(fn, r, ...) ({false;})
457 #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
459 static __always_inline irqreturn_t
timer_handler(const int access
,
460 struct clock_event_device
*evt
)
464 ctrl
= arch_timer_reg_read(access
, ARCH_TIMER_REG_CTRL
, evt
);
465 if (ctrl
& ARCH_TIMER_CTRL_IT_STAT
) {
466 ctrl
|= ARCH_TIMER_CTRL_IT_MASK
;
467 arch_timer_reg_write(access
, ARCH_TIMER_REG_CTRL
, ctrl
, evt
);
468 evt
->event_handler(evt
);
475 static irqreturn_t
arch_timer_handler_virt(int irq
, void *dev_id
)
477 struct clock_event_device
*evt
= dev_id
;
479 return timer_handler(ARCH_TIMER_VIRT_ACCESS
, evt
);
482 static irqreturn_t
arch_timer_handler_phys(int irq
, void *dev_id
)
484 struct clock_event_device
*evt
= dev_id
;
486 return timer_handler(ARCH_TIMER_PHYS_ACCESS
, evt
);
489 static irqreturn_t
arch_timer_handler_phys_mem(int irq
, void *dev_id
)
491 struct clock_event_device
*evt
= dev_id
;
493 return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS
, evt
);
496 static irqreturn_t
arch_timer_handler_virt_mem(int irq
, void *dev_id
)
498 struct clock_event_device
*evt
= dev_id
;
500 return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS
, evt
);
503 static __always_inline
int timer_shutdown(const int access
,
504 struct clock_event_device
*clk
)
508 ctrl
= arch_timer_reg_read(access
, ARCH_TIMER_REG_CTRL
, clk
);
509 ctrl
&= ~ARCH_TIMER_CTRL_ENABLE
;
510 arch_timer_reg_write(access
, ARCH_TIMER_REG_CTRL
, ctrl
, clk
);
515 static int arch_timer_shutdown_virt(struct clock_event_device
*clk
)
517 return timer_shutdown(ARCH_TIMER_VIRT_ACCESS
, clk
);
520 static int arch_timer_shutdown_phys(struct clock_event_device
*clk
)
522 return timer_shutdown(ARCH_TIMER_PHYS_ACCESS
, clk
);
525 static int arch_timer_shutdown_virt_mem(struct clock_event_device
*clk
)
527 return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS
, clk
);
530 static int arch_timer_shutdown_phys_mem(struct clock_event_device
*clk
)
532 return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS
, clk
);
535 static __always_inline
void set_next_event(const int access
, unsigned long evt
,
536 struct clock_event_device
*clk
)
539 ctrl
= arch_timer_reg_read(access
, ARCH_TIMER_REG_CTRL
, clk
);
540 ctrl
|= ARCH_TIMER_CTRL_ENABLE
;
541 ctrl
&= ~ARCH_TIMER_CTRL_IT_MASK
;
542 arch_timer_reg_write(access
, ARCH_TIMER_REG_TVAL
, evt
, clk
);
543 arch_timer_reg_write(access
, ARCH_TIMER_REG_CTRL
, ctrl
, clk
);
546 static int arch_timer_set_next_event_virt(unsigned long evt
,
547 struct clock_event_device
*clk
)
551 if (erratum_handler(set_next_event_virt
, ret
, evt
, clk
))
554 set_next_event(ARCH_TIMER_VIRT_ACCESS
, evt
, clk
);
558 static int arch_timer_set_next_event_phys(unsigned long evt
,
559 struct clock_event_device
*clk
)
563 if (erratum_handler(set_next_event_phys
, ret
, evt
, clk
))
566 set_next_event(ARCH_TIMER_PHYS_ACCESS
, evt
, clk
);
570 static int arch_timer_set_next_event_virt_mem(unsigned long evt
,
571 struct clock_event_device
*clk
)
573 set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS
, evt
, clk
);
577 static int arch_timer_set_next_event_phys_mem(unsigned long evt
,
578 struct clock_event_device
*clk
)
580 set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS
, evt
, clk
);
584 static void __arch_timer_setup(unsigned type
,
585 struct clock_event_device
*clk
)
587 clk
->features
= CLOCK_EVT_FEAT_ONESHOT
;
589 if (type
== ARCH_CP15_TIMER
) {
590 if (arch_timer_c3stop
)
591 clk
->features
|= CLOCK_EVT_FEAT_C3STOP
;
592 clk
->name
= "arch_sys_timer";
594 clk
->cpumask
= cpumask_of(smp_processor_id());
595 clk
->irq
= arch_timer_ppi
[arch_timer_uses_ppi
];
596 switch (arch_timer_uses_ppi
) {
598 clk
->set_state_shutdown
= arch_timer_shutdown_virt
;
599 clk
->set_state_oneshot_stopped
= arch_timer_shutdown_virt
;
600 clk
->set_next_event
= arch_timer_set_next_event_virt
;
602 case PHYS_SECURE_PPI
:
603 case PHYS_NONSECURE_PPI
:
605 clk
->set_state_shutdown
= arch_timer_shutdown_phys
;
606 clk
->set_state_oneshot_stopped
= arch_timer_shutdown_phys
;
607 clk
->set_next_event
= arch_timer_set_next_event_phys
;
613 arch_timer_check_ool_workaround(ate_match_local_cap_id
, NULL
);
615 clk
->features
|= CLOCK_EVT_FEAT_DYNIRQ
;
616 clk
->name
= "arch_mem_timer";
618 clk
->cpumask
= cpu_all_mask
;
619 if (arch_timer_mem_use_virtual
) {
620 clk
->set_state_shutdown
= arch_timer_shutdown_virt_mem
;
621 clk
->set_state_oneshot_stopped
= arch_timer_shutdown_virt_mem
;
622 clk
->set_next_event
=
623 arch_timer_set_next_event_virt_mem
;
625 clk
->set_state_shutdown
= arch_timer_shutdown_phys_mem
;
626 clk
->set_state_oneshot_stopped
= arch_timer_shutdown_phys_mem
;
627 clk
->set_next_event
=
628 arch_timer_set_next_event_phys_mem
;
632 clk
->set_state_shutdown(clk
);
634 clockevents_config_and_register(clk
, arch_timer_rate
, 0xf, 0x7fffffff);
637 static void arch_timer_evtstrm_enable(int divider
)
639 u32 cntkctl
= arch_timer_get_cntkctl();
641 cntkctl
&= ~ARCH_TIMER_EVT_TRIGGER_MASK
;
642 /* Set the divider and enable virtual event stream */
643 cntkctl
|= (divider
<< ARCH_TIMER_EVT_TRIGGER_SHIFT
)
644 | ARCH_TIMER_VIRT_EVT_EN
;
645 arch_timer_set_cntkctl(cntkctl
);
646 elf_hwcap
|= HWCAP_EVTSTRM
;
648 compat_elf_hwcap
|= COMPAT_HWCAP_EVTSTRM
;
652 static void arch_timer_configure_evtstream(void)
654 int evt_stream_div
, pos
;
656 /* Find the closest power of two to the divisor */
657 evt_stream_div
= arch_timer_rate
/ ARCH_TIMER_EVT_STREAM_FREQ
;
658 pos
= fls(evt_stream_div
);
659 if (pos
> 1 && !(evt_stream_div
& (1 << (pos
- 2))))
661 /* enable event stream */
662 arch_timer_evtstrm_enable(min(pos
, 15));
665 static void arch_counter_set_user_access(void)
667 u32 cntkctl
= arch_timer_get_cntkctl();
669 /* Disable user access to the timers and the physical counter */
670 /* Also disable virtual event stream */
671 cntkctl
&= ~(ARCH_TIMER_USR_PT_ACCESS_EN
672 | ARCH_TIMER_USR_VT_ACCESS_EN
673 | ARCH_TIMER_VIRT_EVT_EN
674 | ARCH_TIMER_USR_PCT_ACCESS_EN
);
676 /* Enable user access to the virtual counter */
677 cntkctl
|= ARCH_TIMER_USR_VCT_ACCESS_EN
;
679 arch_timer_set_cntkctl(cntkctl
);
682 static bool arch_timer_has_nonsecure_ppi(void)
684 return (arch_timer_uses_ppi
== PHYS_SECURE_PPI
&&
685 arch_timer_ppi
[PHYS_NONSECURE_PPI
]);
688 static u32
check_ppi_trigger(int irq
)
690 u32 flags
= irq_get_trigger_type(irq
);
692 if (flags
!= IRQF_TRIGGER_HIGH
&& flags
!= IRQF_TRIGGER_LOW
) {
693 pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq
);
694 pr_warn("WARNING: Please fix your firmware\n");
695 flags
= IRQF_TRIGGER_LOW
;
701 static int arch_timer_starting_cpu(unsigned int cpu
)
703 struct clock_event_device
*clk
= this_cpu_ptr(arch_timer_evt
);
706 __arch_timer_setup(ARCH_CP15_TIMER
, clk
);
708 flags
= check_ppi_trigger(arch_timer_ppi
[arch_timer_uses_ppi
]);
709 enable_percpu_irq(arch_timer_ppi
[arch_timer_uses_ppi
], flags
);
711 if (arch_timer_has_nonsecure_ppi()) {
712 flags
= check_ppi_trigger(arch_timer_ppi
[PHYS_NONSECURE_PPI
]);
713 enable_percpu_irq(arch_timer_ppi
[PHYS_NONSECURE_PPI
], flags
);
716 arch_counter_set_user_access();
718 arch_timer_configure_evtstream();
724 arch_timer_detect_rate(void __iomem
*cntbase
, struct device_node
*np
)
726 /* Who has more than one independent system counter? */
731 * Try to determine the frequency from the device tree or CNTFRQ,
732 * if ACPI is enabled, get the frequency from CNTFRQ ONLY.
734 if (!acpi_disabled
||
735 of_property_read_u32(np
, "clock-frequency", &arch_timer_rate
)) {
737 arch_timer_rate
= readl_relaxed(cntbase
+ CNTFRQ
);
739 arch_timer_rate
= arch_timer_get_cntfrq();
742 /* Check the timer frequency. */
743 if (arch_timer_rate
== 0)
744 pr_warn("Architected timer frequency not available\n");
747 static void arch_timer_banner(unsigned type
)
749 pr_info("Architected %s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
750 type
& ARCH_CP15_TIMER
? "cp15" : "",
751 type
== (ARCH_CP15_TIMER
| ARCH_MEM_TIMER
) ? " and " : "",
752 type
& ARCH_MEM_TIMER
? "mmio" : "",
753 (unsigned long)arch_timer_rate
/ 1000000,
754 (unsigned long)(arch_timer_rate
/ 10000) % 100,
755 type
& ARCH_CP15_TIMER
?
756 (arch_timer_uses_ppi
== VIRT_PPI
) ? "virt" : "phys" :
758 type
== (ARCH_CP15_TIMER
| ARCH_MEM_TIMER
) ? "/" : "",
759 type
& ARCH_MEM_TIMER
?
760 arch_timer_mem_use_virtual
? "virt" : "phys" :
764 u32
arch_timer_get_rate(void)
766 return arch_timer_rate
;
769 static u64
arch_counter_get_cntvct_mem(void)
771 u32 vct_lo
, vct_hi
, tmp_hi
;
774 vct_hi
= readl_relaxed(arch_counter_base
+ CNTVCT_HI
);
775 vct_lo
= readl_relaxed(arch_counter_base
+ CNTVCT_LO
);
776 tmp_hi
= readl_relaxed(arch_counter_base
+ CNTVCT_HI
);
777 } while (vct_hi
!= tmp_hi
);
779 return ((u64
) vct_hi
<< 32) | vct_lo
;
782 static struct arch_timer_kvm_info arch_timer_kvm_info
;
784 struct arch_timer_kvm_info
*arch_timer_get_kvm_info(void)
786 return &arch_timer_kvm_info
;
789 static void __init
arch_counter_register(unsigned type
)
793 /* Register the CP15 based counter if we have one */
794 if (type
& ARCH_CP15_TIMER
) {
795 if (IS_ENABLED(CONFIG_ARM64
) || arch_timer_uses_ppi
== VIRT_PPI
)
796 arch_timer_read_counter
= arch_counter_get_cntvct
;
798 arch_timer_read_counter
= arch_counter_get_cntpct
;
800 clocksource_counter
.archdata
.vdso_direct
= true;
802 #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
804 * Don't use the vdso fastpath if errata require using
805 * the out-of-line counter accessor.
807 if (static_branch_unlikely(&arch_timer_read_ool_enabled
))
808 clocksource_counter
.archdata
.vdso_direct
= false;
811 arch_timer_read_counter
= arch_counter_get_cntvct_mem
;
814 if (!arch_counter_suspend_stop
)
815 clocksource_counter
.flags
|= CLOCK_SOURCE_SUSPEND_NONSTOP
;
816 start_count
= arch_timer_read_counter();
817 clocksource_register_hz(&clocksource_counter
, arch_timer_rate
);
818 cyclecounter
.mult
= clocksource_counter
.mult
;
819 cyclecounter
.shift
= clocksource_counter
.shift
;
820 timecounter_init(&arch_timer_kvm_info
.timecounter
,
821 &cyclecounter
, start_count
);
823 /* 56 bits minimum, so we assume worst case rollover */
824 sched_clock_register(arch_timer_read_counter
, 56, arch_timer_rate
);
827 static void arch_timer_stop(struct clock_event_device
*clk
)
829 pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
830 clk
->irq
, smp_processor_id());
832 disable_percpu_irq(arch_timer_ppi
[arch_timer_uses_ppi
]);
833 if (arch_timer_has_nonsecure_ppi())
834 disable_percpu_irq(arch_timer_ppi
[PHYS_NONSECURE_PPI
]);
836 clk
->set_state_shutdown(clk
);
839 static int arch_timer_dying_cpu(unsigned int cpu
)
841 struct clock_event_device
*clk
= this_cpu_ptr(arch_timer_evt
);
843 arch_timer_stop(clk
);
848 static unsigned int saved_cntkctl
;
849 static int arch_timer_cpu_pm_notify(struct notifier_block
*self
,
850 unsigned long action
, void *hcpu
)
852 if (action
== CPU_PM_ENTER
)
853 saved_cntkctl
= arch_timer_get_cntkctl();
854 else if (action
== CPU_PM_ENTER_FAILED
|| action
== CPU_PM_EXIT
)
855 arch_timer_set_cntkctl(saved_cntkctl
);
859 static struct notifier_block arch_timer_cpu_pm_notifier
= {
860 .notifier_call
= arch_timer_cpu_pm_notify
,
863 static int __init
arch_timer_cpu_pm_init(void)
865 return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier
);
868 static void __init
arch_timer_cpu_pm_deinit(void)
870 WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier
));
874 static int __init
arch_timer_cpu_pm_init(void)
879 static void __init
arch_timer_cpu_pm_deinit(void)
884 static int __init
arch_timer_register(void)
889 arch_timer_evt
= alloc_percpu(struct clock_event_device
);
890 if (!arch_timer_evt
) {
895 ppi
= arch_timer_ppi
[arch_timer_uses_ppi
];
896 switch (arch_timer_uses_ppi
) {
898 err
= request_percpu_irq(ppi
, arch_timer_handler_virt
,
899 "arch_timer", arch_timer_evt
);
901 case PHYS_SECURE_PPI
:
902 case PHYS_NONSECURE_PPI
:
903 err
= request_percpu_irq(ppi
, arch_timer_handler_phys
,
904 "arch_timer", arch_timer_evt
);
905 if (!err
&& arch_timer_ppi
[PHYS_NONSECURE_PPI
]) {
906 ppi
= arch_timer_ppi
[PHYS_NONSECURE_PPI
];
907 err
= request_percpu_irq(ppi
, arch_timer_handler_phys
,
908 "arch_timer", arch_timer_evt
);
910 free_percpu_irq(arch_timer_ppi
[PHYS_SECURE_PPI
],
915 err
= request_percpu_irq(ppi
, arch_timer_handler_phys
,
916 "arch_timer", arch_timer_evt
);
923 pr_err("arch_timer: can't register interrupt %d (%d)\n",
928 err
= arch_timer_cpu_pm_init();
930 goto out_unreg_notify
;
933 /* Register and immediately configure the timer on the boot CPU */
934 err
= cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING
,
935 "clockevents/arm/arch_timer:starting",
936 arch_timer_starting_cpu
, arch_timer_dying_cpu
);
938 goto out_unreg_cpupm
;
942 arch_timer_cpu_pm_deinit();
945 free_percpu_irq(arch_timer_ppi
[arch_timer_uses_ppi
], arch_timer_evt
);
946 if (arch_timer_has_nonsecure_ppi())
947 free_percpu_irq(arch_timer_ppi
[PHYS_NONSECURE_PPI
],
951 free_percpu(arch_timer_evt
);
956 static int __init
arch_timer_mem_register(void __iomem
*base
, unsigned int irq
)
960 struct arch_timer
*t
;
962 t
= kzalloc(sizeof(*t
), GFP_KERNEL
);
968 __arch_timer_setup(ARCH_MEM_TIMER
, &t
->evt
);
970 if (arch_timer_mem_use_virtual
)
971 func
= arch_timer_handler_virt_mem
;
973 func
= arch_timer_handler_phys_mem
;
975 ret
= request_irq(irq
, func
, IRQF_TIMER
, "arch_mem_timer", &t
->evt
);
977 pr_err("arch_timer: Failed to request mem timer irq\n");
984 static const struct of_device_id arch_timer_of_match
[] __initconst
= {
985 { .compatible
= "arm,armv7-timer", },
986 { .compatible
= "arm,armv8-timer", },
990 static const struct of_device_id arch_timer_mem_of_match
[] __initconst
= {
991 { .compatible
= "arm,armv7-timer-mem", },
996 arch_timer_needs_probing(int type
, const struct of_device_id
*matches
)
998 struct device_node
*dn
;
999 bool needs_probing
= false;
1001 dn
= of_find_matching_node(NULL
, matches
);
1002 if (dn
&& of_device_is_available(dn
) && !(arch_timers_present
& type
))
1003 needs_probing
= true;
1006 return needs_probing
;
1009 static int __init
arch_timer_common_init(void)
1011 unsigned mask
= ARCH_CP15_TIMER
| ARCH_MEM_TIMER
;
1013 /* Wait until both nodes are probed if we have two timers */
1014 if ((arch_timers_present
& mask
) != mask
) {
1015 if (arch_timer_needs_probing(ARCH_MEM_TIMER
, arch_timer_mem_of_match
))
1017 if (arch_timer_needs_probing(ARCH_CP15_TIMER
, arch_timer_of_match
))
1021 arch_timer_banner(arch_timers_present
);
1022 arch_counter_register(arch_timers_present
);
1023 return arch_timer_arch_init();
1026 static int __init
arch_timer_init(void)
1030 * If HYP mode is available, we know that the physical timer
1031 * has been configured to be accessible from PL1. Use it, so
1032 * that a guest can use the virtual timer instead.
1034 * If no interrupt provided for virtual timer, we'll have to
1035 * stick to the physical timer. It'd better be accessible...
1037 * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE
1038 * accesses to CNTP_*_EL1 registers are silently redirected to
1039 * their CNTHP_*_EL2 counterparts, and use a different PPI
1042 if (is_hyp_mode_available() || !arch_timer_ppi
[VIRT_PPI
]) {
1045 if (is_kernel_in_hyp_mode()) {
1046 arch_timer_uses_ppi
= HYP_PPI
;
1047 has_ppi
= !!arch_timer_ppi
[HYP_PPI
];
1049 arch_timer_uses_ppi
= PHYS_SECURE_PPI
;
1050 has_ppi
= (!!arch_timer_ppi
[PHYS_SECURE_PPI
] ||
1051 !!arch_timer_ppi
[PHYS_NONSECURE_PPI
]);
1055 pr_warn("arch_timer: No interrupt available, giving up\n");
1060 ret
= arch_timer_register();
1064 ret
= arch_timer_common_init();
1068 arch_timer_kvm_info
.virtual_irq
= arch_timer_ppi
[VIRT_PPI
];
1073 static int __init
arch_timer_of_init(struct device_node
*np
)
1077 if (arch_timers_present
& ARCH_CP15_TIMER
) {
1078 pr_warn("arch_timer: multiple nodes in dt, skipping\n");
1082 arch_timers_present
|= ARCH_CP15_TIMER
;
1083 for (i
= PHYS_SECURE_PPI
; i
< MAX_TIMER_PPI
; i
++)
1084 arch_timer_ppi
[i
] = irq_of_parse_and_map(np
, i
);
1086 arch_timer_detect_rate(NULL
, np
);
1088 arch_timer_c3stop
= !of_property_read_bool(np
, "always-on");
1090 /* Check for globally applicable workarounds */
1091 arch_timer_check_ool_workaround(ate_match_dt
, np
);
1092 arch_timer_check_ool_workaround(ate_match_global_cap_id
, NULL
);
1095 * If we cannot rely on firmware initializing the timer registers then
1096 * we should use the physical timers instead.
1098 if (IS_ENABLED(CONFIG_ARM
) &&
1099 of_property_read_bool(np
, "arm,cpu-registers-not-fw-configured"))
1100 arch_timer_uses_ppi
= PHYS_SECURE_PPI
;
1102 /* On some systems, the counter stops ticking when in suspend. */
1103 arch_counter_suspend_stop
= of_property_read_bool(np
,
1104 "arm,no-tick-in-suspend");
1106 return arch_timer_init();
1108 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer
, "arm,armv7-timer", arch_timer_of_init
);
1109 CLOCKSOURCE_OF_DECLARE(armv8_arch_timer
, "arm,armv8-timer", arch_timer_of_init
);
1111 static int __init
arch_timer_mem_init(struct device_node
*np
)
1113 struct device_node
*frame
, *best_frame
= NULL
;
1114 void __iomem
*cntctlbase
, *base
;
1115 unsigned int irq
, ret
= -EINVAL
;
1118 arch_timers_present
|= ARCH_MEM_TIMER
;
1119 cntctlbase
= of_iomap(np
, 0);
1121 pr_err("arch_timer: Can't find CNTCTLBase\n");
1125 cnttidr
= readl_relaxed(cntctlbase
+ CNTTIDR
);
1128 * Try to find a virtual capable frame. Otherwise fall back to a
1129 * physical capable frame.
1131 for_each_available_child_of_node(np
, frame
) {
1135 if (of_property_read_u32(frame
, "frame-number", &n
)) {
1136 pr_err("arch_timer: Missing frame-number\n");
1141 /* Try enabling everything, and see what sticks */
1142 cntacr
= CNTACR_RFRQ
| CNTACR_RWPT
| CNTACR_RPCT
|
1143 CNTACR_RWVT
| CNTACR_RVOFF
| CNTACR_RVCT
;
1144 writel_relaxed(cntacr
, cntctlbase
+ CNTACR(n
));
1145 cntacr
= readl_relaxed(cntctlbase
+ CNTACR(n
));
1147 if ((cnttidr
& CNTTIDR_VIRT(n
)) &&
1148 !(~cntacr
& (CNTACR_RWVT
| CNTACR_RVCT
))) {
1149 of_node_put(best_frame
);
1151 arch_timer_mem_use_virtual
= true;
1155 if (~cntacr
& (CNTACR_RWPT
| CNTACR_RPCT
))
1158 of_node_put(best_frame
);
1159 best_frame
= of_node_get(frame
);
1163 base
= arch_counter_base
= of_io_request_and_map(best_frame
, 0,
1166 pr_err("arch_timer: Can't map frame's registers\n");
1170 if (arch_timer_mem_use_virtual
)
1171 irq
= irq_of_parse_and_map(best_frame
, 1);
1173 irq
= irq_of_parse_and_map(best_frame
, 0);
1177 pr_err("arch_timer: Frame missing %s irq",
1178 arch_timer_mem_use_virtual
? "virt" : "phys");
1182 arch_timer_detect_rate(base
, np
);
1183 ret
= arch_timer_mem_register(base
, irq
);
1187 return arch_timer_common_init();
1189 iounmap(cntctlbase
);
1190 of_node_put(best_frame
);
1193 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem
, "arm,armv7-timer-mem",
1194 arch_timer_mem_init
);
1197 static int __init
map_generic_timer_interrupt(u32 interrupt
, u32 flags
)
1199 int trigger
, polarity
;
1204 trigger
= (flags
& ACPI_GTDT_INTERRUPT_MODE
) ? ACPI_EDGE_SENSITIVE
1205 : ACPI_LEVEL_SENSITIVE
;
1207 polarity
= (flags
& ACPI_GTDT_INTERRUPT_POLARITY
) ? ACPI_ACTIVE_LOW
1210 return acpi_register_gsi(NULL
, interrupt
, trigger
, polarity
);
1213 /* Initialize per-processor generic timer */
1214 static int __init
arch_timer_acpi_init(struct acpi_table_header
*table
)
1216 struct acpi_table_gtdt
*gtdt
;
1218 if (arch_timers_present
& ARCH_CP15_TIMER
) {
1219 pr_warn("arch_timer: already initialized, skipping\n");
1223 gtdt
= container_of(table
, struct acpi_table_gtdt
, header
);
1225 arch_timers_present
|= ARCH_CP15_TIMER
;
1227 arch_timer_ppi
[PHYS_SECURE_PPI
] =
1228 map_generic_timer_interrupt(gtdt
->secure_el1_interrupt
,
1229 gtdt
->secure_el1_flags
);
1231 arch_timer_ppi
[PHYS_NONSECURE_PPI
] =
1232 map_generic_timer_interrupt(gtdt
->non_secure_el1_interrupt
,
1233 gtdt
->non_secure_el1_flags
);
1235 arch_timer_ppi
[VIRT_PPI
] =
1236 map_generic_timer_interrupt(gtdt
->virtual_timer_interrupt
,
1237 gtdt
->virtual_timer_flags
);
1239 arch_timer_ppi
[HYP_PPI
] =
1240 map_generic_timer_interrupt(gtdt
->non_secure_el2_interrupt
,
1241 gtdt
->non_secure_el2_flags
);
1243 /* Get the frequency from CNTFRQ */
1244 arch_timer_detect_rate(NULL
, NULL
);
1246 /* Always-on capability */
1247 arch_timer_c3stop
= !(gtdt
->non_secure_el1_flags
& ACPI_GTDT_ALWAYS_ON
);
1249 /* Check for globally applicable workarounds */
1250 arch_timer_check_ool_workaround(ate_match_global_cap_id
, NULL
);
1255 CLOCKSOURCE_ACPI_DECLARE(arch_timer
, ACPI_SIG_GTDT
, arch_timer_acpi_init
);