2 * linux/drivers/clocksource/arm_arch_timer.c
4 * Copyright (C) 2011 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #define pr_fmt(fmt) "arm_arch_timer: " fmt
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/device.h>
17 #include <linux/smp.h>
18 #include <linux/cpu.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/clockchips.h>
21 #include <linux/clocksource.h>
22 #include <linux/interrupt.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_address.h>
26 #include <linux/slab.h>
27 #include <linux/sched/clock.h>
28 #include <linux/sched_clock.h>
29 #include <linux/acpi.h>
31 #include <asm/arch_timer.h>
34 #include <clocksource/arm_arch_timer.h>
37 #define pr_fmt(fmt) "arch_timer: " fmt
40 #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
42 #define CNTACR(n) (0x40 + ((n) * 4))
43 #define CNTACR_RPCT BIT(0)
44 #define CNTACR_RVCT BIT(1)
45 #define CNTACR_RFRQ BIT(2)
46 #define CNTACR_RVOFF BIT(3)
47 #define CNTACR_RWVT BIT(4)
48 #define CNTACR_RWPT BIT(5)
50 #define CNTVCT_LO 0x08
51 #define CNTVCT_HI 0x0c
53 #define CNTP_TVAL 0x28
55 #define CNTV_TVAL 0x38
58 static unsigned arch_timers_present __initdata
;
60 static void __iomem
*arch_counter_base
;
64 struct clock_event_device evt
;
67 #define to_arch_timer(e) container_of(e, struct arch_timer, evt)
69 static u32 arch_timer_rate
;
70 static int arch_timer_ppi
[ARCH_TIMER_MAX_TIMER_PPI
];
72 static struct clock_event_device __percpu
*arch_timer_evt
;
74 static enum arch_timer_ppi_nr arch_timer_uses_ppi
= ARCH_TIMER_VIRT_PPI
;
75 static bool arch_timer_c3stop
;
76 static bool arch_timer_mem_use_virtual
;
77 static bool arch_counter_suspend_stop
;
78 static bool vdso_default
= true;
80 static bool evtstrm_enable
= IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM
);
82 static int __init
early_evtstrm_cfg(char *buf
)
84 return strtobool(buf
, &evtstrm_enable
);
86 early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg
);
89 * Architected system timer support.
92 static __always_inline
93 void arch_timer_reg_write(int access
, enum arch_timer_reg reg
, u32 val
,
94 struct clock_event_device
*clk
)
96 if (access
== ARCH_TIMER_MEM_PHYS_ACCESS
) {
97 struct arch_timer
*timer
= to_arch_timer(clk
);
99 case ARCH_TIMER_REG_CTRL
:
100 writel_relaxed(val
, timer
->base
+ CNTP_CTL
);
102 case ARCH_TIMER_REG_TVAL
:
103 writel_relaxed(val
, timer
->base
+ CNTP_TVAL
);
106 } else if (access
== ARCH_TIMER_MEM_VIRT_ACCESS
) {
107 struct arch_timer
*timer
= to_arch_timer(clk
);
109 case ARCH_TIMER_REG_CTRL
:
110 writel_relaxed(val
, timer
->base
+ CNTV_CTL
);
112 case ARCH_TIMER_REG_TVAL
:
113 writel_relaxed(val
, timer
->base
+ CNTV_TVAL
);
117 arch_timer_reg_write_cp15(access
, reg
, val
);
121 static __always_inline
122 u32
arch_timer_reg_read(int access
, enum arch_timer_reg reg
,
123 struct clock_event_device
*clk
)
127 if (access
== ARCH_TIMER_MEM_PHYS_ACCESS
) {
128 struct arch_timer
*timer
= to_arch_timer(clk
);
130 case ARCH_TIMER_REG_CTRL
:
131 val
= readl_relaxed(timer
->base
+ CNTP_CTL
);
133 case ARCH_TIMER_REG_TVAL
:
134 val
= readl_relaxed(timer
->base
+ CNTP_TVAL
);
137 } else if (access
== ARCH_TIMER_MEM_VIRT_ACCESS
) {
138 struct arch_timer
*timer
= to_arch_timer(clk
);
140 case ARCH_TIMER_REG_CTRL
:
141 val
= readl_relaxed(timer
->base
+ CNTV_CTL
);
143 case ARCH_TIMER_REG_TVAL
:
144 val
= readl_relaxed(timer
->base
+ CNTV_TVAL
);
148 val
= arch_timer_reg_read_cp15(access
, reg
);
155 * Default to cp15 based access because arm64 uses this function for
156 * sched_clock() before DT is probed and the cp15 method is guaranteed
157 * to exist on arm64. arm doesn't use this before DT is probed so even
158 * if we don't have the cp15 accessors we won't have a problem.
160 u64 (*arch_timer_read_counter
)(void) = arch_counter_get_cntvct
;
162 static u64
arch_counter_read(struct clocksource
*cs
)
164 return arch_timer_read_counter();
167 static u64
arch_counter_read_cc(const struct cyclecounter
*cc
)
169 return arch_timer_read_counter();
172 static struct clocksource clocksource_counter
= {
173 .name
= "arch_sys_counter",
175 .read
= arch_counter_read
,
176 .mask
= CLOCKSOURCE_MASK(56),
177 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
180 static struct cyclecounter cyclecounter __ro_after_init
= {
181 .read
= arch_counter_read_cc
,
182 .mask
= CLOCKSOURCE_MASK(56),
185 struct ate_acpi_oem_info
{
186 char oem_id
[ACPI_OEM_ID_SIZE
+ 1];
187 char oem_table_id
[ACPI_OEM_TABLE_ID_SIZE
+ 1];
191 #ifdef CONFIG_FSL_ERRATUM_A008585
193 * The number of retries is an arbitrary value well beyond the highest number
194 * of iterations the loop has been observed to take.
196 #define __fsl_a008585_read_reg(reg) ({ \
198 int _retries = 200; \
201 _old = read_sysreg(reg); \
202 _new = read_sysreg(reg); \
204 } while (unlikely(_old != _new) && _retries); \
206 WARN_ON_ONCE(!_retries); \
210 static u32 notrace
fsl_a008585_read_cntp_tval_el0(void)
212 return __fsl_a008585_read_reg(cntp_tval_el0
);
215 static u32 notrace
fsl_a008585_read_cntv_tval_el0(void)
217 return __fsl_a008585_read_reg(cntv_tval_el0
);
220 static u64 notrace
fsl_a008585_read_cntvct_el0(void)
222 return __fsl_a008585_read_reg(cntvct_el0
);
226 #ifdef CONFIG_HISILICON_ERRATUM_161010101
228 * Verify whether the value of the second read is larger than the first by
229 * less than 32 is the only way to confirm the value is correct, so clear the
230 * lower 5 bits to check whether the difference is greater than 32 or not.
231 * Theoretically the erratum should not occur more than twice in succession
232 * when reading the system counter, but it is possible that some interrupts
233 * may lead to more than twice read errors, triggering the warning, so setting
234 * the number of retries far beyond the number of iterations the loop has been
237 #define __hisi_161010101_read_reg(reg) ({ \
242 _old = read_sysreg(reg); \
243 _new = read_sysreg(reg); \
245 } while (unlikely((_new - _old) >> 5) && _retries); \
247 WARN_ON_ONCE(!_retries); \
251 static u32 notrace
hisi_161010101_read_cntp_tval_el0(void)
253 return __hisi_161010101_read_reg(cntp_tval_el0
);
256 static u32 notrace
hisi_161010101_read_cntv_tval_el0(void)
258 return __hisi_161010101_read_reg(cntv_tval_el0
);
261 static u64 notrace
hisi_161010101_read_cntvct_el0(void)
263 return __hisi_161010101_read_reg(cntvct_el0
);
266 static struct ate_acpi_oem_info hisi_161010101_oem_info
[] = {
268 * Note that trailing spaces are required to properly match
269 * the OEM table information.
273 .oem_table_id
= "HIP05 ",
278 .oem_table_id
= "HIP06 ",
283 .oem_table_id
= "HIP07 ",
286 { /* Sentinel indicating the end of the OEM array */ },
290 #ifdef CONFIG_ARM64_ERRATUM_858921
291 static u64 notrace
arm64_858921_read_cntvct_el0(void)
295 old
= read_sysreg(cntvct_el0
);
296 new = read_sysreg(cntvct_el0
);
297 return (((old
^ new) >> 32) & 1) ? old
: new;
301 #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
302 DEFINE_PER_CPU(const struct arch_timer_erratum_workaround
*,
303 timer_unstable_counter_workaround
);
304 EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround
);
306 DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled
);
307 EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled
);
309 static void erratum_set_next_event_tval_generic(const int access
, unsigned long evt
,
310 struct clock_event_device
*clk
)
313 u64 cval
= evt
+ arch_counter_get_cntvct();
315 ctrl
= arch_timer_reg_read(access
, ARCH_TIMER_REG_CTRL
, clk
);
316 ctrl
|= ARCH_TIMER_CTRL_ENABLE
;
317 ctrl
&= ~ARCH_TIMER_CTRL_IT_MASK
;
319 if (access
== ARCH_TIMER_PHYS_ACCESS
)
320 write_sysreg(cval
, cntp_cval_el0
);
322 write_sysreg(cval
, cntv_cval_el0
);
324 arch_timer_reg_write(access
, ARCH_TIMER_REG_CTRL
, ctrl
, clk
);
327 static __maybe_unused
int erratum_set_next_event_tval_virt(unsigned long evt
,
328 struct clock_event_device
*clk
)
330 erratum_set_next_event_tval_generic(ARCH_TIMER_VIRT_ACCESS
, evt
, clk
);
334 static __maybe_unused
int erratum_set_next_event_tval_phys(unsigned long evt
,
335 struct clock_event_device
*clk
)
337 erratum_set_next_event_tval_generic(ARCH_TIMER_PHYS_ACCESS
, evt
, clk
);
341 static const struct arch_timer_erratum_workaround ool_workarounds
[] = {
342 #ifdef CONFIG_FSL_ERRATUM_A008585
344 .match_type
= ate_match_dt
,
345 .id
= "fsl,erratum-a008585",
346 .desc
= "Freescale erratum a005858",
347 .read_cntp_tval_el0
= fsl_a008585_read_cntp_tval_el0
,
348 .read_cntv_tval_el0
= fsl_a008585_read_cntv_tval_el0
,
349 .read_cntvct_el0
= fsl_a008585_read_cntvct_el0
,
350 .set_next_event_phys
= erratum_set_next_event_tval_phys
,
351 .set_next_event_virt
= erratum_set_next_event_tval_virt
,
354 #ifdef CONFIG_HISILICON_ERRATUM_161010101
356 .match_type
= ate_match_dt
,
357 .id
= "hisilicon,erratum-161010101",
358 .desc
= "HiSilicon erratum 161010101",
359 .read_cntp_tval_el0
= hisi_161010101_read_cntp_tval_el0
,
360 .read_cntv_tval_el0
= hisi_161010101_read_cntv_tval_el0
,
361 .read_cntvct_el0
= hisi_161010101_read_cntvct_el0
,
362 .set_next_event_phys
= erratum_set_next_event_tval_phys
,
363 .set_next_event_virt
= erratum_set_next_event_tval_virt
,
366 .match_type
= ate_match_acpi_oem_info
,
367 .id
= hisi_161010101_oem_info
,
368 .desc
= "HiSilicon erratum 161010101",
369 .read_cntp_tval_el0
= hisi_161010101_read_cntp_tval_el0
,
370 .read_cntv_tval_el0
= hisi_161010101_read_cntv_tval_el0
,
371 .read_cntvct_el0
= hisi_161010101_read_cntvct_el0
,
372 .set_next_event_phys
= erratum_set_next_event_tval_phys
,
373 .set_next_event_virt
= erratum_set_next_event_tval_virt
,
376 #ifdef CONFIG_ARM64_ERRATUM_858921
378 .match_type
= ate_match_local_cap_id
,
379 .id
= (void *)ARM64_WORKAROUND_858921
,
380 .desc
= "ARM erratum 858921",
381 .read_cntvct_el0
= arm64_858921_read_cntvct_el0
,
386 typedef bool (*ate_match_fn_t
)(const struct arch_timer_erratum_workaround
*,
390 bool arch_timer_check_dt_erratum(const struct arch_timer_erratum_workaround
*wa
,
393 const struct device_node
*np
= arg
;
395 return of_property_read_bool(np
, wa
->id
);
399 bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround
*wa
,
402 return this_cpu_has_cap((uintptr_t)wa
->id
);
407 bool arch_timer_check_acpi_oem_erratum(const struct arch_timer_erratum_workaround
*wa
,
410 static const struct ate_acpi_oem_info empty_oem_info
= {};
411 const struct ate_acpi_oem_info
*info
= wa
->id
;
412 const struct acpi_table_header
*table
= arg
;
414 /* Iterate over the ACPI OEM info array, looking for a match */
415 while (memcmp(info
, &empty_oem_info
, sizeof(*info
))) {
416 if (!memcmp(info
->oem_id
, table
->oem_id
, ACPI_OEM_ID_SIZE
) &&
417 !memcmp(info
->oem_table_id
, table
->oem_table_id
, ACPI_OEM_TABLE_ID_SIZE
) &&
418 info
->oem_revision
== table
->oem_revision
)
427 static const struct arch_timer_erratum_workaround
*
428 arch_timer_iterate_errata(enum arch_timer_erratum_match_type type
,
429 ate_match_fn_t match_fn
,
434 for (i
= 0; i
< ARRAY_SIZE(ool_workarounds
); i
++) {
435 if (ool_workarounds
[i
].match_type
!= type
)
438 if (match_fn(&ool_workarounds
[i
], arg
))
439 return &ool_workarounds
[i
];
446 void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround
*wa
,
452 __this_cpu_write(timer_unstable_counter_workaround
, wa
);
454 for_each_possible_cpu(i
)
455 per_cpu(timer_unstable_counter_workaround
, i
) = wa
;
458 static_branch_enable(&arch_timer_read_ool_enabled
);
461 * Don't use the vdso fastpath if errata require using the
462 * out-of-line counter accessor. We may change our mind pretty
463 * late in the game (with a per-CPU erratum, for example), so
464 * change both the default value and the vdso itself.
466 if (wa
->read_cntvct_el0
) {
467 clocksource_counter
.archdata
.vdso_direct
= false;
468 vdso_default
= false;
472 static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type type
,
475 const struct arch_timer_erratum_workaround
*wa
;
476 ate_match_fn_t match_fn
= NULL
;
481 match_fn
= arch_timer_check_dt_erratum
;
483 case ate_match_local_cap_id
:
484 match_fn
= arch_timer_check_local_cap_erratum
;
487 case ate_match_acpi_oem_info
:
488 match_fn
= arch_timer_check_acpi_oem_erratum
;
495 wa
= arch_timer_iterate_errata(type
, match_fn
, arg
);
499 if (needs_unstable_timer_counter_workaround()) {
500 const struct arch_timer_erratum_workaround
*__wa
;
501 __wa
= __this_cpu_read(timer_unstable_counter_workaround
);
502 if (__wa
&& wa
!= __wa
)
503 pr_warn("Can't enable workaround for %s (clashes with %s\n)",
504 wa
->desc
, __wa
->desc
);
510 arch_timer_enable_workaround(wa
, local
);
511 pr_info("Enabling %s workaround for %s\n",
512 local
? "local" : "global", wa
->desc
);
515 #define erratum_handler(fn, r, ...) \
518 if (needs_unstable_timer_counter_workaround()) { \
519 const struct arch_timer_erratum_workaround *__wa; \
520 __wa = __this_cpu_read(timer_unstable_counter_workaround); \
521 if (__wa && __wa->fn) { \
522 r = __wa->fn(__VA_ARGS__); \
533 static bool arch_timer_this_cpu_has_cntvct_wa(void)
535 const struct arch_timer_erratum_workaround
*wa
;
537 wa
= __this_cpu_read(timer_unstable_counter_workaround
);
538 return wa
&& wa
->read_cntvct_el0
;
541 #define arch_timer_check_ool_workaround(t,a) do { } while(0)
542 #define erratum_set_next_event_tval_virt(...) ({BUG(); 0;})
543 #define erratum_set_next_event_tval_phys(...) ({BUG(); 0;})
544 #define erratum_handler(fn, r, ...) ({false;})
545 #define arch_timer_this_cpu_has_cntvct_wa() ({false;})
546 #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
548 static __always_inline irqreturn_t
timer_handler(const int access
,
549 struct clock_event_device
*evt
)
553 ctrl
= arch_timer_reg_read(access
, ARCH_TIMER_REG_CTRL
, evt
);
554 if (ctrl
& ARCH_TIMER_CTRL_IT_STAT
) {
555 ctrl
|= ARCH_TIMER_CTRL_IT_MASK
;
556 arch_timer_reg_write(access
, ARCH_TIMER_REG_CTRL
, ctrl
, evt
);
557 evt
->event_handler(evt
);
564 static irqreturn_t
arch_timer_handler_virt(int irq
, void *dev_id
)
566 struct clock_event_device
*evt
= dev_id
;
568 return timer_handler(ARCH_TIMER_VIRT_ACCESS
, evt
);
571 static irqreturn_t
arch_timer_handler_phys(int irq
, void *dev_id
)
573 struct clock_event_device
*evt
= dev_id
;
575 return timer_handler(ARCH_TIMER_PHYS_ACCESS
, evt
);
578 static irqreturn_t
arch_timer_handler_phys_mem(int irq
, void *dev_id
)
580 struct clock_event_device
*evt
= dev_id
;
582 return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS
, evt
);
585 static irqreturn_t
arch_timer_handler_virt_mem(int irq
, void *dev_id
)
587 struct clock_event_device
*evt
= dev_id
;
589 return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS
, evt
);
592 static __always_inline
int timer_shutdown(const int access
,
593 struct clock_event_device
*clk
)
597 ctrl
= arch_timer_reg_read(access
, ARCH_TIMER_REG_CTRL
, clk
);
598 ctrl
&= ~ARCH_TIMER_CTRL_ENABLE
;
599 arch_timer_reg_write(access
, ARCH_TIMER_REG_CTRL
, ctrl
, clk
);
604 static int arch_timer_shutdown_virt(struct clock_event_device
*clk
)
606 return timer_shutdown(ARCH_TIMER_VIRT_ACCESS
, clk
);
609 static int arch_timer_shutdown_phys(struct clock_event_device
*clk
)
611 return timer_shutdown(ARCH_TIMER_PHYS_ACCESS
, clk
);
614 static int arch_timer_shutdown_virt_mem(struct clock_event_device
*clk
)
616 return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS
, clk
);
619 static int arch_timer_shutdown_phys_mem(struct clock_event_device
*clk
)
621 return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS
, clk
);
624 static __always_inline
void set_next_event(const int access
, unsigned long evt
,
625 struct clock_event_device
*clk
)
628 ctrl
= arch_timer_reg_read(access
, ARCH_TIMER_REG_CTRL
, clk
);
629 ctrl
|= ARCH_TIMER_CTRL_ENABLE
;
630 ctrl
&= ~ARCH_TIMER_CTRL_IT_MASK
;
631 arch_timer_reg_write(access
, ARCH_TIMER_REG_TVAL
, evt
, clk
);
632 arch_timer_reg_write(access
, ARCH_TIMER_REG_CTRL
, ctrl
, clk
);
635 static int arch_timer_set_next_event_virt(unsigned long evt
,
636 struct clock_event_device
*clk
)
640 if (erratum_handler(set_next_event_virt
, ret
, evt
, clk
))
643 set_next_event(ARCH_TIMER_VIRT_ACCESS
, evt
, clk
);
647 static int arch_timer_set_next_event_phys(unsigned long evt
,
648 struct clock_event_device
*clk
)
652 if (erratum_handler(set_next_event_phys
, ret
, evt
, clk
))
655 set_next_event(ARCH_TIMER_PHYS_ACCESS
, evt
, clk
);
659 static int arch_timer_set_next_event_virt_mem(unsigned long evt
,
660 struct clock_event_device
*clk
)
662 set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS
, evt
, clk
);
666 static int arch_timer_set_next_event_phys_mem(unsigned long evt
,
667 struct clock_event_device
*clk
)
669 set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS
, evt
, clk
);
673 static void __arch_timer_setup(unsigned type
,
674 struct clock_event_device
*clk
)
676 clk
->features
= CLOCK_EVT_FEAT_ONESHOT
;
678 if (type
== ARCH_TIMER_TYPE_CP15
) {
679 if (arch_timer_c3stop
)
680 clk
->features
|= CLOCK_EVT_FEAT_C3STOP
;
681 clk
->name
= "arch_sys_timer";
683 clk
->cpumask
= cpumask_of(smp_processor_id());
684 clk
->irq
= arch_timer_ppi
[arch_timer_uses_ppi
];
685 switch (arch_timer_uses_ppi
) {
686 case ARCH_TIMER_VIRT_PPI
:
687 clk
->set_state_shutdown
= arch_timer_shutdown_virt
;
688 clk
->set_state_oneshot_stopped
= arch_timer_shutdown_virt
;
689 clk
->set_next_event
= arch_timer_set_next_event_virt
;
691 case ARCH_TIMER_PHYS_SECURE_PPI
:
692 case ARCH_TIMER_PHYS_NONSECURE_PPI
:
693 case ARCH_TIMER_HYP_PPI
:
694 clk
->set_state_shutdown
= arch_timer_shutdown_phys
;
695 clk
->set_state_oneshot_stopped
= arch_timer_shutdown_phys
;
696 clk
->set_next_event
= arch_timer_set_next_event_phys
;
702 arch_timer_check_ool_workaround(ate_match_local_cap_id
, NULL
);
704 clk
->features
|= CLOCK_EVT_FEAT_DYNIRQ
;
705 clk
->name
= "arch_mem_timer";
707 clk
->cpumask
= cpu_all_mask
;
708 if (arch_timer_mem_use_virtual
) {
709 clk
->set_state_shutdown
= arch_timer_shutdown_virt_mem
;
710 clk
->set_state_oneshot_stopped
= arch_timer_shutdown_virt_mem
;
711 clk
->set_next_event
=
712 arch_timer_set_next_event_virt_mem
;
714 clk
->set_state_shutdown
= arch_timer_shutdown_phys_mem
;
715 clk
->set_state_oneshot_stopped
= arch_timer_shutdown_phys_mem
;
716 clk
->set_next_event
=
717 arch_timer_set_next_event_phys_mem
;
721 clk
->set_state_shutdown(clk
);
723 clockevents_config_and_register(clk
, arch_timer_rate
, 0xf, 0x7fffffff);
726 static void arch_timer_evtstrm_enable(int divider
)
728 u32 cntkctl
= arch_timer_get_cntkctl();
730 cntkctl
&= ~ARCH_TIMER_EVT_TRIGGER_MASK
;
731 /* Set the divider and enable virtual event stream */
732 cntkctl
|= (divider
<< ARCH_TIMER_EVT_TRIGGER_SHIFT
)
733 | ARCH_TIMER_VIRT_EVT_EN
;
734 arch_timer_set_cntkctl(cntkctl
);
735 elf_hwcap
|= HWCAP_EVTSTRM
;
737 compat_elf_hwcap
|= COMPAT_HWCAP_EVTSTRM
;
741 static void arch_timer_configure_evtstream(void)
743 int evt_stream_div
, pos
;
745 /* Find the closest power of two to the divisor */
746 evt_stream_div
= arch_timer_rate
/ ARCH_TIMER_EVT_STREAM_FREQ
;
747 pos
= fls(evt_stream_div
);
748 if (pos
> 1 && !(evt_stream_div
& (1 << (pos
- 2))))
750 /* enable event stream */
751 arch_timer_evtstrm_enable(min(pos
, 15));
754 static void arch_counter_set_user_access(void)
756 u32 cntkctl
= arch_timer_get_cntkctl();
758 /* Disable user access to the timers and both counters */
759 /* Also disable virtual event stream */
760 cntkctl
&= ~(ARCH_TIMER_USR_PT_ACCESS_EN
761 | ARCH_TIMER_USR_VT_ACCESS_EN
762 | ARCH_TIMER_USR_VCT_ACCESS_EN
763 | ARCH_TIMER_VIRT_EVT_EN
764 | ARCH_TIMER_USR_PCT_ACCESS_EN
);
767 * Enable user access to the virtual counter if it doesn't
768 * need to be workaround. The vdso may have been already
771 if (arch_timer_this_cpu_has_cntvct_wa())
772 pr_info("CPU%d: Trapping CNTVCT access\n", smp_processor_id());
774 cntkctl
|= ARCH_TIMER_USR_VCT_ACCESS_EN
;
776 arch_timer_set_cntkctl(cntkctl
);
779 static bool arch_timer_has_nonsecure_ppi(void)
781 return (arch_timer_uses_ppi
== ARCH_TIMER_PHYS_SECURE_PPI
&&
782 arch_timer_ppi
[ARCH_TIMER_PHYS_NONSECURE_PPI
]);
785 static u32
check_ppi_trigger(int irq
)
787 u32 flags
= irq_get_trigger_type(irq
);
789 if (flags
!= IRQF_TRIGGER_HIGH
&& flags
!= IRQF_TRIGGER_LOW
) {
790 pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq
);
791 pr_warn("WARNING: Please fix your firmware\n");
792 flags
= IRQF_TRIGGER_LOW
;
798 static int arch_timer_starting_cpu(unsigned int cpu
)
800 struct clock_event_device
*clk
= this_cpu_ptr(arch_timer_evt
);
803 __arch_timer_setup(ARCH_TIMER_TYPE_CP15
, clk
);
805 flags
= check_ppi_trigger(arch_timer_ppi
[arch_timer_uses_ppi
]);
806 enable_percpu_irq(arch_timer_ppi
[arch_timer_uses_ppi
], flags
);
808 if (arch_timer_has_nonsecure_ppi()) {
809 flags
= check_ppi_trigger(arch_timer_ppi
[ARCH_TIMER_PHYS_NONSECURE_PPI
]);
810 enable_percpu_irq(arch_timer_ppi
[ARCH_TIMER_PHYS_NONSECURE_PPI
],
814 arch_counter_set_user_access();
816 arch_timer_configure_evtstream();
822 * For historical reasons, when probing with DT we use whichever (non-zero)
823 * rate was probed first, and don't verify that others match. If the first node
824 * probed has a clock-frequency property, this overrides the HW register.
826 static void arch_timer_of_configure_rate(u32 rate
, struct device_node
*np
)
828 /* Who has more than one independent system counter? */
832 if (of_property_read_u32(np
, "clock-frequency", &arch_timer_rate
))
833 arch_timer_rate
= rate
;
835 /* Check the timer frequency. */
836 if (arch_timer_rate
== 0)
837 pr_warn("frequency not available\n");
840 static void arch_timer_banner(unsigned type
)
842 pr_info("%s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
843 type
& ARCH_TIMER_TYPE_CP15
? "cp15" : "",
844 type
== (ARCH_TIMER_TYPE_CP15
| ARCH_TIMER_TYPE_MEM
) ?
846 type
& ARCH_TIMER_TYPE_MEM
? "mmio" : "",
847 (unsigned long)arch_timer_rate
/ 1000000,
848 (unsigned long)(arch_timer_rate
/ 10000) % 100,
849 type
& ARCH_TIMER_TYPE_CP15
?
850 (arch_timer_uses_ppi
== ARCH_TIMER_VIRT_PPI
) ? "virt" : "phys" :
852 type
== (ARCH_TIMER_TYPE_CP15
| ARCH_TIMER_TYPE_MEM
) ? "/" : "",
853 type
& ARCH_TIMER_TYPE_MEM
?
854 arch_timer_mem_use_virtual
? "virt" : "phys" :
858 u32
arch_timer_get_rate(void)
860 return arch_timer_rate
;
863 static u64
arch_counter_get_cntvct_mem(void)
865 u32 vct_lo
, vct_hi
, tmp_hi
;
868 vct_hi
= readl_relaxed(arch_counter_base
+ CNTVCT_HI
);
869 vct_lo
= readl_relaxed(arch_counter_base
+ CNTVCT_LO
);
870 tmp_hi
= readl_relaxed(arch_counter_base
+ CNTVCT_HI
);
871 } while (vct_hi
!= tmp_hi
);
873 return ((u64
) vct_hi
<< 32) | vct_lo
;
876 static struct arch_timer_kvm_info arch_timer_kvm_info
;
878 struct arch_timer_kvm_info
*arch_timer_get_kvm_info(void)
880 return &arch_timer_kvm_info
;
883 static void __init
arch_counter_register(unsigned type
)
887 /* Register the CP15 based counter if we have one */
888 if (type
& ARCH_TIMER_TYPE_CP15
) {
889 if (IS_ENABLED(CONFIG_ARM64
) ||
890 arch_timer_uses_ppi
== ARCH_TIMER_VIRT_PPI
)
891 arch_timer_read_counter
= arch_counter_get_cntvct
;
893 arch_timer_read_counter
= arch_counter_get_cntpct
;
895 clocksource_counter
.archdata
.vdso_direct
= vdso_default
;
897 arch_timer_read_counter
= arch_counter_get_cntvct_mem
;
900 if (!arch_counter_suspend_stop
)
901 clocksource_counter
.flags
|= CLOCK_SOURCE_SUSPEND_NONSTOP
;
902 start_count
= arch_timer_read_counter();
903 clocksource_register_hz(&clocksource_counter
, arch_timer_rate
);
904 cyclecounter
.mult
= clocksource_counter
.mult
;
905 cyclecounter
.shift
= clocksource_counter
.shift
;
906 timecounter_init(&arch_timer_kvm_info
.timecounter
,
907 &cyclecounter
, start_count
);
909 /* 56 bits minimum, so we assume worst case rollover */
910 sched_clock_register(arch_timer_read_counter
, 56, arch_timer_rate
);
913 static void arch_timer_stop(struct clock_event_device
*clk
)
915 pr_debug("disable IRQ%d cpu #%d\n", clk
->irq
, smp_processor_id());
917 disable_percpu_irq(arch_timer_ppi
[arch_timer_uses_ppi
]);
918 if (arch_timer_has_nonsecure_ppi())
919 disable_percpu_irq(arch_timer_ppi
[ARCH_TIMER_PHYS_NONSECURE_PPI
]);
921 clk
->set_state_shutdown(clk
);
924 static int arch_timer_dying_cpu(unsigned int cpu
)
926 struct clock_event_device
*clk
= this_cpu_ptr(arch_timer_evt
);
928 arch_timer_stop(clk
);
933 static DEFINE_PER_CPU(unsigned long, saved_cntkctl
);
934 static int arch_timer_cpu_pm_notify(struct notifier_block
*self
,
935 unsigned long action
, void *hcpu
)
937 if (action
== CPU_PM_ENTER
)
938 __this_cpu_write(saved_cntkctl
, arch_timer_get_cntkctl());
939 else if (action
== CPU_PM_ENTER_FAILED
|| action
== CPU_PM_EXIT
)
940 arch_timer_set_cntkctl(__this_cpu_read(saved_cntkctl
));
944 static struct notifier_block arch_timer_cpu_pm_notifier
= {
945 .notifier_call
= arch_timer_cpu_pm_notify
,
948 static int __init
arch_timer_cpu_pm_init(void)
950 return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier
);
953 static void __init
arch_timer_cpu_pm_deinit(void)
955 WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier
));
959 static int __init
arch_timer_cpu_pm_init(void)
964 static void __init
arch_timer_cpu_pm_deinit(void)
969 static int __init
arch_timer_register(void)
974 arch_timer_evt
= alloc_percpu(struct clock_event_device
);
975 if (!arch_timer_evt
) {
980 ppi
= arch_timer_ppi
[arch_timer_uses_ppi
];
981 switch (arch_timer_uses_ppi
) {
982 case ARCH_TIMER_VIRT_PPI
:
983 err
= request_percpu_irq(ppi
, arch_timer_handler_virt
,
984 "arch_timer", arch_timer_evt
);
986 case ARCH_TIMER_PHYS_SECURE_PPI
:
987 case ARCH_TIMER_PHYS_NONSECURE_PPI
:
988 err
= request_percpu_irq(ppi
, arch_timer_handler_phys
,
989 "arch_timer", arch_timer_evt
);
990 if (!err
&& arch_timer_has_nonsecure_ppi()) {
991 ppi
= arch_timer_ppi
[ARCH_TIMER_PHYS_NONSECURE_PPI
];
992 err
= request_percpu_irq(ppi
, arch_timer_handler_phys
,
993 "arch_timer", arch_timer_evt
);
995 free_percpu_irq(arch_timer_ppi
[ARCH_TIMER_PHYS_SECURE_PPI
],
999 case ARCH_TIMER_HYP_PPI
:
1000 err
= request_percpu_irq(ppi
, arch_timer_handler_phys
,
1001 "arch_timer", arch_timer_evt
);
1008 pr_err("can't register interrupt %d (%d)\n", ppi
, err
);
1012 err
= arch_timer_cpu_pm_init();
1014 goto out_unreg_notify
;
1017 /* Register and immediately configure the timer on the boot CPU */
1018 err
= cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING
,
1019 "clockevents/arm/arch_timer:starting",
1020 arch_timer_starting_cpu
, arch_timer_dying_cpu
);
1022 goto out_unreg_cpupm
;
1026 arch_timer_cpu_pm_deinit();
1029 free_percpu_irq(arch_timer_ppi
[arch_timer_uses_ppi
], arch_timer_evt
);
1030 if (arch_timer_has_nonsecure_ppi())
1031 free_percpu_irq(arch_timer_ppi
[ARCH_TIMER_PHYS_NONSECURE_PPI
],
1035 free_percpu(arch_timer_evt
);
1040 static int __init
arch_timer_mem_register(void __iomem
*base
, unsigned int irq
)
1044 struct arch_timer
*t
;
1046 t
= kzalloc(sizeof(*t
), GFP_KERNEL
);
1052 __arch_timer_setup(ARCH_TIMER_TYPE_MEM
, &t
->evt
);
1054 if (arch_timer_mem_use_virtual
)
1055 func
= arch_timer_handler_virt_mem
;
1057 func
= arch_timer_handler_phys_mem
;
1059 ret
= request_irq(irq
, func
, IRQF_TIMER
, "arch_mem_timer", &t
->evt
);
1061 pr_err("Failed to request mem timer irq\n");
1068 static const struct of_device_id arch_timer_of_match
[] __initconst
= {
1069 { .compatible
= "arm,armv7-timer", },
1070 { .compatible
= "arm,armv8-timer", },
1074 static const struct of_device_id arch_timer_mem_of_match
[] __initconst
= {
1075 { .compatible
= "arm,armv7-timer-mem", },
1079 static bool __init
arch_timer_needs_of_probing(void)
1081 struct device_node
*dn
;
1082 bool needs_probing
= false;
1083 unsigned int mask
= ARCH_TIMER_TYPE_CP15
| ARCH_TIMER_TYPE_MEM
;
1085 /* We have two timers, and both device-tree nodes are probed. */
1086 if ((arch_timers_present
& mask
) == mask
)
1090 * Only one type of timer is probed,
1091 * check if we have another type of timer node in device-tree.
1093 if (arch_timers_present
& ARCH_TIMER_TYPE_CP15
)
1094 dn
= of_find_matching_node(NULL
, arch_timer_mem_of_match
);
1096 dn
= of_find_matching_node(NULL
, arch_timer_of_match
);
1098 if (dn
&& of_device_is_available(dn
))
1099 needs_probing
= true;
1103 return needs_probing
;
1106 static int __init
arch_timer_common_init(void)
1108 arch_timer_banner(arch_timers_present
);
1109 arch_counter_register(arch_timers_present
);
1110 return arch_timer_arch_init();
1114 * arch_timer_select_ppi() - Select suitable PPI for the current system.
1116 * If HYP mode is available, we know that the physical timer
1117 * has been configured to be accessible from PL1. Use it, so
1118 * that a guest can use the virtual timer instead.
1120 * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE
1121 * accesses to CNTP_*_EL1 registers are silently redirected to
1122 * their CNTHP_*_EL2 counterparts, and use a different PPI
1125 * If no interrupt provided for virtual timer, we'll have to
1126 * stick to the physical timer. It'd better be accessible...
1127 * For arm64 we never use the secure interrupt.
1129 * Return: a suitable PPI type for the current system.
1131 static enum arch_timer_ppi_nr __init
arch_timer_select_ppi(void)
1133 if (is_kernel_in_hyp_mode())
1134 return ARCH_TIMER_HYP_PPI
;
1136 if (!is_hyp_mode_available() && arch_timer_ppi
[ARCH_TIMER_VIRT_PPI
])
1137 return ARCH_TIMER_VIRT_PPI
;
1139 if (IS_ENABLED(CONFIG_ARM64
))
1140 return ARCH_TIMER_PHYS_NONSECURE_PPI
;
1142 return ARCH_TIMER_PHYS_SECURE_PPI
;
1145 static int __init
arch_timer_of_init(struct device_node
*np
)
1150 if (arch_timers_present
& ARCH_TIMER_TYPE_CP15
) {
1151 pr_warn("multiple nodes in dt, skipping\n");
1155 arch_timers_present
|= ARCH_TIMER_TYPE_CP15
;
1156 for (i
= ARCH_TIMER_PHYS_SECURE_PPI
; i
< ARCH_TIMER_MAX_TIMER_PPI
; i
++)
1157 arch_timer_ppi
[i
] = irq_of_parse_and_map(np
, i
);
1159 arch_timer_kvm_info
.virtual_irq
= arch_timer_ppi
[ARCH_TIMER_VIRT_PPI
];
1161 rate
= arch_timer_get_cntfrq();
1162 arch_timer_of_configure_rate(rate
, np
);
1164 arch_timer_c3stop
= !of_property_read_bool(np
, "always-on");
1166 /* Check for globally applicable workarounds */
1167 arch_timer_check_ool_workaround(ate_match_dt
, np
);
1170 * If we cannot rely on firmware initializing the timer registers then
1171 * we should use the physical timers instead.
1173 if (IS_ENABLED(CONFIG_ARM
) &&
1174 of_property_read_bool(np
, "arm,cpu-registers-not-fw-configured"))
1175 arch_timer_uses_ppi
= ARCH_TIMER_PHYS_SECURE_PPI
;
1177 arch_timer_uses_ppi
= arch_timer_select_ppi();
1179 if (!arch_timer_ppi
[arch_timer_uses_ppi
]) {
1180 pr_err("No interrupt available, giving up\n");
1184 /* On some systems, the counter stops ticking when in suspend. */
1185 arch_counter_suspend_stop
= of_property_read_bool(np
,
1186 "arm,no-tick-in-suspend");
1188 ret
= arch_timer_register();
1192 if (arch_timer_needs_of_probing())
1195 return arch_timer_common_init();
1197 TIMER_OF_DECLARE(armv7_arch_timer
, "arm,armv7-timer", arch_timer_of_init
);
1198 TIMER_OF_DECLARE(armv8_arch_timer
, "arm,armv8-timer", arch_timer_of_init
);
1201 arch_timer_mem_frame_get_cntfrq(struct arch_timer_mem_frame
*frame
)
1206 base
= ioremap(frame
->cntbase
, frame
->size
);
1208 pr_err("Unable to map frame @ %pa\n", &frame
->cntbase
);
1212 rate
= readl_relaxed(base
+ CNTFRQ
);
1219 static struct arch_timer_mem_frame
* __init
1220 arch_timer_mem_find_best_frame(struct arch_timer_mem
*timer_mem
)
1222 struct arch_timer_mem_frame
*frame
, *best_frame
= NULL
;
1223 void __iomem
*cntctlbase
;
1227 cntctlbase
= ioremap(timer_mem
->cntctlbase
, timer_mem
->size
);
1229 pr_err("Can't map CNTCTLBase @ %pa\n",
1230 &timer_mem
->cntctlbase
);
1234 cnttidr
= readl_relaxed(cntctlbase
+ CNTTIDR
);
1237 * Try to find a virtual capable frame. Otherwise fall back to a
1238 * physical capable frame.
1240 for (i
= 0; i
< ARCH_TIMER_MEM_MAX_FRAMES
; i
++) {
1241 u32 cntacr
= CNTACR_RFRQ
| CNTACR_RWPT
| CNTACR_RPCT
|
1242 CNTACR_RWVT
| CNTACR_RVOFF
| CNTACR_RVCT
;
1244 frame
= &timer_mem
->frame
[i
];
1248 /* Try enabling everything, and see what sticks */
1249 writel_relaxed(cntacr
, cntctlbase
+ CNTACR(i
));
1250 cntacr
= readl_relaxed(cntctlbase
+ CNTACR(i
));
1252 if ((cnttidr
& CNTTIDR_VIRT(i
)) &&
1253 !(~cntacr
& (CNTACR_RWVT
| CNTACR_RVCT
))) {
1255 arch_timer_mem_use_virtual
= true;
1259 if (~cntacr
& (CNTACR_RWPT
| CNTACR_RPCT
))
1265 iounmap(cntctlbase
);
1268 pr_err("Unable to find a suitable frame in timer @ %pa\n",
1269 &timer_mem
->cntctlbase
);
1275 arch_timer_mem_frame_register(struct arch_timer_mem_frame
*frame
)
1280 if (arch_timer_mem_use_virtual
)
1281 irq
= frame
->virt_irq
;
1283 irq
= frame
->phys_irq
;
1286 pr_err("Frame missing %s irq.\n",
1287 arch_timer_mem_use_virtual
? "virt" : "phys");
1291 if (!request_mem_region(frame
->cntbase
, frame
->size
,
1295 base
= ioremap(frame
->cntbase
, frame
->size
);
1297 pr_err("Can't map frame's registers\n");
1301 ret
= arch_timer_mem_register(base
, irq
);
1307 arch_counter_base
= base
;
1308 arch_timers_present
|= ARCH_TIMER_TYPE_MEM
;
1313 static int __init
arch_timer_mem_of_init(struct device_node
*np
)
1315 struct arch_timer_mem
*timer_mem
;
1316 struct arch_timer_mem_frame
*frame
;
1317 struct device_node
*frame_node
;
1318 struct resource res
;
1322 timer_mem
= kzalloc(sizeof(*timer_mem
), GFP_KERNEL
);
1326 if (of_address_to_resource(np
, 0, &res
))
1328 timer_mem
->cntctlbase
= res
.start
;
1329 timer_mem
->size
= resource_size(&res
);
1331 for_each_available_child_of_node(np
, frame_node
) {
1333 struct arch_timer_mem_frame
*frame
;
1335 if (of_property_read_u32(frame_node
, "frame-number", &n
)) {
1336 pr_err(FW_BUG
"Missing frame-number.\n");
1337 of_node_put(frame_node
);
1340 if (n
>= ARCH_TIMER_MEM_MAX_FRAMES
) {
1341 pr_err(FW_BUG
"Wrong frame-number, only 0-%u are permitted.\n",
1342 ARCH_TIMER_MEM_MAX_FRAMES
- 1);
1343 of_node_put(frame_node
);
1346 frame
= &timer_mem
->frame
[n
];
1349 pr_err(FW_BUG
"Duplicated frame-number.\n");
1350 of_node_put(frame_node
);
1354 if (of_address_to_resource(frame_node
, 0, &res
)) {
1355 of_node_put(frame_node
);
1358 frame
->cntbase
= res
.start
;
1359 frame
->size
= resource_size(&res
);
1361 frame
->virt_irq
= irq_of_parse_and_map(frame_node
,
1362 ARCH_TIMER_VIRT_SPI
);
1363 frame
->phys_irq
= irq_of_parse_and_map(frame_node
,
1364 ARCH_TIMER_PHYS_SPI
);
1366 frame
->valid
= true;
1369 frame
= arch_timer_mem_find_best_frame(timer_mem
);
1375 rate
= arch_timer_mem_frame_get_cntfrq(frame
);
1376 arch_timer_of_configure_rate(rate
, np
);
1378 ret
= arch_timer_mem_frame_register(frame
);
1379 if (!ret
&& !arch_timer_needs_of_probing())
1380 ret
= arch_timer_common_init();
1385 TIMER_OF_DECLARE(armv7_arch_timer_mem
, "arm,armv7-timer-mem",
1386 arch_timer_mem_of_init
);
1388 #ifdef CONFIG_ACPI_GTDT
1390 arch_timer_mem_verify_cntfrq(struct arch_timer_mem
*timer_mem
)
1392 struct arch_timer_mem_frame
*frame
;
1396 for (i
= 0; i
< ARCH_TIMER_MEM_MAX_FRAMES
; i
++) {
1397 frame
= &timer_mem
->frame
[i
];
1402 rate
= arch_timer_mem_frame_get_cntfrq(frame
);
1403 if (rate
== arch_timer_rate
)
1406 pr_err(FW_BUG
"CNTFRQ mismatch: frame @ %pa: (0x%08lx), CPU: (0x%08lx)\n",
1408 (unsigned long)rate
, (unsigned long)arch_timer_rate
);
1416 static int __init
arch_timer_mem_acpi_init(int platform_timer_count
)
1418 struct arch_timer_mem
*timers
, *timer
;
1419 struct arch_timer_mem_frame
*frame
;
1420 int timer_count
, i
, ret
= 0;
1422 timers
= kcalloc(platform_timer_count
, sizeof(*timers
),
1427 ret
= acpi_arch_timer_mem_init(timers
, &timer_count
);
1428 if (ret
|| !timer_count
)
1431 for (i
= 0; i
< timer_count
; i
++) {
1432 ret
= arch_timer_mem_verify_cntfrq(&timers
[i
]);
1434 pr_err("Disabling MMIO timers due to CNTFRQ mismatch\n");
1440 * While unlikely, it's theoretically possible that none of the frames
1441 * in a timer expose the combination of feature we want.
1443 for (i
= i
; i
< timer_count
; i
++) {
1446 frame
= arch_timer_mem_find_best_frame(timer
);
1452 ret
= arch_timer_mem_frame_register(frame
);
1458 /* Initialize per-processor generic timer and memory-mapped timer(if present) */
1459 static int __init
arch_timer_acpi_init(struct acpi_table_header
*table
)
1461 int ret
, platform_timer_count
;
1463 if (arch_timers_present
& ARCH_TIMER_TYPE_CP15
) {
1464 pr_warn("already initialized, skipping\n");
1468 arch_timers_present
|= ARCH_TIMER_TYPE_CP15
;
1470 ret
= acpi_gtdt_init(table
, &platform_timer_count
);
1472 pr_err("Failed to init GTDT table.\n");
1476 arch_timer_ppi
[ARCH_TIMER_PHYS_NONSECURE_PPI
] =
1477 acpi_gtdt_map_ppi(ARCH_TIMER_PHYS_NONSECURE_PPI
);
1479 arch_timer_ppi
[ARCH_TIMER_VIRT_PPI
] =
1480 acpi_gtdt_map_ppi(ARCH_TIMER_VIRT_PPI
);
1482 arch_timer_ppi
[ARCH_TIMER_HYP_PPI
] =
1483 acpi_gtdt_map_ppi(ARCH_TIMER_HYP_PPI
);
1485 arch_timer_kvm_info
.virtual_irq
= arch_timer_ppi
[ARCH_TIMER_VIRT_PPI
];
1488 * When probing via ACPI, we have no mechanism to override the sysreg
1489 * CNTFRQ value. This *must* be correct.
1491 arch_timer_rate
= arch_timer_get_cntfrq();
1492 if (!arch_timer_rate
) {
1493 pr_err(FW_BUG
"frequency not available.\n");
1497 arch_timer_uses_ppi
= arch_timer_select_ppi();
1498 if (!arch_timer_ppi
[arch_timer_uses_ppi
]) {
1499 pr_err("No interrupt available, giving up\n");
1503 /* Always-on capability */
1504 arch_timer_c3stop
= acpi_gtdt_c3stop(arch_timer_uses_ppi
);
1506 /* Check for globally applicable workarounds */
1507 arch_timer_check_ool_workaround(ate_match_acpi_oem_info
, table
);
1509 ret
= arch_timer_register();
1513 if (platform_timer_count
&&
1514 arch_timer_mem_acpi_init(platform_timer_count
))
1515 pr_err("Failed to initialize memory-mapped timer.\n");
1517 return arch_timer_common_init();
1519 TIMER_ACPI_DECLARE(arch_timer
, ACPI_SIG_GTDT
, arch_timer_acpi_init
);