1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clocksource/arm_global_timer.c
5 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
6 * Author: Stuart Menefy <stuart.menefy@st.com>
7 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
12 #include <linux/clocksource.h>
13 #include <linux/clockchips.h>
14 #include <linux/cpu.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/err.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_address.h>
22 #include <linux/sched_clock.h>
24 #include <asm/cputype.h>
26 #define GT_COUNTER0 0x00
27 #define GT_COUNTER1 0x04
29 #define GT_CONTROL 0x08
30 #define GT_CONTROL_TIMER_ENABLE BIT(0) /* this bit is NOT banked */
31 #define GT_CONTROL_COMP_ENABLE BIT(1) /* banked */
32 #define GT_CONTROL_IRQ_ENABLE BIT(2) /* banked */
33 #define GT_CONTROL_AUTO_INC BIT(3) /* banked */
34 #define GT_CONTROL_PRESCALER_SHIFT 8
35 #define GT_CONTROL_PRESCALER_MAX 0xF
36 #define GT_CONTROL_PRESCALER_MASK (GT_CONTROL_PRESCALER_MAX << \
37 GT_CONTROL_PRESCALER_SHIFT)
39 #define GT_INT_STATUS 0x0c
40 #define GT_INT_STATUS_EVENT_FLAG BIT(0)
44 #define GT_AUTO_INC 0x18
48 * We are expecting to be clocked by the ARM peripheral clock.
50 * Note: it is assumed we are using a prescaler value of zero, so this is
51 * the units for all operations.
53 static void __iomem
*gt_base
;
54 static struct notifier_block gt_clk_rate_change_nb
;
55 static u32 gt_psv_new
, gt_psv_bck
, gt_target_rate
;
57 static struct clock_event_device __percpu
*gt_evt
;
60 * To get the value from the Global Timer Counter register proceed as follows:
61 * 1. Read the upper 32-bit timer counter register
62 * 2. Read the lower 32-bit timer counter register
63 * 3. Read the upper 32-bit timer counter register again. If the value is
64 * different to the 32-bit upper value read previously, go back to step 2.
65 * Otherwise the 64-bit timer counter value is correct.
67 static u64 notrace
_gt_counter_read(void)
73 upper
= readl_relaxed(gt_base
+ GT_COUNTER1
);
76 lower
= readl_relaxed(gt_base
+ GT_COUNTER0
);
77 upper
= readl_relaxed(gt_base
+ GT_COUNTER1
);
78 } while (upper
!= old_upper
);
86 static u64
gt_counter_read(void)
88 return _gt_counter_read();
92 * To ensure that updates to comparator value register do not set the
93 * Interrupt Status Register proceed as follows:
94 * 1. Clear the Comp Enable bit in the Timer Control Register.
95 * 2. Write the lower 32-bit Comparator Value Register.
96 * 3. Write the upper 32-bit Comparator Value Register.
97 * 4. Set the Comp Enable bit and, if necessary, the IRQ enable bit.
99 static void gt_compare_set(unsigned long delta
, int periodic
)
101 u64 counter
= gt_counter_read();
105 ctrl
= readl(gt_base
+ GT_CONTROL
);
106 ctrl
&= ~(GT_CONTROL_COMP_ENABLE
| GT_CONTROL_IRQ_ENABLE
|
107 GT_CONTROL_AUTO_INC
);
108 ctrl
|= GT_CONTROL_TIMER_ENABLE
;
109 writel_relaxed(ctrl
, gt_base
+ GT_CONTROL
);
110 writel_relaxed(lower_32_bits(counter
), gt_base
+ GT_COMP0
);
111 writel_relaxed(upper_32_bits(counter
), gt_base
+ GT_COMP1
);
114 writel_relaxed(delta
, gt_base
+ GT_AUTO_INC
);
115 ctrl
|= GT_CONTROL_AUTO_INC
;
118 ctrl
|= GT_CONTROL_COMP_ENABLE
| GT_CONTROL_IRQ_ENABLE
;
119 writel_relaxed(ctrl
, gt_base
+ GT_CONTROL
);
122 static int gt_clockevent_shutdown(struct clock_event_device
*evt
)
126 ctrl
= readl(gt_base
+ GT_CONTROL
);
127 ctrl
&= ~(GT_CONTROL_COMP_ENABLE
| GT_CONTROL_IRQ_ENABLE
|
128 GT_CONTROL_AUTO_INC
);
129 writel(ctrl
, gt_base
+ GT_CONTROL
);
133 static int gt_clockevent_set_periodic(struct clock_event_device
*evt
)
135 gt_compare_set(DIV_ROUND_CLOSEST(gt_target_rate
, HZ
), 1);
139 static int gt_clockevent_set_next_event(unsigned long evt
,
140 struct clock_event_device
*unused
)
142 gt_compare_set(evt
, 0);
146 static irqreturn_t
gt_clockevent_interrupt(int irq
, void *dev_id
)
148 struct clock_event_device
*evt
= dev_id
;
150 if (!(readl_relaxed(gt_base
+ GT_INT_STATUS
) &
151 GT_INT_STATUS_EVENT_FLAG
))
155 * ERRATA 740657( Global Timer can send 2 interrupts for
156 * the same event in single-shot mode)
158 * Either disable single-shot mode.
160 * Modify the Interrupt Handler to avoid the
161 * offending sequence. This is achieved by clearing
162 * the Global Timer flag _after_ having incremented
163 * the Comparator register value to a higher value.
165 if (clockevent_state_oneshot(evt
))
166 gt_compare_set(ULONG_MAX
, 0);
168 writel_relaxed(GT_INT_STATUS_EVENT_FLAG
, gt_base
+ GT_INT_STATUS
);
169 evt
->event_handler(evt
);
174 static int gt_starting_cpu(unsigned int cpu
)
176 struct clock_event_device
*clk
= this_cpu_ptr(gt_evt
);
178 clk
->name
= "arm_global_timer";
179 clk
->features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
|
180 CLOCK_EVT_FEAT_PERCPU
;
181 clk
->set_state_shutdown
= gt_clockevent_shutdown
;
182 clk
->set_state_periodic
= gt_clockevent_set_periodic
;
183 clk
->set_state_oneshot
= gt_clockevent_shutdown
;
184 clk
->set_state_oneshot_stopped
= gt_clockevent_shutdown
;
185 clk
->set_next_event
= gt_clockevent_set_next_event
;
186 clk
->cpumask
= cpumask_of(cpu
);
189 clockevents_config_and_register(clk
, gt_target_rate
,
191 enable_percpu_irq(clk
->irq
, IRQ_TYPE_NONE
);
195 static int gt_dying_cpu(unsigned int cpu
)
197 struct clock_event_device
*clk
= this_cpu_ptr(gt_evt
);
199 gt_clockevent_shutdown(clk
);
200 disable_percpu_irq(clk
->irq
);
204 static u64
gt_clocksource_read(struct clocksource
*cs
)
206 return gt_counter_read();
209 static void gt_resume(struct clocksource
*cs
)
213 ctrl
= readl(gt_base
+ GT_CONTROL
);
214 if (!(ctrl
& GT_CONTROL_TIMER_ENABLE
))
215 /* re-enable timer on resume */
216 writel(GT_CONTROL_TIMER_ENABLE
, gt_base
+ GT_CONTROL
);
219 static struct clocksource gt_clocksource
= {
220 .name
= "arm_global_timer",
222 .read
= gt_clocksource_read
,
223 .mask
= CLOCKSOURCE_MASK(64),
224 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
228 #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
229 static u64 notrace
gt_sched_clock_read(void)
231 return _gt_counter_read();
235 static unsigned long gt_read_long(void)
237 return readl_relaxed(gt_base
+ GT_COUNTER0
);
240 static struct delay_timer gt_delay_timer
= {
241 .read_current_timer
= gt_read_long
,
244 static void gt_write_presc(u32 psv
)
248 reg
= readl(gt_base
+ GT_CONTROL
);
249 reg
&= ~GT_CONTROL_PRESCALER_MASK
;
250 reg
|= psv
<< GT_CONTROL_PRESCALER_SHIFT
;
251 writel(reg
, gt_base
+ GT_CONTROL
);
254 static u32
gt_read_presc(void)
258 reg
= readl(gt_base
+ GT_CONTROL
);
259 reg
&= GT_CONTROL_PRESCALER_MASK
;
260 return reg
>> GT_CONTROL_PRESCALER_SHIFT
;
263 static void __init
gt_delay_timer_init(void)
265 gt_delay_timer
.freq
= gt_target_rate
;
266 register_current_timer_delay(>_delay_timer
);
269 static int __init
gt_clocksource_init(void)
271 writel(0, gt_base
+ GT_CONTROL
);
272 writel(0, gt_base
+ GT_COUNTER0
);
273 writel(0, gt_base
+ GT_COUNTER1
);
274 /* set prescaler and enable timer on all the cores */
275 writel(((CONFIG_ARM_GT_INITIAL_PRESCALER_VAL
- 1) <<
276 GT_CONTROL_PRESCALER_SHIFT
)
277 | GT_CONTROL_TIMER_ENABLE
, gt_base
+ GT_CONTROL
);
279 #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
280 sched_clock_register(gt_sched_clock_read
, 64, gt_target_rate
);
282 return clocksource_register_hz(>_clocksource
, gt_target_rate
);
285 static int gt_clk_rate_change_cb(struct notifier_block
*nb
,
286 unsigned long event
, void *data
)
288 struct clk_notifier_data
*ndata
= data
;
291 case PRE_RATE_CHANGE
:
295 psv
= DIV_ROUND_CLOSEST(ndata
->new_rate
,
298 if (abs(gt_target_rate
- (ndata
->new_rate
/ psv
)) > MAX_F_ERR
)
303 /* prescaler within legal range? */
304 if (psv
< 0 || psv
> GT_CONTROL_PRESCALER_MAX
)
308 * store timer clock ctrl register so we can restore it in case
311 gt_psv_bck
= gt_read_presc();
313 /* scale down: adjust divider in post-change notification */
314 if (ndata
->new_rate
< ndata
->old_rate
)
317 /* scale up: adjust divider now - before frequency change */
321 case POST_RATE_CHANGE
:
322 /* scale up: pre-change notification did the adjustment */
323 if (ndata
->new_rate
> ndata
->old_rate
)
326 /* scale down: adjust divider now - after frequency change */
327 gt_write_presc(gt_psv_new
);
330 case ABORT_RATE_CHANGE
:
331 /* we have to undo the adjustment in case we scale up */
332 if (ndata
->new_rate
< ndata
->old_rate
)
335 /* restore original register value */
336 gt_write_presc(gt_psv_bck
);
345 static int __init
global_timer_of_register(struct device_node
*np
)
348 static unsigned long gt_clk_rate
;
352 * In A9 r2p0 the comparators for each processor with the global timer
353 * fire when the timer value is greater than or equal to. In previous
354 * revisions the comparators fired when the timer value was equal to.
356 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9
357 && (read_cpuid_id() & 0xf0000f) < 0x200000) {
358 pr_warn("global-timer: non support for this cpu version.\n");
362 gt_ppi
= irq_of_parse_and_map(np
, 0);
364 pr_warn("global-timer: unable to parse irq\n");
368 gt_base
= of_iomap(np
, 0);
370 pr_warn("global-timer: invalid base address\n");
374 gt_clk
= of_clk_get(np
, 0);
375 if (!IS_ERR(gt_clk
)) {
376 err
= clk_prepare_enable(gt_clk
);
380 pr_warn("global-timer: clk not found\n");
385 gt_clk_rate
= clk_get_rate(gt_clk
);
386 gt_target_rate
= gt_clk_rate
/ CONFIG_ARM_GT_INITIAL_PRESCALER_VAL
;
387 gt_clk_rate_change_nb
.notifier_call
=
388 gt_clk_rate_change_cb
;
389 err
= clk_notifier_register(gt_clk
, >_clk_rate_change_nb
);
391 pr_warn("Unable to register clock notifier\n");
395 gt_evt
= alloc_percpu(struct clock_event_device
);
397 pr_warn("global-timer: can't allocate memory\n");
402 err
= request_percpu_irq(gt_ppi
, gt_clockevent_interrupt
,
405 pr_warn("global-timer: can't register interrupt %d (%d)\n",
410 /* Register and immediately configure the timer on the boot CPU */
411 err
= gt_clocksource_init();
415 err
= cpuhp_setup_state(CPUHP_AP_ARM_GLOBAL_TIMER_STARTING
,
416 "clockevents/arm/global_timer:starting",
417 gt_starting_cpu
, gt_dying_cpu
);
421 gt_delay_timer_init();
426 free_percpu_irq(gt_ppi
, gt_evt
);
430 clk_notifier_unregister(gt_clk
, >_clk_rate_change_nb
);
432 clk_disable_unprepare(gt_clk
);
435 WARN(err
, "ARM Global timer register failed (%d)\n", err
);
440 /* Only tested on r2p2 and r3p0 */
441 TIMER_OF_DECLARE(arm_gt
, "arm,cortex-a9-global-timer",
442 global_timer_of_register
);