drivers/clocksource/cadence_ttc_timer.c

   1 /*
   2  * This file contains driver for the Cadence Triple Timer Counter Rev 06
   3  *
   4  *  Copyright (C) 2011-2013 Xilinx
   5  *
   6  * based on arch/mips/kernel/time.c timer driver
   7  *
   8  * This software is licensed under the terms of the GNU General Public
   9  * License version 2, as published by the Free Software Foundation, and
  10  * may be copied, distributed, and modified under those terms.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/clk.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/clockchips.h>
  21 #include <linux/of_address.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/slab.h>
  24 #include <linux/sched_clock.h>
  25
  26 /*
  27  * This driver configures the 2 16-bit count-up timers as follows:
  28  *
  29  * T1: Timer 1, clocksource for generic timekeeping
  30  * T2: Timer 2, clockevent source for hrtimers
  31  * T3: Timer 3, <unused>
  32  *
  33  * The input frequency to the timer module for emulation is 2.5MHz which is
  34  * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
  35  * the timers are clocked at 78.125KHz (12.8 us resolution).
  36
  37  * The input frequency to the timer module in silicon is configurable and
  38  * obtained from device tree. The pre-scaler of 32 is used.
  39  */
  40
  41 /*
  42  * Timer Register Offset Definitions of Timer 1, Increment base address by 4
  43  * and use same offsets for Timer 2
  44  */
  45 #define TTC_CLK_CNTRL_OFFSET            0x00 /* Clock Control Reg, RW */
  46 #define TTC_CNT_CNTRL_OFFSET            0x0C /* Counter Control Reg, RW */
  47 #define TTC_COUNT_VAL_OFFSET            0x18 /* Counter Value Reg, RO */
  48 #define TTC_INTR_VAL_OFFSET             0x24 /* Interval Count Reg, RW */
  49 #define TTC_ISR_OFFSET          0x54 /* Interrupt Status Reg, RO */
  50 #define TTC_IER_OFFSET          0x60 /* Interrupt Enable Reg, RW */
  51
  52 #define TTC_CNT_CNTRL_DISABLE_MASK      0x1
  53
  54 #define TTC_CLK_CNTRL_CSRC_MASK         (1 << 5)        /* clock source */
  55
  56 /*
  57  * Setup the timers to use pre-scaling, using a fixed value for now that will
  58  * work across most input frequency, but it may need to be more dynamic
  59  */
  60 #define PRESCALE_EXPONENT       11      /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
  61 #define PRESCALE                2048    /* The exponent must match this */
  62 #define CLK_CNTRL_PRESCALE      ((PRESCALE_EXPONENT - 1) << 1)
  63 #define CLK_CNTRL_PRESCALE_EN   1
  64 #define CNT_CNTRL_RESET         (1 << 4)
  65
  66 /**
  67  * struct ttc_timer - This definition defines local timer structure
  68  *
  69  * @base_addr:  Base address of timer
  70  * @freq:       Timer input clock frequency
  71  * @clk:        Associated clock source
  72  * @clk_rate_change_nb  Notifier block for clock rate changes
  73  */
  74 struct ttc_timer {
  75         void __iomem *base_addr;
  76         unsigned long freq;
  77         struct clk *clk;
  78         struct notifier_block clk_rate_change_nb;
  79 };
  80
  81 #define to_ttc_timer(x) \
  82                 container_of(x, struct ttc_timer, clk_rate_change_nb)
  83
  84 struct ttc_timer_clocksource {
  85         struct ttc_timer        ttc;
  86         struct clocksource      cs;
  87 };
  88
  89 #define to_ttc_timer_clksrc(x) \
  90                 container_of(x, struct ttc_timer_clocksource, cs)
  91
  92 struct ttc_timer_clockevent {
  93         struct ttc_timer                ttc;
  94         struct clock_event_device       ce;
  95 };
  96
  97 #define to_ttc_timer_clkevent(x) \
  98                 container_of(x, struct ttc_timer_clockevent, ce)
  99
 100 static void __iomem *ttc_sched_clock_val_reg;
 101
 102 /**
 103  * ttc_set_interval - Set the timer interval value
 104  *
 105  * @timer:      Pointer to the timer instance
 106  * @cycles:     Timer interval ticks
 107  **/
 108 static void ttc_set_interval(struct ttc_timer *timer,
 109                                         unsigned long cycles)
 110 {
 111         u32 ctrl_reg;
 112
 113         /* Disable the counter, set the counter value  and re-enable counter */
 114         ctrl_reg = __raw_readl(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
 115         ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
 116         __raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
 117
 118         __raw_writel(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
 119
 120         /*
 121          * Reset the counter (0x10) so that it starts from 0, one-shot
 122          * mode makes this needed for timing to be right.
 123          */
 124         ctrl_reg |= CNT_CNTRL_RESET;
 125         ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
 126         __raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
 127 }
 128
 129 /**
 130  * ttc_clock_event_interrupt - Clock event timer interrupt handler
 131  *
 132  * @irq:        IRQ number of the Timer
 133  * @dev_id:     void pointer to the ttc_timer instance
 134  *
 135  * returns: Always IRQ_HANDLED - success
 136  **/
 137 static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
 138 {
 139         struct ttc_timer_clockevent *ttce = dev_id;
 140         struct ttc_timer *timer = &ttce->ttc;
 141
 142         /* Acknowledge the interrupt and call event handler */
 143         __raw_readl(timer->base_addr + TTC_ISR_OFFSET);
 144
 145         ttce->ce.event_handler(&ttce->ce);
 146
 147         return IRQ_HANDLED;
 148 }
 149
 150 /**
 151  * __ttc_clocksource_read - Reads the timer counter register
 152  *
 153  * returns: Current timer counter register value
 154  **/
 155 static cycle_t __ttc_clocksource_read(struct clocksource *cs)
 156 {
 157         struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
 158
 159         return (cycle_t)__raw_readl(timer->base_addr +
 160                                 TTC_COUNT_VAL_OFFSET);
 161 }
 162
 163 static u64 notrace ttc_sched_clock_read(void)
 164 {
 165         return __raw_readl(ttc_sched_clock_val_reg);
 166 }
 167
 168 /**
 169  * ttc_set_next_event - Sets the time interval for next event
 170  *
 171  * @cycles:     Timer interval ticks
 172  * @evt:        Address of clock event instance
 173  *
 174  * returns: Always 0 - success
 175  **/
 176 static int ttc_set_next_event(unsigned long cycles,
 177                                         struct clock_event_device *evt)
 178 {
 179         struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
 180         struct ttc_timer *timer = &ttce->ttc;
 181
 182         ttc_set_interval(timer, cycles);
 183         return 0;
 184 }
 185
 186 /**
 187  * ttc_set_mode - Sets the mode of timer
 188  *
 189  * @mode:       Mode to be set
 190  * @evt:        Address of clock event instance
 191  **/
 192 static void ttc_set_mode(enum clock_event_mode mode,
 193                                         struct clock_event_device *evt)
 194 {
 195         struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
 196         struct ttc_timer *timer = &ttce->ttc;
 197         u32 ctrl_reg;
 198
 199         switch (mode) {
 200         case CLOCK_EVT_MODE_PERIODIC:
 201                 ttc_set_interval(timer, DIV_ROUND_CLOSEST(ttce->ttc.freq,
 202                                                 PRESCALE * HZ));
 203                 break;
 204         case CLOCK_EVT_MODE_ONESHOT:
 205         case CLOCK_EVT_MODE_UNUSED:
 206         case CLOCK_EVT_MODE_SHUTDOWN:
 207                 ctrl_reg = __raw_readl(timer->base_addr +
 208                                         TTC_CNT_CNTRL_OFFSET);
 209                 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
 210                 __raw_writel(ctrl_reg,
 211                                 timer->base_addr + TTC_CNT_CNTRL_OFFSET);
 212                 break;
 213         case CLOCK_EVT_MODE_RESUME:
 214                 ctrl_reg = __raw_readl(timer->base_addr +
 215                                         TTC_CNT_CNTRL_OFFSET);
 216                 ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
 217                 __raw_writel(ctrl_reg,
 218                                 timer->base_addr + TTC_CNT_CNTRL_OFFSET);
 219                 break;
 220         }
 221 }
 222
 223 static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
 224                 unsigned long event, void *data)
 225 {
 226         struct clk_notifier_data *ndata = data;
 227         struct ttc_timer *ttc = to_ttc_timer(nb);
 228         struct ttc_timer_clocksource *ttccs = container_of(ttc,
 229                         struct ttc_timer_clocksource, ttc);
 230
 231         switch (event) {
 232         case POST_RATE_CHANGE:
 233                 /*
 234                  * Do whatever is necessary to maintain a proper time base
 235                  *
 236                  * I cannot find a way to adjust the currently used clocksource
 237                  * to the new frequency. __clocksource_updatefreq_hz() sounds
 238                  * good, but does not work. Not sure what's that missing.
 239                  *
 240                  * This approach works, but triggers two clocksource switches.
 241                  * The first after unregister to clocksource jiffies. And
 242                  * another one after the register to the newly registered timer.
 243                  *
 244                  * Alternatively we could 'waste' another HW timer to ping pong
 245                  * between clock sources. That would also use one register and
 246                  * one unregister call, but only trigger one clocksource switch
 247                  * for the cost of another HW timer used by the OS.
 248                  */
 249                 clocksource_unregister(&ttccs->cs);
 250                 clocksource_register_hz(&ttccs->cs,
 251                                 ndata->new_rate / PRESCALE);
 252                 /* fall through */
 253         case PRE_RATE_CHANGE:
 254         case ABORT_RATE_CHANGE:
 255         default:
 256                 return NOTIFY_DONE;
 257         }
 258 }
 259
 260 static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base)
 261 {
 262         struct ttc_timer_clocksource *ttccs;
 263         int err;
 264
 265         ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
 266         if (WARN_ON(!ttccs))
 267                 return;
 268
 269         ttccs->ttc.clk = clk;
 270
 271         err = clk_prepare_enable(ttccs->ttc.clk);
 272         if (WARN_ON(err)) {
 273                 kfree(ttccs);
 274                 return;
 275         }
 276
 277         ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk);
 278
 279         ttccs->ttc.clk_rate_change_nb.notifier_call =
 280                 ttc_rate_change_clocksource_cb;
 281         ttccs->ttc.clk_rate_change_nb.next = NULL;
 282         if (clk_notifier_register(ttccs->ttc.clk,
 283                                 &ttccs->ttc.clk_rate_change_nb))
 284                 pr_warn("Unable to register clock notifier.\n");
 285
 286         ttccs->ttc.base_addr = base;
 287         ttccs->cs.name = "ttc_clocksource";
 288         ttccs->cs.rating = 200;
 289         ttccs->cs.read = __ttc_clocksource_read;
 290         ttccs->cs.mask = CLOCKSOURCE_MASK(16);
 291         ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
 292
 293         /*
 294          * Setup the clock source counter to be an incrementing counter
 295          * with no interrupt and it rolls over at 0xFFFF. Pre-scale
 296          * it by 32 also. Let it start running now.
 297          */
 298         __raw_writel(0x0,  ttccs->ttc.base_addr + TTC_IER_OFFSET);
 299         __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
 300                      ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
 301         __raw_writel(CNT_CNTRL_RESET,
 302                      ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
 303
 304         err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
 305         if (WARN_ON(err)) {
 306                 kfree(ttccs);
 307                 return;
 308         }
 309
 310         ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
 311         sched_clock_register(ttc_sched_clock_read, 16, ttccs->ttc.freq / PRESCALE);
 312 }
 313
 314 static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
 315                 unsigned long event, void *data)
 316 {
 317         struct clk_notifier_data *ndata = data;
 318         struct ttc_timer *ttc = to_ttc_timer(nb);
 319         struct ttc_timer_clockevent *ttcce = container_of(ttc,
 320                         struct ttc_timer_clockevent, ttc);
 321
 322         switch (event) {
 323         case POST_RATE_CHANGE:
 324         {
 325                 unsigned long flags;
 326
 327                 /*
 328                  * clockevents_update_freq should be called with IRQ disabled on
 329                  * the CPU the timer provides events for. The timer we use is
 330                  * common to both CPUs, not sure if we need to run on both
 331                  * cores.
 332                  */
 333                 local_irq_save(flags);
 334                 clockevents_update_freq(&ttcce->ce,
 335                                 ndata->new_rate / PRESCALE);
 336                 local_irq_restore(flags);
 337
 338                 /* update cached frequency */
 339                 ttc->freq = ndata->new_rate;
 340
 341                 /* fall through */
 342         }
 343         case PRE_RATE_CHANGE:
 344         case ABORT_RATE_CHANGE:
 345         default:
 346                 return NOTIFY_DONE;
 347         }
 348 }
 349
 350 static void __init ttc_setup_clockevent(struct clk *clk,
 351                                                 void __iomem *base, u32 irq)
 352 {
 353         struct ttc_timer_clockevent *ttcce;
 354         int err;
 355
 356         ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
 357         if (WARN_ON(!ttcce))
 358                 return;
 359
 360         ttcce->ttc.clk = clk;
 361
 362         err = clk_prepare_enable(ttcce->ttc.clk);
 363         if (WARN_ON(err)) {
 364                 kfree(ttcce);
 365                 return;
 366         }
 367
 368         ttcce->ttc.clk_rate_change_nb.notifier_call =
 369                 ttc_rate_change_clockevent_cb;
 370         ttcce->ttc.clk_rate_change_nb.next = NULL;
 371         if (clk_notifier_register(ttcce->ttc.clk,
 372                                 &ttcce->ttc.clk_rate_change_nb))
 373                 pr_warn("Unable to register clock notifier.\n");
 374         ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);
 375
 376         ttcce->ttc.base_addr = base;
 377         ttcce->ce.name = "ttc_clockevent";
 378         ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
 379         ttcce->ce.set_next_event = ttc_set_next_event;
 380         ttcce->ce.set_mode = ttc_set_mode;
 381         ttcce->ce.rating = 200;
 382         ttcce->ce.irq = irq;
 383         ttcce->ce.cpumask = cpu_possible_mask;
 384
 385         /*
 386          * Setup the clock event timer to be an interval timer which
 387          * is prescaled by 32 using the interval interrupt. Leave it
 388          * disabled for now.
 389          */
 390         __raw_writel(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
 391         __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
 392                      ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
 393         __raw_writel(0x1,  ttcce->ttc.base_addr + TTC_IER_OFFSET);
 394
 395         err = request_irq(irq, ttc_clock_event_interrupt,
 396                           IRQF_TIMER, ttcce->ce.name, ttcce);
 397         if (WARN_ON(err)) {
 398                 kfree(ttcce);
 399                 return;
 400         }
 401
 402         clockevents_config_and_register(&ttcce->ce,
 403                         ttcce->ttc.freq / PRESCALE, 1, 0xfffe);
 404 }
 405
 406 /**
 407  * ttc_timer_init - Initialize the timer
 408  *
 409  * Initializes the timer hardware and register the clock source and clock event
 410  * timers with Linux kernal timer framework
 411  */
 412 static void __init ttc_timer_init(struct device_node *timer)
 413 {
 414         unsigned int irq;
 415         void __iomem *timer_baseaddr;
 416         struct clk *clk_cs, *clk_ce;
 417         static int initialized;
 418         int clksel;
 419
 420         if (initialized)
 421                 return;
 422
 423         initialized = 1;
 424
 425         /*
 426          * Get the 1st Triple Timer Counter (TTC) block from the device tree
 427          * and use it. Note that the event timer uses the interrupt and it's the
 428          * 2nd TTC hence the irq_of_parse_and_map(,1)
 429          */
 430         timer_baseaddr = of_iomap(timer, 0);
 431         if (!timer_baseaddr) {
 432                 pr_err("ERROR: invalid timer base address\n");
 433                 BUG();
 434         }
 435
 436         irq = irq_of_parse_and_map(timer, 1);
 437         if (irq <= 0) {
 438                 pr_err("ERROR: invalid interrupt number\n");
 439                 BUG();
 440         }
 441
 442         clksel = __raw_readl(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
 443         clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
 444         clk_cs = of_clk_get(timer, clksel);
 445         if (IS_ERR(clk_cs)) {
 446                 pr_err("ERROR: timer input clock not found\n");
 447                 BUG();
 448         }
 449
 450         clksel = __raw_readl(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
 451         clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
 452         clk_ce = of_clk_get(timer, clksel);
 453         if (IS_ERR(clk_ce)) {
 454                 pr_err("ERROR: timer input clock not found\n");
 455                 BUG();
 456         }
 457
 458         ttc_setup_clocksource(clk_cs, timer_baseaddr);
 459         ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
 460
 461         pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq);
 462 }
 463
 464 CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init);