]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/clocksource/nomadik-mtu.c
Merge tag 'ceph-for-4.8-rc1' of git://github.com/ceph/ceph-client
[mirror_ubuntu-artful-kernel.git] / drivers / clocksource / nomadik-mtu.c
1 /*
2 * Copyright (C) 2008 STMicroelectronics
3 * Copyright (C) 2010 Alessandro Rubini
4 * Copyright (C) 2010 Linus Walleij for ST-Ericsson
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 */
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/io.h>
14 #include <linux/clockchips.h>
15 #include <linux/clocksource.h>
16 #include <linux/of_address.h>
17 #include <linux/of_irq.h>
18 #include <linux/of_platform.h>
19 #include <linux/clk.h>
20 #include <linux/jiffies.h>
21 #include <linux/delay.h>
22 #include <linux/err.h>
23 #include <linux/sched_clock.h>
24 #include <asm/mach/time.h>
25
26 /*
27 * The MTU device hosts four different counters, with 4 set of
28 * registers. These are register names.
29 */
30
31 #define MTU_IMSC 0x00 /* Interrupt mask set/clear */
32 #define MTU_RIS 0x04 /* Raw interrupt status */
33 #define MTU_MIS 0x08 /* Masked interrupt status */
34 #define MTU_ICR 0x0C /* Interrupt clear register */
35
36 /* per-timer registers take 0..3 as argument */
37 #define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
38 #define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
39 #define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
40 #define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
41
42 /* bits for the control register */
43 #define MTU_CRn_ENA 0x80
44 #define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
45 #define MTU_CRn_PRESCALE_MASK 0x0c
46 #define MTU_CRn_PRESCALE_1 0x00
47 #define MTU_CRn_PRESCALE_16 0x04
48 #define MTU_CRn_PRESCALE_256 0x08
49 #define MTU_CRn_32BITS 0x02
50 #define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
51
52 /* Other registers are usual amba/primecell registers, currently not used */
53 #define MTU_ITCR 0xff0
54 #define MTU_ITOP 0xff4
55
56 #define MTU_PERIPH_ID0 0xfe0
57 #define MTU_PERIPH_ID1 0xfe4
58 #define MTU_PERIPH_ID2 0xfe8
59 #define MTU_PERIPH_ID3 0xfeC
60
61 #define MTU_PCELL0 0xff0
62 #define MTU_PCELL1 0xff4
63 #define MTU_PCELL2 0xff8
64 #define MTU_PCELL3 0xffC
65
66 static void __iomem *mtu_base;
67 static bool clkevt_periodic;
68 static u32 clk_prescale;
69 static u32 nmdk_cycle; /* write-once */
70 static struct delay_timer mtu_delay_timer;
71
72 #ifdef CONFIG_CLKSRC_NOMADIK_MTU_SCHED_CLOCK
73 /*
74 * Override the global weak sched_clock symbol with this
75 * local implementation which uses the clocksource to get some
76 * better resolution when scheduling the kernel.
77 */
78 static u64 notrace nomadik_read_sched_clock(void)
79 {
80 if (unlikely(!mtu_base))
81 return 0;
82
83 return -readl(mtu_base + MTU_VAL(0));
84 }
85 #endif
86
87 static unsigned long nmdk_timer_read_current_timer(void)
88 {
89 return ~readl_relaxed(mtu_base + MTU_VAL(0));
90 }
91
92 /* Clockevent device: use one-shot mode */
93 static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
94 {
95 writel(1 << 1, mtu_base + MTU_IMSC);
96 writel(evt, mtu_base + MTU_LR(1));
97 /* Load highest value, enable device, enable interrupts */
98 writel(MTU_CRn_ONESHOT | clk_prescale |
99 MTU_CRn_32BITS | MTU_CRn_ENA,
100 mtu_base + MTU_CR(1));
101
102 return 0;
103 }
104
105 static void nmdk_clkevt_reset(void)
106 {
107 if (clkevt_periodic) {
108 /* Timer: configure load and background-load, and fire it up */
109 writel(nmdk_cycle, mtu_base + MTU_LR(1));
110 writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
111
112 writel(MTU_CRn_PERIODIC | clk_prescale |
113 MTU_CRn_32BITS | MTU_CRn_ENA,
114 mtu_base + MTU_CR(1));
115 writel(1 << 1, mtu_base + MTU_IMSC);
116 } else {
117 /* Generate an interrupt to start the clockevent again */
118 (void) nmdk_clkevt_next(nmdk_cycle, NULL);
119 }
120 }
121
122 static int nmdk_clkevt_shutdown(struct clock_event_device *evt)
123 {
124 writel(0, mtu_base + MTU_IMSC);
125 /* disable timer */
126 writel(0, mtu_base + MTU_CR(1));
127 /* load some high default value */
128 writel(0xffffffff, mtu_base + MTU_LR(1));
129 return 0;
130 }
131
132 static int nmdk_clkevt_set_oneshot(struct clock_event_device *evt)
133 {
134 clkevt_periodic = false;
135 return 0;
136 }
137
138 static int nmdk_clkevt_set_periodic(struct clock_event_device *evt)
139 {
140 clkevt_periodic = true;
141 nmdk_clkevt_reset();
142 return 0;
143 }
144
145 static void nmdk_clksrc_reset(void)
146 {
147 /* Disable */
148 writel(0, mtu_base + MTU_CR(0));
149
150 /* ClockSource: configure load and background-load, and fire it up */
151 writel(nmdk_cycle, mtu_base + MTU_LR(0));
152 writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
153
154 writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA,
155 mtu_base + MTU_CR(0));
156 }
157
158 static void nmdk_clkevt_resume(struct clock_event_device *cedev)
159 {
160 nmdk_clkevt_reset();
161 nmdk_clksrc_reset();
162 }
163
164 static struct clock_event_device nmdk_clkevt = {
165 .name = "mtu_1",
166 .features = CLOCK_EVT_FEAT_ONESHOT |
167 CLOCK_EVT_FEAT_PERIODIC |
168 CLOCK_EVT_FEAT_DYNIRQ,
169 .rating = 200,
170 .set_state_shutdown = nmdk_clkevt_shutdown,
171 .set_state_periodic = nmdk_clkevt_set_periodic,
172 .set_state_oneshot = nmdk_clkevt_set_oneshot,
173 .set_next_event = nmdk_clkevt_next,
174 .resume = nmdk_clkevt_resume,
175 };
176
177 /*
178 * IRQ Handler for timer 1 of the MTU block.
179 */
180 static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
181 {
182 struct clock_event_device *evdev = dev_id;
183
184 writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
185 evdev->event_handler(evdev);
186 return IRQ_HANDLED;
187 }
188
189 static struct irqaction nmdk_timer_irq = {
190 .name = "Nomadik Timer Tick",
191 .flags = IRQF_TIMER,
192 .handler = nmdk_timer_interrupt,
193 .dev_id = &nmdk_clkevt,
194 };
195
196 static int __init nmdk_timer_init(void __iomem *base, int irq,
197 struct clk *pclk, struct clk *clk)
198 {
199 unsigned long rate;
200 int ret;
201
202 mtu_base = base;
203
204 BUG_ON(clk_prepare_enable(pclk));
205 BUG_ON(clk_prepare_enable(clk));
206
207 /*
208 * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
209 * for ux500.
210 * Use a divide-by-16 counter if the tick rate is more than 32MHz.
211 * At 32 MHz, the timer (with 32 bit counter) can be programmed
212 * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
213 * with 16 gives too low timer resolution.
214 */
215 rate = clk_get_rate(clk);
216 if (rate > 32000000) {
217 rate /= 16;
218 clk_prescale = MTU_CRn_PRESCALE_16;
219 } else {
220 clk_prescale = MTU_CRn_PRESCALE_1;
221 }
222
223 /* Cycles for periodic mode */
224 nmdk_cycle = DIV_ROUND_CLOSEST(rate, HZ);
225
226
227 /* Timer 0 is the free running clocksource */
228 nmdk_clksrc_reset();
229
230 ret = clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
231 rate, 200, 32, clocksource_mmio_readl_down);
232 if (ret) {
233 pr_err("timer: failed to initialize clock source %s\n", "mtu_0");
234 return ret;
235 }
236
237 #ifdef CONFIG_CLKSRC_NOMADIK_MTU_SCHED_CLOCK
238 sched_clock_register(nomadik_read_sched_clock, 32, rate);
239 #endif
240
241 /* Timer 1 is used for events, register irq and clockevents */
242 setup_irq(irq, &nmdk_timer_irq);
243 nmdk_clkevt.cpumask = cpumask_of(0);
244 nmdk_clkevt.irq = irq;
245 clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU);
246
247 mtu_delay_timer.read_current_timer = &nmdk_timer_read_current_timer;
248 mtu_delay_timer.freq = rate;
249 register_current_timer_delay(&mtu_delay_timer);
250
251 return 0;
252 }
253
254 static int __init nmdk_timer_of_init(struct device_node *node)
255 {
256 struct clk *pclk;
257 struct clk *clk;
258 void __iomem *base;
259 int irq;
260
261 base = of_iomap(node, 0);
262 if (!base) {
263 pr_err("Can't remap registers");
264 return -ENXIO;
265 }
266
267 pclk = of_clk_get_by_name(node, "apb_pclk");
268 if (IS_ERR(pclk)) {
269 pr_err("could not get apb_pclk");
270 return PTR_ERR(pclk);
271 }
272
273 clk = of_clk_get_by_name(node, "timclk");
274 if (IS_ERR(clk)) {
275 pr_err("could not get timclk");
276 return PTR_ERR(clk);
277 }
278
279 irq = irq_of_parse_and_map(node, 0);
280 if (irq <= 0) {
281 pr_err("Can't parse IRQ");
282 return -EINVAL;
283 }
284
285 return nmdk_timer_init(base, irq, pclk, clk);
286 }
287 CLOCKSOURCE_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu",
288 nmdk_timer_of_init);