2 * SuperH Timer Support - CMT
4 * Copyright (C) 2008 Magnus Damm
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/clk.h>
17 #include <linux/clockchips.h>
18 #include <linux/clocksource.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
25 #include <linux/irq.h>
26 #include <linux/module.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_domain.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/sh_timer.h>
32 #include <linux/slab.h>
33 #include <linux/spinlock.h>
38 * The CMT comes in 5 different identified flavours, depending not only on the
39 * SoC but also on the particular instance. The following table lists the main
40 * characteristics of those flavours.
42 * 16B 32B 32B-F 48B R-Car Gen2
43 * -----------------------------------------------------------------------------
44 * Channels 2 1/4 1 6 2/8
45 * Control Width 16 16 16 16 32
46 * Counter Width 16 32 32 32/48 32/48
47 * Shared Start/Stop Y Y Y Y N
49 * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register
50 * located in the channel registers block. All other versions have a shared
51 * start/stop register located in the global space.
53 * Channels are indexed from 0 to N-1 in the documentation. The channel index
54 * infers the start/stop bit position in the control register and the channel
55 * registers block address. Some CMT instances have a subset of channels
56 * available, in which case the index in the documentation doesn't match the
57 * "real" index as implemented in hardware. This is for instance the case with
58 * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
59 * in the documentation but using start/stop bit 5 and having its registers
62 * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
63 * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
75 enum sh_cmt_model model
;
77 unsigned int channels_mask
;
79 unsigned long width
; /* 16 or 32 bit version of hardware block */
80 unsigned long overflow_bit
;
81 unsigned long clear_bits
;
83 /* callbacks for CMSTR and CMCSR access */
84 unsigned long (*read_control
)(void __iomem
*base
, unsigned long offs
);
85 void (*write_control
)(void __iomem
*base
, unsigned long offs
,
88 /* callbacks for CMCNT and CMCOR access */
89 unsigned long (*read_count
)(void __iomem
*base
, unsigned long offs
);
90 void (*write_count
)(void __iomem
*base
, unsigned long offs
,
94 struct sh_cmt_channel
{
95 struct sh_cmt_device
*cmt
;
97 unsigned int index
; /* Index in the documentation */
98 unsigned int hwidx
; /* Real hardware index */
100 void __iomem
*iostart
;
101 void __iomem
*ioctrl
;
103 unsigned int timer_bit
;
105 unsigned long match_value
;
106 unsigned long next_match_value
;
107 unsigned long max_match_value
;
109 struct clock_event_device ced
;
110 struct clocksource cs
;
111 unsigned long total_cycles
;
115 struct sh_cmt_device
{
116 struct platform_device
*pdev
;
118 const struct sh_cmt_info
*info
;
120 void __iomem
*mapbase
;
124 raw_spinlock_t lock
; /* Protect the shared start/stop register */
126 struct sh_cmt_channel
*channels
;
127 unsigned int num_channels
;
128 unsigned int hw_channels
;
131 bool has_clocksource
;
134 #define SH_CMT16_CMCSR_CMF (1 << 7)
135 #define SH_CMT16_CMCSR_CMIE (1 << 6)
136 #define SH_CMT16_CMCSR_CKS8 (0 << 0)
137 #define SH_CMT16_CMCSR_CKS32 (1 << 0)
138 #define SH_CMT16_CMCSR_CKS128 (2 << 0)
139 #define SH_CMT16_CMCSR_CKS512 (3 << 0)
140 #define SH_CMT16_CMCSR_CKS_MASK (3 << 0)
142 #define SH_CMT32_CMCSR_CMF (1 << 15)
143 #define SH_CMT32_CMCSR_OVF (1 << 14)
144 #define SH_CMT32_CMCSR_WRFLG (1 << 13)
145 #define SH_CMT32_CMCSR_STTF (1 << 12)
146 #define SH_CMT32_CMCSR_STPF (1 << 11)
147 #define SH_CMT32_CMCSR_SSIE (1 << 10)
148 #define SH_CMT32_CMCSR_CMS (1 << 9)
149 #define SH_CMT32_CMCSR_CMM (1 << 8)
150 #define SH_CMT32_CMCSR_CMTOUT_IE (1 << 7)
151 #define SH_CMT32_CMCSR_CMR_NONE (0 << 4)
152 #define SH_CMT32_CMCSR_CMR_DMA (1 << 4)
153 #define SH_CMT32_CMCSR_CMR_IRQ (2 << 4)
154 #define SH_CMT32_CMCSR_CMR_MASK (3 << 4)
155 #define SH_CMT32_CMCSR_DBGIVD (1 << 3)
156 #define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0)
157 #define SH_CMT32_CMCSR_CKS_RCLK32 (5 << 0)
158 #define SH_CMT32_CMCSR_CKS_RCLK128 (6 << 0)
159 #define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0)
160 #define SH_CMT32_CMCSR_CKS_MASK (7 << 0)
162 static unsigned long sh_cmt_read16(void __iomem
*base
, unsigned long offs
)
164 return ioread16(base
+ (offs
<< 1));
167 static unsigned long sh_cmt_read32(void __iomem
*base
, unsigned long offs
)
169 return ioread32(base
+ (offs
<< 2));
172 static void sh_cmt_write16(void __iomem
*base
, unsigned long offs
,
175 iowrite16(value
, base
+ (offs
<< 1));
178 static void sh_cmt_write32(void __iomem
*base
, unsigned long offs
,
181 iowrite32(value
, base
+ (offs
<< 2));
184 static const struct sh_cmt_info sh_cmt_info
[] = {
186 .model
= SH_CMT_16BIT
,
188 .overflow_bit
= SH_CMT16_CMCSR_CMF
,
189 .clear_bits
= ~SH_CMT16_CMCSR_CMF
,
190 .read_control
= sh_cmt_read16
,
191 .write_control
= sh_cmt_write16
,
192 .read_count
= sh_cmt_read16
,
193 .write_count
= sh_cmt_write16
,
196 .model
= SH_CMT_32BIT
,
198 .overflow_bit
= SH_CMT32_CMCSR_CMF
,
199 .clear_bits
= ~(SH_CMT32_CMCSR_CMF
| SH_CMT32_CMCSR_OVF
),
200 .read_control
= sh_cmt_read16
,
201 .write_control
= sh_cmt_write16
,
202 .read_count
= sh_cmt_read32
,
203 .write_count
= sh_cmt_write32
,
206 .model
= SH_CMT_48BIT
,
207 .channels_mask
= 0x3f,
209 .overflow_bit
= SH_CMT32_CMCSR_CMF
,
210 .clear_bits
= ~(SH_CMT32_CMCSR_CMF
| SH_CMT32_CMCSR_OVF
),
211 .read_control
= sh_cmt_read32
,
212 .write_control
= sh_cmt_write32
,
213 .read_count
= sh_cmt_read32
,
214 .write_count
= sh_cmt_write32
,
216 [SH_CMT0_RCAR_GEN2
] = {
217 .model
= SH_CMT0_RCAR_GEN2
,
218 .channels_mask
= 0x60,
220 .overflow_bit
= SH_CMT32_CMCSR_CMF
,
221 .clear_bits
= ~(SH_CMT32_CMCSR_CMF
| SH_CMT32_CMCSR_OVF
),
222 .read_control
= sh_cmt_read32
,
223 .write_control
= sh_cmt_write32
,
224 .read_count
= sh_cmt_read32
,
225 .write_count
= sh_cmt_write32
,
227 [SH_CMT1_RCAR_GEN2
] = {
228 .model
= SH_CMT1_RCAR_GEN2
,
229 .channels_mask
= 0xff,
231 .overflow_bit
= SH_CMT32_CMCSR_CMF
,
232 .clear_bits
= ~(SH_CMT32_CMCSR_CMF
| SH_CMT32_CMCSR_OVF
),
233 .read_control
= sh_cmt_read32
,
234 .write_control
= sh_cmt_write32
,
235 .read_count
= sh_cmt_read32
,
236 .write_count
= sh_cmt_write32
,
240 #define CMCSR 0 /* channel register */
241 #define CMCNT 1 /* channel register */
242 #define CMCOR 2 /* channel register */
244 static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_channel
*ch
)
247 return ch
->cmt
->info
->read_control(ch
->iostart
, 0);
249 return ch
->cmt
->info
->read_control(ch
->cmt
->mapbase
, 0);
252 static inline void sh_cmt_write_cmstr(struct sh_cmt_channel
*ch
,
256 ch
->cmt
->info
->write_control(ch
->iostart
, 0, value
);
258 ch
->cmt
->info
->write_control(ch
->cmt
->mapbase
, 0, value
);
261 static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_channel
*ch
)
263 return ch
->cmt
->info
->read_control(ch
->ioctrl
, CMCSR
);
266 static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel
*ch
,
269 ch
->cmt
->info
->write_control(ch
->ioctrl
, CMCSR
, value
);
272 static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_channel
*ch
)
274 return ch
->cmt
->info
->read_count(ch
->ioctrl
, CMCNT
);
277 static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel
*ch
,
280 ch
->cmt
->info
->write_count(ch
->ioctrl
, CMCNT
, value
);
283 static inline void sh_cmt_write_cmcor(struct sh_cmt_channel
*ch
,
286 ch
->cmt
->info
->write_count(ch
->ioctrl
, CMCOR
, value
);
289 static unsigned long sh_cmt_get_counter(struct sh_cmt_channel
*ch
,
292 unsigned long v1
, v2
, v3
;
295 o1
= sh_cmt_read_cmcsr(ch
) & ch
->cmt
->info
->overflow_bit
;
297 /* Make sure the timer value is stable. Stolen from acpi_pm.c */
300 v1
= sh_cmt_read_cmcnt(ch
);
301 v2
= sh_cmt_read_cmcnt(ch
);
302 v3
= sh_cmt_read_cmcnt(ch
);
303 o1
= sh_cmt_read_cmcsr(ch
) & ch
->cmt
->info
->overflow_bit
;
304 } while (unlikely((o1
!= o2
) || (v1
> v2
&& v1
< v3
)
305 || (v2
> v3
&& v2
< v1
) || (v3
> v1
&& v3
< v2
)));
311 static void sh_cmt_start_stop_ch(struct sh_cmt_channel
*ch
, int start
)
313 unsigned long flags
, value
;
315 /* start stop register shared by multiple timer channels */
316 raw_spin_lock_irqsave(&ch
->cmt
->lock
, flags
);
317 value
= sh_cmt_read_cmstr(ch
);
320 value
|= 1 << ch
->timer_bit
;
322 value
&= ~(1 << ch
->timer_bit
);
324 sh_cmt_write_cmstr(ch
, value
);
325 raw_spin_unlock_irqrestore(&ch
->cmt
->lock
, flags
);
328 static int sh_cmt_enable(struct sh_cmt_channel
*ch
)
332 pm_runtime_get_sync(&ch
->cmt
->pdev
->dev
);
333 dev_pm_syscore_device(&ch
->cmt
->pdev
->dev
, true);
336 ret
= clk_enable(ch
->cmt
->clk
);
338 dev_err(&ch
->cmt
->pdev
->dev
, "ch%u: cannot enable clock\n",
343 /* make sure channel is disabled */
344 sh_cmt_start_stop_ch(ch
, 0);
346 /* configure channel, periodic mode and maximum timeout */
347 if (ch
->cmt
->info
->width
== 16) {
348 sh_cmt_write_cmcsr(ch
, SH_CMT16_CMCSR_CMIE
|
349 SH_CMT16_CMCSR_CKS512
);
351 sh_cmt_write_cmcsr(ch
, SH_CMT32_CMCSR_CMM
|
352 SH_CMT32_CMCSR_CMTOUT_IE
|
353 SH_CMT32_CMCSR_CMR_IRQ
|
354 SH_CMT32_CMCSR_CKS_RCLK8
);
357 sh_cmt_write_cmcor(ch
, 0xffffffff);
358 sh_cmt_write_cmcnt(ch
, 0);
361 * According to the sh73a0 user's manual, as CMCNT can be operated
362 * only by the RCLK (Pseudo 32 KHz), there's one restriction on
363 * modifying CMCNT register; two RCLK cycles are necessary before
364 * this register is either read or any modification of the value
365 * it holds is reflected in the LSI's actual operation.
367 * While at it, we're supposed to clear out the CMCNT as of this
368 * moment, so make sure it's processed properly here. This will
369 * take RCLKx2 at maximum.
371 for (k
= 0; k
< 100; k
++) {
372 if (!sh_cmt_read_cmcnt(ch
))
377 if (sh_cmt_read_cmcnt(ch
)) {
378 dev_err(&ch
->cmt
->pdev
->dev
, "ch%u: cannot clear CMCNT\n",
385 sh_cmt_start_stop_ch(ch
, 1);
389 clk_disable(ch
->cmt
->clk
);
395 static void sh_cmt_disable(struct sh_cmt_channel
*ch
)
397 /* disable channel */
398 sh_cmt_start_stop_ch(ch
, 0);
400 /* disable interrupts in CMT block */
401 sh_cmt_write_cmcsr(ch
, 0);
404 clk_disable(ch
->cmt
->clk
);
406 dev_pm_syscore_device(&ch
->cmt
->pdev
->dev
, false);
407 pm_runtime_put(&ch
->cmt
->pdev
->dev
);
411 #define FLAG_CLOCKEVENT (1 << 0)
412 #define FLAG_CLOCKSOURCE (1 << 1)
413 #define FLAG_REPROGRAM (1 << 2)
414 #define FLAG_SKIPEVENT (1 << 3)
415 #define FLAG_IRQCONTEXT (1 << 4)
417 static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel
*ch
,
420 unsigned long new_match
;
421 unsigned long value
= ch
->next_match_value
;
422 unsigned long delay
= 0;
423 unsigned long now
= 0;
426 now
= sh_cmt_get_counter(ch
, &has_wrapped
);
427 ch
->flags
|= FLAG_REPROGRAM
; /* force reprogram */
430 /* we're competing with the interrupt handler.
431 * -> let the interrupt handler reprogram the timer.
432 * -> interrupt number two handles the event.
434 ch
->flags
|= FLAG_SKIPEVENT
;
442 /* reprogram the timer hardware,
443 * but don't save the new match value yet.
445 new_match
= now
+ value
+ delay
;
446 if (new_match
> ch
->max_match_value
)
447 new_match
= ch
->max_match_value
;
449 sh_cmt_write_cmcor(ch
, new_match
);
451 now
= sh_cmt_get_counter(ch
, &has_wrapped
);
452 if (has_wrapped
&& (new_match
> ch
->match_value
)) {
453 /* we are changing to a greater match value,
454 * so this wrap must be caused by the counter
455 * matching the old value.
456 * -> first interrupt reprograms the timer.
457 * -> interrupt number two handles the event.
459 ch
->flags
|= FLAG_SKIPEVENT
;
464 /* we are changing to a smaller match value,
465 * so the wrap must be caused by the counter
466 * matching the new value.
467 * -> save programmed match value.
468 * -> let isr handle the event.
470 ch
->match_value
= new_match
;
474 /* be safe: verify hardware settings */
475 if (now
< new_match
) {
476 /* timer value is below match value, all good.
477 * this makes sure we won't miss any match events.
478 * -> save programmed match value.
479 * -> let isr handle the event.
481 ch
->match_value
= new_match
;
485 /* the counter has reached a value greater
486 * than our new match value. and since the
487 * has_wrapped flag isn't set we must have
488 * programmed a too close event.
489 * -> increase delay and retry.
497 dev_warn(&ch
->cmt
->pdev
->dev
, "ch%u: too long delay\n",
503 static void __sh_cmt_set_next(struct sh_cmt_channel
*ch
, unsigned long delta
)
505 if (delta
> ch
->max_match_value
)
506 dev_warn(&ch
->cmt
->pdev
->dev
, "ch%u: delta out of range\n",
509 ch
->next_match_value
= delta
;
510 sh_cmt_clock_event_program_verify(ch
, 0);
513 static void sh_cmt_set_next(struct sh_cmt_channel
*ch
, unsigned long delta
)
517 raw_spin_lock_irqsave(&ch
->lock
, flags
);
518 __sh_cmt_set_next(ch
, delta
);
519 raw_spin_unlock_irqrestore(&ch
->lock
, flags
);
522 static irqreturn_t
sh_cmt_interrupt(int irq
, void *dev_id
)
524 struct sh_cmt_channel
*ch
= dev_id
;
527 sh_cmt_write_cmcsr(ch
, sh_cmt_read_cmcsr(ch
) &
528 ch
->cmt
->info
->clear_bits
);
530 /* update clock source counter to begin with if enabled
531 * the wrap flag should be cleared by the timer specific
532 * isr before we end up here.
534 if (ch
->flags
& FLAG_CLOCKSOURCE
)
535 ch
->total_cycles
+= ch
->match_value
+ 1;
537 if (!(ch
->flags
& FLAG_REPROGRAM
))
538 ch
->next_match_value
= ch
->max_match_value
;
540 ch
->flags
|= FLAG_IRQCONTEXT
;
542 if (ch
->flags
& FLAG_CLOCKEVENT
) {
543 if (!(ch
->flags
& FLAG_SKIPEVENT
)) {
544 if (clockevent_state_oneshot(&ch
->ced
)) {
545 ch
->next_match_value
= ch
->max_match_value
;
546 ch
->flags
|= FLAG_REPROGRAM
;
549 ch
->ced
.event_handler(&ch
->ced
);
553 ch
->flags
&= ~FLAG_SKIPEVENT
;
555 if (ch
->flags
& FLAG_REPROGRAM
) {
556 ch
->flags
&= ~FLAG_REPROGRAM
;
557 sh_cmt_clock_event_program_verify(ch
, 1);
559 if (ch
->flags
& FLAG_CLOCKEVENT
)
560 if ((clockevent_state_shutdown(&ch
->ced
))
561 || (ch
->match_value
== ch
->next_match_value
))
562 ch
->flags
&= ~FLAG_REPROGRAM
;
565 ch
->flags
&= ~FLAG_IRQCONTEXT
;
570 static int sh_cmt_start(struct sh_cmt_channel
*ch
, unsigned long flag
)
575 raw_spin_lock_irqsave(&ch
->lock
, flags
);
577 if (!(ch
->flags
& (FLAG_CLOCKEVENT
| FLAG_CLOCKSOURCE
)))
578 ret
= sh_cmt_enable(ch
);
584 /* setup timeout if no clockevent */
585 if ((flag
== FLAG_CLOCKSOURCE
) && (!(ch
->flags
& FLAG_CLOCKEVENT
)))
586 __sh_cmt_set_next(ch
, ch
->max_match_value
);
588 raw_spin_unlock_irqrestore(&ch
->lock
, flags
);
593 static void sh_cmt_stop(struct sh_cmt_channel
*ch
, unsigned long flag
)
598 raw_spin_lock_irqsave(&ch
->lock
, flags
);
600 f
= ch
->flags
& (FLAG_CLOCKEVENT
| FLAG_CLOCKSOURCE
);
603 if (f
&& !(ch
->flags
& (FLAG_CLOCKEVENT
| FLAG_CLOCKSOURCE
)))
606 /* adjust the timeout to maximum if only clocksource left */
607 if ((flag
== FLAG_CLOCKEVENT
) && (ch
->flags
& FLAG_CLOCKSOURCE
))
608 __sh_cmt_set_next(ch
, ch
->max_match_value
);
610 raw_spin_unlock_irqrestore(&ch
->lock
, flags
);
613 static struct sh_cmt_channel
*cs_to_sh_cmt(struct clocksource
*cs
)
615 return container_of(cs
, struct sh_cmt_channel
, cs
);
618 static u64
sh_cmt_clocksource_read(struct clocksource
*cs
)
620 struct sh_cmt_channel
*ch
= cs_to_sh_cmt(cs
);
621 unsigned long flags
, raw
;
625 raw_spin_lock_irqsave(&ch
->lock
, flags
);
626 value
= ch
->total_cycles
;
627 raw
= sh_cmt_get_counter(ch
, &has_wrapped
);
629 if (unlikely(has_wrapped
))
630 raw
+= ch
->match_value
+ 1;
631 raw_spin_unlock_irqrestore(&ch
->lock
, flags
);
636 static int sh_cmt_clocksource_enable(struct clocksource
*cs
)
639 struct sh_cmt_channel
*ch
= cs_to_sh_cmt(cs
);
641 WARN_ON(ch
->cs_enabled
);
643 ch
->total_cycles
= 0;
645 ret
= sh_cmt_start(ch
, FLAG_CLOCKSOURCE
);
647 ch
->cs_enabled
= true;
652 static void sh_cmt_clocksource_disable(struct clocksource
*cs
)
654 struct sh_cmt_channel
*ch
= cs_to_sh_cmt(cs
);
656 WARN_ON(!ch
->cs_enabled
);
658 sh_cmt_stop(ch
, FLAG_CLOCKSOURCE
);
659 ch
->cs_enabled
= false;
662 static void sh_cmt_clocksource_suspend(struct clocksource
*cs
)
664 struct sh_cmt_channel
*ch
= cs_to_sh_cmt(cs
);
669 sh_cmt_stop(ch
, FLAG_CLOCKSOURCE
);
670 pm_genpd_syscore_poweroff(&ch
->cmt
->pdev
->dev
);
673 static void sh_cmt_clocksource_resume(struct clocksource
*cs
)
675 struct sh_cmt_channel
*ch
= cs_to_sh_cmt(cs
);
680 pm_genpd_syscore_poweron(&ch
->cmt
->pdev
->dev
);
681 sh_cmt_start(ch
, FLAG_CLOCKSOURCE
);
684 static int sh_cmt_register_clocksource(struct sh_cmt_channel
*ch
,
687 struct clocksource
*cs
= &ch
->cs
;
691 cs
->read
= sh_cmt_clocksource_read
;
692 cs
->enable
= sh_cmt_clocksource_enable
;
693 cs
->disable
= sh_cmt_clocksource_disable
;
694 cs
->suspend
= sh_cmt_clocksource_suspend
;
695 cs
->resume
= sh_cmt_clocksource_resume
;
696 cs
->mask
= CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
697 cs
->flags
= CLOCK_SOURCE_IS_CONTINUOUS
;
699 dev_info(&ch
->cmt
->pdev
->dev
, "ch%u: used as clock source\n",
702 clocksource_register_hz(cs
, ch
->cmt
->rate
);
706 static struct sh_cmt_channel
*ced_to_sh_cmt(struct clock_event_device
*ced
)
708 return container_of(ced
, struct sh_cmt_channel
, ced
);
711 static void sh_cmt_clock_event_start(struct sh_cmt_channel
*ch
, int periodic
)
713 sh_cmt_start(ch
, FLAG_CLOCKEVENT
);
716 sh_cmt_set_next(ch
, ((ch
->cmt
->rate
+ HZ
/2) / HZ
) - 1);
718 sh_cmt_set_next(ch
, ch
->max_match_value
);
721 static int sh_cmt_clock_event_shutdown(struct clock_event_device
*ced
)
723 struct sh_cmt_channel
*ch
= ced_to_sh_cmt(ced
);
725 sh_cmt_stop(ch
, FLAG_CLOCKEVENT
);
729 static int sh_cmt_clock_event_set_state(struct clock_event_device
*ced
,
732 struct sh_cmt_channel
*ch
= ced_to_sh_cmt(ced
);
734 /* deal with old setting first */
735 if (clockevent_state_oneshot(ced
) || clockevent_state_periodic(ced
))
736 sh_cmt_stop(ch
, FLAG_CLOCKEVENT
);
738 dev_info(&ch
->cmt
->pdev
->dev
, "ch%u: used for %s clock events\n",
739 ch
->index
, periodic
? "periodic" : "oneshot");
740 sh_cmt_clock_event_start(ch
, periodic
);
744 static int sh_cmt_clock_event_set_oneshot(struct clock_event_device
*ced
)
746 return sh_cmt_clock_event_set_state(ced
, 0);
749 static int sh_cmt_clock_event_set_periodic(struct clock_event_device
*ced
)
751 return sh_cmt_clock_event_set_state(ced
, 1);
754 static int sh_cmt_clock_event_next(unsigned long delta
,
755 struct clock_event_device
*ced
)
757 struct sh_cmt_channel
*ch
= ced_to_sh_cmt(ced
);
759 BUG_ON(!clockevent_state_oneshot(ced
));
760 if (likely(ch
->flags
& FLAG_IRQCONTEXT
))
761 ch
->next_match_value
= delta
- 1;
763 sh_cmt_set_next(ch
, delta
- 1);
768 static void sh_cmt_clock_event_suspend(struct clock_event_device
*ced
)
770 struct sh_cmt_channel
*ch
= ced_to_sh_cmt(ced
);
772 pm_genpd_syscore_poweroff(&ch
->cmt
->pdev
->dev
);
773 clk_unprepare(ch
->cmt
->clk
);
776 static void sh_cmt_clock_event_resume(struct clock_event_device
*ced
)
778 struct sh_cmt_channel
*ch
= ced_to_sh_cmt(ced
);
780 clk_prepare(ch
->cmt
->clk
);
781 pm_genpd_syscore_poweron(&ch
->cmt
->pdev
->dev
);
784 static int sh_cmt_register_clockevent(struct sh_cmt_channel
*ch
,
787 struct clock_event_device
*ced
= &ch
->ced
;
791 irq
= platform_get_irq(ch
->cmt
->pdev
, ch
->index
);
793 dev_err(&ch
->cmt
->pdev
->dev
, "ch%u: failed to get irq\n",
798 ret
= request_irq(irq
, sh_cmt_interrupt
,
799 IRQF_TIMER
| IRQF_IRQPOLL
| IRQF_NOBALANCING
,
800 dev_name(&ch
->cmt
->pdev
->dev
), ch
);
802 dev_err(&ch
->cmt
->pdev
->dev
, "ch%u: failed to request irq %d\n",
808 ced
->features
= CLOCK_EVT_FEAT_PERIODIC
;
809 ced
->features
|= CLOCK_EVT_FEAT_ONESHOT
;
811 ced
->cpumask
= cpu_possible_mask
;
812 ced
->set_next_event
= sh_cmt_clock_event_next
;
813 ced
->set_state_shutdown
= sh_cmt_clock_event_shutdown
;
814 ced
->set_state_periodic
= sh_cmt_clock_event_set_periodic
;
815 ced
->set_state_oneshot
= sh_cmt_clock_event_set_oneshot
;
816 ced
->suspend
= sh_cmt_clock_event_suspend
;
817 ced
->resume
= sh_cmt_clock_event_resume
;
819 /* TODO: calculate good shift from rate and counter bit width */
821 ced
->mult
= div_sc(ch
->cmt
->rate
, NSEC_PER_SEC
, ced
->shift
);
822 ced
->max_delta_ns
= clockevent_delta2ns(ch
->max_match_value
, ced
);
823 ced
->max_delta_ticks
= ch
->max_match_value
;
824 ced
->min_delta_ns
= clockevent_delta2ns(0x1f, ced
);
825 ced
->min_delta_ticks
= 0x1f;
827 dev_info(&ch
->cmt
->pdev
->dev
, "ch%u: used for clock events\n",
829 clockevents_register_device(ced
);
834 static int sh_cmt_register(struct sh_cmt_channel
*ch
, const char *name
,
835 bool clockevent
, bool clocksource
)
840 ch
->cmt
->has_clockevent
= true;
841 ret
= sh_cmt_register_clockevent(ch
, name
);
847 ch
->cmt
->has_clocksource
= true;
848 sh_cmt_register_clocksource(ch
, name
);
854 static int sh_cmt_setup_channel(struct sh_cmt_channel
*ch
, unsigned int index
,
855 unsigned int hwidx
, bool clockevent
,
856 bool clocksource
, struct sh_cmt_device
*cmt
)
860 /* Skip unused channels. */
861 if (!clockevent
&& !clocksource
)
867 ch
->timer_bit
= hwidx
;
870 * Compute the address of the channel control register block. For the
871 * timers with a per-channel start/stop register, compute its address
874 switch (cmt
->info
->model
) {
876 ch
->ioctrl
= cmt
->mapbase
+ 2 + ch
->hwidx
* 6;
880 ch
->ioctrl
= cmt
->mapbase
+ 0x10 + ch
->hwidx
* 0x10;
882 case SH_CMT0_RCAR_GEN2
:
883 case SH_CMT1_RCAR_GEN2
:
884 ch
->iostart
= cmt
->mapbase
+ ch
->hwidx
* 0x100;
885 ch
->ioctrl
= ch
->iostart
+ 0x10;
890 if (cmt
->info
->width
== (sizeof(ch
->max_match_value
) * 8))
891 ch
->max_match_value
= ~0;
893 ch
->max_match_value
= (1 << cmt
->info
->width
) - 1;
895 ch
->match_value
= ch
->max_match_value
;
896 raw_spin_lock_init(&ch
->lock
);
898 ret
= sh_cmt_register(ch
, dev_name(&cmt
->pdev
->dev
),
899 clockevent
, clocksource
);
901 dev_err(&cmt
->pdev
->dev
, "ch%u: registration failed\n",
905 ch
->cs_enabled
= false;
910 static int sh_cmt_map_memory(struct sh_cmt_device
*cmt
)
912 struct resource
*mem
;
914 mem
= platform_get_resource(cmt
->pdev
, IORESOURCE_MEM
, 0);
916 dev_err(&cmt
->pdev
->dev
, "failed to get I/O memory\n");
920 cmt
->mapbase
= ioremap_nocache(mem
->start
, resource_size(mem
));
921 if (cmt
->mapbase
== NULL
) {
922 dev_err(&cmt
->pdev
->dev
, "failed to remap I/O memory\n");
929 static const struct platform_device_id sh_cmt_id_table
[] = {
930 { "sh-cmt-16", (kernel_ulong_t
)&sh_cmt_info
[SH_CMT_16BIT
] },
931 { "sh-cmt-32", (kernel_ulong_t
)&sh_cmt_info
[SH_CMT_32BIT
] },
934 MODULE_DEVICE_TABLE(platform
, sh_cmt_id_table
);
936 static const struct of_device_id sh_cmt_of_table
[] __maybe_unused
= {
937 { .compatible
= "renesas,cmt-48", .data
= &sh_cmt_info
[SH_CMT_48BIT
] },
938 { .compatible
= "renesas,cmt-48-gen2", .data
= &sh_cmt_info
[SH_CMT0_RCAR_GEN2
] },
939 { .compatible
= "renesas,rcar-gen2-cmt0", .data
= &sh_cmt_info
[SH_CMT0_RCAR_GEN2
] },
940 { .compatible
= "renesas,rcar-gen2-cmt1", .data
= &sh_cmt_info
[SH_CMT1_RCAR_GEN2
] },
943 MODULE_DEVICE_TABLE(of
, sh_cmt_of_table
);
945 static int sh_cmt_parse_dt(struct sh_cmt_device
*cmt
)
947 struct device_node
*np
= cmt
->pdev
->dev
.of_node
;
949 return of_property_read_u32(np
, "renesas,channels-mask",
953 static int sh_cmt_setup(struct sh_cmt_device
*cmt
, struct platform_device
*pdev
)
960 raw_spin_lock_init(&cmt
->lock
);
962 if (IS_ENABLED(CONFIG_OF
) && pdev
->dev
.of_node
) {
963 const struct of_device_id
*id
;
965 id
= of_match_node(sh_cmt_of_table
, pdev
->dev
.of_node
);
966 cmt
->info
= id
->data
;
968 /* prefer in-driver channel configuration over DT */
969 if (cmt
->info
->channels_mask
) {
970 cmt
->hw_channels
= cmt
->info
->channels_mask
;
972 ret
= sh_cmt_parse_dt(cmt
);
976 } else if (pdev
->dev
.platform_data
) {
977 struct sh_timer_config
*cfg
= pdev
->dev
.platform_data
;
978 const struct platform_device_id
*id
= pdev
->id_entry
;
980 cmt
->info
= (const struct sh_cmt_info
*)id
->driver_data
;
981 cmt
->hw_channels
= cfg
->channels_mask
;
983 dev_err(&cmt
->pdev
->dev
, "missing platform data\n");
987 /* Get hold of clock. */
988 cmt
->clk
= clk_get(&cmt
->pdev
->dev
, "fck");
989 if (IS_ERR(cmt
->clk
)) {
990 dev_err(&cmt
->pdev
->dev
, "cannot get clock\n");
991 return PTR_ERR(cmt
->clk
);
994 ret
= clk_prepare(cmt
->clk
);
998 /* Determine clock rate. */
999 ret
= clk_enable(cmt
->clk
);
1001 goto err_clk_unprepare
;
1003 if (cmt
->info
->width
== 16)
1004 cmt
->rate
= clk_get_rate(cmt
->clk
) / 512;
1006 cmt
->rate
= clk_get_rate(cmt
->clk
) / 8;
1008 clk_disable(cmt
->clk
);
1010 /* Map the memory resource(s). */
1011 ret
= sh_cmt_map_memory(cmt
);
1013 goto err_clk_unprepare
;
1015 /* Allocate and setup the channels. */
1016 cmt
->num_channels
= hweight8(cmt
->hw_channels
);
1017 cmt
->channels
= kzalloc(cmt
->num_channels
* sizeof(*cmt
->channels
),
1019 if (cmt
->channels
== NULL
) {
1025 * Use the first channel as a clock event device and the second channel
1026 * as a clock source. If only one channel is available use it for both.
1028 for (i
= 0, mask
= cmt
->hw_channels
; i
< cmt
->num_channels
; ++i
) {
1029 unsigned int hwidx
= ffs(mask
) - 1;
1030 bool clocksource
= i
== 1 || cmt
->num_channels
== 1;
1031 bool clockevent
= i
== 0;
1033 ret
= sh_cmt_setup_channel(&cmt
->channels
[i
], i
, hwidx
,
1034 clockevent
, clocksource
, cmt
);
1038 mask
&= ~(1 << hwidx
);
1041 platform_set_drvdata(pdev
, cmt
);
1046 kfree(cmt
->channels
);
1047 iounmap(cmt
->mapbase
);
1049 clk_unprepare(cmt
->clk
);
1055 static int sh_cmt_probe(struct platform_device
*pdev
)
1057 struct sh_cmt_device
*cmt
= platform_get_drvdata(pdev
);
1060 if (!is_early_platform_device(pdev
)) {
1061 pm_runtime_set_active(&pdev
->dev
);
1062 pm_runtime_enable(&pdev
->dev
);
1066 dev_info(&pdev
->dev
, "kept as earlytimer\n");
1070 cmt
= kzalloc(sizeof(*cmt
), GFP_KERNEL
);
1074 ret
= sh_cmt_setup(cmt
, pdev
);
1077 pm_runtime_idle(&pdev
->dev
);
1080 if (is_early_platform_device(pdev
))
1084 if (cmt
->has_clockevent
|| cmt
->has_clocksource
)
1085 pm_runtime_irq_safe(&pdev
->dev
);
1087 pm_runtime_idle(&pdev
->dev
);
1092 static int sh_cmt_remove(struct platform_device
*pdev
)
1094 return -EBUSY
; /* cannot unregister clockevent and clocksource */
1097 static struct platform_driver sh_cmt_device_driver
= {
1098 .probe
= sh_cmt_probe
,
1099 .remove
= sh_cmt_remove
,
1102 .of_match_table
= of_match_ptr(sh_cmt_of_table
),
1104 .id_table
= sh_cmt_id_table
,
1107 static int __init
sh_cmt_init(void)
1109 return platform_driver_register(&sh_cmt_device_driver
);
1112 static void __exit
sh_cmt_exit(void)
1114 platform_driver_unregister(&sh_cmt_device_driver
);
1117 early_platform_init("earlytimer", &sh_cmt_device_driver
);
1118 subsys_initcall(sh_cmt_init
);
1119 module_exit(sh_cmt_exit
);
1121 MODULE_AUTHOR("Magnus Damm");
1122 MODULE_DESCRIPTION("SuperH CMT Timer Driver");
1123 MODULE_LICENSE("GPL v2");