drivers/clocksource/tcb_clksrc.c

   1 #include <linux/init.h>
   2 #include <linux/clocksource.h>
   3 #include <linux/clockchips.h>
   4 #include <linux/interrupt.h>
   5 #include <linux/irq.h>
   6
   7 #include <linux/clk.h>
   8 #include <linux/err.h>
   9 #include <linux/ioport.h>
  10 #include <linux/io.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/atmel_tc.h>
  13 #include <linux/sched_clock.h>
  14
  15
  16 /*
  17  * We're configured to use a specific TC block, one that's not hooked
  18  * up to external hardware, to provide a time solution:
  19  *
  20  *   - Two channels combine to create a free-running 32 bit counter
  21  *     with a base rate of 5+ MHz, packaged as a clocksource (with
  22  *     resolution better than 200 nsec).
  23  *   - Some chips support 32 bit counter. A single channel is used for
  24  *     this 32 bit free-running counter. the second channel is not used.
  25  *
  26  *   - The third channel may be used to provide a 16-bit clockevent
  27  *     source, used in either periodic or oneshot mode.  This runs
  28  *     at 32 KiHZ, and can handle delays of up to two seconds.
  29  *
  30  * A boot clocksource and clockevent source are also currently needed,
  31  * unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so
  32  * this code can be used when init_timers() is called, well before most
  33  * devices are set up.  (Some low end AT91 parts, which can run uClinux,
  34  * have only the timers in one TC block... they currently don't support
  35  * the tclib code, because of that initialization issue.)
  36  *
  37  * REVISIT behavior during system suspend states... we should disable
  38  * all clocks and save the power.  Easily done for clockevent devices,
  39  * but clocksources won't necessarily get the needed notifications.
  40  * For deeper system sleep states, this will be mandatory...
  41  */
  42
  43 static void __iomem *tcaddr;
  44
  45 static u64 tc_get_cycles(struct clocksource *cs)
  46 {
  47         unsigned long   flags;
  48         u32             lower, upper;
  49
  50         raw_local_irq_save(flags);
  51         do {
  52                 upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
  53                 lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
  54         } while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
  55
  56         raw_local_irq_restore(flags);
  57         return (upper << 16) | lower;
  58 }
  59
  60 static u32 tc_get_cv32(void)
  61 {
  62         return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
  63 }
  64
  65 static u64 tc_get_cycles32(struct clocksource *cs)
  66 {
  67         return tc_get_cv32();
  68 }
  69
  70 static struct clocksource clksrc = {
  71         .name           = "tcb_clksrc",
  72         .rating         = 200,
  73         .read           = tc_get_cycles,
  74         .mask           = CLOCKSOURCE_MASK(32),
  75         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  76 };
  77
  78 static u64 notrace tc_read_sched_clock(void)
  79 {
  80         return tc_get_cv32();
  81 }
  82
  83 #ifdef CONFIG_GENERIC_CLOCKEVENTS
  84
  85 struct tc_clkevt_device {
  86         struct clock_event_device       clkevt;
  87         struct clk                      *clk;
  88         void __iomem                    *regs;
  89 };
  90
  91 static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt)
  92 {
  93         return container_of(clkevt, struct tc_clkevt_device, clkevt);
  94 }
  95
  96 /* For now, we always use the 32K clock ... this optimizes for NO_HZ,
  97  * because using one of the divided clocks would usually mean the
  98  * tick rate can never be less than several dozen Hz (vs 0.5 Hz).
  99  *
 100  * A divided clock could be good for high resolution timers, since
 101  * 30.5 usec resolution can seem "low".
 102  */
 103 static u32 timer_clock;
 104
 105 static int tc_shutdown(struct clock_event_device *d)
 106 {
 107         struct tc_clkevt_device *tcd = to_tc_clkevt(d);
 108         void __iomem            *regs = tcd->regs;
 109
 110         __raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
 111         __raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
 112         if (!clockevent_state_detached(d))
 113                 clk_disable(tcd->clk);
 114
 115         return 0;
 116 }
 117
 118 static int tc_set_oneshot(struct clock_event_device *d)
 119 {
 120         struct tc_clkevt_device *tcd = to_tc_clkevt(d);
 121         void __iomem            *regs = tcd->regs;
 122
 123         if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
 124                 tc_shutdown(d);
 125
 126         clk_enable(tcd->clk);
 127
 128         /* slow clock, count up to RC, then irq and stop */
 129         __raw_writel(timer_clock | ATMEL_TC_CPCSTOP | ATMEL_TC_WAVE |
 130                      ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR));
 131         __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
 132
 133         /* set_next_event() configures and starts the timer */
 134         return 0;
 135 }
 136
 137 static int tc_set_periodic(struct clock_event_device *d)
 138 {
 139         struct tc_clkevt_device *tcd = to_tc_clkevt(d);
 140         void __iomem            *regs = tcd->regs;
 141
 142         if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
 143                 tc_shutdown(d);
 144
 145         /* By not making the gentime core emulate periodic mode on top
 146          * of oneshot, we get lower overhead and improved accuracy.
 147          */
 148         clk_enable(tcd->clk);
 149
 150         /* slow clock, count up to RC, then irq and restart */
 151         __raw_writel(timer_clock | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
 152                      regs + ATMEL_TC_REG(2, CMR));
 153         __raw_writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
 154
 155         /* Enable clock and interrupts on RC compare */
 156         __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
 157
 158         /* go go gadget! */
 159         __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, regs +
 160                      ATMEL_TC_REG(2, CCR));
 161         return 0;
 162 }
 163
 164 static int tc_next_event(unsigned long delta, struct clock_event_device *d)
 165 {
 166         __raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
 167
 168         /* go go gadget! */
 169         __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
 170                         tcaddr + ATMEL_TC_REG(2, CCR));
 171         return 0;
 172 }
 173
 174 static struct tc_clkevt_device clkevt = {
 175         .clkevt = {
 176                 .name                   = "tc_clkevt",
 177                 .features               = CLOCK_EVT_FEAT_PERIODIC |
 178                                           CLOCK_EVT_FEAT_ONESHOT,
 179                 /* Should be lower than at91rm9200's system timer */
 180                 .rating                 = 125,
 181                 .set_next_event         = tc_next_event,
 182                 .set_state_shutdown     = tc_shutdown,
 183                 .set_state_periodic     = tc_set_periodic,
 184                 .set_state_oneshot      = tc_set_oneshot,
 185         },
 186 };
 187
 188 static irqreturn_t ch2_irq(int irq, void *handle)
 189 {
 190         struct tc_clkevt_device *dev = handle;
 191         unsigned int            sr;
 192
 193         sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
 194         if (sr & ATMEL_TC_CPCS) {
 195                 dev->clkevt.event_handler(&dev->clkevt);
 196                 return IRQ_HANDLED;
 197         }
 198
 199         return IRQ_NONE;
 200 }
 201
 202 static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
 203 {
 204         int ret;
 205         struct clk *t2_clk = tc->clk[2];
 206         int irq = tc->irq[2];
 207
 208         ret = clk_prepare_enable(tc->slow_clk);
 209         if (ret)
 210                 return ret;
 211
 212         /* try to enable t2 clk to avoid future errors in mode change */
 213         ret = clk_prepare_enable(t2_clk);
 214         if (ret) {
 215                 clk_disable_unprepare(tc->slow_clk);
 216                 return ret;
 217         }
 218
 219         clk_disable(t2_clk);
 220
 221         clkevt.regs = tc->regs;
 222         clkevt.clk = t2_clk;
 223
 224         timer_clock = clk32k_divisor_idx;
 225
 226         clkevt.clkevt.cpumask = cpumask_of(0);
 227
 228         ret = request_irq(irq, ch2_irq, IRQF_TIMER, "tc_clkevt", &clkevt);
 229         if (ret) {
 230                 clk_unprepare(t2_clk);
 231                 clk_disable_unprepare(tc->slow_clk);
 232                 return ret;
 233         }
 234
 235         clockevents_config_and_register(&clkevt.clkevt, 32768, 1, 0xffff);
 236
 237         return ret;
 238 }
 239
 240 #else /* !CONFIG_GENERIC_CLOCKEVENTS */
 241
 242 static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
 243 {
 244         /* NOTHING */
 245         return 0;
 246 }
 247
 248 #endif
 249
 250 static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
 251 {
 252         /* channel 0:  waveform mode, input mclk/8, clock TIOA0 on overflow */
 253         __raw_writel(mck_divisor_idx                    /* likely divide-by-8 */
 254                         | ATMEL_TC_WAVE
 255                         | ATMEL_TC_WAVESEL_UP           /* free-run */
 256                         | ATMEL_TC_ACPA_SET             /* TIOA0 rises at 0 */
 257                         | ATMEL_TC_ACPC_CLEAR,          /* (duty cycle 50%) */
 258                         tcaddr + ATMEL_TC_REG(0, CMR));
 259         __raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
 260         __raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
 261         __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));      /* no irqs */
 262         __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
 263
 264         /* channel 1:  waveform mode, input TIOA0 */
 265         __raw_writel(ATMEL_TC_XC1                       /* input: TIOA0 */
 266                         | ATMEL_TC_WAVE
 267                         | ATMEL_TC_WAVESEL_UP,          /* free-run */
 268                         tcaddr + ATMEL_TC_REG(1, CMR));
 269         __raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));      /* no irqs */
 270         __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
 271
 272         /* chain channel 0 to channel 1*/
 273         __raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
 274         /* then reset all the timers */
 275         __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
 276 }
 277
 278 static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
 279 {
 280         /* channel 0:  waveform mode, input mclk/8 */
 281         __raw_writel(mck_divisor_idx                    /* likely divide-by-8 */
 282                         | ATMEL_TC_WAVE
 283                         | ATMEL_TC_WAVESEL_UP,          /* free-run */
 284                         tcaddr + ATMEL_TC_REG(0, CMR));
 285         __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));      /* no irqs */
 286         __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
 287
 288         /* then reset all the timers */
 289         __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
 290 }
 291
 292 static int __init tcb_clksrc_init(void)
 293 {
 294         static char bootinfo[] __initdata
 295                 = KERN_DEBUG "%s: tc%d at %d.%03d MHz\n";
 296
 297         struct platform_device *pdev;
 298         struct atmel_tc *tc;
 299         struct clk *t0_clk;
 300         u32 rate, divided_rate = 0;
 301         int best_divisor_idx = -1;
 302         int clk32k_divisor_idx = -1;
 303         int i;
 304         int ret;
 305
 306         tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK);
 307         if (!tc) {
 308                 pr_debug("can't alloc TC for clocksource\n");
 309                 return -ENODEV;
 310         }
 311         tcaddr = tc->regs;
 312         pdev = tc->pdev;
 313
 314         t0_clk = tc->clk[0];
 315         ret = clk_prepare_enable(t0_clk);
 316         if (ret) {
 317                 pr_debug("can't enable T0 clk\n");
 318                 goto err_free_tc;
 319         }
 320
 321         /* How fast will we be counting?  Pick something over 5 MHz.  */
 322         rate = (u32) clk_get_rate(t0_clk);
 323         for (i = 0; i < 5; i++) {
 324                 unsigned divisor = atmel_tc_divisors[i];
 325                 unsigned tmp;
 326
 327                 /* remember 32 KiHz clock for later */
 328                 if (!divisor) {
 329                         clk32k_divisor_idx = i;
 330                         continue;
 331                 }
 332
 333                 tmp = rate / divisor;
 334                 pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
 335                 if (best_divisor_idx > 0) {
 336                         if (tmp < 5 * 1000 * 1000)
 337                                 continue;
 338                 }
 339                 divided_rate = tmp;
 340                 best_divisor_idx = i;
 341         }
 342
 343
 344         printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
 345                         divided_rate / 1000000,
 346                         ((divided_rate + 500000) % 1000000) / 1000);
 347
 348         if (tc->tcb_config && tc->tcb_config->counter_width == 32) {
 349                 /* use apropriate function to read 32 bit counter */
 350                 clksrc.read = tc_get_cycles32;
 351                 /* setup ony channel 0 */
 352                 tcb_setup_single_chan(tc, best_divisor_idx);
 353
 354                 /* register sched_clock on chips with single 32 bit counter */
 355                 sched_clock_register(tc_read_sched_clock, 32, divided_rate);
 356         } else {
 357                 /* tclib will give us three clocks no matter what the
 358                  * underlying platform supports.
 359                  */
 360                 ret = clk_prepare_enable(tc->clk[1]);
 361                 if (ret) {
 362                         pr_debug("can't enable T1 clk\n");
 363                         goto err_disable_t0;
 364                 }
 365                 /* setup both channel 0 & 1 */
 366                 tcb_setup_dual_chan(tc, best_divisor_idx);
 367         }
 368
 369         /* and away we go! */
 370         ret = clocksource_register_hz(&clksrc, divided_rate);
 371         if (ret)
 372                 goto err_disable_t1;
 373
 374         /* channel 2:  periodic and oneshot timer support */
 375         ret = setup_clkevents(tc, clk32k_divisor_idx);
 376         if (ret)
 377                 goto err_unregister_clksrc;
 378
 379         return 0;
 380
 381 err_unregister_clksrc:
 382         clocksource_unregister(&clksrc);
 383
 384 err_disable_t1:
 385         if (!tc->tcb_config || tc->tcb_config->counter_width != 32)
 386                 clk_disable_unprepare(tc->clk[1]);
 387
 388 err_disable_t0:
 389         clk_disable_unprepare(t0_clk);
 390
 391 err_free_tc:
 392         atmel_tc_free(tc);
 393         return ret;
 394 }
 395 arch_initcall(tcb_clksrc_init);