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[mirror_ubuntu-bionic-kernel.git] / drivers / clocksource / tcb_clksrc.c
1 #include <linux/init.h>
2 #include <linux/clocksource.h>
3 #include <linux/clockchips.h>
4 #include <linux/interrupt.h>
5 #include <linux/irq.h>
6
7 #include <linux/clk.h>
8 #include <linux/err.h>
9 #include <linux/ioport.h>
10 #include <linux/io.h>
11 #include <linux/platform_device.h>
12 #include <linux/atmel_tc.h>
13
14
15 /*
16 * We're configured to use a specific TC block, one that's not hooked
17 * up to external hardware, to provide a time solution:
18 *
19 * - Two channels combine to create a free-running 32 bit counter
20 * with a base rate of 5+ MHz, packaged as a clocksource (with
21 * resolution better than 200 nsec).
22 * - Some chips support 32 bit counter. A single channel is used for
23 * this 32 bit free-running counter. the second channel is not used.
24 *
25 * - The third channel may be used to provide a 16-bit clockevent
26 * source, used in either periodic or oneshot mode. This runs
27 * at 32 KiHZ, and can handle delays of up to two seconds.
28 *
29 * A boot clocksource and clockevent source are also currently needed,
30 * unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so
31 * this code can be used when init_timers() is called, well before most
32 * devices are set up. (Some low end AT91 parts, which can run uClinux,
33 * have only the timers in one TC block... they currently don't support
34 * the tclib code, because of that initialization issue.)
35 *
36 * REVISIT behavior during system suspend states... we should disable
37 * all clocks and save the power. Easily done for clockevent devices,
38 * but clocksources won't necessarily get the needed notifications.
39 * For deeper system sleep states, this will be mandatory...
40 */
41
42 static void __iomem *tcaddr;
43
44 static cycle_t tc_get_cycles(struct clocksource *cs)
45 {
46 unsigned long flags;
47 u32 lower, upper;
48
49 raw_local_irq_save(flags);
50 do {
51 upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
52 lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
53 } while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
54
55 raw_local_irq_restore(flags);
56 return (upper << 16) | lower;
57 }
58
59 static cycle_t tc_get_cycles32(struct clocksource *cs)
60 {
61 return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
62 }
63
64 static struct clocksource clksrc = {
65 .name = "tcb_clksrc",
66 .rating = 200,
67 .read = tc_get_cycles,
68 .mask = CLOCKSOURCE_MASK(32),
69 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
70 };
71
72 #ifdef CONFIG_GENERIC_CLOCKEVENTS
73
74 struct tc_clkevt_device {
75 struct clock_event_device clkevt;
76 struct clk *clk;
77 void __iomem *regs;
78 };
79
80 static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt)
81 {
82 return container_of(clkevt, struct tc_clkevt_device, clkevt);
83 }
84
85 /* For now, we always use the 32K clock ... this optimizes for NO_HZ,
86 * because using one of the divided clocks would usually mean the
87 * tick rate can never be less than several dozen Hz (vs 0.5 Hz).
88 *
89 * A divided clock could be good for high resolution timers, since
90 * 30.5 usec resolution can seem "low".
91 */
92 static u32 timer_clock;
93
94 static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
95 {
96 struct tc_clkevt_device *tcd = to_tc_clkevt(d);
97 void __iomem *regs = tcd->regs;
98
99 if (tcd->clkevt.mode == CLOCK_EVT_MODE_PERIODIC
100 || tcd->clkevt.mode == CLOCK_EVT_MODE_ONESHOT) {
101 __raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
102 __raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
103 clk_disable(tcd->clk);
104 }
105
106 switch (m) {
107
108 /* By not making the gentime core emulate periodic mode on top
109 * of oneshot, we get lower overhead and improved accuracy.
110 */
111 case CLOCK_EVT_MODE_PERIODIC:
112 clk_enable(tcd->clk);
113
114 /* slow clock, count up to RC, then irq and restart */
115 __raw_writel(timer_clock
116 | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
117 regs + ATMEL_TC_REG(2, CMR));
118 __raw_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
119
120 /* Enable clock and interrupts on RC compare */
121 __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
122
123 /* go go gadget! */
124 __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
125 regs + ATMEL_TC_REG(2, CCR));
126 break;
127
128 case CLOCK_EVT_MODE_ONESHOT:
129 clk_enable(tcd->clk);
130
131 /* slow clock, count up to RC, then irq and stop */
132 __raw_writel(timer_clock | ATMEL_TC_CPCSTOP
133 | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
134 regs + ATMEL_TC_REG(2, CMR));
135 __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
136
137 /* set_next_event() configures and starts the timer */
138 break;
139
140 default:
141 break;
142 }
143 }
144
145 static int tc_next_event(unsigned long delta, struct clock_event_device *d)
146 {
147 __raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
148
149 /* go go gadget! */
150 __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
151 tcaddr + ATMEL_TC_REG(2, CCR));
152 return 0;
153 }
154
155 static struct tc_clkevt_device clkevt = {
156 .clkevt = {
157 .name = "tc_clkevt",
158 .features = CLOCK_EVT_FEAT_PERIODIC
159 | CLOCK_EVT_FEAT_ONESHOT,
160 /* Should be lower than at91rm9200's system timer */
161 .rating = 125,
162 .set_next_event = tc_next_event,
163 .set_mode = tc_mode,
164 },
165 };
166
167 static irqreturn_t ch2_irq(int irq, void *handle)
168 {
169 struct tc_clkevt_device *dev = handle;
170 unsigned int sr;
171
172 sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
173 if (sr & ATMEL_TC_CPCS) {
174 dev->clkevt.event_handler(&dev->clkevt);
175 return IRQ_HANDLED;
176 }
177
178 return IRQ_NONE;
179 }
180
181 static struct irqaction tc_irqaction = {
182 .name = "tc_clkevt",
183 .flags = IRQF_TIMER,
184 .handler = ch2_irq,
185 };
186
187 static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
188 {
189 int ret;
190 struct clk *t2_clk = tc->clk[2];
191 int irq = tc->irq[2];
192
193 /* try to enable t2 clk to avoid future errors in mode change */
194 ret = clk_prepare_enable(t2_clk);
195 if (ret)
196 return ret;
197 clk_disable(t2_clk);
198
199 clkevt.regs = tc->regs;
200 clkevt.clk = t2_clk;
201 tc_irqaction.dev_id = &clkevt;
202
203 timer_clock = clk32k_divisor_idx;
204
205 clkevt.clkevt.cpumask = cpumask_of(0);
206
207 ret = setup_irq(irq, &tc_irqaction);
208 if (ret)
209 return ret;
210
211 clockevents_config_and_register(&clkevt.clkevt, 32768, 1, 0xffff);
212
213 return ret;
214 }
215
216 #else /* !CONFIG_GENERIC_CLOCKEVENTS */
217
218 static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
219 {
220 /* NOTHING */
221 return 0;
222 }
223
224 #endif
225
226 static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
227 {
228 /* channel 0: waveform mode, input mclk/8, clock TIOA0 on overflow */
229 __raw_writel(mck_divisor_idx /* likely divide-by-8 */
230 | ATMEL_TC_WAVE
231 | ATMEL_TC_WAVESEL_UP /* free-run */
232 | ATMEL_TC_ACPA_SET /* TIOA0 rises at 0 */
233 | ATMEL_TC_ACPC_CLEAR, /* (duty cycle 50%) */
234 tcaddr + ATMEL_TC_REG(0, CMR));
235 __raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
236 __raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
237 __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
238 __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
239
240 /* channel 1: waveform mode, input TIOA0 */
241 __raw_writel(ATMEL_TC_XC1 /* input: TIOA0 */
242 | ATMEL_TC_WAVE
243 | ATMEL_TC_WAVESEL_UP, /* free-run */
244 tcaddr + ATMEL_TC_REG(1, CMR));
245 __raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR)); /* no irqs */
246 __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
247
248 /* chain channel 0 to channel 1*/
249 __raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
250 /* then reset all the timers */
251 __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
252 }
253
254 static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
255 {
256 /* channel 0: waveform mode, input mclk/8 */
257 __raw_writel(mck_divisor_idx /* likely divide-by-8 */
258 | ATMEL_TC_WAVE
259 | ATMEL_TC_WAVESEL_UP, /* free-run */
260 tcaddr + ATMEL_TC_REG(0, CMR));
261 __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
262 __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
263
264 /* then reset all the timers */
265 __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
266 }
267
268 static int __init tcb_clksrc_init(void)
269 {
270 static char bootinfo[] __initdata
271 = KERN_DEBUG "%s: tc%d at %d.%03d MHz\n";
272
273 struct platform_device *pdev;
274 struct atmel_tc *tc;
275 struct clk *t0_clk;
276 u32 rate, divided_rate = 0;
277 int best_divisor_idx = -1;
278 int clk32k_divisor_idx = -1;
279 int i;
280 int ret;
281
282 tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK, clksrc.name);
283 if (!tc) {
284 pr_debug("can't alloc TC for clocksource\n");
285 return -ENODEV;
286 }
287 tcaddr = tc->regs;
288 pdev = tc->pdev;
289
290 t0_clk = tc->clk[0];
291 ret = clk_prepare_enable(t0_clk);
292 if (ret) {
293 pr_debug("can't enable T0 clk\n");
294 goto err_free_tc;
295 }
296
297 /* How fast will we be counting? Pick something over 5 MHz. */
298 rate = (u32) clk_get_rate(t0_clk);
299 for (i = 0; i < 5; i++) {
300 unsigned divisor = atmel_tc_divisors[i];
301 unsigned tmp;
302
303 /* remember 32 KiHz clock for later */
304 if (!divisor) {
305 clk32k_divisor_idx = i;
306 continue;
307 }
308
309 tmp = rate / divisor;
310 pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
311 if (best_divisor_idx > 0) {
312 if (tmp < 5 * 1000 * 1000)
313 continue;
314 }
315 divided_rate = tmp;
316 best_divisor_idx = i;
317 }
318
319
320 printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
321 divided_rate / 1000000,
322 ((divided_rate + 500000) % 1000000) / 1000);
323
324 if (tc->tcb_config && tc->tcb_config->counter_width == 32) {
325 /* use apropriate function to read 32 bit counter */
326 clksrc.read = tc_get_cycles32;
327 /* setup ony channel 0 */
328 tcb_setup_single_chan(tc, best_divisor_idx);
329 } else {
330 /* tclib will give us three clocks no matter what the
331 * underlying platform supports.
332 */
333 ret = clk_prepare_enable(tc->clk[1]);
334 if (ret) {
335 pr_debug("can't enable T1 clk\n");
336 goto err_disable_t0;
337 }
338 /* setup both channel 0 & 1 */
339 tcb_setup_dual_chan(tc, best_divisor_idx);
340 }
341
342 /* and away we go! */
343 ret = clocksource_register_hz(&clksrc, divided_rate);
344 if (ret)
345 goto err_disable_t1;
346
347 /* channel 2: periodic and oneshot timer support */
348 ret = setup_clkevents(tc, clk32k_divisor_idx);
349 if (ret)
350 goto err_unregister_clksrc;
351
352 return 0;
353
354 err_unregister_clksrc:
355 clocksource_unregister(&clksrc);
356
357 err_disable_t1:
358 if (!tc->tcb_config || tc->tcb_config->counter_width != 32)
359 clk_disable_unprepare(tc->clk[1]);
360
361 err_disable_t0:
362 clk_disable_unprepare(t0_clk);
363
364 err_free_tc:
365 atmel_tc_free(tc);
366 return ret;
367 }
368 arch_initcall(tcb_clksrc_init);