drivers/clocksource/timer-atlas7.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * System timer for CSR SiRFprimaII
   4  *
   5  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/clockchips.h>
  11 #include <linux/clocksource.h>
  12 #include <linux/cpu.h>
  13 #include <linux/bitops.h>
  14 #include <linux/irq.h>
  15 #include <linux/clk.h>
  16 #include <linux/slab.h>
  17 #include <linux/of.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/of_address.h>
  20 #include <linux/sched_clock.h>
  21
  22 #define SIRFSOC_TIMER_32COUNTER_0_CTRL                  0x0000
  23 #define SIRFSOC_TIMER_32COUNTER_1_CTRL                  0x0004
  24 #define SIRFSOC_TIMER_MATCH_0                           0x0018
  25 #define SIRFSOC_TIMER_MATCH_1                           0x001c
  26 #define SIRFSOC_TIMER_COUNTER_0                         0x0048
  27 #define SIRFSOC_TIMER_COUNTER_1                         0x004c
  28 #define SIRFSOC_TIMER_INTR_STATUS                       0x0060
  29 #define SIRFSOC_TIMER_WATCHDOG_EN                       0x0064
  30 #define SIRFSOC_TIMER_64COUNTER_CTRL                    0x0068
  31 #define SIRFSOC_TIMER_64COUNTER_LO                      0x006c
  32 #define SIRFSOC_TIMER_64COUNTER_HI                      0x0070
  33 #define SIRFSOC_TIMER_64COUNTER_LOAD_LO                 0x0074
  34 #define SIRFSOC_TIMER_64COUNTER_LOAD_HI                 0x0078
  35 #define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO             0x007c
  36 #define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI             0x0080
  37
  38 #define SIRFSOC_TIMER_REG_CNT 6
  39
  40 static unsigned long atlas7_timer_rate;
  41
  42 static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
  43         SIRFSOC_TIMER_WATCHDOG_EN,
  44         SIRFSOC_TIMER_32COUNTER_0_CTRL,
  45         SIRFSOC_TIMER_32COUNTER_1_CTRL,
  46         SIRFSOC_TIMER_64COUNTER_CTRL,
  47         SIRFSOC_TIMER_64COUNTER_RLATCHED_LO,
  48         SIRFSOC_TIMER_64COUNTER_RLATCHED_HI,
  49 };
  50
  51 static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
  52
  53 static void __iomem *sirfsoc_timer_base;
  54
  55 /* disable count and interrupt */
  56 static inline void sirfsoc_timer_count_disable(int idx)
  57 {
  58         writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,
  59                 sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
  60 }
  61
  62 /* enable count and interrupt */
  63 static inline void sirfsoc_timer_count_enable(int idx)
  64 {
  65         writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3,
  66                 sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
  67 }
  68
  69 /* timer interrupt handler */
  70 static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
  71 {
  72         struct clock_event_device *ce = dev_id;
  73         int cpu = smp_processor_id();
  74
  75         /* clear timer interrupt */
  76         writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
  77
  78         if (clockevent_state_oneshot(ce))
  79                 sirfsoc_timer_count_disable(cpu);
  80
  81         ce->event_handler(ce);
  82
  83         return IRQ_HANDLED;
  84 }
  85
  86 /* read 64-bit timer counter */
  87 static u64 sirfsoc_timer_read(struct clocksource *cs)
  88 {
  89         u64 cycles;
  90
  91         writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
  92                         BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
  93
  94         cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);
  95         cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);
  96
  97         return cycles;
  98 }
  99
 100 static int sirfsoc_timer_set_next_event(unsigned long delta,
 101         struct clock_event_device *ce)
 102 {
 103         int cpu = smp_processor_id();
 104
 105         /* disable timer first, then modify the related registers */
 106         sirfsoc_timer_count_disable(cpu);
 107
 108         writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
 109                 4 * cpu);
 110         writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +
 111                 4 * cpu);
 112
 113         /* enable the tick */
 114         sirfsoc_timer_count_enable(cpu);
 115
 116         return 0;
 117 }
 118
 119 /* Oneshot is enabled in set_next_event */
 120 static int sirfsoc_timer_shutdown(struct clock_event_device *evt)
 121 {
 122         sirfsoc_timer_count_disable(smp_processor_id());
 123         return 0;
 124 }
 125
 126 static void sirfsoc_clocksource_suspend(struct clocksource *cs)
 127 {
 128         int i;
 129
 130         for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
 131                 sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
 132 }
 133
 134 static void sirfsoc_clocksource_resume(struct clocksource *cs)
 135 {
 136         int i;
 137
 138         for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
 139                 writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
 140
 141         writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
 142                 sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
 143         writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
 144                 sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
 145
 146         writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
 147                 BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
 148 }
 149
 150 static struct clock_event_device __percpu *sirfsoc_clockevent;
 151
 152 static struct clocksource sirfsoc_clocksource = {
 153         .name = "sirfsoc_clocksource",
 154         .rating = 200,
 155         .mask = CLOCKSOURCE_MASK(64),
 156         .flags = CLOCK_SOURCE_IS_CONTINUOUS,
 157         .read = sirfsoc_timer_read,
 158         .suspend = sirfsoc_clocksource_suspend,
 159         .resume = sirfsoc_clocksource_resume,
 160 };
 161
 162 static struct irqaction sirfsoc_timer_irq = {
 163         .name = "sirfsoc_timer0",
 164         .flags = IRQF_TIMER | IRQF_NOBALANCING,
 165         .handler = sirfsoc_timer_interrupt,
 166 };
 167
 168 static struct irqaction sirfsoc_timer1_irq = {
 169         .name = "sirfsoc_timer1",
 170         .flags = IRQF_TIMER | IRQF_NOBALANCING,
 171         .handler = sirfsoc_timer_interrupt,
 172 };
 173
 174 static int sirfsoc_local_timer_starting_cpu(unsigned int cpu)
 175 {
 176         struct clock_event_device *ce = per_cpu_ptr(sirfsoc_clockevent, cpu);
 177         struct irqaction *action;
 178
 179         if (cpu == 0)
 180                 action = &sirfsoc_timer_irq;
 181         else
 182                 action = &sirfsoc_timer1_irq;
 183
 184         ce->irq = action->irq;
 185         ce->name = "local_timer";
 186         ce->features = CLOCK_EVT_FEAT_ONESHOT;
 187         ce->rating = 200;
 188         ce->set_state_shutdown = sirfsoc_timer_shutdown;
 189         ce->set_state_oneshot = sirfsoc_timer_shutdown;
 190         ce->tick_resume = sirfsoc_timer_shutdown;
 191         ce->set_next_event = sirfsoc_timer_set_next_event;
 192         clockevents_calc_mult_shift(ce, atlas7_timer_rate, 60);
 193         ce->max_delta_ns = clockevent_delta2ns(-2, ce);
 194         ce->max_delta_ticks = (unsigned long)-2;
 195         ce->min_delta_ns = clockevent_delta2ns(2, ce);
 196         ce->min_delta_ticks = 2;
 197         ce->cpumask = cpumask_of(cpu);
 198
 199         action->dev_id = ce;
 200         BUG_ON(setup_irq(ce->irq, action));
 201         irq_force_affinity(action->irq, cpumask_of(cpu));
 202
 203         clockevents_register_device(ce);
 204         return 0;
 205 }
 206
 207 static int sirfsoc_local_timer_dying_cpu(unsigned int cpu)
 208 {
 209         sirfsoc_timer_count_disable(1);
 210
 211         if (cpu == 0)
 212                 remove_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq);
 213         else
 214                 remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq);
 215         return 0;
 216 }
 217
 218 static int __init sirfsoc_clockevent_init(void)
 219 {
 220         sirfsoc_clockevent = alloc_percpu(struct clock_event_device);
 221         BUG_ON(!sirfsoc_clockevent);
 222
 223         /* Install and invoke hotplug callbacks */
 224         return cpuhp_setup_state(CPUHP_AP_MARCO_TIMER_STARTING,
 225                                  "clockevents/marco:starting",
 226                                  sirfsoc_local_timer_starting_cpu,
 227                                  sirfsoc_local_timer_dying_cpu);
 228 }
 229
 230 /* initialize the kernel jiffy timer source */
 231 static int __init sirfsoc_atlas7_timer_init(struct device_node *np)
 232 {
 233         struct clk *clk;
 234
 235         clk = of_clk_get(np, 0);
 236         BUG_ON(IS_ERR(clk));
 237
 238         BUG_ON(clk_prepare_enable(clk));
 239
 240         atlas7_timer_rate = clk_get_rate(clk);
 241
 242         /* timer dividers: 0, not divided */
 243         writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
 244         writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
 245         writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);
 246
 247         /* Initialize timer counters to 0 */
 248         writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
 249         writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
 250         writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
 251                 BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
 252         writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
 253         writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);
 254
 255         /* Clear all interrupts */
 256         writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
 257
 258         BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, atlas7_timer_rate));
 259
 260         return sirfsoc_clockevent_init();
 261 }
 262
 263 static int __init sirfsoc_of_timer_init(struct device_node *np)
 264 {
 265         sirfsoc_timer_base = of_iomap(np, 0);
 266         if (!sirfsoc_timer_base) {
 267                 pr_err("unable to map timer cpu registers\n");
 268                 return -ENXIO;
 269         }
 270
 271         sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
 272         if (!sirfsoc_timer_irq.irq) {
 273                 pr_err("No irq passed for timer0 via DT\n");
 274                 return -EINVAL;
 275         }
 276
 277         sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1);
 278         if (!sirfsoc_timer1_irq.irq) {
 279                 pr_err("No irq passed for timer1 via DT\n");
 280                 return -EINVAL;
 281         }
 282
 283         return sirfsoc_atlas7_timer_init(np);
 284 }
 285 TIMER_OF_DECLARE(sirfsoc_atlas7_timer, "sirf,atlas7-tick", sirfsoc_of_timer_init);