drivers/clocksource/timer-riscv.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2012 Regents of the University of California
   4  * Copyright (C) 2017 SiFive
   5  *
   6  * All RISC-V systems have a timer attached to every hart.  These timers can
   7  * either be read from the "time" and "timeh" CSRs, and can use the SBI to
   8  * setup events, or directly accessed using MMIO registers.
   9  */
  10 #include <linux/clocksource.h>
  11 #include <linux/clockchips.h>
  12 #include <linux/cpu.h>
  13 #include <linux/delay.h>
  14 #include <linux/irq.h>
  15 #include <linux/irqdomain.h>
  16 #include <linux/sched_clock.h>
  17 #include <linux/io-64-nonatomic-lo-hi.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/of_irq.h>
  20 #include <asm/smp.h>
  21 #include <asm/sbi.h>
  22 #include <asm/timex.h>
  23
  24 static int riscv_clock_next_event(unsigned long delta,
  25                 struct clock_event_device *ce)
  26 {
  27         csr_set(CSR_IE, IE_TIE);
  28         sbi_set_timer(get_cycles64() + delta);
  29         return 0;
  30 }
  31
  32 static unsigned int riscv_clock_event_irq;
  33 static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
  34         .name                   = "riscv_timer_clockevent",
  35         .features               = CLOCK_EVT_FEAT_ONESHOT,
  36         .rating                 = 100,
  37         .set_next_event         = riscv_clock_next_event,
  38 };
  39
  40 /*
  41  * It is guaranteed that all the timers across all the harts are synchronized
  42  * within one tick of each other, so while this could technically go
  43  * backwards when hopping between CPUs, practically it won't happen.
  44  */
  45 static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
  46 {
  47         return get_cycles64();
  48 }
  49
  50 static u64 notrace riscv_sched_clock(void)
  51 {
  52         return get_cycles64();
  53 }
  54
  55 static struct clocksource riscv_clocksource = {
  56         .name           = "riscv_clocksource",
  57         .rating         = 300,
  58         .mask           = CLOCKSOURCE_MASK(64),
  59         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  60         .read           = riscv_clocksource_rdtime,
  61 };
  62
  63 static int riscv_timer_starting_cpu(unsigned int cpu)
  64 {
  65         struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
  66
  67         ce->cpumask = cpumask_of(cpu);
  68         ce->irq = riscv_clock_event_irq;
  69         clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
  70
  71         enable_percpu_irq(riscv_clock_event_irq,
  72                           irq_get_trigger_type(riscv_clock_event_irq));
  73         return 0;
  74 }
  75
  76 static int riscv_timer_dying_cpu(unsigned int cpu)
  77 {
  78         disable_percpu_irq(riscv_clock_event_irq);
  79         return 0;
  80 }
  81
  82 /* called directly from the low-level interrupt handler */
  83 static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
  84 {
  85         struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);
  86
  87         csr_clear(CSR_IE, IE_TIE);
  88         evdev->event_handler(evdev);
  89
  90         return IRQ_HANDLED;
  91 }
  92
  93 static int __init riscv_timer_init_dt(struct device_node *n)
  94 {
  95         int cpuid, hartid, error;
  96         struct device_node *child;
  97         struct irq_domain *domain;
  98
  99         hartid = riscv_of_processor_hartid(n);
 100         if (hartid < 0) {
 101                 pr_warn("Not valid hartid for node [%pOF] error = [%d]\n",
 102                         n, hartid);
 103                 return hartid;
 104         }
 105
 106         cpuid = riscv_hartid_to_cpuid(hartid);
 107         if (cpuid < 0) {
 108                 pr_warn("Invalid cpuid for hartid [%d]\n", hartid);
 109                 return cpuid;
 110         }
 111
 112         if (cpuid != smp_processor_id())
 113                 return 0;
 114
 115         domain = NULL;
 116         child = of_get_compatible_child(n, "riscv,cpu-intc");
 117         if (!child) {
 118                 pr_err("Failed to find INTC node [%pOF]\n", n);
 119                 return -ENODEV;
 120         }
 121         domain = irq_find_host(child);
 122         of_node_put(child);
 123         if (!domain) {
 124                 pr_err("Failed to find IRQ domain for node [%pOF]\n", n);
 125                 return -ENODEV;
 126         }
 127
 128         riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
 129         if (!riscv_clock_event_irq) {
 130                 pr_err("Failed to map timer interrupt for node [%pOF]\n", n);
 131                 return -ENODEV;
 132         }
 133
 134         pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n",
 135                __func__, cpuid, hartid);
 136         error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
 137         if (error) {
 138                 pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
 139                        error, cpuid);
 140                 return error;
 141         }
 142
 143         sched_clock_register(riscv_sched_clock, 64, riscv_timebase);
 144
 145         error = request_percpu_irq(riscv_clock_event_irq,
 146                                     riscv_timer_interrupt,
 147                                     "riscv-timer", &riscv_clock_event);
 148         if (error) {
 149                 pr_err("registering percpu irq failed [%d]\n", error);
 150                 return error;
 151         }
 152
 153         error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
 154                          "clockevents/riscv/timer:starting",
 155                          riscv_timer_starting_cpu, riscv_timer_dying_cpu);
 156         if (error)
 157                 pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
 158                        error);
 159         return error;
 160 }
 161
 162 TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);