drivers/cpufreq/imx6q-cpufreq.c

   1 /*
   2  * Copyright (C) 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/cpu.h>
  11 #include <linux/cpufreq.h>
  12 #include <linux/err.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/pm_opp.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/regulator/consumer.h>
  18
  19 #define PU_SOC_VOLTAGE_NORMAL   1250000
  20 #define PU_SOC_VOLTAGE_HIGH     1275000
  21 #define FREQ_1P2_GHZ            1200000000
  22
  23 static struct regulator *arm_reg;
  24 static struct regulator *pu_reg;
  25 static struct regulator *soc_reg;
  26
  27 static struct clk *arm_clk;
  28 static struct clk *pll1_sys_clk;
  29 static struct clk *pll1_sw_clk;
  30 static struct clk *step_clk;
  31 static struct clk *pll2_pfd2_396m_clk;
  32
  33 /* clk used by i.MX6UL */
  34 static struct clk *pll2_bus_clk;
  35 static struct clk *secondary_sel_clk;
  36
  37 static struct device *cpu_dev;
  38 static bool free_opp;
  39 static struct cpufreq_frequency_table *freq_table;
  40 static unsigned int transition_latency;
  41
  42 static u32 *imx6_soc_volt;
  43 static u32 soc_opp_count;
  44
  45 static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
  46 {
  47         struct dev_pm_opp *opp;
  48         unsigned long freq_hz, volt, volt_old;
  49         unsigned int old_freq, new_freq;
  50         bool pll1_sys_temp_enabled = false;
  51         int ret;
  52
  53         new_freq = freq_table[index].frequency;
  54         freq_hz = new_freq * 1000;
  55         old_freq = clk_get_rate(arm_clk) / 1000;
  56
  57         opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
  58         if (IS_ERR(opp)) {
  59                 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
  60                 return PTR_ERR(opp);
  61         }
  62
  63         volt = dev_pm_opp_get_voltage(opp);
  64         dev_pm_opp_put(opp);
  65
  66         volt_old = regulator_get_voltage(arm_reg);
  67
  68         dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
  69                 old_freq / 1000, volt_old / 1000,
  70                 new_freq / 1000, volt / 1000);
  71
  72         /* scaling up?  scale voltage before frequency */
  73         if (new_freq > old_freq) {
  74                 if (!IS_ERR(pu_reg)) {
  75                         ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
  76                         if (ret) {
  77                                 dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
  78                                 return ret;
  79                         }
  80                 }
  81                 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
  82                 if (ret) {
  83                         dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
  84                         return ret;
  85                 }
  86                 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
  87                 if (ret) {
  88                         dev_err(cpu_dev,
  89                                 "failed to scale vddarm up: %d\n", ret);
  90                         return ret;
  91                 }
  92         }
  93
  94         /*
  95          * The setpoints are selected per PLL/PDF frequencies, so we need to
  96          * reprogram PLL for frequency scaling.  The procedure of reprogramming
  97          * PLL1 is as below.
  98          * For i.MX6UL, it has a secondary clk mux, the cpu frequency change
  99          * flow is slightly different from other i.MX6 OSC.
 100          * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
 101          *  - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
 102          *  - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
 103          *  - Disable pll2_pfd2_396m_clk
 104          */
 105         if (of_machine_is_compatible("fsl,imx6ul") ||
 106             of_machine_is_compatible("fsl,imx6ull")) {
 107                 /*
 108                  * When changing pll1_sw_clk's parent to pll1_sys_clk,
 109                  * CPU may run at higher than 528MHz, this will lead to
 110                  * the system unstable if the voltage is lower than the
 111                  * voltage of 528MHz, so lower the CPU frequency to one
 112                  * half before changing CPU frequency.
 113                  */
 114                 clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
 115                 clk_set_parent(pll1_sw_clk, pll1_sys_clk);
 116                 if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
 117                         clk_set_parent(secondary_sel_clk, pll2_bus_clk);
 118                 else
 119                         clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
 120                 clk_set_parent(step_clk, secondary_sel_clk);
 121                 clk_set_parent(pll1_sw_clk, step_clk);
 122         } else {
 123                 clk_set_parent(step_clk, pll2_pfd2_396m_clk);
 124                 clk_set_parent(pll1_sw_clk, step_clk);
 125                 if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
 126                         clk_set_rate(pll1_sys_clk, new_freq * 1000);
 127                         clk_set_parent(pll1_sw_clk, pll1_sys_clk);
 128                 } else {
 129                         /* pll1_sys needs to be enabled for divider rate change to work. */
 130                         pll1_sys_temp_enabled = true;
 131                         clk_prepare_enable(pll1_sys_clk);
 132                 }
 133         }
 134
 135         /* Ensure the arm clock divider is what we expect */
 136         ret = clk_set_rate(arm_clk, new_freq * 1000);
 137         if (ret) {
 138                 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
 139                 regulator_set_voltage_tol(arm_reg, volt_old, 0);
 140                 return ret;
 141         }
 142
 143         /* PLL1 is only needed until after ARM-PODF is set. */
 144         if (pll1_sys_temp_enabled)
 145                 clk_disable_unprepare(pll1_sys_clk);
 146
 147         /* scaling down?  scale voltage after frequency */
 148         if (new_freq < old_freq) {
 149                 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
 150                 if (ret) {
 151                         dev_warn(cpu_dev,
 152                                  "failed to scale vddarm down: %d\n", ret);
 153                         ret = 0;
 154                 }
 155                 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
 156                 if (ret) {
 157                         dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
 158                         ret = 0;
 159                 }
 160                 if (!IS_ERR(pu_reg)) {
 161                         ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
 162                         if (ret) {
 163                                 dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
 164                                 ret = 0;
 165                         }
 166                 }
 167         }
 168
 169         return 0;
 170 }
 171
 172 static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
 173 {
 174         int ret;
 175
 176         policy->clk = arm_clk;
 177         ret = cpufreq_generic_init(policy, freq_table, transition_latency);
 178         policy->suspend_freq = policy->max;
 179
 180         return ret;
 181 }
 182
 183 static struct cpufreq_driver imx6q_cpufreq_driver = {
 184         .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
 185         .verify = cpufreq_generic_frequency_table_verify,
 186         .target_index = imx6q_set_target,
 187         .get = cpufreq_generic_get,
 188         .init = imx6q_cpufreq_init,
 189         .name = "imx6q-cpufreq",
 190         .attr = cpufreq_generic_attr,
 191         .suspend = cpufreq_generic_suspend,
 192 };
 193
 194 static int imx6q_cpufreq_probe(struct platform_device *pdev)
 195 {
 196         struct device_node *np;
 197         struct dev_pm_opp *opp;
 198         unsigned long min_volt, max_volt;
 199         int num, ret;
 200         const struct property *prop;
 201         const __be32 *val;
 202         u32 nr, i, j;
 203
 204         cpu_dev = get_cpu_device(0);
 205         if (!cpu_dev) {
 206                 pr_err("failed to get cpu0 device\n");
 207                 return -ENODEV;
 208         }
 209
 210         np = of_node_get(cpu_dev->of_node);
 211         if (!np) {
 212                 dev_err(cpu_dev, "failed to find cpu0 node\n");
 213                 return -ENOENT;
 214         }
 215
 216         arm_clk = clk_get(cpu_dev, "arm");
 217         pll1_sys_clk = clk_get(cpu_dev, "pll1_sys");
 218         pll1_sw_clk = clk_get(cpu_dev, "pll1_sw");
 219         step_clk = clk_get(cpu_dev, "step");
 220         pll2_pfd2_396m_clk = clk_get(cpu_dev, "pll2_pfd2_396m");
 221         if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
 222             IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
 223                 dev_err(cpu_dev, "failed to get clocks\n");
 224                 ret = -ENOENT;
 225                 goto put_clk;
 226         }
 227
 228         if (of_machine_is_compatible("fsl,imx6ul") ||
 229             of_machine_is_compatible("fsl,imx6ull")) {
 230                 pll2_bus_clk = clk_get(cpu_dev, "pll2_bus");
 231                 secondary_sel_clk = clk_get(cpu_dev, "secondary_sel");
 232                 if (IS_ERR(pll2_bus_clk) || IS_ERR(secondary_sel_clk)) {
 233                         dev_err(cpu_dev, "failed to get clocks specific to imx6ul\n");
 234                         ret = -ENOENT;
 235                         goto put_clk;
 236                 }
 237         }
 238
 239         arm_reg = regulator_get(cpu_dev, "arm");
 240         pu_reg = regulator_get_optional(cpu_dev, "pu");
 241         soc_reg = regulator_get(cpu_dev, "soc");
 242         if (PTR_ERR(arm_reg) == -EPROBE_DEFER ||
 243                         PTR_ERR(soc_reg) == -EPROBE_DEFER ||
 244                         PTR_ERR(pu_reg) == -EPROBE_DEFER) {
 245                 ret = -EPROBE_DEFER;
 246                 dev_dbg(cpu_dev, "regulators not ready, defer\n");
 247                 goto put_reg;
 248         }
 249         if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) {
 250                 dev_err(cpu_dev, "failed to get regulators\n");
 251                 ret = -ENOENT;
 252                 goto put_reg;
 253         }
 254
 255         /*
 256          * We expect an OPP table supplied by platform.
 257          * Just, incase the platform did not supply the OPP
 258          * table, it will try to get it.
 259          */
 260         num = dev_pm_opp_get_opp_count(cpu_dev);
 261         if (num < 0) {
 262                 ret = dev_pm_opp_of_add_table(cpu_dev);
 263                 if (ret < 0) {
 264                         dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
 265                         goto put_reg;
 266                 }
 267
 268                 /* Because we have added the OPPs here, we must free them */
 269                 free_opp = true;
 270
 271                 num = dev_pm_opp_get_opp_count(cpu_dev);
 272                 if (num < 0) {
 273                         ret = num;
 274                         dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
 275                         goto out_free_opp;
 276                 }
 277         }
 278
 279         ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
 280         if (ret) {
 281                 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
 282                 goto out_free_opp;
 283         }
 284
 285         /* Make imx6_soc_volt array's size same as arm opp number */
 286         imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(*imx6_soc_volt) * num, GFP_KERNEL);
 287         if (imx6_soc_volt == NULL) {
 288                 ret = -ENOMEM;
 289                 goto free_freq_table;
 290         }
 291
 292         prop = of_find_property(np, "fsl,soc-operating-points", NULL);
 293         if (!prop || !prop->value)
 294                 goto soc_opp_out;
 295
 296         /*
 297          * Each OPP is a set of tuples consisting of frequency and
 298          * voltage like <freq-kHz vol-uV>.
 299          */
 300         nr = prop->length / sizeof(u32);
 301         if (nr % 2 || (nr / 2) < num)
 302                 goto soc_opp_out;
 303
 304         for (j = 0; j < num; j++) {
 305                 val = prop->value;
 306                 for (i = 0; i < nr / 2; i++) {
 307                         unsigned long freq = be32_to_cpup(val++);
 308                         unsigned long volt = be32_to_cpup(val++);
 309                         if (freq_table[j].frequency == freq) {
 310                                 imx6_soc_volt[soc_opp_count++] = volt;
 311                                 break;
 312                         }
 313                 }
 314         }
 315
 316 soc_opp_out:
 317         /* use fixed soc opp volt if no valid soc opp info found in dtb */
 318         if (soc_opp_count != num) {
 319                 dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
 320                 for (j = 0; j < num; j++)
 321                         imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
 322                 if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
 323                         imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
 324         }
 325
 326         if (of_property_read_u32(np, "clock-latency", &transition_latency))
 327                 transition_latency = CPUFREQ_ETERNAL;
 328
 329         /*
 330          * Calculate the ramp time for max voltage change in the
 331          * VDDSOC and VDDPU regulators.
 332          */
 333         ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
 334         if (ret > 0)
 335                 transition_latency += ret * 1000;
 336         if (!IS_ERR(pu_reg)) {
 337                 ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
 338                 if (ret > 0)
 339                         transition_latency += ret * 1000;
 340         }
 341
 342         /*
 343          * OPP is maintained in order of increasing frequency, and
 344          * freq_table initialised from OPP is therefore sorted in the
 345          * same order.
 346          */
 347         opp = dev_pm_opp_find_freq_exact(cpu_dev,
 348                                   freq_table[0].frequency * 1000, true);
 349         min_volt = dev_pm_opp_get_voltage(opp);
 350         dev_pm_opp_put(opp);
 351         opp = dev_pm_opp_find_freq_exact(cpu_dev,
 352                                   freq_table[--num].frequency * 1000, true);
 353         max_volt = dev_pm_opp_get_voltage(opp);
 354         dev_pm_opp_put(opp);
 355
 356         ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
 357         if (ret > 0)
 358                 transition_latency += ret * 1000;
 359
 360         ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
 361         if (ret) {
 362                 dev_err(cpu_dev, "failed register driver: %d\n", ret);
 363                 goto free_freq_table;
 364         }
 365
 366         of_node_put(np);
 367         return 0;
 368
 369 free_freq_table:
 370         dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
 371 out_free_opp:
 372         if (free_opp)
 373                 dev_pm_opp_of_remove_table(cpu_dev);
 374 put_reg:
 375         if (!IS_ERR(arm_reg))
 376                 regulator_put(arm_reg);
 377         if (!IS_ERR(pu_reg))
 378                 regulator_put(pu_reg);
 379         if (!IS_ERR(soc_reg))
 380                 regulator_put(soc_reg);
 381 put_clk:
 382         if (!IS_ERR(arm_clk))
 383                 clk_put(arm_clk);
 384         if (!IS_ERR(pll1_sys_clk))
 385                 clk_put(pll1_sys_clk);
 386         if (!IS_ERR(pll1_sw_clk))
 387                 clk_put(pll1_sw_clk);
 388         if (!IS_ERR(step_clk))
 389                 clk_put(step_clk);
 390         if (!IS_ERR(pll2_pfd2_396m_clk))
 391                 clk_put(pll2_pfd2_396m_clk);
 392         if (!IS_ERR(pll2_bus_clk))
 393                 clk_put(pll2_bus_clk);
 394         if (!IS_ERR(secondary_sel_clk))
 395                 clk_put(secondary_sel_clk);
 396         of_node_put(np);
 397         return ret;
 398 }
 399
 400 static int imx6q_cpufreq_remove(struct platform_device *pdev)
 401 {
 402         cpufreq_unregister_driver(&imx6q_cpufreq_driver);
 403         dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
 404         if (free_opp)
 405                 dev_pm_opp_of_remove_table(cpu_dev);
 406         regulator_put(arm_reg);
 407         if (!IS_ERR(pu_reg))
 408                 regulator_put(pu_reg);
 409         regulator_put(soc_reg);
 410         clk_put(arm_clk);
 411         clk_put(pll1_sys_clk);
 412         clk_put(pll1_sw_clk);
 413         clk_put(step_clk);
 414         clk_put(pll2_pfd2_396m_clk);
 415         clk_put(pll2_bus_clk);
 416         clk_put(secondary_sel_clk);
 417
 418         return 0;
 419 }
 420
 421 static struct platform_driver imx6q_cpufreq_platdrv = {
 422         .driver = {
 423                 .name   = "imx6q-cpufreq",
 424         },
 425         .probe          = imx6q_cpufreq_probe,
 426         .remove         = imx6q_cpufreq_remove,
 427 };
 428 module_platform_driver(imx6q_cpufreq_platdrv);
 429
 430 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
 431 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
 432 MODULE_LICENSE("GPL");