1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Freescale Semiconductor, Inc.
8 #include <linux/cpufreq.h>
10 #include <linux/module.h>
11 #include <linux/nvmem-consumer.h>
13 #include <linux/of_address.h>
14 #include <linux/pm_opp.h>
15 #include <linux/platform_device.h>
16 #include <linux/regulator/consumer.h>
18 #define PU_SOC_VOLTAGE_NORMAL 1250000
19 #define PU_SOC_VOLTAGE_HIGH 1275000
20 #define FREQ_1P2_GHZ 1200000000
22 static struct regulator
*arm_reg
;
23 static struct regulator
*pu_reg
;
24 static struct regulator
*soc_reg
;
26 enum IMX6_CPUFREQ_CLKS
{
32 /* MX6UL requires two more clks */
36 #define IMX6Q_CPUFREQ_CLK_NUM 5
37 #define IMX6UL_CPUFREQ_CLK_NUM 7
40 static struct clk_bulk_data clks
[] = {
45 { .id
= "pll2_pfd2_396m" },
47 { .id
= "secondary_sel" },
50 static struct device
*cpu_dev
;
52 static struct cpufreq_frequency_table
*freq_table
;
53 static unsigned int max_freq
;
54 static unsigned int transition_latency
;
56 static u32
*imx6_soc_volt
;
57 static u32 soc_opp_count
;
59 static int imx6q_set_target(struct cpufreq_policy
*policy
, unsigned int index
)
61 struct dev_pm_opp
*opp
;
62 unsigned long freq_hz
, volt
, volt_old
;
63 unsigned int old_freq
, new_freq
;
64 bool pll1_sys_temp_enabled
= false;
67 new_freq
= freq_table
[index
].frequency
;
68 freq_hz
= new_freq
* 1000;
69 old_freq
= clk_get_rate(clks
[ARM
].clk
) / 1000;
71 opp
= dev_pm_opp_find_freq_ceil(cpu_dev
, &freq_hz
);
73 dev_err(cpu_dev
, "failed to find OPP for %ld\n", freq_hz
);
77 volt
= dev_pm_opp_get_voltage(opp
);
80 volt_old
= regulator_get_voltage(arm_reg
);
82 dev_dbg(cpu_dev
, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
83 old_freq
/ 1000, volt_old
/ 1000,
84 new_freq
/ 1000, volt
/ 1000);
86 /* scaling up? scale voltage before frequency */
87 if (new_freq
> old_freq
) {
88 if (!IS_ERR(pu_reg
)) {
89 ret
= regulator_set_voltage_tol(pu_reg
, imx6_soc_volt
[index
], 0);
91 dev_err(cpu_dev
, "failed to scale vddpu up: %d\n", ret
);
95 ret
= regulator_set_voltage_tol(soc_reg
, imx6_soc_volt
[index
], 0);
97 dev_err(cpu_dev
, "failed to scale vddsoc up: %d\n", ret
);
100 ret
= regulator_set_voltage_tol(arm_reg
, volt
, 0);
103 "failed to scale vddarm up: %d\n", ret
);
109 * The setpoints are selected per PLL/PDF frequencies, so we need to
110 * reprogram PLL for frequency scaling. The procedure of reprogramming
112 * For i.MX6UL, it has a secondary clk mux, the cpu frequency change
113 * flow is slightly different from other i.MX6 OSC.
114 * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
115 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
116 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
117 * - Disable pll2_pfd2_396m_clk
119 if (of_machine_is_compatible("fsl,imx6ul") ||
120 of_machine_is_compatible("fsl,imx6ull")) {
122 * When changing pll1_sw_clk's parent to pll1_sys_clk,
123 * CPU may run at higher than 528MHz, this will lead to
124 * the system unstable if the voltage is lower than the
125 * voltage of 528MHz, so lower the CPU frequency to one
126 * half before changing CPU frequency.
128 clk_set_rate(clks
[ARM
].clk
, (old_freq
>> 1) * 1000);
129 clk_set_parent(clks
[PLL1_SW
].clk
, clks
[PLL1_SYS
].clk
);
130 if (freq_hz
> clk_get_rate(clks
[PLL2_PFD2_396M
].clk
))
131 clk_set_parent(clks
[SECONDARY_SEL
].clk
,
134 clk_set_parent(clks
[SECONDARY_SEL
].clk
,
135 clks
[PLL2_PFD2_396M
].clk
);
136 clk_set_parent(clks
[STEP
].clk
, clks
[SECONDARY_SEL
].clk
);
137 clk_set_parent(clks
[PLL1_SW
].clk
, clks
[STEP
].clk
);
138 if (freq_hz
> clk_get_rate(clks
[PLL2_BUS
].clk
)) {
139 clk_set_rate(clks
[PLL1_SYS
].clk
, new_freq
* 1000);
140 clk_set_parent(clks
[PLL1_SW
].clk
, clks
[PLL1_SYS
].clk
);
143 clk_set_parent(clks
[STEP
].clk
, clks
[PLL2_PFD2_396M
].clk
);
144 clk_set_parent(clks
[PLL1_SW
].clk
, clks
[STEP
].clk
);
145 if (freq_hz
> clk_get_rate(clks
[PLL2_PFD2_396M
].clk
)) {
146 clk_set_rate(clks
[PLL1_SYS
].clk
, new_freq
* 1000);
147 clk_set_parent(clks
[PLL1_SW
].clk
, clks
[PLL1_SYS
].clk
);
149 /* pll1_sys needs to be enabled for divider rate change to work. */
150 pll1_sys_temp_enabled
= true;
151 clk_prepare_enable(clks
[PLL1_SYS
].clk
);
155 /* Ensure the arm clock divider is what we expect */
156 ret
= clk_set_rate(clks
[ARM
].clk
, new_freq
* 1000);
160 dev_err(cpu_dev
, "failed to set clock rate: %d\n", ret
);
161 ret1
= regulator_set_voltage_tol(arm_reg
, volt_old
, 0);
164 "failed to restore vddarm voltage: %d\n", ret1
);
168 /* PLL1 is only needed until after ARM-PODF is set. */
169 if (pll1_sys_temp_enabled
)
170 clk_disable_unprepare(clks
[PLL1_SYS
].clk
);
172 /* scaling down? scale voltage after frequency */
173 if (new_freq
< old_freq
) {
174 ret
= regulator_set_voltage_tol(arm_reg
, volt
, 0);
177 "failed to scale vddarm down: %d\n", ret
);
178 ret
= regulator_set_voltage_tol(soc_reg
, imx6_soc_volt
[index
], 0);
180 dev_warn(cpu_dev
, "failed to scale vddsoc down: %d\n", ret
);
181 if (!IS_ERR(pu_reg
)) {
182 ret
= regulator_set_voltage_tol(pu_reg
, imx6_soc_volt
[index
], 0);
184 dev_warn(cpu_dev
, "failed to scale vddpu down: %d\n", ret
);
191 static int imx6q_cpufreq_init(struct cpufreq_policy
*policy
)
195 policy
->clk
= clks
[ARM
].clk
;
196 ret
= cpufreq_generic_init(policy
, freq_table
, transition_latency
);
197 policy
->suspend_freq
= max_freq
;
198 dev_pm_opp_of_register_em(policy
->cpus
);
203 static struct cpufreq_driver imx6q_cpufreq_driver
= {
204 .flags
= CPUFREQ_NEED_INITIAL_FREQ_CHECK
|
205 CPUFREQ_IS_COOLING_DEV
,
206 .verify
= cpufreq_generic_frequency_table_verify
,
207 .target_index
= imx6q_set_target
,
208 .get
= cpufreq_generic_get
,
209 .init
= imx6q_cpufreq_init
,
210 .name
= "imx6q-cpufreq",
211 .attr
= cpufreq_generic_attr
,
212 .suspend
= cpufreq_generic_suspend
,
215 #define OCOTP_CFG3 0x440
216 #define OCOTP_CFG3_SPEED_SHIFT 16
217 #define OCOTP_CFG3_SPEED_1P2GHZ 0x3
218 #define OCOTP_CFG3_SPEED_996MHZ 0x2
219 #define OCOTP_CFG3_SPEED_852MHZ 0x1
221 static void imx6q_opp_check_speed_grading(struct device
*dev
)
223 struct device_node
*np
;
227 np
= of_find_compatible_node(NULL
, NULL
, "fsl,imx6q-ocotp");
231 base
= of_iomap(np
, 0);
233 dev_err(dev
, "failed to map ocotp\n");
238 * SPEED_GRADING[1:0] defines the max speed of ARM:
239 * 2b'11: 1200000000Hz;
240 * 2b'10: 996000000Hz;
241 * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
242 * 2b'00: 792000000Hz;
243 * We need to set the max speed of ARM according to fuse map.
245 val
= readl_relaxed(base
+ OCOTP_CFG3
);
246 val
>>= OCOTP_CFG3_SPEED_SHIFT
;
249 if (val
< OCOTP_CFG3_SPEED_996MHZ
)
250 if (dev_pm_opp_disable(dev
, 996000000))
251 dev_warn(dev
, "failed to disable 996MHz OPP\n");
253 if (of_machine_is_compatible("fsl,imx6q") ||
254 of_machine_is_compatible("fsl,imx6qp")) {
255 if (val
!= OCOTP_CFG3_SPEED_852MHZ
)
256 if (dev_pm_opp_disable(dev
, 852000000))
257 dev_warn(dev
, "failed to disable 852MHz OPP\n");
258 if (val
!= OCOTP_CFG3_SPEED_1P2GHZ
)
259 if (dev_pm_opp_disable(dev
, 1200000000))
260 dev_warn(dev
, "failed to disable 1.2GHz OPP\n");
267 #define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2
268 #define OCOTP_CFG3_6ULL_SPEED_792MHZ 0x2
269 #define OCOTP_CFG3_6ULL_SPEED_900MHZ 0x3
271 static int imx6ul_opp_check_speed_grading(struct device
*dev
)
276 if (of_find_property(dev
->of_node
, "nvmem-cells", NULL
)) {
277 ret
= nvmem_cell_read_u32(dev
, "speed_grade", &val
);
281 struct device_node
*np
;
284 np
= of_find_compatible_node(NULL
, NULL
, "fsl,imx6ul-ocotp");
288 base
= of_iomap(np
, 0);
291 dev_err(dev
, "failed to map ocotp\n");
295 val
= readl_relaxed(base
+ OCOTP_CFG3
);
300 * Speed GRADING[1:0] defines the max speed of ARM:
302 * 2b'01: 528000000Hz;
303 * 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL;
304 * 2b'11: 900000000Hz on i.MX6ULL only;
305 * We need to set the max speed of ARM according to fuse map.
307 val
>>= OCOTP_CFG3_SPEED_SHIFT
;
310 if (of_machine_is_compatible("fsl,imx6ul")) {
311 if (val
!= OCOTP_CFG3_6UL_SPEED_696MHZ
)
312 if (dev_pm_opp_disable(dev
, 696000000))
313 dev_warn(dev
, "failed to disable 696MHz OPP\n");
316 if (of_machine_is_compatible("fsl,imx6ull")) {
317 if (val
!= OCOTP_CFG3_6ULL_SPEED_792MHZ
)
318 if (dev_pm_opp_disable(dev
, 792000000))
319 dev_warn(dev
, "failed to disable 792MHz OPP\n");
321 if (val
!= OCOTP_CFG3_6ULL_SPEED_900MHZ
)
322 if (dev_pm_opp_disable(dev
, 900000000))
323 dev_warn(dev
, "failed to disable 900MHz OPP\n");
329 static int imx6q_cpufreq_probe(struct platform_device
*pdev
)
331 struct device_node
*np
;
332 struct dev_pm_opp
*opp
;
333 unsigned long min_volt
, max_volt
;
335 const struct property
*prop
;
339 cpu_dev
= get_cpu_device(0);
341 pr_err("failed to get cpu0 device\n");
345 np
= of_node_get(cpu_dev
->of_node
);
347 dev_err(cpu_dev
, "failed to find cpu0 node\n");
351 if (of_machine_is_compatible("fsl,imx6ul") ||
352 of_machine_is_compatible("fsl,imx6ull"))
353 num_clks
= IMX6UL_CPUFREQ_CLK_NUM
;
355 num_clks
= IMX6Q_CPUFREQ_CLK_NUM
;
357 ret
= clk_bulk_get(cpu_dev
, num_clks
, clks
);
361 arm_reg
= regulator_get(cpu_dev
, "arm");
362 pu_reg
= regulator_get_optional(cpu_dev
, "pu");
363 soc_reg
= regulator_get(cpu_dev
, "soc");
364 if (PTR_ERR(arm_reg
) == -EPROBE_DEFER
||
365 PTR_ERR(soc_reg
) == -EPROBE_DEFER
||
366 PTR_ERR(pu_reg
) == -EPROBE_DEFER
) {
368 dev_dbg(cpu_dev
, "regulators not ready, defer\n");
371 if (IS_ERR(arm_reg
) || IS_ERR(soc_reg
)) {
372 dev_err(cpu_dev
, "failed to get regulators\n");
377 ret
= dev_pm_opp_of_add_table(cpu_dev
);
379 dev_err(cpu_dev
, "failed to init OPP table: %d\n", ret
);
383 if (of_machine_is_compatible("fsl,imx6ul") ||
384 of_machine_is_compatible("fsl,imx6ull")) {
385 ret
= imx6ul_opp_check_speed_grading(cpu_dev
);
387 if (ret
== -EPROBE_DEFER
)
390 dev_err(cpu_dev
, "failed to read ocotp: %d\n",
395 imx6q_opp_check_speed_grading(cpu_dev
);
398 /* Because we have added the OPPs here, we must free them */
400 num
= dev_pm_opp_get_opp_count(cpu_dev
);
403 dev_err(cpu_dev
, "no OPP table is found: %d\n", ret
);
407 ret
= dev_pm_opp_init_cpufreq_table(cpu_dev
, &freq_table
);
409 dev_err(cpu_dev
, "failed to init cpufreq table: %d\n", ret
);
413 /* Make imx6_soc_volt array's size same as arm opp number */
414 imx6_soc_volt
= devm_kcalloc(cpu_dev
, num
, sizeof(*imx6_soc_volt
),
416 if (imx6_soc_volt
== NULL
) {
418 goto free_freq_table
;
421 prop
= of_find_property(np
, "fsl,soc-operating-points", NULL
);
422 if (!prop
|| !prop
->value
)
426 * Each OPP is a set of tuples consisting of frequency and
427 * voltage like <freq-kHz vol-uV>.
429 nr
= prop
->length
/ sizeof(u32
);
430 if (nr
% 2 || (nr
/ 2) < num
)
433 for (j
= 0; j
< num
; j
++) {
435 for (i
= 0; i
< nr
/ 2; i
++) {
436 unsigned long freq
= be32_to_cpup(val
++);
437 unsigned long volt
= be32_to_cpup(val
++);
438 if (freq_table
[j
].frequency
== freq
) {
439 imx6_soc_volt
[soc_opp_count
++] = volt
;
446 /* use fixed soc opp volt if no valid soc opp info found in dtb */
447 if (soc_opp_count
!= num
) {
448 dev_warn(cpu_dev
, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
449 for (j
= 0; j
< num
; j
++)
450 imx6_soc_volt
[j
] = PU_SOC_VOLTAGE_NORMAL
;
451 if (freq_table
[num
- 1].frequency
* 1000 == FREQ_1P2_GHZ
)
452 imx6_soc_volt
[num
- 1] = PU_SOC_VOLTAGE_HIGH
;
455 if (of_property_read_u32(np
, "clock-latency", &transition_latency
))
456 transition_latency
= CPUFREQ_ETERNAL
;
459 * Calculate the ramp time for max voltage change in the
460 * VDDSOC and VDDPU regulators.
462 ret
= regulator_set_voltage_time(soc_reg
, imx6_soc_volt
[0], imx6_soc_volt
[num
- 1]);
464 transition_latency
+= ret
* 1000;
465 if (!IS_ERR(pu_reg
)) {
466 ret
= regulator_set_voltage_time(pu_reg
, imx6_soc_volt
[0], imx6_soc_volt
[num
- 1]);
468 transition_latency
+= ret
* 1000;
472 * OPP is maintained in order of increasing frequency, and
473 * freq_table initialised from OPP is therefore sorted in the
476 max_freq
= freq_table
[--num
].frequency
;
477 opp
= dev_pm_opp_find_freq_exact(cpu_dev
,
478 freq_table
[0].frequency
* 1000, true);
479 min_volt
= dev_pm_opp_get_voltage(opp
);
481 opp
= dev_pm_opp_find_freq_exact(cpu_dev
, max_freq
* 1000, true);
482 max_volt
= dev_pm_opp_get_voltage(opp
);
485 ret
= regulator_set_voltage_time(arm_reg
, min_volt
, max_volt
);
487 transition_latency
+= ret
* 1000;
489 ret
= cpufreq_register_driver(&imx6q_cpufreq_driver
);
491 dev_err(cpu_dev
, "failed register driver: %d\n", ret
);
492 goto free_freq_table
;
499 dev_pm_opp_free_cpufreq_table(cpu_dev
, &freq_table
);
502 dev_pm_opp_of_remove_table(cpu_dev
);
504 if (!IS_ERR(arm_reg
))
505 regulator_put(arm_reg
);
507 regulator_put(pu_reg
);
508 if (!IS_ERR(soc_reg
))
509 regulator_put(soc_reg
);
511 clk_bulk_put(num_clks
, clks
);
518 static int imx6q_cpufreq_remove(struct platform_device
*pdev
)
520 cpufreq_unregister_driver(&imx6q_cpufreq_driver
);
521 dev_pm_opp_free_cpufreq_table(cpu_dev
, &freq_table
);
523 dev_pm_opp_of_remove_table(cpu_dev
);
524 regulator_put(arm_reg
);
526 regulator_put(pu_reg
);
527 regulator_put(soc_reg
);
529 clk_bulk_put(num_clks
, clks
);
534 static struct platform_driver imx6q_cpufreq_platdrv
= {
536 .name
= "imx6q-cpufreq",
538 .probe
= imx6q_cpufreq_probe
,
539 .remove
= imx6q_cpufreq_remove
,
541 module_platform_driver(imx6q_cpufreq_platdrv
);
543 MODULE_ALIAS("platform:imx6q-cpufreq");
544 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
545 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
546 MODULE_LICENSE("GPL");