2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/cpu.h>
11 #include <linux/cpufreq.h>
12 #include <linux/err.h>
13 #include <linux/module.h>
15 #include <linux/pm_opp.h>
16 #include <linux/platform_device.h>
17 #include <linux/regulator/consumer.h>
19 #define PU_SOC_VOLTAGE_NORMAL 1250000
20 #define PU_SOC_VOLTAGE_HIGH 1275000
21 #define FREQ_1P2_GHZ 1200000000
23 static struct regulator
*arm_reg
;
24 static struct regulator
*pu_reg
;
25 static struct regulator
*soc_reg
;
27 static struct clk
*arm_clk
;
28 static struct clk
*pll1_sys_clk
;
29 static struct clk
*pll1_sw_clk
;
30 static struct clk
*step_clk
;
31 static struct clk
*pll2_pfd2_396m_clk
;
33 /* clk used by i.MX6UL */
34 static struct clk
*pll2_bus_clk
;
35 static struct clk
*secondary_sel_clk
;
37 static struct device
*cpu_dev
;
39 static struct cpufreq_frequency_table
*freq_table
;
40 static unsigned int transition_latency
;
42 static u32
*imx6_soc_volt
;
43 static u32 soc_opp_count
;
45 static int imx6q_set_target(struct cpufreq_policy
*policy
, unsigned int index
)
47 struct dev_pm_opp
*opp
;
48 unsigned long freq_hz
, volt
, volt_old
;
49 unsigned int old_freq
, new_freq
;
52 new_freq
= freq_table
[index
].frequency
;
53 freq_hz
= new_freq
* 1000;
54 old_freq
= clk_get_rate(arm_clk
) / 1000;
56 opp
= dev_pm_opp_find_freq_ceil(cpu_dev
, &freq_hz
);
58 dev_err(cpu_dev
, "failed to find OPP for %ld\n", freq_hz
);
62 volt
= dev_pm_opp_get_voltage(opp
);
65 volt_old
= regulator_get_voltage(arm_reg
);
67 dev_dbg(cpu_dev
, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
68 old_freq
/ 1000, volt_old
/ 1000,
69 new_freq
/ 1000, volt
/ 1000);
71 /* scaling up? scale voltage before frequency */
72 if (new_freq
> old_freq
) {
73 if (!IS_ERR(pu_reg
)) {
74 ret
= regulator_set_voltage_tol(pu_reg
, imx6_soc_volt
[index
], 0);
76 dev_err(cpu_dev
, "failed to scale vddpu up: %d\n", ret
);
80 ret
= regulator_set_voltage_tol(soc_reg
, imx6_soc_volt
[index
], 0);
82 dev_err(cpu_dev
, "failed to scale vddsoc up: %d\n", ret
);
85 ret
= regulator_set_voltage_tol(arm_reg
, volt
, 0);
88 "failed to scale vddarm up: %d\n", ret
);
94 * The setpoints are selected per PLL/PDF frequencies, so we need to
95 * reprogram PLL for frequency scaling. The procedure of reprogramming
97 * For i.MX6UL, it has a secondary clk mux, the cpu frequency change
98 * flow is slightly different from other i.MX6 OSC.
99 * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
100 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
101 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
102 * - Disable pll2_pfd2_396m_clk
104 if (of_machine_is_compatible("fsl,imx6ul")) {
106 * When changing pll1_sw_clk's parent to pll1_sys_clk,
107 * CPU may run at higher than 528MHz, this will lead to
108 * the system unstable if the voltage is lower than the
109 * voltage of 528MHz, so lower the CPU frequency to one
110 * half before changing CPU frequency.
112 clk_set_rate(arm_clk
, (old_freq
>> 1) * 1000);
113 clk_set_parent(pll1_sw_clk
, pll1_sys_clk
);
114 if (freq_hz
> clk_get_rate(pll2_pfd2_396m_clk
))
115 clk_set_parent(secondary_sel_clk
, pll2_bus_clk
);
117 clk_set_parent(secondary_sel_clk
, pll2_pfd2_396m_clk
);
118 clk_set_parent(step_clk
, secondary_sel_clk
);
119 clk_set_parent(pll1_sw_clk
, step_clk
);
121 clk_set_parent(step_clk
, pll2_pfd2_396m_clk
);
122 clk_set_parent(pll1_sw_clk
, step_clk
);
123 if (freq_hz
> clk_get_rate(pll2_pfd2_396m_clk
)) {
124 clk_set_rate(pll1_sys_clk
, new_freq
* 1000);
125 clk_set_parent(pll1_sw_clk
, pll1_sys_clk
);
129 /* Ensure the arm clock divider is what we expect */
130 ret
= clk_set_rate(arm_clk
, new_freq
* 1000);
132 dev_err(cpu_dev
, "failed to set clock rate: %d\n", ret
);
133 regulator_set_voltage_tol(arm_reg
, volt_old
, 0);
137 /* scaling down? scale voltage after frequency */
138 if (new_freq
< old_freq
) {
139 ret
= regulator_set_voltage_tol(arm_reg
, volt
, 0);
142 "failed to scale vddarm down: %d\n", ret
);
145 ret
= regulator_set_voltage_tol(soc_reg
, imx6_soc_volt
[index
], 0);
147 dev_warn(cpu_dev
, "failed to scale vddsoc down: %d\n", ret
);
150 if (!IS_ERR(pu_reg
)) {
151 ret
= regulator_set_voltage_tol(pu_reg
, imx6_soc_volt
[index
], 0);
153 dev_warn(cpu_dev
, "failed to scale vddpu down: %d\n", ret
);
162 static int imx6q_cpufreq_init(struct cpufreq_policy
*policy
)
164 policy
->clk
= arm_clk
;
165 return cpufreq_generic_init(policy
, freq_table
, transition_latency
);
168 static struct cpufreq_driver imx6q_cpufreq_driver
= {
169 .flags
= CPUFREQ_NEED_INITIAL_FREQ_CHECK
,
170 .verify
= cpufreq_generic_frequency_table_verify
,
171 .target_index
= imx6q_set_target
,
172 .get
= cpufreq_generic_get
,
173 .init
= imx6q_cpufreq_init
,
174 .name
= "imx6q-cpufreq",
175 .attr
= cpufreq_generic_attr
,
178 static int imx6q_cpufreq_probe(struct platform_device
*pdev
)
180 struct device_node
*np
;
181 struct dev_pm_opp
*opp
;
182 unsigned long min_volt
, max_volt
;
184 const struct property
*prop
;
188 cpu_dev
= get_cpu_device(0);
190 pr_err("failed to get cpu0 device\n");
194 np
= of_node_get(cpu_dev
->of_node
);
196 dev_err(cpu_dev
, "failed to find cpu0 node\n");
200 arm_clk
= clk_get(cpu_dev
, "arm");
201 pll1_sys_clk
= clk_get(cpu_dev
, "pll1_sys");
202 pll1_sw_clk
= clk_get(cpu_dev
, "pll1_sw");
203 step_clk
= clk_get(cpu_dev
, "step");
204 pll2_pfd2_396m_clk
= clk_get(cpu_dev
, "pll2_pfd2_396m");
205 if (IS_ERR(arm_clk
) || IS_ERR(pll1_sys_clk
) || IS_ERR(pll1_sw_clk
) ||
206 IS_ERR(step_clk
) || IS_ERR(pll2_pfd2_396m_clk
)) {
207 dev_err(cpu_dev
, "failed to get clocks\n");
212 if (of_machine_is_compatible("fsl,imx6ul")) {
213 pll2_bus_clk
= clk_get(cpu_dev
, "pll2_bus");
214 secondary_sel_clk
= clk_get(cpu_dev
, "secondary_sel");
215 if (IS_ERR(pll2_bus_clk
) || IS_ERR(secondary_sel_clk
)) {
216 dev_err(cpu_dev
, "failed to get clocks specific to imx6ul\n");
222 arm_reg
= regulator_get(cpu_dev
, "arm");
223 pu_reg
= regulator_get_optional(cpu_dev
, "pu");
224 soc_reg
= regulator_get(cpu_dev
, "soc");
225 if (IS_ERR(arm_reg
) || IS_ERR(soc_reg
)) {
226 dev_err(cpu_dev
, "failed to get regulators\n");
232 * We expect an OPP table supplied by platform.
233 * Just, incase the platform did not supply the OPP
234 * table, it will try to get it.
236 num
= dev_pm_opp_get_opp_count(cpu_dev
);
238 ret
= dev_pm_opp_of_add_table(cpu_dev
);
240 dev_err(cpu_dev
, "failed to init OPP table: %d\n", ret
);
244 /* Because we have added the OPPs here, we must free them */
247 num
= dev_pm_opp_get_opp_count(cpu_dev
);
250 dev_err(cpu_dev
, "no OPP table is found: %d\n", ret
);
255 ret
= dev_pm_opp_init_cpufreq_table(cpu_dev
, &freq_table
);
257 dev_err(cpu_dev
, "failed to init cpufreq table: %d\n", ret
);
261 /* Make imx6_soc_volt array's size same as arm opp number */
262 imx6_soc_volt
= devm_kzalloc(cpu_dev
, sizeof(*imx6_soc_volt
) * num
, GFP_KERNEL
);
263 if (imx6_soc_volt
== NULL
) {
265 goto free_freq_table
;
268 prop
= of_find_property(np
, "fsl,soc-operating-points", NULL
);
269 if (!prop
|| !prop
->value
)
273 * Each OPP is a set of tuples consisting of frequency and
274 * voltage like <freq-kHz vol-uV>.
276 nr
= prop
->length
/ sizeof(u32
);
277 if (nr
% 2 || (nr
/ 2) < num
)
280 for (j
= 0; j
< num
; j
++) {
282 for (i
= 0; i
< nr
/ 2; i
++) {
283 unsigned long freq
= be32_to_cpup(val
++);
284 unsigned long volt
= be32_to_cpup(val
++);
285 if (freq_table
[j
].frequency
== freq
) {
286 imx6_soc_volt
[soc_opp_count
++] = volt
;
293 /* use fixed soc opp volt if no valid soc opp info found in dtb */
294 if (soc_opp_count
!= num
) {
295 dev_warn(cpu_dev
, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
296 for (j
= 0; j
< num
; j
++)
297 imx6_soc_volt
[j
] = PU_SOC_VOLTAGE_NORMAL
;
298 if (freq_table
[num
- 1].frequency
* 1000 == FREQ_1P2_GHZ
)
299 imx6_soc_volt
[num
- 1] = PU_SOC_VOLTAGE_HIGH
;
302 if (of_property_read_u32(np
, "clock-latency", &transition_latency
))
303 transition_latency
= CPUFREQ_ETERNAL
;
306 * Calculate the ramp time for max voltage change in the
307 * VDDSOC and VDDPU regulators.
309 ret
= regulator_set_voltage_time(soc_reg
, imx6_soc_volt
[0], imx6_soc_volt
[num
- 1]);
311 transition_latency
+= ret
* 1000;
312 if (!IS_ERR(pu_reg
)) {
313 ret
= regulator_set_voltage_time(pu_reg
, imx6_soc_volt
[0], imx6_soc_volt
[num
- 1]);
315 transition_latency
+= ret
* 1000;
319 * OPP is maintained in order of increasing frequency, and
320 * freq_table initialised from OPP is therefore sorted in the
323 opp
= dev_pm_opp_find_freq_exact(cpu_dev
,
324 freq_table
[0].frequency
* 1000, true);
325 min_volt
= dev_pm_opp_get_voltage(opp
);
327 opp
= dev_pm_opp_find_freq_exact(cpu_dev
,
328 freq_table
[--num
].frequency
* 1000, true);
329 max_volt
= dev_pm_opp_get_voltage(opp
);
332 ret
= regulator_set_voltage_time(arm_reg
, min_volt
, max_volt
);
334 transition_latency
+= ret
* 1000;
336 ret
= cpufreq_register_driver(&imx6q_cpufreq_driver
);
338 dev_err(cpu_dev
, "failed register driver: %d\n", ret
);
339 goto free_freq_table
;
346 dev_pm_opp_free_cpufreq_table(cpu_dev
, &freq_table
);
349 dev_pm_opp_of_remove_table(cpu_dev
);
351 if (!IS_ERR(arm_reg
))
352 regulator_put(arm_reg
);
354 regulator_put(pu_reg
);
355 if (!IS_ERR(soc_reg
))
356 regulator_put(soc_reg
);
358 if (!IS_ERR(arm_clk
))
360 if (!IS_ERR(pll1_sys_clk
))
361 clk_put(pll1_sys_clk
);
362 if (!IS_ERR(pll1_sw_clk
))
363 clk_put(pll1_sw_clk
);
364 if (!IS_ERR(step_clk
))
366 if (!IS_ERR(pll2_pfd2_396m_clk
))
367 clk_put(pll2_pfd2_396m_clk
);
368 if (!IS_ERR(pll2_bus_clk
))
369 clk_put(pll2_bus_clk
);
370 if (!IS_ERR(secondary_sel_clk
))
371 clk_put(secondary_sel_clk
);
376 static int imx6q_cpufreq_remove(struct platform_device
*pdev
)
378 cpufreq_unregister_driver(&imx6q_cpufreq_driver
);
379 dev_pm_opp_free_cpufreq_table(cpu_dev
, &freq_table
);
381 dev_pm_opp_of_remove_table(cpu_dev
);
382 regulator_put(arm_reg
);
384 regulator_put(pu_reg
);
385 regulator_put(soc_reg
);
387 clk_put(pll1_sys_clk
);
388 clk_put(pll1_sw_clk
);
390 clk_put(pll2_pfd2_396m_clk
);
391 clk_put(pll2_bus_clk
);
392 clk_put(secondary_sel_clk
);
397 static struct platform_driver imx6q_cpufreq_platdrv
= {
399 .name
= "imx6q-cpufreq",
401 .probe
= imx6q_cpufreq_probe
,
402 .remove
= imx6q_cpufreq_remove
,
404 module_platform_driver(imx6q_cpufreq_platdrv
);
406 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
407 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
408 MODULE_LICENSE("GPL");