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cpufreq: intel_pstate: Enable HWP during system resume on CPU0
[mirror_ubuntu-bionic-kernel.git] / drivers / cpufreq / intel_pstate.c
1 /*
2 * intel_pstate.c: Native P state management for Intel processors
3 *
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 */
12
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15 #include <linux/kernel.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/ktime.h>
19 #include <linux/hrtimer.h>
20 #include <linux/tick.h>
21 #include <linux/slab.h>
22 #include <linux/sched/cpufreq.h>
23 #include <linux/list.h>
24 #include <linux/cpu.h>
25 #include <linux/cpufreq.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
28 #include <linux/fs.h>
29 #include <linux/debugfs.h>
30 #include <linux/acpi.h>
31 #include <linux/vmalloc.h>
32 #include <trace/events/power.h>
33
34 #include <asm/div64.h>
35 #include <asm/msr.h>
36 #include <asm/cpu_device_id.h>
37 #include <asm/cpufeature.h>
38 #include <asm/intel-family.h>
39
40 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
41
42 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
43 #define INTEL_CPUFREQ_TRANSITION_DELAY 500
44
45 #ifdef CONFIG_ACPI
46 #include <acpi/processor.h>
47 #include <acpi/cppc_acpi.h>
48 #endif
49
50 #define FRAC_BITS 8
51 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
52 #define fp_toint(X) ((X) >> FRAC_BITS)
53
54 #define EXT_BITS 6
55 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
56 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
57 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
58
59 static inline int32_t mul_fp(int32_t x, int32_t y)
60 {
61 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
62 }
63
64 static inline int32_t div_fp(s64 x, s64 y)
65 {
66 return div64_s64((int64_t)x << FRAC_BITS, y);
67 }
68
69 static inline int ceiling_fp(int32_t x)
70 {
71 int mask, ret;
72
73 ret = fp_toint(x);
74 mask = (1 << FRAC_BITS) - 1;
75 if (x & mask)
76 ret += 1;
77 return ret;
78 }
79
80 static inline int32_t percent_fp(int percent)
81 {
82 return div_fp(percent, 100);
83 }
84
85 static inline u64 mul_ext_fp(u64 x, u64 y)
86 {
87 return (x * y) >> EXT_FRAC_BITS;
88 }
89
90 static inline u64 div_ext_fp(u64 x, u64 y)
91 {
92 return div64_u64(x << EXT_FRAC_BITS, y);
93 }
94
95 static inline int32_t percent_ext_fp(int percent)
96 {
97 return div_ext_fp(percent, 100);
98 }
99
100 /**
101 * struct sample - Store performance sample
102 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
103 * performance during last sample period
104 * @busy_scaled: Scaled busy value which is used to calculate next
105 * P state. This can be different than core_avg_perf
106 * to account for cpu idle period
107 * @aperf: Difference of actual performance frequency clock count
108 * read from APERF MSR between last and current sample
109 * @mperf: Difference of maximum performance frequency clock count
110 * read from MPERF MSR between last and current sample
111 * @tsc: Difference of time stamp counter between last and
112 * current sample
113 * @time: Current time from scheduler
114 *
115 * This structure is used in the cpudata structure to store performance sample
116 * data for choosing next P State.
117 */
118 struct sample {
119 int32_t core_avg_perf;
120 int32_t busy_scaled;
121 u64 aperf;
122 u64 mperf;
123 u64 tsc;
124 u64 time;
125 };
126
127 /**
128 * struct pstate_data - Store P state data
129 * @current_pstate: Current requested P state
130 * @min_pstate: Min P state possible for this platform
131 * @max_pstate: Max P state possible for this platform
132 * @max_pstate_physical:This is physical Max P state for a processor
133 * This can be higher than the max_pstate which can
134 * be limited by platform thermal design power limits
135 * @scaling: Scaling factor to convert frequency to cpufreq
136 * frequency units
137 * @turbo_pstate: Max Turbo P state possible for this platform
138 * @max_freq: @max_pstate frequency in cpufreq units
139 * @turbo_freq: @turbo_pstate frequency in cpufreq units
140 *
141 * Stores the per cpu model P state limits and current P state.
142 */
143 struct pstate_data {
144 int current_pstate;
145 int min_pstate;
146 int max_pstate;
147 int max_pstate_physical;
148 int scaling;
149 int turbo_pstate;
150 unsigned int max_freq;
151 unsigned int turbo_freq;
152 };
153
154 /**
155 * struct vid_data - Stores voltage information data
156 * @min: VID data for this platform corresponding to
157 * the lowest P state
158 * @max: VID data corresponding to the highest P State.
159 * @turbo: VID data for turbo P state
160 * @ratio: Ratio of (vid max - vid min) /
161 * (max P state - Min P State)
162 *
163 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
164 * This data is used in Atom platforms, where in addition to target P state,
165 * the voltage data needs to be specified to select next P State.
166 */
167 struct vid_data {
168 int min;
169 int max;
170 int turbo;
171 int32_t ratio;
172 };
173
174 /**
175 * struct global_params - Global parameters, mostly tunable via sysfs.
176 * @no_turbo: Whether or not to use turbo P-states.
177 * @turbo_disabled: Whethet or not turbo P-states are available at all,
178 * based on the MSR_IA32_MISC_ENABLE value and whether or
179 * not the maximum reported turbo P-state is different from
180 * the maximum reported non-turbo one.
181 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
182 * P-state capacity.
183 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
184 * P-state capacity.
185 */
186 struct global_params {
187 bool no_turbo;
188 bool turbo_disabled;
189 int max_perf_pct;
190 int min_perf_pct;
191 };
192
193 /**
194 * struct cpudata - Per CPU instance data storage
195 * @cpu: CPU number for this instance data
196 * @policy: CPUFreq policy value
197 * @update_util: CPUFreq utility callback information
198 * @update_util_set: CPUFreq utility callback is set
199 * @iowait_boost: iowait-related boost fraction
200 * @last_update: Time of the last update.
201 * @pstate: Stores P state limits for this CPU
202 * @vid: Stores VID limits for this CPU
203 * @last_sample_time: Last Sample time
204 * @aperf_mperf_shift: Number of clock cycles after aperf, merf is incremented
205 * This shift is a multiplier to mperf delta to
206 * calculate CPU busy.
207 * @prev_aperf: Last APERF value read from APERF MSR
208 * @prev_mperf: Last MPERF value read from MPERF MSR
209 * @prev_tsc: Last timestamp counter (TSC) value
210 * @prev_cummulative_iowait: IO Wait time difference from last and
211 * current sample
212 * @sample: Storage for storing last Sample data
213 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
214 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
215 * @acpi_perf_data: Stores ACPI perf information read from _PSS
216 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
217 * @epp_powersave: Last saved HWP energy performance preference
218 * (EPP) or energy performance bias (EPB),
219 * when policy switched to performance
220 * @epp_policy: Last saved policy used to set EPP/EPB
221 * @epp_default: Power on default HWP energy performance
222 * preference/bias
223 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
224 * operation
225 *
226 * This structure stores per CPU instance data for all CPUs.
227 */
228 struct cpudata {
229 int cpu;
230
231 unsigned int policy;
232 struct update_util_data update_util;
233 bool update_util_set;
234
235 struct pstate_data pstate;
236 struct vid_data vid;
237
238 u64 last_update;
239 u64 last_sample_time;
240 u64 aperf_mperf_shift;
241 u64 prev_aperf;
242 u64 prev_mperf;
243 u64 prev_tsc;
244 u64 prev_cummulative_iowait;
245 struct sample sample;
246 int32_t min_perf_ratio;
247 int32_t max_perf_ratio;
248 #ifdef CONFIG_ACPI
249 struct acpi_processor_performance acpi_perf_data;
250 bool valid_pss_table;
251 #endif
252 unsigned int iowait_boost;
253 s16 epp_powersave;
254 s16 epp_policy;
255 s16 epp_default;
256 s16 epp_saved;
257 };
258
259 static struct cpudata **all_cpu_data;
260
261 /**
262 * struct pstate_funcs - Per CPU model specific callbacks
263 * @get_max: Callback to get maximum non turbo effective P state
264 * @get_max_physical: Callback to get maximum non turbo physical P state
265 * @get_min: Callback to get minimum P state
266 * @get_turbo: Callback to get turbo P state
267 * @get_scaling: Callback to get frequency scaling factor
268 * @get_val: Callback to convert P state to actual MSR write value
269 * @get_vid: Callback to get VID data for Atom platforms
270 *
271 * Core and Atom CPU models have different way to get P State limits. This
272 * structure is used to store those callbacks.
273 */
274 struct pstate_funcs {
275 int (*get_max)(void);
276 int (*get_max_physical)(void);
277 int (*get_min)(void);
278 int (*get_turbo)(void);
279 int (*get_scaling)(void);
280 int (*get_aperf_mperf_shift)(void);
281 u64 (*get_val)(struct cpudata*, int pstate);
282 void (*get_vid)(struct cpudata *);
283 };
284
285 static struct pstate_funcs pstate_funcs __read_mostly;
286
287 static int hwp_active __read_mostly;
288 static bool per_cpu_limits __read_mostly;
289
290 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
291
292 #ifdef CONFIG_ACPI
293 static bool acpi_ppc;
294 #endif
295
296 static struct global_params global;
297
298 static DEFINE_MUTEX(intel_pstate_driver_lock);
299 static DEFINE_MUTEX(intel_pstate_limits_lock);
300
301 #ifdef CONFIG_ACPI
302
303 static bool intel_pstate_get_ppc_enable_status(void)
304 {
305 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
306 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
307 return true;
308
309 return acpi_ppc;
310 }
311
312 #ifdef CONFIG_ACPI_CPPC_LIB
313
314 /* The work item is needed to avoid CPU hotplug locking issues */
315 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
316 {
317 sched_set_itmt_support();
318 }
319
320 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
321
322 static void intel_pstate_set_itmt_prio(int cpu)
323 {
324 struct cppc_perf_caps cppc_perf;
325 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
326 int ret;
327
328 ret = cppc_get_perf_caps(cpu, &cppc_perf);
329 if (ret)
330 return;
331
332 /*
333 * The priorities can be set regardless of whether or not
334 * sched_set_itmt_support(true) has been called and it is valid to
335 * update them at any time after it has been called.
336 */
337 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
338
339 if (max_highest_perf <= min_highest_perf) {
340 if (cppc_perf.highest_perf > max_highest_perf)
341 max_highest_perf = cppc_perf.highest_perf;
342
343 if (cppc_perf.highest_perf < min_highest_perf)
344 min_highest_perf = cppc_perf.highest_perf;
345
346 if (max_highest_perf > min_highest_perf) {
347 /*
348 * This code can be run during CPU online under the
349 * CPU hotplug locks, so sched_set_itmt_support()
350 * cannot be called from here. Queue up a work item
351 * to invoke it.
352 */
353 schedule_work(&sched_itmt_work);
354 }
355 }
356 }
357 #else
358 static void intel_pstate_set_itmt_prio(int cpu)
359 {
360 }
361 #endif
362
363 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
364 {
365 struct cpudata *cpu;
366 int ret;
367 int i;
368
369 if (hwp_active) {
370 intel_pstate_set_itmt_prio(policy->cpu);
371 return;
372 }
373
374 if (!intel_pstate_get_ppc_enable_status())
375 return;
376
377 cpu = all_cpu_data[policy->cpu];
378
379 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
380 policy->cpu);
381 if (ret)
382 return;
383
384 /*
385 * Check if the control value in _PSS is for PERF_CTL MSR, which should
386 * guarantee that the states returned by it map to the states in our
387 * list directly.
388 */
389 if (cpu->acpi_perf_data.control_register.space_id !=
390 ACPI_ADR_SPACE_FIXED_HARDWARE)
391 goto err;
392
393 /*
394 * If there is only one entry _PSS, simply ignore _PSS and continue as
395 * usual without taking _PSS into account
396 */
397 if (cpu->acpi_perf_data.state_count < 2)
398 goto err;
399
400 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
401 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
402 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
403 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
404 (u32) cpu->acpi_perf_data.states[i].core_frequency,
405 (u32) cpu->acpi_perf_data.states[i].power,
406 (u32) cpu->acpi_perf_data.states[i].control);
407 }
408
409 /*
410 * The _PSS table doesn't contain whole turbo frequency range.
411 * This just contains +1 MHZ above the max non turbo frequency,
412 * with control value corresponding to max turbo ratio. But
413 * when cpufreq set policy is called, it will call with this
414 * max frequency, which will cause a reduced performance as
415 * this driver uses real max turbo frequency as the max
416 * frequency. So correct this frequency in _PSS table to
417 * correct max turbo frequency based on the turbo state.
418 * Also need to convert to MHz as _PSS freq is in MHz.
419 */
420 if (!global.turbo_disabled)
421 cpu->acpi_perf_data.states[0].core_frequency =
422 policy->cpuinfo.max_freq / 1000;
423 cpu->valid_pss_table = true;
424 pr_debug("_PPC limits will be enforced\n");
425
426 return;
427
428 err:
429 cpu->valid_pss_table = false;
430 acpi_processor_unregister_performance(policy->cpu);
431 }
432
433 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
434 {
435 struct cpudata *cpu;
436
437 cpu = all_cpu_data[policy->cpu];
438 if (!cpu->valid_pss_table)
439 return;
440
441 acpi_processor_unregister_performance(policy->cpu);
442 }
443 #else
444 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
445 {
446 }
447
448 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
449 {
450 }
451 #endif
452
453 static inline void update_turbo_state(void)
454 {
455 u64 misc_en;
456 struct cpudata *cpu;
457
458 cpu = all_cpu_data[0];
459 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
460 global.turbo_disabled =
461 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
462 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
463 }
464
465 static int min_perf_pct_min(void)
466 {
467 struct cpudata *cpu = all_cpu_data[0];
468 int turbo_pstate = cpu->pstate.turbo_pstate;
469
470 return turbo_pstate ?
471 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
472 }
473
474 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
475 {
476 u64 epb;
477 int ret;
478
479 if (!static_cpu_has(X86_FEATURE_EPB))
480 return -ENXIO;
481
482 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
483 if (ret)
484 return (s16)ret;
485
486 return (s16)(epb & 0x0f);
487 }
488
489 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
490 {
491 s16 epp;
492
493 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
494 /*
495 * When hwp_req_data is 0, means that caller didn't read
496 * MSR_HWP_REQUEST, so need to read and get EPP.
497 */
498 if (!hwp_req_data) {
499 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
500 &hwp_req_data);
501 if (epp)
502 return epp;
503 }
504 epp = (hwp_req_data >> 24) & 0xff;
505 } else {
506 /* When there is no EPP present, HWP uses EPB settings */
507 epp = intel_pstate_get_epb(cpu_data);
508 }
509
510 return epp;
511 }
512
513 static int intel_pstate_set_epb(int cpu, s16 pref)
514 {
515 u64 epb;
516 int ret;
517
518 if (!static_cpu_has(X86_FEATURE_EPB))
519 return -ENXIO;
520
521 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
522 if (ret)
523 return ret;
524
525 epb = (epb & ~0x0f) | pref;
526 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
527
528 return 0;
529 }
530
531 /*
532 * EPP/EPB display strings corresponding to EPP index in the
533 * energy_perf_strings[]
534 * index String
535 *-------------------------------------
536 * 0 default
537 * 1 performance
538 * 2 balance_performance
539 * 3 balance_power
540 * 4 power
541 */
542 static const char * const energy_perf_strings[] = {
543 "default",
544 "performance",
545 "balance_performance",
546 "balance_power",
547 "power",
548 NULL
549 };
550 static const unsigned int epp_values[] = {
551 HWP_EPP_PERFORMANCE,
552 HWP_EPP_BALANCE_PERFORMANCE,
553 HWP_EPP_BALANCE_POWERSAVE,
554 HWP_EPP_POWERSAVE
555 };
556
557 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
558 {
559 s16 epp;
560 int index = -EINVAL;
561
562 epp = intel_pstate_get_epp(cpu_data, 0);
563 if (epp < 0)
564 return epp;
565
566 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
567 if (epp == HWP_EPP_PERFORMANCE)
568 return 1;
569 if (epp <= HWP_EPP_BALANCE_PERFORMANCE)
570 return 2;
571 if (epp <= HWP_EPP_BALANCE_POWERSAVE)
572 return 3;
573 else
574 return 4;
575 } else if (static_cpu_has(X86_FEATURE_EPB)) {
576 /*
577 * Range:
578 * 0x00-0x03 : Performance
579 * 0x04-0x07 : Balance performance
580 * 0x08-0x0B : Balance power
581 * 0x0C-0x0F : Power
582 * The EPB is a 4 bit value, but our ranges restrict the
583 * value which can be set. Here only using top two bits
584 * effectively.
585 */
586 index = (epp >> 2) + 1;
587 }
588
589 return index;
590 }
591
592 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
593 int pref_index)
594 {
595 int epp = -EINVAL;
596 int ret;
597
598 if (!pref_index)
599 epp = cpu_data->epp_default;
600
601 mutex_lock(&intel_pstate_limits_lock);
602
603 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
604 u64 value;
605
606 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
607 if (ret)
608 goto return_pref;
609
610 value &= ~GENMASK_ULL(31, 24);
611
612 if (epp == -EINVAL)
613 epp = epp_values[pref_index - 1];
614
615 value |= (u64)epp << 24;
616 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
617 } else {
618 if (epp == -EINVAL)
619 epp = (pref_index - 1) << 2;
620 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
621 }
622 return_pref:
623 mutex_unlock(&intel_pstate_limits_lock);
624
625 return ret;
626 }
627
628 static ssize_t show_energy_performance_available_preferences(
629 struct cpufreq_policy *policy, char *buf)
630 {
631 int i = 0;
632 int ret = 0;
633
634 while (energy_perf_strings[i] != NULL)
635 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
636
637 ret += sprintf(&buf[ret], "\n");
638
639 return ret;
640 }
641
642 cpufreq_freq_attr_ro(energy_performance_available_preferences);
643
644 static ssize_t store_energy_performance_preference(
645 struct cpufreq_policy *policy, const char *buf, size_t count)
646 {
647 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
648 char str_preference[21];
649 int ret, i = 0;
650
651 ret = sscanf(buf, "%20s", str_preference);
652 if (ret != 1)
653 return -EINVAL;
654
655 while (energy_perf_strings[i] != NULL) {
656 if (!strcmp(str_preference, energy_perf_strings[i])) {
657 intel_pstate_set_energy_pref_index(cpu_data, i);
658 return count;
659 }
660 ++i;
661 }
662
663 return -EINVAL;
664 }
665
666 static ssize_t show_energy_performance_preference(
667 struct cpufreq_policy *policy, char *buf)
668 {
669 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
670 int preference;
671
672 preference = intel_pstate_get_energy_pref_index(cpu_data);
673 if (preference < 0)
674 return preference;
675
676 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
677 }
678
679 cpufreq_freq_attr_rw(energy_performance_preference);
680
681 static struct freq_attr *hwp_cpufreq_attrs[] = {
682 &energy_performance_preference,
683 &energy_performance_available_preferences,
684 NULL,
685 };
686
687 static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max,
688 int *current_max)
689 {
690 u64 cap;
691
692 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
693 if (global.no_turbo)
694 *current_max = HWP_GUARANTEED_PERF(cap);
695 else
696 *current_max = HWP_HIGHEST_PERF(cap);
697
698 *phy_max = HWP_HIGHEST_PERF(cap);
699 }
700
701 static void intel_pstate_hwp_set(unsigned int cpu)
702 {
703 struct cpudata *cpu_data = all_cpu_data[cpu];
704 int max, min;
705 u64 value;
706 s16 epp;
707
708 max = cpu_data->max_perf_ratio;
709 min = cpu_data->min_perf_ratio;
710
711 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
712 min = max;
713
714 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
715
716 value &= ~HWP_MIN_PERF(~0L);
717 value |= HWP_MIN_PERF(min);
718
719 value &= ~HWP_MAX_PERF(~0L);
720 value |= HWP_MAX_PERF(max);
721
722 if (cpu_data->epp_policy == cpu_data->policy)
723 goto skip_epp;
724
725 cpu_data->epp_policy = cpu_data->policy;
726
727 if (cpu_data->epp_saved >= 0) {
728 epp = cpu_data->epp_saved;
729 cpu_data->epp_saved = -EINVAL;
730 goto update_epp;
731 }
732
733 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
734 epp = intel_pstate_get_epp(cpu_data, value);
735 cpu_data->epp_powersave = epp;
736 /* If EPP read was failed, then don't try to write */
737 if (epp < 0)
738 goto skip_epp;
739
740 epp = 0;
741 } else {
742 /* skip setting EPP, when saved value is invalid */
743 if (cpu_data->epp_powersave < 0)
744 goto skip_epp;
745
746 /*
747 * No need to restore EPP when it is not zero. This
748 * means:
749 * - Policy is not changed
750 * - user has manually changed
751 * - Error reading EPB
752 */
753 epp = intel_pstate_get_epp(cpu_data, value);
754 if (epp)
755 goto skip_epp;
756
757 epp = cpu_data->epp_powersave;
758 }
759 update_epp:
760 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
761 value &= ~GENMASK_ULL(31, 24);
762 value |= (u64)epp << 24;
763 } else {
764 intel_pstate_set_epb(cpu, epp);
765 }
766 skip_epp:
767 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
768 }
769
770 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
771 {
772 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
773
774 if (!hwp_active)
775 return 0;
776
777 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
778
779 return 0;
780 }
781
782 static void intel_pstate_hwp_enable(struct cpudata *cpudata);
783
784 static int intel_pstate_resume(struct cpufreq_policy *policy)
785 {
786 if (!hwp_active)
787 return 0;
788
789 mutex_lock(&intel_pstate_limits_lock);
790
791 if (policy->cpu == 0)
792 intel_pstate_hwp_enable(all_cpu_data[policy->cpu]);
793
794 all_cpu_data[policy->cpu]->epp_policy = 0;
795 intel_pstate_hwp_set(policy->cpu);
796
797 mutex_unlock(&intel_pstate_limits_lock);
798
799 return 0;
800 }
801
802 static void intel_pstate_update_policies(void)
803 {
804 int cpu;
805
806 for_each_possible_cpu(cpu)
807 cpufreq_update_policy(cpu);
808 }
809
810 /************************** sysfs begin ************************/
811 #define show_one(file_name, object) \
812 static ssize_t show_##file_name \
813 (struct kobject *kobj, struct attribute *attr, char *buf) \
814 { \
815 return sprintf(buf, "%u\n", global.object); \
816 }
817
818 static ssize_t intel_pstate_show_status(char *buf);
819 static int intel_pstate_update_status(const char *buf, size_t size);
820
821 static ssize_t show_status(struct kobject *kobj,
822 struct attribute *attr, char *buf)
823 {
824 ssize_t ret;
825
826 mutex_lock(&intel_pstate_driver_lock);
827 ret = intel_pstate_show_status(buf);
828 mutex_unlock(&intel_pstate_driver_lock);
829
830 return ret;
831 }
832
833 static ssize_t store_status(struct kobject *a, struct attribute *b,
834 const char *buf, size_t count)
835 {
836 char *p = memchr(buf, '\n', count);
837 int ret;
838
839 mutex_lock(&intel_pstate_driver_lock);
840 ret = intel_pstate_update_status(buf, p ? p - buf : count);
841 mutex_unlock(&intel_pstate_driver_lock);
842
843 return ret < 0 ? ret : count;
844 }
845
846 static ssize_t show_turbo_pct(struct kobject *kobj,
847 struct attribute *attr, char *buf)
848 {
849 struct cpudata *cpu;
850 int total, no_turbo, turbo_pct;
851 uint32_t turbo_fp;
852
853 mutex_lock(&intel_pstate_driver_lock);
854
855 if (!intel_pstate_driver) {
856 mutex_unlock(&intel_pstate_driver_lock);
857 return -EAGAIN;
858 }
859
860 cpu = all_cpu_data[0];
861
862 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
863 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
864 turbo_fp = div_fp(no_turbo, total);
865 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
866
867 mutex_unlock(&intel_pstate_driver_lock);
868
869 return sprintf(buf, "%u\n", turbo_pct);
870 }
871
872 static ssize_t show_num_pstates(struct kobject *kobj,
873 struct attribute *attr, char *buf)
874 {
875 struct cpudata *cpu;
876 int total;
877
878 mutex_lock(&intel_pstate_driver_lock);
879
880 if (!intel_pstate_driver) {
881 mutex_unlock(&intel_pstate_driver_lock);
882 return -EAGAIN;
883 }
884
885 cpu = all_cpu_data[0];
886 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
887
888 mutex_unlock(&intel_pstate_driver_lock);
889
890 return sprintf(buf, "%u\n", total);
891 }
892
893 static ssize_t show_no_turbo(struct kobject *kobj,
894 struct attribute *attr, char *buf)
895 {
896 ssize_t ret;
897
898 mutex_lock(&intel_pstate_driver_lock);
899
900 if (!intel_pstate_driver) {
901 mutex_unlock(&intel_pstate_driver_lock);
902 return -EAGAIN;
903 }
904
905 update_turbo_state();
906 if (global.turbo_disabled)
907 ret = sprintf(buf, "%u\n", global.turbo_disabled);
908 else
909 ret = sprintf(buf, "%u\n", global.no_turbo);
910
911 mutex_unlock(&intel_pstate_driver_lock);
912
913 return ret;
914 }
915
916 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
917 const char *buf, size_t count)
918 {
919 unsigned int input;
920 int ret;
921
922 ret = sscanf(buf, "%u", &input);
923 if (ret != 1)
924 return -EINVAL;
925
926 mutex_lock(&intel_pstate_driver_lock);
927
928 if (!intel_pstate_driver) {
929 mutex_unlock(&intel_pstate_driver_lock);
930 return -EAGAIN;
931 }
932
933 mutex_lock(&intel_pstate_limits_lock);
934
935 update_turbo_state();
936 if (global.turbo_disabled) {
937 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
938 mutex_unlock(&intel_pstate_limits_lock);
939 mutex_unlock(&intel_pstate_driver_lock);
940 return -EPERM;
941 }
942
943 global.no_turbo = clamp_t(int, input, 0, 1);
944
945 if (global.no_turbo) {
946 struct cpudata *cpu = all_cpu_data[0];
947 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
948
949 /* Squash the global minimum into the permitted range. */
950 if (global.min_perf_pct > pct)
951 global.min_perf_pct = pct;
952 }
953
954 mutex_unlock(&intel_pstate_limits_lock);
955
956 intel_pstate_update_policies();
957
958 mutex_unlock(&intel_pstate_driver_lock);
959
960 return count;
961 }
962
963 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
964 const char *buf, size_t count)
965 {
966 unsigned int input;
967 int ret;
968
969 ret = sscanf(buf, "%u", &input);
970 if (ret != 1)
971 return -EINVAL;
972
973 mutex_lock(&intel_pstate_driver_lock);
974
975 if (!intel_pstate_driver) {
976 mutex_unlock(&intel_pstate_driver_lock);
977 return -EAGAIN;
978 }
979
980 mutex_lock(&intel_pstate_limits_lock);
981
982 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
983
984 mutex_unlock(&intel_pstate_limits_lock);
985
986 intel_pstate_update_policies();
987
988 mutex_unlock(&intel_pstate_driver_lock);
989
990 return count;
991 }
992
993 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
994 const char *buf, size_t count)
995 {
996 unsigned int input;
997 int ret;
998
999 ret = sscanf(buf, "%u", &input);
1000 if (ret != 1)
1001 return -EINVAL;
1002
1003 mutex_lock(&intel_pstate_driver_lock);
1004
1005 if (!intel_pstate_driver) {
1006 mutex_unlock(&intel_pstate_driver_lock);
1007 return -EAGAIN;
1008 }
1009
1010 mutex_lock(&intel_pstate_limits_lock);
1011
1012 global.min_perf_pct = clamp_t(int, input,
1013 min_perf_pct_min(), global.max_perf_pct);
1014
1015 mutex_unlock(&intel_pstate_limits_lock);
1016
1017 intel_pstate_update_policies();
1018
1019 mutex_unlock(&intel_pstate_driver_lock);
1020
1021 return count;
1022 }
1023
1024 show_one(max_perf_pct, max_perf_pct);
1025 show_one(min_perf_pct, min_perf_pct);
1026
1027 define_one_global_rw(status);
1028 define_one_global_rw(no_turbo);
1029 define_one_global_rw(max_perf_pct);
1030 define_one_global_rw(min_perf_pct);
1031 define_one_global_ro(turbo_pct);
1032 define_one_global_ro(num_pstates);
1033
1034 static struct attribute *intel_pstate_attributes[] = {
1035 &status.attr,
1036 &no_turbo.attr,
1037 &turbo_pct.attr,
1038 &num_pstates.attr,
1039 NULL
1040 };
1041
1042 static const struct attribute_group intel_pstate_attr_group = {
1043 .attrs = intel_pstate_attributes,
1044 };
1045
1046 static void __init intel_pstate_sysfs_expose_params(void)
1047 {
1048 struct kobject *intel_pstate_kobject;
1049 int rc;
1050
1051 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1052 &cpu_subsys.dev_root->kobj);
1053 if (WARN_ON(!intel_pstate_kobject))
1054 return;
1055
1056 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1057 if (WARN_ON(rc))
1058 return;
1059
1060 /*
1061 * If per cpu limits are enforced there are no global limits, so
1062 * return without creating max/min_perf_pct attributes
1063 */
1064 if (per_cpu_limits)
1065 return;
1066
1067 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1068 WARN_ON(rc);
1069
1070 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1071 WARN_ON(rc);
1072
1073 }
1074 /************************** sysfs end ************************/
1075
1076 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1077 {
1078 /* First disable HWP notification interrupt as we don't process them */
1079 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1080 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1081
1082 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1083 cpudata->epp_policy = 0;
1084 if (cpudata->epp_default == -EINVAL)
1085 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1086 }
1087
1088 #define MSR_IA32_POWER_CTL_BIT_EE 19
1089
1090 /* Disable energy efficiency optimization */
1091 static void intel_pstate_disable_ee(int cpu)
1092 {
1093 u64 power_ctl;
1094 int ret;
1095
1096 ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1097 if (ret)
1098 return;
1099
1100 if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1101 pr_info("Disabling energy efficiency optimization\n");
1102 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1103 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1104 }
1105 }
1106
1107 static int atom_get_min_pstate(void)
1108 {
1109 u64 value;
1110
1111 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1112 return (value >> 8) & 0x7F;
1113 }
1114
1115 static int atom_get_max_pstate(void)
1116 {
1117 u64 value;
1118
1119 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1120 return (value >> 16) & 0x7F;
1121 }
1122
1123 static int atom_get_turbo_pstate(void)
1124 {
1125 u64 value;
1126
1127 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1128 return value & 0x7F;
1129 }
1130
1131 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1132 {
1133 u64 val;
1134 int32_t vid_fp;
1135 u32 vid;
1136
1137 val = (u64)pstate << 8;
1138 if (global.no_turbo && !global.turbo_disabled)
1139 val |= (u64)1 << 32;
1140
1141 vid_fp = cpudata->vid.min + mul_fp(
1142 int_tofp(pstate - cpudata->pstate.min_pstate),
1143 cpudata->vid.ratio);
1144
1145 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1146 vid = ceiling_fp(vid_fp);
1147
1148 if (pstate > cpudata->pstate.max_pstate)
1149 vid = cpudata->vid.turbo;
1150
1151 return val | vid;
1152 }
1153
1154 static int silvermont_get_scaling(void)
1155 {
1156 u64 value;
1157 int i;
1158 /* Defined in Table 35-6 from SDM (Sept 2015) */
1159 static int silvermont_freq_table[] = {
1160 83300, 100000, 133300, 116700, 80000};
1161
1162 rdmsrl(MSR_FSB_FREQ, value);
1163 i = value & 0x7;
1164 WARN_ON(i > 4);
1165
1166 return silvermont_freq_table[i];
1167 }
1168
1169 static int airmont_get_scaling(void)
1170 {
1171 u64 value;
1172 int i;
1173 /* Defined in Table 35-10 from SDM (Sept 2015) */
1174 static int airmont_freq_table[] = {
1175 83300, 100000, 133300, 116700, 80000,
1176 93300, 90000, 88900, 87500};
1177
1178 rdmsrl(MSR_FSB_FREQ, value);
1179 i = value & 0xF;
1180 WARN_ON(i > 8);
1181
1182 return airmont_freq_table[i];
1183 }
1184
1185 static void atom_get_vid(struct cpudata *cpudata)
1186 {
1187 u64 value;
1188
1189 rdmsrl(MSR_ATOM_CORE_VIDS, value);
1190 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1191 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1192 cpudata->vid.ratio = div_fp(
1193 cpudata->vid.max - cpudata->vid.min,
1194 int_tofp(cpudata->pstate.max_pstate -
1195 cpudata->pstate.min_pstate));
1196
1197 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1198 cpudata->vid.turbo = value & 0x7f;
1199 }
1200
1201 static int core_get_min_pstate(void)
1202 {
1203 u64 value;
1204
1205 rdmsrl(MSR_PLATFORM_INFO, value);
1206 return (value >> 40) & 0xFF;
1207 }
1208
1209 static int core_get_max_pstate_physical(void)
1210 {
1211 u64 value;
1212
1213 rdmsrl(MSR_PLATFORM_INFO, value);
1214 return (value >> 8) & 0xFF;
1215 }
1216
1217 static int core_get_tdp_ratio(u64 plat_info)
1218 {
1219 /* Check how many TDP levels present */
1220 if (plat_info & 0x600000000) {
1221 u64 tdp_ctrl;
1222 u64 tdp_ratio;
1223 int tdp_msr;
1224 int err;
1225
1226 /* Get the TDP level (0, 1, 2) to get ratios */
1227 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1228 if (err)
1229 return err;
1230
1231 /* TDP MSR are continuous starting at 0x648 */
1232 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1233 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1234 if (err)
1235 return err;
1236
1237 /* For level 1 and 2, bits[23:16] contain the ratio */
1238 if (tdp_ctrl & 0x03)
1239 tdp_ratio >>= 16;
1240
1241 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1242 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1243
1244 return (int)tdp_ratio;
1245 }
1246
1247 return -ENXIO;
1248 }
1249
1250 static int core_get_max_pstate(void)
1251 {
1252 u64 tar;
1253 u64 plat_info;
1254 int max_pstate;
1255 int tdp_ratio;
1256 int err;
1257
1258 rdmsrl(MSR_PLATFORM_INFO, plat_info);
1259 max_pstate = (plat_info >> 8) & 0xFF;
1260
1261 tdp_ratio = core_get_tdp_ratio(plat_info);
1262 if (tdp_ratio <= 0)
1263 return max_pstate;
1264
1265 if (hwp_active) {
1266 /* Turbo activation ratio is not used on HWP platforms */
1267 return tdp_ratio;
1268 }
1269
1270 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1271 if (!err) {
1272 int tar_levels;
1273
1274 /* Do some sanity checking for safety */
1275 tar_levels = tar & 0xff;
1276 if (tdp_ratio - 1 == tar_levels) {
1277 max_pstate = tar_levels;
1278 pr_debug("max_pstate=TAC %x\n", max_pstate);
1279 }
1280 }
1281
1282 return max_pstate;
1283 }
1284
1285 static int core_get_turbo_pstate(void)
1286 {
1287 u64 value;
1288 int nont, ret;
1289
1290 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1291 nont = core_get_max_pstate();
1292 ret = (value) & 255;
1293 if (ret <= nont)
1294 ret = nont;
1295 return ret;
1296 }
1297
1298 static inline int core_get_scaling(void)
1299 {
1300 return 100000;
1301 }
1302
1303 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1304 {
1305 u64 val;
1306
1307 val = (u64)pstate << 8;
1308 if (global.no_turbo && !global.turbo_disabled)
1309 val |= (u64)1 << 32;
1310
1311 return val;
1312 }
1313
1314 static int knl_get_aperf_mperf_shift(void)
1315 {
1316 return 10;
1317 }
1318
1319 static int knl_get_turbo_pstate(void)
1320 {
1321 u64 value;
1322 int nont, ret;
1323
1324 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1325 nont = core_get_max_pstate();
1326 ret = (((value) >> 8) & 0xFF);
1327 if (ret <= nont)
1328 ret = nont;
1329 return ret;
1330 }
1331
1332 static int intel_pstate_get_base_pstate(struct cpudata *cpu)
1333 {
1334 return global.no_turbo || global.turbo_disabled ?
1335 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1336 }
1337
1338 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1339 {
1340 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1341 cpu->pstate.current_pstate = pstate;
1342 /*
1343 * Generally, there is no guarantee that this code will always run on
1344 * the CPU being updated, so force the register update to run on the
1345 * right CPU.
1346 */
1347 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1348 pstate_funcs.get_val(cpu, pstate));
1349 }
1350
1351 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1352 {
1353 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1354 }
1355
1356 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1357 {
1358 int pstate;
1359
1360 update_turbo_state();
1361 pstate = intel_pstate_get_base_pstate(cpu);
1362 pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
1363 intel_pstate_set_pstate(cpu, pstate);
1364 }
1365
1366 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1367 {
1368 cpu->pstate.min_pstate = pstate_funcs.get_min();
1369 cpu->pstate.max_pstate = pstate_funcs.get_max();
1370 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1371 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1372 cpu->pstate.scaling = pstate_funcs.get_scaling();
1373 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1374 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1375
1376 if (pstate_funcs.get_aperf_mperf_shift)
1377 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
1378
1379 if (pstate_funcs.get_vid)
1380 pstate_funcs.get_vid(cpu);
1381
1382 intel_pstate_set_min_pstate(cpu);
1383 }
1384
1385 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1386 {
1387 struct sample *sample = &cpu->sample;
1388
1389 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1390 }
1391
1392 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1393 {
1394 u64 aperf, mperf;
1395 unsigned long flags;
1396 u64 tsc;
1397
1398 local_irq_save(flags);
1399 rdmsrl(MSR_IA32_APERF, aperf);
1400 rdmsrl(MSR_IA32_MPERF, mperf);
1401 tsc = rdtsc();
1402 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1403 local_irq_restore(flags);
1404 return false;
1405 }
1406 local_irq_restore(flags);
1407
1408 cpu->last_sample_time = cpu->sample.time;
1409 cpu->sample.time = time;
1410 cpu->sample.aperf = aperf;
1411 cpu->sample.mperf = mperf;
1412 cpu->sample.tsc = tsc;
1413 cpu->sample.aperf -= cpu->prev_aperf;
1414 cpu->sample.mperf -= cpu->prev_mperf;
1415 cpu->sample.tsc -= cpu->prev_tsc;
1416
1417 cpu->prev_aperf = aperf;
1418 cpu->prev_mperf = mperf;
1419 cpu->prev_tsc = tsc;
1420 /*
1421 * First time this function is invoked in a given cycle, all of the
1422 * previous sample data fields are equal to zero or stale and they must
1423 * be populated with meaningful numbers for things to work, so assume
1424 * that sample.time will always be reset before setting the utilization
1425 * update hook and make the caller skip the sample then.
1426 */
1427 if (cpu->last_sample_time) {
1428 intel_pstate_calc_avg_perf(cpu);
1429 return true;
1430 }
1431 return false;
1432 }
1433
1434 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1435 {
1436 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
1437 }
1438
1439 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1440 {
1441 return mul_ext_fp(cpu->pstate.max_pstate_physical,
1442 cpu->sample.core_avg_perf);
1443 }
1444
1445 static inline int32_t get_target_pstate(struct cpudata *cpu)
1446 {
1447 struct sample *sample = &cpu->sample;
1448 int32_t busy_frac, boost;
1449 int target, avg_pstate;
1450
1451 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
1452 sample->tsc);
1453
1454 boost = cpu->iowait_boost;
1455 cpu->iowait_boost >>= 1;
1456
1457 if (busy_frac < boost)
1458 busy_frac = boost;
1459
1460 sample->busy_scaled = busy_frac * 100;
1461
1462 target = global.no_turbo || global.turbo_disabled ?
1463 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1464 target += target >> 2;
1465 target = mul_fp(target, busy_frac);
1466 if (target < cpu->pstate.min_pstate)
1467 target = cpu->pstate.min_pstate;
1468
1469 /*
1470 * If the average P-state during the previous cycle was higher than the
1471 * current target, add 50% of the difference to the target to reduce
1472 * possible performance oscillations and offset possible performance
1473 * loss related to moving the workload from one CPU to another within
1474 * a package/module.
1475 */
1476 avg_pstate = get_avg_pstate(cpu);
1477 if (avg_pstate > target)
1478 target += (avg_pstate - target) >> 1;
1479
1480 return target;
1481 }
1482
1483 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1484 {
1485 int max_pstate = intel_pstate_get_base_pstate(cpu);
1486 int min_pstate;
1487
1488 min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
1489 max_pstate = max(min_pstate, cpu->max_perf_ratio);
1490 return clamp_t(int, pstate, min_pstate, max_pstate);
1491 }
1492
1493 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1494 {
1495 if (pstate == cpu->pstate.current_pstate)
1496 return;
1497
1498 cpu->pstate.current_pstate = pstate;
1499 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1500 }
1501
1502 static void intel_pstate_adjust_pstate(struct cpudata *cpu)
1503 {
1504 int from = cpu->pstate.current_pstate;
1505 struct sample *sample;
1506 int target_pstate;
1507
1508 update_turbo_state();
1509
1510 target_pstate = get_target_pstate(cpu);
1511 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1512 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1513 intel_pstate_update_pstate(cpu, target_pstate);
1514
1515 sample = &cpu->sample;
1516 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1517 fp_toint(sample->busy_scaled),
1518 from,
1519 cpu->pstate.current_pstate,
1520 sample->mperf,
1521 sample->aperf,
1522 sample->tsc,
1523 get_avg_frequency(cpu),
1524 fp_toint(cpu->iowait_boost * 100));
1525 }
1526
1527 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1528 unsigned int flags)
1529 {
1530 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1531 u64 delta_ns;
1532
1533 /* Don't allow remote callbacks */
1534 if (smp_processor_id() != cpu->cpu)
1535 return;
1536
1537 if (flags & SCHED_CPUFREQ_IOWAIT) {
1538 cpu->iowait_boost = int_tofp(1);
1539 cpu->last_update = time;
1540 /*
1541 * The last time the busy was 100% so P-state was max anyway
1542 * so avoid overhead of computation.
1543 */
1544 if (fp_toint(cpu->sample.busy_scaled) == 100)
1545 return;
1546
1547 goto set_pstate;
1548 } else if (cpu->iowait_boost) {
1549 /* Clear iowait_boost if the CPU may have been idle. */
1550 delta_ns = time - cpu->last_update;
1551 if (delta_ns > TICK_NSEC)
1552 cpu->iowait_boost = 0;
1553 }
1554 cpu->last_update = time;
1555 delta_ns = time - cpu->sample.time;
1556 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
1557 return;
1558
1559 set_pstate:
1560 if (intel_pstate_sample(cpu, time))
1561 intel_pstate_adjust_pstate(cpu);
1562 }
1563
1564 static struct pstate_funcs core_funcs = {
1565 .get_max = core_get_max_pstate,
1566 .get_max_physical = core_get_max_pstate_physical,
1567 .get_min = core_get_min_pstate,
1568 .get_turbo = core_get_turbo_pstate,
1569 .get_scaling = core_get_scaling,
1570 .get_val = core_get_val,
1571 };
1572
1573 static const struct pstate_funcs silvermont_funcs = {
1574 .get_max = atom_get_max_pstate,
1575 .get_max_physical = atom_get_max_pstate,
1576 .get_min = atom_get_min_pstate,
1577 .get_turbo = atom_get_turbo_pstate,
1578 .get_val = atom_get_val,
1579 .get_scaling = silvermont_get_scaling,
1580 .get_vid = atom_get_vid,
1581 };
1582
1583 static const struct pstate_funcs airmont_funcs = {
1584 .get_max = atom_get_max_pstate,
1585 .get_max_physical = atom_get_max_pstate,
1586 .get_min = atom_get_min_pstate,
1587 .get_turbo = atom_get_turbo_pstate,
1588 .get_val = atom_get_val,
1589 .get_scaling = airmont_get_scaling,
1590 .get_vid = atom_get_vid,
1591 };
1592
1593 static const struct pstate_funcs knl_funcs = {
1594 .get_max = core_get_max_pstate,
1595 .get_max_physical = core_get_max_pstate_physical,
1596 .get_min = core_get_min_pstate,
1597 .get_turbo = knl_get_turbo_pstate,
1598 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
1599 .get_scaling = core_get_scaling,
1600 .get_val = core_get_val,
1601 };
1602
1603 static const struct pstate_funcs bxt_funcs = {
1604 .get_max = core_get_max_pstate,
1605 .get_max_physical = core_get_max_pstate_physical,
1606 .get_min = core_get_min_pstate,
1607 .get_turbo = core_get_turbo_pstate,
1608 .get_scaling = core_get_scaling,
1609 .get_val = core_get_val,
1610 };
1611
1612 #define ICPU(model, policy) \
1613 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1614 (unsigned long)&policy }
1615
1616 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1617 ICPU(INTEL_FAM6_SANDYBRIDGE, core_funcs),
1618 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_funcs),
1619 ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_funcs),
1620 ICPU(INTEL_FAM6_IVYBRIDGE, core_funcs),
1621 ICPU(INTEL_FAM6_HASWELL_CORE, core_funcs),
1622 ICPU(INTEL_FAM6_BROADWELL_CORE, core_funcs),
1623 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_funcs),
1624 ICPU(INTEL_FAM6_HASWELL_X, core_funcs),
1625 ICPU(INTEL_FAM6_HASWELL_ULT, core_funcs),
1626 ICPU(INTEL_FAM6_HASWELL_GT3E, core_funcs),
1627 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_funcs),
1628 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_funcs),
1629 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_funcs),
1630 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1631 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
1632 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1633 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_funcs),
1634 ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_funcs),
1635 ICPU(INTEL_FAM6_ATOM_GOLDMONT, bxt_funcs),
1636 ICPU(INTEL_FAM6_ATOM_GEMINI_LAKE, bxt_funcs),
1637 {}
1638 };
1639 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1640
1641 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1642 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1643 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1644 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1645 {}
1646 };
1647
1648 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1649 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_funcs),
1650 {}
1651 };
1652
1653 static int intel_pstate_init_cpu(unsigned int cpunum)
1654 {
1655 struct cpudata *cpu;
1656
1657 cpu = all_cpu_data[cpunum];
1658
1659 if (!cpu) {
1660 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
1661 if (!cpu)
1662 return -ENOMEM;
1663
1664 all_cpu_data[cpunum] = cpu;
1665
1666 cpu->epp_default = -EINVAL;
1667 cpu->epp_powersave = -EINVAL;
1668 cpu->epp_saved = -EINVAL;
1669 }
1670
1671 cpu = all_cpu_data[cpunum];
1672
1673 cpu->cpu = cpunum;
1674
1675 if (hwp_active) {
1676 const struct x86_cpu_id *id;
1677
1678 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
1679 if (id)
1680 intel_pstate_disable_ee(cpunum);
1681
1682 intel_pstate_hwp_enable(cpu);
1683 }
1684
1685 intel_pstate_get_cpu_pstates(cpu);
1686
1687 pr_debug("controlling: cpu %d\n", cpunum);
1688
1689 return 0;
1690 }
1691
1692 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
1693 {
1694 struct cpudata *cpu = all_cpu_data[cpu_num];
1695
1696 if (hwp_active)
1697 return;
1698
1699 if (cpu->update_util_set)
1700 return;
1701
1702 /* Prevent intel_pstate_update_util() from using stale data. */
1703 cpu->sample.time = 0;
1704 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1705 intel_pstate_update_util);
1706 cpu->update_util_set = true;
1707 }
1708
1709 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1710 {
1711 struct cpudata *cpu_data = all_cpu_data[cpu];
1712
1713 if (!cpu_data->update_util_set)
1714 return;
1715
1716 cpufreq_remove_update_util_hook(cpu);
1717 cpu_data->update_util_set = false;
1718 synchronize_sched();
1719 }
1720
1721 static int intel_pstate_get_max_freq(struct cpudata *cpu)
1722 {
1723 return global.turbo_disabled || global.no_turbo ?
1724 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
1725 }
1726
1727 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
1728 struct cpudata *cpu)
1729 {
1730 int max_freq = intel_pstate_get_max_freq(cpu);
1731 int32_t max_policy_perf, min_policy_perf;
1732 int max_state, turbo_max;
1733
1734 /*
1735 * HWP needs some special consideration, because on BDX the
1736 * HWP_REQUEST uses abstract value to represent performance
1737 * rather than pure ratios.
1738 */
1739 if (hwp_active) {
1740 intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state);
1741 } else {
1742 max_state = intel_pstate_get_base_pstate(cpu);
1743 turbo_max = cpu->pstate.turbo_pstate;
1744 }
1745
1746 max_policy_perf = max_state * policy->max / max_freq;
1747 if (policy->max == policy->min) {
1748 min_policy_perf = max_policy_perf;
1749 } else {
1750 min_policy_perf = max_state * policy->min / max_freq;
1751 min_policy_perf = clamp_t(int32_t, min_policy_perf,
1752 0, max_policy_perf);
1753 }
1754
1755 pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n",
1756 policy->cpu, max_state,
1757 min_policy_perf, max_policy_perf);
1758
1759 /* Normalize user input to [min_perf, max_perf] */
1760 if (per_cpu_limits) {
1761 cpu->min_perf_ratio = min_policy_perf;
1762 cpu->max_perf_ratio = max_policy_perf;
1763 } else {
1764 int32_t global_min, global_max;
1765
1766 /* Global limits are in percent of the maximum turbo P-state. */
1767 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
1768 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
1769 global_min = clamp_t(int32_t, global_min, 0, global_max);
1770
1771 pr_debug("cpu:%d global_min:%d global_max:%d\n", policy->cpu,
1772 global_min, global_max);
1773
1774 cpu->min_perf_ratio = max(min_policy_perf, global_min);
1775 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
1776 cpu->max_perf_ratio = min(max_policy_perf, global_max);
1777 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
1778
1779 /* Make sure min_perf <= max_perf */
1780 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
1781 cpu->max_perf_ratio);
1782
1783 }
1784 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", policy->cpu,
1785 cpu->max_perf_ratio,
1786 cpu->min_perf_ratio);
1787 }
1788
1789 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
1790 {
1791 struct cpudata *cpu;
1792
1793 if (!policy->cpuinfo.max_freq)
1794 return -ENODEV;
1795
1796 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
1797 policy->cpuinfo.max_freq, policy->max);
1798
1799 cpu = all_cpu_data[policy->cpu];
1800 cpu->policy = policy->policy;
1801
1802 mutex_lock(&intel_pstate_limits_lock);
1803
1804 intel_pstate_update_perf_limits(policy, cpu);
1805
1806 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
1807 /*
1808 * NOHZ_FULL CPUs need this as the governor callback may not
1809 * be invoked on them.
1810 */
1811 intel_pstate_clear_update_util_hook(policy->cpu);
1812 intel_pstate_max_within_limits(cpu);
1813 } else {
1814 intel_pstate_set_update_util_hook(policy->cpu);
1815 }
1816
1817 if (hwp_active)
1818 intel_pstate_hwp_set(policy->cpu);
1819
1820 mutex_unlock(&intel_pstate_limits_lock);
1821
1822 return 0;
1823 }
1824
1825 static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy,
1826 struct cpudata *cpu)
1827 {
1828 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
1829 policy->max < policy->cpuinfo.max_freq &&
1830 policy->max > cpu->pstate.max_freq) {
1831 pr_debug("policy->max > max non turbo frequency\n");
1832 policy->max = policy->cpuinfo.max_freq;
1833 }
1834 }
1835
1836 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
1837 {
1838 struct cpudata *cpu = all_cpu_data[policy->cpu];
1839
1840 update_turbo_state();
1841 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
1842 intel_pstate_get_max_freq(cpu));
1843
1844 if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
1845 policy->policy != CPUFREQ_POLICY_PERFORMANCE)
1846 return -EINVAL;
1847
1848 intel_pstate_adjust_policy_max(policy, cpu);
1849
1850 return 0;
1851 }
1852
1853 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
1854 {
1855 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
1856 }
1857
1858 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
1859 {
1860 pr_debug("CPU %d exiting\n", policy->cpu);
1861
1862 intel_pstate_clear_update_util_hook(policy->cpu);
1863 if (hwp_active)
1864 intel_pstate_hwp_save_state(policy);
1865 else
1866 intel_cpufreq_stop_cpu(policy);
1867 }
1868
1869 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
1870 {
1871 intel_pstate_exit_perf_limits(policy);
1872
1873 policy->fast_switch_possible = false;
1874
1875 return 0;
1876 }
1877
1878 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
1879 {
1880 struct cpudata *cpu;
1881 int rc;
1882
1883 rc = intel_pstate_init_cpu(policy->cpu);
1884 if (rc)
1885 return rc;
1886
1887 cpu = all_cpu_data[policy->cpu];
1888
1889 cpu->max_perf_ratio = 0xFF;
1890 cpu->min_perf_ratio = 0;
1891
1892 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
1893 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1894
1895 /* cpuinfo and default policy values */
1896 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
1897 update_turbo_state();
1898 policy->cpuinfo.max_freq = global.turbo_disabled ?
1899 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1900 policy->cpuinfo.max_freq *= cpu->pstate.scaling;
1901
1902 intel_pstate_init_acpi_perf_limits(policy);
1903
1904 policy->fast_switch_possible = true;
1905
1906 return 0;
1907 }
1908
1909 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
1910 {
1911 int ret = __intel_pstate_cpu_init(policy);
1912
1913 if (ret)
1914 return ret;
1915
1916 if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
1917 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
1918 else
1919 policy->policy = CPUFREQ_POLICY_POWERSAVE;
1920
1921 return 0;
1922 }
1923
1924 static struct cpufreq_driver intel_pstate = {
1925 .flags = CPUFREQ_CONST_LOOPS,
1926 .verify = intel_pstate_verify_policy,
1927 .setpolicy = intel_pstate_set_policy,
1928 .suspend = intel_pstate_hwp_save_state,
1929 .resume = intel_pstate_resume,
1930 .init = intel_pstate_cpu_init,
1931 .exit = intel_pstate_cpu_exit,
1932 .stop_cpu = intel_pstate_stop_cpu,
1933 .name = "intel_pstate",
1934 };
1935
1936 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
1937 {
1938 struct cpudata *cpu = all_cpu_data[policy->cpu];
1939
1940 update_turbo_state();
1941 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
1942 intel_pstate_get_max_freq(cpu));
1943
1944 intel_pstate_adjust_policy_max(policy, cpu);
1945
1946 intel_pstate_update_perf_limits(policy, cpu);
1947
1948 return 0;
1949 }
1950
1951 static int intel_cpufreq_target(struct cpufreq_policy *policy,
1952 unsigned int target_freq,
1953 unsigned int relation)
1954 {
1955 struct cpudata *cpu = all_cpu_data[policy->cpu];
1956 struct cpufreq_freqs freqs;
1957 int target_pstate;
1958
1959 update_turbo_state();
1960
1961 freqs.old = policy->cur;
1962 freqs.new = target_freq;
1963
1964 cpufreq_freq_transition_begin(policy, &freqs);
1965 switch (relation) {
1966 case CPUFREQ_RELATION_L:
1967 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
1968 break;
1969 case CPUFREQ_RELATION_H:
1970 target_pstate = freqs.new / cpu->pstate.scaling;
1971 break;
1972 default:
1973 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
1974 break;
1975 }
1976 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1977 if (target_pstate != cpu->pstate.current_pstate) {
1978 cpu->pstate.current_pstate = target_pstate;
1979 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
1980 pstate_funcs.get_val(cpu, target_pstate));
1981 }
1982 freqs.new = target_pstate * cpu->pstate.scaling;
1983 cpufreq_freq_transition_end(policy, &freqs, false);
1984
1985 return 0;
1986 }
1987
1988 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
1989 unsigned int target_freq)
1990 {
1991 struct cpudata *cpu = all_cpu_data[policy->cpu];
1992 int target_pstate;
1993
1994 update_turbo_state();
1995
1996 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
1997 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1998 intel_pstate_update_pstate(cpu, target_pstate);
1999 return target_pstate * cpu->pstate.scaling;
2000 }
2001
2002 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2003 {
2004 int ret = __intel_pstate_cpu_init(policy);
2005
2006 if (ret)
2007 return ret;
2008
2009 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2010 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
2011 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2012 policy->cur = policy->cpuinfo.min_freq;
2013
2014 return 0;
2015 }
2016
2017 static struct cpufreq_driver intel_cpufreq = {
2018 .flags = CPUFREQ_CONST_LOOPS,
2019 .verify = intel_cpufreq_verify_policy,
2020 .target = intel_cpufreq_target,
2021 .fast_switch = intel_cpufreq_fast_switch,
2022 .init = intel_cpufreq_cpu_init,
2023 .exit = intel_pstate_cpu_exit,
2024 .stop_cpu = intel_cpufreq_stop_cpu,
2025 .name = "intel_cpufreq",
2026 };
2027
2028 static struct cpufreq_driver *default_driver = &intel_pstate;
2029
2030 static void intel_pstate_driver_cleanup(void)
2031 {
2032 unsigned int cpu;
2033
2034 get_online_cpus();
2035 for_each_online_cpu(cpu) {
2036 if (all_cpu_data[cpu]) {
2037 if (intel_pstate_driver == &intel_pstate)
2038 intel_pstate_clear_update_util_hook(cpu);
2039
2040 kfree(all_cpu_data[cpu]);
2041 all_cpu_data[cpu] = NULL;
2042 }
2043 }
2044 put_online_cpus();
2045 intel_pstate_driver = NULL;
2046 }
2047
2048 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
2049 {
2050 int ret;
2051
2052 memset(&global, 0, sizeof(global));
2053 global.max_perf_pct = 100;
2054
2055 intel_pstate_driver = driver;
2056 ret = cpufreq_register_driver(intel_pstate_driver);
2057 if (ret) {
2058 intel_pstate_driver_cleanup();
2059 return ret;
2060 }
2061
2062 global.min_perf_pct = min_perf_pct_min();
2063
2064 return 0;
2065 }
2066
2067 static int intel_pstate_unregister_driver(void)
2068 {
2069 if (hwp_active)
2070 return -EBUSY;
2071
2072 cpufreq_unregister_driver(intel_pstate_driver);
2073 intel_pstate_driver_cleanup();
2074
2075 return 0;
2076 }
2077
2078 static ssize_t intel_pstate_show_status(char *buf)
2079 {
2080 if (!intel_pstate_driver)
2081 return sprintf(buf, "off\n");
2082
2083 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2084 "active" : "passive");
2085 }
2086
2087 static int intel_pstate_update_status(const char *buf, size_t size)
2088 {
2089 int ret;
2090
2091 if (size == 3 && !strncmp(buf, "off", size))
2092 return intel_pstate_driver ?
2093 intel_pstate_unregister_driver() : -EINVAL;
2094
2095 if (size == 6 && !strncmp(buf, "active", size)) {
2096 if (intel_pstate_driver) {
2097 if (intel_pstate_driver == &intel_pstate)
2098 return 0;
2099
2100 ret = intel_pstate_unregister_driver();
2101 if (ret)
2102 return ret;
2103 }
2104
2105 return intel_pstate_register_driver(&intel_pstate);
2106 }
2107
2108 if (size == 7 && !strncmp(buf, "passive", size)) {
2109 if (intel_pstate_driver) {
2110 if (intel_pstate_driver == &intel_cpufreq)
2111 return 0;
2112
2113 ret = intel_pstate_unregister_driver();
2114 if (ret)
2115 return ret;
2116 }
2117
2118 return intel_pstate_register_driver(&intel_cpufreq);
2119 }
2120
2121 return -EINVAL;
2122 }
2123
2124 static int no_load __initdata;
2125 static int no_hwp __initdata;
2126 static int hwp_only __initdata;
2127 static unsigned int force_load __initdata;
2128
2129 static int __init intel_pstate_msrs_not_valid(void)
2130 {
2131 if (!pstate_funcs.get_max() ||
2132 !pstate_funcs.get_min() ||
2133 !pstate_funcs.get_turbo())
2134 return -ENODEV;
2135
2136 return 0;
2137 }
2138
2139 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2140 {
2141 pstate_funcs.get_max = funcs->get_max;
2142 pstate_funcs.get_max_physical = funcs->get_max_physical;
2143 pstate_funcs.get_min = funcs->get_min;
2144 pstate_funcs.get_turbo = funcs->get_turbo;
2145 pstate_funcs.get_scaling = funcs->get_scaling;
2146 pstate_funcs.get_val = funcs->get_val;
2147 pstate_funcs.get_vid = funcs->get_vid;
2148 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
2149 }
2150
2151 #ifdef CONFIG_ACPI
2152
2153 static bool __init intel_pstate_no_acpi_pss(void)
2154 {
2155 int i;
2156
2157 for_each_possible_cpu(i) {
2158 acpi_status status;
2159 union acpi_object *pss;
2160 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2161 struct acpi_processor *pr = per_cpu(processors, i);
2162
2163 if (!pr)
2164 continue;
2165
2166 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2167 if (ACPI_FAILURE(status))
2168 continue;
2169
2170 pss = buffer.pointer;
2171 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2172 kfree(pss);
2173 return false;
2174 }
2175
2176 kfree(pss);
2177 }
2178
2179 return true;
2180 }
2181
2182 static bool __init intel_pstate_has_acpi_ppc(void)
2183 {
2184 int i;
2185
2186 for_each_possible_cpu(i) {
2187 struct acpi_processor *pr = per_cpu(processors, i);
2188
2189 if (!pr)
2190 continue;
2191 if (acpi_has_method(pr->handle, "_PPC"))
2192 return true;
2193 }
2194 return false;
2195 }
2196
2197 enum {
2198 PSS,
2199 PPC,
2200 };
2201
2202 /* Hardware vendor-specific info that has its own power management modes */
2203 static struct acpi_platform_list plat_info[] __initdata = {
2204 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, 0, PSS},
2205 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2206 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2207 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2208 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2209 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2210 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2211 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2212 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2213 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2214 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2215 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2216 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2217 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2218 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2219 { } /* End */
2220 };
2221
2222 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2223 {
2224 const struct x86_cpu_id *id;
2225 u64 misc_pwr;
2226 int idx;
2227
2228 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2229 if (id) {
2230 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2231 if ( misc_pwr & (1 << 8))
2232 return true;
2233 }
2234
2235 idx = acpi_match_platform_list(plat_info);
2236 if (idx < 0)
2237 return false;
2238
2239 switch (plat_info[idx].data) {
2240 case PSS:
2241 return intel_pstate_no_acpi_pss();
2242 case PPC:
2243 return intel_pstate_has_acpi_ppc() && !force_load;
2244 }
2245
2246 return false;
2247 }
2248
2249 static void intel_pstate_request_control_from_smm(void)
2250 {
2251 /*
2252 * It may be unsafe to request P-states control from SMM if _PPC support
2253 * has not been enabled.
2254 */
2255 if (acpi_ppc)
2256 acpi_processor_pstate_control();
2257 }
2258 #else /* CONFIG_ACPI not enabled */
2259 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2260 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2261 static inline void intel_pstate_request_control_from_smm(void) {}
2262 #endif /* CONFIG_ACPI */
2263
2264 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2265 { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
2266 {}
2267 };
2268
2269 static int __init intel_pstate_init(void)
2270 {
2271 int rc;
2272
2273 if (no_load)
2274 return -ENODEV;
2275
2276 if (x86_match_cpu(hwp_support_ids)) {
2277 copy_cpu_funcs(&core_funcs);
2278 if (!no_hwp) {
2279 hwp_active++;
2280 intel_pstate.attr = hwp_cpufreq_attrs;
2281 goto hwp_cpu_matched;
2282 }
2283 } else {
2284 const struct x86_cpu_id *id;
2285
2286 id = x86_match_cpu(intel_pstate_cpu_ids);
2287 if (!id)
2288 return -ENODEV;
2289
2290 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
2291 }
2292
2293 if (intel_pstate_msrs_not_valid())
2294 return -ENODEV;
2295
2296 hwp_cpu_matched:
2297 /*
2298 * The Intel pstate driver will be ignored if the platform
2299 * firmware has its own power management modes.
2300 */
2301 if (intel_pstate_platform_pwr_mgmt_exists())
2302 return -ENODEV;
2303
2304 if (!hwp_active && hwp_only)
2305 return -ENOTSUPP;
2306
2307 pr_info("Intel P-state driver initializing\n");
2308
2309 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
2310 if (!all_cpu_data)
2311 return -ENOMEM;
2312
2313 intel_pstate_request_control_from_smm();
2314
2315 intel_pstate_sysfs_expose_params();
2316
2317 mutex_lock(&intel_pstate_driver_lock);
2318 rc = intel_pstate_register_driver(default_driver);
2319 mutex_unlock(&intel_pstate_driver_lock);
2320 if (rc)
2321 return rc;
2322
2323 if (hwp_active)
2324 pr_info("HWP enabled\n");
2325
2326 return 0;
2327 }
2328 device_initcall(intel_pstate_init);
2329
2330 static int __init intel_pstate_setup(char *str)
2331 {
2332 if (!str)
2333 return -EINVAL;
2334
2335 if (!strcmp(str, "disable")) {
2336 no_load = 1;
2337 } else if (!strcmp(str, "passive")) {
2338 pr_info("Passive mode enabled\n");
2339 default_driver = &intel_cpufreq;
2340 no_hwp = 1;
2341 }
2342 if (!strcmp(str, "no_hwp")) {
2343 pr_info("HWP disabled\n");
2344 no_hwp = 1;
2345 }
2346 if (!strcmp(str, "force"))
2347 force_load = 1;
2348 if (!strcmp(str, "hwp_only"))
2349 hwp_only = 1;
2350 if (!strcmp(str, "per_cpu_perf_limits"))
2351 per_cpu_limits = true;
2352
2353 #ifdef CONFIG_ACPI
2354 if (!strcmp(str, "support_acpi_ppc"))
2355 acpi_ppc = true;
2356 #endif
2357
2358 return 0;
2359 }
2360 early_param("intel_pstate", intel_pstate_setup);
2361
2362 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2363 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2364 MODULE_LICENSE("GPL");
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