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Merge tag 'powerpc-4.13-8' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc...
[mirror_ubuntu-artful-kernel.git] / drivers / cpufreq / intel_pstate.c
1 /*
2 * intel_pstate.c: Native P state management for Intel processors
3 *
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 */
12
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15 #include <linux/kernel.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/ktime.h>
19 #include <linux/hrtimer.h>
20 #include <linux/tick.h>
21 #include <linux/slab.h>
22 #include <linux/sched/cpufreq.h>
23 #include <linux/list.h>
24 #include <linux/cpu.h>
25 #include <linux/cpufreq.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
28 #include <linux/fs.h>
29 #include <linux/debugfs.h>
30 #include <linux/acpi.h>
31 #include <linux/vmalloc.h>
32 #include <trace/events/power.h>
33
34 #include <asm/div64.h>
35 #include <asm/msr.h>
36 #include <asm/cpu_device_id.h>
37 #include <asm/cpufeature.h>
38 #include <asm/intel-family.h>
39
40 #define INTEL_PSTATE_DEFAULT_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
41 #define INTEL_PSTATE_HWP_SAMPLING_INTERVAL (50 * NSEC_PER_MSEC)
42
43 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
44 #define INTEL_CPUFREQ_TRANSITION_DELAY 500
45
46 #ifdef CONFIG_ACPI
47 #include <acpi/processor.h>
48 #include <acpi/cppc_acpi.h>
49 #endif
50
51 #define FRAC_BITS 8
52 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
53 #define fp_toint(X) ((X) >> FRAC_BITS)
54
55 #define EXT_BITS 6
56 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
57 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
58 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
59
60 static inline int32_t mul_fp(int32_t x, int32_t y)
61 {
62 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
63 }
64
65 static inline int32_t div_fp(s64 x, s64 y)
66 {
67 return div64_s64((int64_t)x << FRAC_BITS, y);
68 }
69
70 static inline int ceiling_fp(int32_t x)
71 {
72 int mask, ret;
73
74 ret = fp_toint(x);
75 mask = (1 << FRAC_BITS) - 1;
76 if (x & mask)
77 ret += 1;
78 return ret;
79 }
80
81 static inline int32_t percent_fp(int percent)
82 {
83 return div_fp(percent, 100);
84 }
85
86 static inline u64 mul_ext_fp(u64 x, u64 y)
87 {
88 return (x * y) >> EXT_FRAC_BITS;
89 }
90
91 static inline u64 div_ext_fp(u64 x, u64 y)
92 {
93 return div64_u64(x << EXT_FRAC_BITS, y);
94 }
95
96 static inline int32_t percent_ext_fp(int percent)
97 {
98 return div_ext_fp(percent, 100);
99 }
100
101 /**
102 * struct sample - Store performance sample
103 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
104 * performance during last sample period
105 * @busy_scaled: Scaled busy value which is used to calculate next
106 * P state. This can be different than core_avg_perf
107 * to account for cpu idle period
108 * @aperf: Difference of actual performance frequency clock count
109 * read from APERF MSR between last and current sample
110 * @mperf: Difference of maximum performance frequency clock count
111 * read from MPERF MSR between last and current sample
112 * @tsc: Difference of time stamp counter between last and
113 * current sample
114 * @time: Current time from scheduler
115 *
116 * This structure is used in the cpudata structure to store performance sample
117 * data for choosing next P State.
118 */
119 struct sample {
120 int32_t core_avg_perf;
121 int32_t busy_scaled;
122 u64 aperf;
123 u64 mperf;
124 u64 tsc;
125 u64 time;
126 };
127
128 /**
129 * struct pstate_data - Store P state data
130 * @current_pstate: Current requested P state
131 * @min_pstate: Min P state possible for this platform
132 * @max_pstate: Max P state possible for this platform
133 * @max_pstate_physical:This is physical Max P state for a processor
134 * This can be higher than the max_pstate which can
135 * be limited by platform thermal design power limits
136 * @scaling: Scaling factor to convert frequency to cpufreq
137 * frequency units
138 * @turbo_pstate: Max Turbo P state possible for this platform
139 * @max_freq: @max_pstate frequency in cpufreq units
140 * @turbo_freq: @turbo_pstate frequency in cpufreq units
141 *
142 * Stores the per cpu model P state limits and current P state.
143 */
144 struct pstate_data {
145 int current_pstate;
146 int min_pstate;
147 int max_pstate;
148 int max_pstate_physical;
149 int scaling;
150 int turbo_pstate;
151 unsigned int max_freq;
152 unsigned int turbo_freq;
153 };
154
155 /**
156 * struct vid_data - Stores voltage information data
157 * @min: VID data for this platform corresponding to
158 * the lowest P state
159 * @max: VID data corresponding to the highest P State.
160 * @turbo: VID data for turbo P state
161 * @ratio: Ratio of (vid max - vid min) /
162 * (max P state - Min P State)
163 *
164 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
165 * This data is used in Atom platforms, where in addition to target P state,
166 * the voltage data needs to be specified to select next P State.
167 */
168 struct vid_data {
169 int min;
170 int max;
171 int turbo;
172 int32_t ratio;
173 };
174
175 /**
176 * struct _pid - Stores PID data
177 * @setpoint: Target set point for busyness or performance
178 * @integral: Storage for accumulated error values
179 * @p_gain: PID proportional gain
180 * @i_gain: PID integral gain
181 * @d_gain: PID derivative gain
182 * @deadband: PID deadband
183 * @last_err: Last error storage for integral part of PID calculation
184 *
185 * Stores PID coefficients and last error for PID controller.
186 */
187 struct _pid {
188 int setpoint;
189 int32_t integral;
190 int32_t p_gain;
191 int32_t i_gain;
192 int32_t d_gain;
193 int deadband;
194 int32_t last_err;
195 };
196
197 /**
198 * struct global_params - Global parameters, mostly tunable via sysfs.
199 * @no_turbo: Whether or not to use turbo P-states.
200 * @turbo_disabled: Whethet or not turbo P-states are available at all,
201 * based on the MSR_IA32_MISC_ENABLE value and whether or
202 * not the maximum reported turbo P-state is different from
203 * the maximum reported non-turbo one.
204 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
205 * P-state capacity.
206 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
207 * P-state capacity.
208 */
209 struct global_params {
210 bool no_turbo;
211 bool turbo_disabled;
212 int max_perf_pct;
213 int min_perf_pct;
214 };
215
216 /**
217 * struct cpudata - Per CPU instance data storage
218 * @cpu: CPU number for this instance data
219 * @policy: CPUFreq policy value
220 * @update_util: CPUFreq utility callback information
221 * @update_util_set: CPUFreq utility callback is set
222 * @iowait_boost: iowait-related boost fraction
223 * @last_update: Time of the last update.
224 * @pstate: Stores P state limits for this CPU
225 * @vid: Stores VID limits for this CPU
226 * @pid: Stores PID parameters for this CPU
227 * @last_sample_time: Last Sample time
228 * @aperf_mperf_shift: Number of clock cycles after aperf, merf is incremented
229 * This shift is a multiplier to mperf delta to
230 * calculate CPU busy.
231 * @prev_aperf: Last APERF value read from APERF MSR
232 * @prev_mperf: Last MPERF value read from MPERF MSR
233 * @prev_tsc: Last timestamp counter (TSC) value
234 * @prev_cummulative_iowait: IO Wait time difference from last and
235 * current sample
236 * @sample: Storage for storing last Sample data
237 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
238 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
239 * @acpi_perf_data: Stores ACPI perf information read from _PSS
240 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
241 * @epp_powersave: Last saved HWP energy performance preference
242 * (EPP) or energy performance bias (EPB),
243 * when policy switched to performance
244 * @epp_policy: Last saved policy used to set EPP/EPB
245 * @epp_default: Power on default HWP energy performance
246 * preference/bias
247 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
248 * operation
249 *
250 * This structure stores per CPU instance data for all CPUs.
251 */
252 struct cpudata {
253 int cpu;
254
255 unsigned int policy;
256 struct update_util_data update_util;
257 bool update_util_set;
258
259 struct pstate_data pstate;
260 struct vid_data vid;
261 struct _pid pid;
262
263 u64 last_update;
264 u64 last_sample_time;
265 u64 aperf_mperf_shift;
266 u64 prev_aperf;
267 u64 prev_mperf;
268 u64 prev_tsc;
269 u64 prev_cummulative_iowait;
270 struct sample sample;
271 int32_t min_perf_ratio;
272 int32_t max_perf_ratio;
273 #ifdef CONFIG_ACPI
274 struct acpi_processor_performance acpi_perf_data;
275 bool valid_pss_table;
276 #endif
277 unsigned int iowait_boost;
278 s16 epp_powersave;
279 s16 epp_policy;
280 s16 epp_default;
281 s16 epp_saved;
282 };
283
284 static struct cpudata **all_cpu_data;
285
286 /**
287 * struct pstate_adjust_policy - Stores static PID configuration data
288 * @sample_rate_ms: PID calculation sample rate in ms
289 * @sample_rate_ns: Sample rate calculation in ns
290 * @deadband: PID deadband
291 * @setpoint: PID Setpoint
292 * @p_gain_pct: PID proportional gain
293 * @i_gain_pct: PID integral gain
294 * @d_gain_pct: PID derivative gain
295 *
296 * Stores per CPU model static PID configuration data.
297 */
298 struct pstate_adjust_policy {
299 int sample_rate_ms;
300 s64 sample_rate_ns;
301 int deadband;
302 int setpoint;
303 int p_gain_pct;
304 int d_gain_pct;
305 int i_gain_pct;
306 };
307
308 /**
309 * struct pstate_funcs - Per CPU model specific callbacks
310 * @get_max: Callback to get maximum non turbo effective P state
311 * @get_max_physical: Callback to get maximum non turbo physical P state
312 * @get_min: Callback to get minimum P state
313 * @get_turbo: Callback to get turbo P state
314 * @get_scaling: Callback to get frequency scaling factor
315 * @get_val: Callback to convert P state to actual MSR write value
316 * @get_vid: Callback to get VID data for Atom platforms
317 * @update_util: Active mode utilization update callback.
318 *
319 * Core and Atom CPU models have different way to get P State limits. This
320 * structure is used to store those callbacks.
321 */
322 struct pstate_funcs {
323 int (*get_max)(void);
324 int (*get_max_physical)(void);
325 int (*get_min)(void);
326 int (*get_turbo)(void);
327 int (*get_scaling)(void);
328 int (*get_aperf_mperf_shift)(void);
329 u64 (*get_val)(struct cpudata*, int pstate);
330 void (*get_vid)(struct cpudata *);
331 void (*update_util)(struct update_util_data *data, u64 time,
332 unsigned int flags);
333 };
334
335 static struct pstate_funcs pstate_funcs __read_mostly;
336 static struct pstate_adjust_policy pid_params __read_mostly = {
337 .sample_rate_ms = 10,
338 .sample_rate_ns = 10 * NSEC_PER_MSEC,
339 .deadband = 0,
340 .setpoint = 97,
341 .p_gain_pct = 20,
342 .d_gain_pct = 0,
343 .i_gain_pct = 0,
344 };
345
346 static int hwp_active __read_mostly;
347 static bool per_cpu_limits __read_mostly;
348
349 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
350
351 #ifdef CONFIG_ACPI
352 static bool acpi_ppc;
353 #endif
354
355 static struct global_params global;
356
357 static DEFINE_MUTEX(intel_pstate_driver_lock);
358 static DEFINE_MUTEX(intel_pstate_limits_lock);
359
360 #ifdef CONFIG_ACPI
361
362 static bool intel_pstate_get_ppc_enable_status(void)
363 {
364 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
365 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
366 return true;
367
368 return acpi_ppc;
369 }
370
371 #ifdef CONFIG_ACPI_CPPC_LIB
372
373 /* The work item is needed to avoid CPU hotplug locking issues */
374 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
375 {
376 sched_set_itmt_support();
377 }
378
379 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
380
381 static void intel_pstate_set_itmt_prio(int cpu)
382 {
383 struct cppc_perf_caps cppc_perf;
384 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
385 int ret;
386
387 ret = cppc_get_perf_caps(cpu, &cppc_perf);
388 if (ret)
389 return;
390
391 /*
392 * The priorities can be set regardless of whether or not
393 * sched_set_itmt_support(true) has been called and it is valid to
394 * update them at any time after it has been called.
395 */
396 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
397
398 if (max_highest_perf <= min_highest_perf) {
399 if (cppc_perf.highest_perf > max_highest_perf)
400 max_highest_perf = cppc_perf.highest_perf;
401
402 if (cppc_perf.highest_perf < min_highest_perf)
403 min_highest_perf = cppc_perf.highest_perf;
404
405 if (max_highest_perf > min_highest_perf) {
406 /*
407 * This code can be run during CPU online under the
408 * CPU hotplug locks, so sched_set_itmt_support()
409 * cannot be called from here. Queue up a work item
410 * to invoke it.
411 */
412 schedule_work(&sched_itmt_work);
413 }
414 }
415 }
416 #else
417 static void intel_pstate_set_itmt_prio(int cpu)
418 {
419 }
420 #endif
421
422 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
423 {
424 struct cpudata *cpu;
425 int ret;
426 int i;
427
428 if (hwp_active) {
429 intel_pstate_set_itmt_prio(policy->cpu);
430 return;
431 }
432
433 if (!intel_pstate_get_ppc_enable_status())
434 return;
435
436 cpu = all_cpu_data[policy->cpu];
437
438 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
439 policy->cpu);
440 if (ret)
441 return;
442
443 /*
444 * Check if the control value in _PSS is for PERF_CTL MSR, which should
445 * guarantee that the states returned by it map to the states in our
446 * list directly.
447 */
448 if (cpu->acpi_perf_data.control_register.space_id !=
449 ACPI_ADR_SPACE_FIXED_HARDWARE)
450 goto err;
451
452 /*
453 * If there is only one entry _PSS, simply ignore _PSS and continue as
454 * usual without taking _PSS into account
455 */
456 if (cpu->acpi_perf_data.state_count < 2)
457 goto err;
458
459 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
460 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
461 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
462 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
463 (u32) cpu->acpi_perf_data.states[i].core_frequency,
464 (u32) cpu->acpi_perf_data.states[i].power,
465 (u32) cpu->acpi_perf_data.states[i].control);
466 }
467
468 /*
469 * The _PSS table doesn't contain whole turbo frequency range.
470 * This just contains +1 MHZ above the max non turbo frequency,
471 * with control value corresponding to max turbo ratio. But
472 * when cpufreq set policy is called, it will call with this
473 * max frequency, which will cause a reduced performance as
474 * this driver uses real max turbo frequency as the max
475 * frequency. So correct this frequency in _PSS table to
476 * correct max turbo frequency based on the turbo state.
477 * Also need to convert to MHz as _PSS freq is in MHz.
478 */
479 if (!global.turbo_disabled)
480 cpu->acpi_perf_data.states[0].core_frequency =
481 policy->cpuinfo.max_freq / 1000;
482 cpu->valid_pss_table = true;
483 pr_debug("_PPC limits will be enforced\n");
484
485 return;
486
487 err:
488 cpu->valid_pss_table = false;
489 acpi_processor_unregister_performance(policy->cpu);
490 }
491
492 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
493 {
494 struct cpudata *cpu;
495
496 cpu = all_cpu_data[policy->cpu];
497 if (!cpu->valid_pss_table)
498 return;
499
500 acpi_processor_unregister_performance(policy->cpu);
501 }
502 #else
503 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
504 {
505 }
506
507 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
508 {
509 }
510 #endif
511
512 static signed int pid_calc(struct _pid *pid, int32_t busy)
513 {
514 signed int result;
515 int32_t pterm, dterm, fp_error;
516 int32_t integral_limit;
517
518 fp_error = pid->setpoint - busy;
519
520 if (abs(fp_error) <= pid->deadband)
521 return 0;
522
523 pterm = mul_fp(pid->p_gain, fp_error);
524
525 pid->integral += fp_error;
526
527 /*
528 * We limit the integral here so that it will never
529 * get higher than 30. This prevents it from becoming
530 * too large an input over long periods of time and allows
531 * it to get factored out sooner.
532 *
533 * The value of 30 was chosen through experimentation.
534 */
535 integral_limit = int_tofp(30);
536 if (pid->integral > integral_limit)
537 pid->integral = integral_limit;
538 if (pid->integral < -integral_limit)
539 pid->integral = -integral_limit;
540
541 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
542 pid->last_err = fp_error;
543
544 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
545 result = result + (1 << (FRAC_BITS-1));
546 return (signed int)fp_toint(result);
547 }
548
549 static inline void intel_pstate_pid_reset(struct cpudata *cpu)
550 {
551 struct _pid *pid = &cpu->pid;
552
553 pid->p_gain = percent_fp(pid_params.p_gain_pct);
554 pid->d_gain = percent_fp(pid_params.d_gain_pct);
555 pid->i_gain = percent_fp(pid_params.i_gain_pct);
556 pid->setpoint = int_tofp(pid_params.setpoint);
557 pid->last_err = pid->setpoint - int_tofp(100);
558 pid->deadband = int_tofp(pid_params.deadband);
559 pid->integral = 0;
560 }
561
562 static inline void update_turbo_state(void)
563 {
564 u64 misc_en;
565 struct cpudata *cpu;
566
567 cpu = all_cpu_data[0];
568 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
569 global.turbo_disabled =
570 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
571 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
572 }
573
574 static int min_perf_pct_min(void)
575 {
576 struct cpudata *cpu = all_cpu_data[0];
577 int turbo_pstate = cpu->pstate.turbo_pstate;
578
579 return turbo_pstate ?
580 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
581 }
582
583 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
584 {
585 u64 epb;
586 int ret;
587
588 if (!static_cpu_has(X86_FEATURE_EPB))
589 return -ENXIO;
590
591 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
592 if (ret)
593 return (s16)ret;
594
595 return (s16)(epb & 0x0f);
596 }
597
598 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
599 {
600 s16 epp;
601
602 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
603 /*
604 * When hwp_req_data is 0, means that caller didn't read
605 * MSR_HWP_REQUEST, so need to read and get EPP.
606 */
607 if (!hwp_req_data) {
608 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
609 &hwp_req_data);
610 if (epp)
611 return epp;
612 }
613 epp = (hwp_req_data >> 24) & 0xff;
614 } else {
615 /* When there is no EPP present, HWP uses EPB settings */
616 epp = intel_pstate_get_epb(cpu_data);
617 }
618
619 return epp;
620 }
621
622 static int intel_pstate_set_epb(int cpu, s16 pref)
623 {
624 u64 epb;
625 int ret;
626
627 if (!static_cpu_has(X86_FEATURE_EPB))
628 return -ENXIO;
629
630 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
631 if (ret)
632 return ret;
633
634 epb = (epb & ~0x0f) | pref;
635 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
636
637 return 0;
638 }
639
640 /*
641 * EPP/EPB display strings corresponding to EPP index in the
642 * energy_perf_strings[]
643 * index String
644 *-------------------------------------
645 * 0 default
646 * 1 performance
647 * 2 balance_performance
648 * 3 balance_power
649 * 4 power
650 */
651 static const char * const energy_perf_strings[] = {
652 "default",
653 "performance",
654 "balance_performance",
655 "balance_power",
656 "power",
657 NULL
658 };
659 static const unsigned int epp_values[] = {
660 HWP_EPP_PERFORMANCE,
661 HWP_EPP_BALANCE_PERFORMANCE,
662 HWP_EPP_BALANCE_POWERSAVE,
663 HWP_EPP_POWERSAVE
664 };
665
666 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
667 {
668 s16 epp;
669 int index = -EINVAL;
670
671 epp = intel_pstate_get_epp(cpu_data, 0);
672 if (epp < 0)
673 return epp;
674
675 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
676 if (epp == HWP_EPP_PERFORMANCE)
677 return 1;
678 if (epp <= HWP_EPP_BALANCE_PERFORMANCE)
679 return 2;
680 if (epp <= HWP_EPP_BALANCE_POWERSAVE)
681 return 3;
682 else
683 return 4;
684 } else if (static_cpu_has(X86_FEATURE_EPB)) {
685 /*
686 * Range:
687 * 0x00-0x03 : Performance
688 * 0x04-0x07 : Balance performance
689 * 0x08-0x0B : Balance power
690 * 0x0C-0x0F : Power
691 * The EPB is a 4 bit value, but our ranges restrict the
692 * value which can be set. Here only using top two bits
693 * effectively.
694 */
695 index = (epp >> 2) + 1;
696 }
697
698 return index;
699 }
700
701 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
702 int pref_index)
703 {
704 int epp = -EINVAL;
705 int ret;
706
707 if (!pref_index)
708 epp = cpu_data->epp_default;
709
710 mutex_lock(&intel_pstate_limits_lock);
711
712 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
713 u64 value;
714
715 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
716 if (ret)
717 goto return_pref;
718
719 value &= ~GENMASK_ULL(31, 24);
720
721 if (epp == -EINVAL)
722 epp = epp_values[pref_index - 1];
723
724 value |= (u64)epp << 24;
725 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
726 } else {
727 if (epp == -EINVAL)
728 epp = (pref_index - 1) << 2;
729 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
730 }
731 return_pref:
732 mutex_unlock(&intel_pstate_limits_lock);
733
734 return ret;
735 }
736
737 static ssize_t show_energy_performance_available_preferences(
738 struct cpufreq_policy *policy, char *buf)
739 {
740 int i = 0;
741 int ret = 0;
742
743 while (energy_perf_strings[i] != NULL)
744 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
745
746 ret += sprintf(&buf[ret], "\n");
747
748 return ret;
749 }
750
751 cpufreq_freq_attr_ro(energy_performance_available_preferences);
752
753 static ssize_t store_energy_performance_preference(
754 struct cpufreq_policy *policy, const char *buf, size_t count)
755 {
756 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
757 char str_preference[21];
758 int ret, i = 0;
759
760 ret = sscanf(buf, "%20s", str_preference);
761 if (ret != 1)
762 return -EINVAL;
763
764 while (energy_perf_strings[i] != NULL) {
765 if (!strcmp(str_preference, energy_perf_strings[i])) {
766 intel_pstate_set_energy_pref_index(cpu_data, i);
767 return count;
768 }
769 ++i;
770 }
771
772 return -EINVAL;
773 }
774
775 static ssize_t show_energy_performance_preference(
776 struct cpufreq_policy *policy, char *buf)
777 {
778 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
779 int preference;
780
781 preference = intel_pstate_get_energy_pref_index(cpu_data);
782 if (preference < 0)
783 return preference;
784
785 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
786 }
787
788 cpufreq_freq_attr_rw(energy_performance_preference);
789
790 static struct freq_attr *hwp_cpufreq_attrs[] = {
791 &energy_performance_preference,
792 &energy_performance_available_preferences,
793 NULL,
794 };
795
796 static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max,
797 int *current_max)
798 {
799 u64 cap;
800
801 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
802 if (global.no_turbo)
803 *current_max = HWP_GUARANTEED_PERF(cap);
804 else
805 *current_max = HWP_HIGHEST_PERF(cap);
806
807 *phy_max = HWP_HIGHEST_PERF(cap);
808 }
809
810 static void intel_pstate_hwp_set(unsigned int cpu)
811 {
812 struct cpudata *cpu_data = all_cpu_data[cpu];
813 int max, min;
814 u64 value;
815 s16 epp;
816
817 max = cpu_data->max_perf_ratio;
818 min = cpu_data->min_perf_ratio;
819
820 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
821 min = max;
822
823 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
824
825 value &= ~HWP_MIN_PERF(~0L);
826 value |= HWP_MIN_PERF(min);
827
828 value &= ~HWP_MAX_PERF(~0L);
829 value |= HWP_MAX_PERF(max);
830
831 if (cpu_data->epp_policy == cpu_data->policy)
832 goto skip_epp;
833
834 cpu_data->epp_policy = cpu_data->policy;
835
836 if (cpu_data->epp_saved >= 0) {
837 epp = cpu_data->epp_saved;
838 cpu_data->epp_saved = -EINVAL;
839 goto update_epp;
840 }
841
842 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
843 epp = intel_pstate_get_epp(cpu_data, value);
844 cpu_data->epp_powersave = epp;
845 /* If EPP read was failed, then don't try to write */
846 if (epp < 0)
847 goto skip_epp;
848
849 epp = 0;
850 } else {
851 /* skip setting EPP, when saved value is invalid */
852 if (cpu_data->epp_powersave < 0)
853 goto skip_epp;
854
855 /*
856 * No need to restore EPP when it is not zero. This
857 * means:
858 * - Policy is not changed
859 * - user has manually changed
860 * - Error reading EPB
861 */
862 epp = intel_pstate_get_epp(cpu_data, value);
863 if (epp)
864 goto skip_epp;
865
866 epp = cpu_data->epp_powersave;
867 }
868 update_epp:
869 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
870 value &= ~GENMASK_ULL(31, 24);
871 value |= (u64)epp << 24;
872 } else {
873 intel_pstate_set_epb(cpu, epp);
874 }
875 skip_epp:
876 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
877 }
878
879 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
880 {
881 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
882
883 if (!hwp_active)
884 return 0;
885
886 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
887
888 return 0;
889 }
890
891 static int intel_pstate_resume(struct cpufreq_policy *policy)
892 {
893 if (!hwp_active)
894 return 0;
895
896 mutex_lock(&intel_pstate_limits_lock);
897
898 all_cpu_data[policy->cpu]->epp_policy = 0;
899 intel_pstate_hwp_set(policy->cpu);
900
901 mutex_unlock(&intel_pstate_limits_lock);
902
903 return 0;
904 }
905
906 static void intel_pstate_update_policies(void)
907 {
908 int cpu;
909
910 for_each_possible_cpu(cpu)
911 cpufreq_update_policy(cpu);
912 }
913
914 /************************** debugfs begin ************************/
915 static int pid_param_set(void *data, u64 val)
916 {
917 unsigned int cpu;
918
919 *(u32 *)data = val;
920 pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
921 for_each_possible_cpu(cpu)
922 if (all_cpu_data[cpu])
923 intel_pstate_pid_reset(all_cpu_data[cpu]);
924
925 return 0;
926 }
927
928 static int pid_param_get(void *data, u64 *val)
929 {
930 *val = *(u32 *)data;
931 return 0;
932 }
933 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
934
935 static struct dentry *debugfs_parent;
936
937 struct pid_param {
938 char *name;
939 void *value;
940 struct dentry *dentry;
941 };
942
943 static struct pid_param pid_files[] = {
944 {"sample_rate_ms", &pid_params.sample_rate_ms, },
945 {"d_gain_pct", &pid_params.d_gain_pct, },
946 {"i_gain_pct", &pid_params.i_gain_pct, },
947 {"deadband", &pid_params.deadband, },
948 {"setpoint", &pid_params.setpoint, },
949 {"p_gain_pct", &pid_params.p_gain_pct, },
950 {NULL, NULL, }
951 };
952
953 static void intel_pstate_debug_expose_params(void)
954 {
955 int i;
956
957 debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
958 if (IS_ERR_OR_NULL(debugfs_parent))
959 return;
960
961 for (i = 0; pid_files[i].name; i++) {
962 struct dentry *dentry;
963
964 dentry = debugfs_create_file(pid_files[i].name, 0660,
965 debugfs_parent, pid_files[i].value,
966 &fops_pid_param);
967 if (!IS_ERR(dentry))
968 pid_files[i].dentry = dentry;
969 }
970 }
971
972 static void intel_pstate_debug_hide_params(void)
973 {
974 int i;
975
976 if (IS_ERR_OR_NULL(debugfs_parent))
977 return;
978
979 for (i = 0; pid_files[i].name; i++) {
980 debugfs_remove(pid_files[i].dentry);
981 pid_files[i].dentry = NULL;
982 }
983
984 debugfs_remove(debugfs_parent);
985 debugfs_parent = NULL;
986 }
987
988 /************************** debugfs end ************************/
989
990 /************************** sysfs begin ************************/
991 #define show_one(file_name, object) \
992 static ssize_t show_##file_name \
993 (struct kobject *kobj, struct attribute *attr, char *buf) \
994 { \
995 return sprintf(buf, "%u\n", global.object); \
996 }
997
998 static ssize_t intel_pstate_show_status(char *buf);
999 static int intel_pstate_update_status(const char *buf, size_t size);
1000
1001 static ssize_t show_status(struct kobject *kobj,
1002 struct attribute *attr, char *buf)
1003 {
1004 ssize_t ret;
1005
1006 mutex_lock(&intel_pstate_driver_lock);
1007 ret = intel_pstate_show_status(buf);
1008 mutex_unlock(&intel_pstate_driver_lock);
1009
1010 return ret;
1011 }
1012
1013 static ssize_t store_status(struct kobject *a, struct attribute *b,
1014 const char *buf, size_t count)
1015 {
1016 char *p = memchr(buf, '\n', count);
1017 int ret;
1018
1019 mutex_lock(&intel_pstate_driver_lock);
1020 ret = intel_pstate_update_status(buf, p ? p - buf : count);
1021 mutex_unlock(&intel_pstate_driver_lock);
1022
1023 return ret < 0 ? ret : count;
1024 }
1025
1026 static ssize_t show_turbo_pct(struct kobject *kobj,
1027 struct attribute *attr, char *buf)
1028 {
1029 struct cpudata *cpu;
1030 int total, no_turbo, turbo_pct;
1031 uint32_t turbo_fp;
1032
1033 mutex_lock(&intel_pstate_driver_lock);
1034
1035 if (!intel_pstate_driver) {
1036 mutex_unlock(&intel_pstate_driver_lock);
1037 return -EAGAIN;
1038 }
1039
1040 cpu = all_cpu_data[0];
1041
1042 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1043 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1044 turbo_fp = div_fp(no_turbo, total);
1045 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1046
1047 mutex_unlock(&intel_pstate_driver_lock);
1048
1049 return sprintf(buf, "%u\n", turbo_pct);
1050 }
1051
1052 static ssize_t show_num_pstates(struct kobject *kobj,
1053 struct attribute *attr, char *buf)
1054 {
1055 struct cpudata *cpu;
1056 int total;
1057
1058 mutex_lock(&intel_pstate_driver_lock);
1059
1060 if (!intel_pstate_driver) {
1061 mutex_unlock(&intel_pstate_driver_lock);
1062 return -EAGAIN;
1063 }
1064
1065 cpu = all_cpu_data[0];
1066 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1067
1068 mutex_unlock(&intel_pstate_driver_lock);
1069
1070 return sprintf(buf, "%u\n", total);
1071 }
1072
1073 static ssize_t show_no_turbo(struct kobject *kobj,
1074 struct attribute *attr, char *buf)
1075 {
1076 ssize_t ret;
1077
1078 mutex_lock(&intel_pstate_driver_lock);
1079
1080 if (!intel_pstate_driver) {
1081 mutex_unlock(&intel_pstate_driver_lock);
1082 return -EAGAIN;
1083 }
1084
1085 update_turbo_state();
1086 if (global.turbo_disabled)
1087 ret = sprintf(buf, "%u\n", global.turbo_disabled);
1088 else
1089 ret = sprintf(buf, "%u\n", global.no_turbo);
1090
1091 mutex_unlock(&intel_pstate_driver_lock);
1092
1093 return ret;
1094 }
1095
1096 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
1097 const char *buf, size_t count)
1098 {
1099 unsigned int input;
1100 int ret;
1101
1102 ret = sscanf(buf, "%u", &input);
1103 if (ret != 1)
1104 return -EINVAL;
1105
1106 mutex_lock(&intel_pstate_driver_lock);
1107
1108 if (!intel_pstate_driver) {
1109 mutex_unlock(&intel_pstate_driver_lock);
1110 return -EAGAIN;
1111 }
1112
1113 mutex_lock(&intel_pstate_limits_lock);
1114
1115 update_turbo_state();
1116 if (global.turbo_disabled) {
1117 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1118 mutex_unlock(&intel_pstate_limits_lock);
1119 mutex_unlock(&intel_pstate_driver_lock);
1120 return -EPERM;
1121 }
1122
1123 global.no_turbo = clamp_t(int, input, 0, 1);
1124
1125 if (global.no_turbo) {
1126 struct cpudata *cpu = all_cpu_data[0];
1127 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1128
1129 /* Squash the global minimum into the permitted range. */
1130 if (global.min_perf_pct > pct)
1131 global.min_perf_pct = pct;
1132 }
1133
1134 mutex_unlock(&intel_pstate_limits_lock);
1135
1136 intel_pstate_update_policies();
1137
1138 mutex_unlock(&intel_pstate_driver_lock);
1139
1140 return count;
1141 }
1142
1143 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
1144 const char *buf, size_t count)
1145 {
1146 unsigned int input;
1147 int ret;
1148
1149 ret = sscanf(buf, "%u", &input);
1150 if (ret != 1)
1151 return -EINVAL;
1152
1153 mutex_lock(&intel_pstate_driver_lock);
1154
1155 if (!intel_pstate_driver) {
1156 mutex_unlock(&intel_pstate_driver_lock);
1157 return -EAGAIN;
1158 }
1159
1160 mutex_lock(&intel_pstate_limits_lock);
1161
1162 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1163
1164 mutex_unlock(&intel_pstate_limits_lock);
1165
1166 intel_pstate_update_policies();
1167
1168 mutex_unlock(&intel_pstate_driver_lock);
1169
1170 return count;
1171 }
1172
1173 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
1174 const char *buf, size_t count)
1175 {
1176 unsigned int input;
1177 int ret;
1178
1179 ret = sscanf(buf, "%u", &input);
1180 if (ret != 1)
1181 return -EINVAL;
1182
1183 mutex_lock(&intel_pstate_driver_lock);
1184
1185 if (!intel_pstate_driver) {
1186 mutex_unlock(&intel_pstate_driver_lock);
1187 return -EAGAIN;
1188 }
1189
1190 mutex_lock(&intel_pstate_limits_lock);
1191
1192 global.min_perf_pct = clamp_t(int, input,
1193 min_perf_pct_min(), global.max_perf_pct);
1194
1195 mutex_unlock(&intel_pstate_limits_lock);
1196
1197 intel_pstate_update_policies();
1198
1199 mutex_unlock(&intel_pstate_driver_lock);
1200
1201 return count;
1202 }
1203
1204 show_one(max_perf_pct, max_perf_pct);
1205 show_one(min_perf_pct, min_perf_pct);
1206
1207 define_one_global_rw(status);
1208 define_one_global_rw(no_turbo);
1209 define_one_global_rw(max_perf_pct);
1210 define_one_global_rw(min_perf_pct);
1211 define_one_global_ro(turbo_pct);
1212 define_one_global_ro(num_pstates);
1213
1214 static struct attribute *intel_pstate_attributes[] = {
1215 &status.attr,
1216 &no_turbo.attr,
1217 &turbo_pct.attr,
1218 &num_pstates.attr,
1219 NULL
1220 };
1221
1222 static const struct attribute_group intel_pstate_attr_group = {
1223 .attrs = intel_pstate_attributes,
1224 };
1225
1226 static void __init intel_pstate_sysfs_expose_params(void)
1227 {
1228 struct kobject *intel_pstate_kobject;
1229 int rc;
1230
1231 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1232 &cpu_subsys.dev_root->kobj);
1233 if (WARN_ON(!intel_pstate_kobject))
1234 return;
1235
1236 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1237 if (WARN_ON(rc))
1238 return;
1239
1240 /*
1241 * If per cpu limits are enforced there are no global limits, so
1242 * return without creating max/min_perf_pct attributes
1243 */
1244 if (per_cpu_limits)
1245 return;
1246
1247 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1248 WARN_ON(rc);
1249
1250 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1251 WARN_ON(rc);
1252
1253 }
1254 /************************** sysfs end ************************/
1255
1256 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1257 {
1258 /* First disable HWP notification interrupt as we don't process them */
1259 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1260 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1261
1262 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1263 cpudata->epp_policy = 0;
1264 if (cpudata->epp_default == -EINVAL)
1265 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1266 }
1267
1268 #define MSR_IA32_POWER_CTL_BIT_EE 19
1269
1270 /* Disable energy efficiency optimization */
1271 static void intel_pstate_disable_ee(int cpu)
1272 {
1273 u64 power_ctl;
1274 int ret;
1275
1276 ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1277 if (ret)
1278 return;
1279
1280 if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1281 pr_info("Disabling energy efficiency optimization\n");
1282 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1283 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1284 }
1285 }
1286
1287 static int atom_get_min_pstate(void)
1288 {
1289 u64 value;
1290
1291 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1292 return (value >> 8) & 0x7F;
1293 }
1294
1295 static int atom_get_max_pstate(void)
1296 {
1297 u64 value;
1298
1299 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1300 return (value >> 16) & 0x7F;
1301 }
1302
1303 static int atom_get_turbo_pstate(void)
1304 {
1305 u64 value;
1306
1307 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1308 return value & 0x7F;
1309 }
1310
1311 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1312 {
1313 u64 val;
1314 int32_t vid_fp;
1315 u32 vid;
1316
1317 val = (u64)pstate << 8;
1318 if (global.no_turbo && !global.turbo_disabled)
1319 val |= (u64)1 << 32;
1320
1321 vid_fp = cpudata->vid.min + mul_fp(
1322 int_tofp(pstate - cpudata->pstate.min_pstate),
1323 cpudata->vid.ratio);
1324
1325 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1326 vid = ceiling_fp(vid_fp);
1327
1328 if (pstate > cpudata->pstate.max_pstate)
1329 vid = cpudata->vid.turbo;
1330
1331 return val | vid;
1332 }
1333
1334 static int silvermont_get_scaling(void)
1335 {
1336 u64 value;
1337 int i;
1338 /* Defined in Table 35-6 from SDM (Sept 2015) */
1339 static int silvermont_freq_table[] = {
1340 83300, 100000, 133300, 116700, 80000};
1341
1342 rdmsrl(MSR_FSB_FREQ, value);
1343 i = value & 0x7;
1344 WARN_ON(i > 4);
1345
1346 return silvermont_freq_table[i];
1347 }
1348
1349 static int airmont_get_scaling(void)
1350 {
1351 u64 value;
1352 int i;
1353 /* Defined in Table 35-10 from SDM (Sept 2015) */
1354 static int airmont_freq_table[] = {
1355 83300, 100000, 133300, 116700, 80000,
1356 93300, 90000, 88900, 87500};
1357
1358 rdmsrl(MSR_FSB_FREQ, value);
1359 i = value & 0xF;
1360 WARN_ON(i > 8);
1361
1362 return airmont_freq_table[i];
1363 }
1364
1365 static void atom_get_vid(struct cpudata *cpudata)
1366 {
1367 u64 value;
1368
1369 rdmsrl(MSR_ATOM_CORE_VIDS, value);
1370 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1371 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1372 cpudata->vid.ratio = div_fp(
1373 cpudata->vid.max - cpudata->vid.min,
1374 int_tofp(cpudata->pstate.max_pstate -
1375 cpudata->pstate.min_pstate));
1376
1377 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1378 cpudata->vid.turbo = value & 0x7f;
1379 }
1380
1381 static int core_get_min_pstate(void)
1382 {
1383 u64 value;
1384
1385 rdmsrl(MSR_PLATFORM_INFO, value);
1386 return (value >> 40) & 0xFF;
1387 }
1388
1389 static int core_get_max_pstate_physical(void)
1390 {
1391 u64 value;
1392
1393 rdmsrl(MSR_PLATFORM_INFO, value);
1394 return (value >> 8) & 0xFF;
1395 }
1396
1397 static int core_get_tdp_ratio(u64 plat_info)
1398 {
1399 /* Check how many TDP levels present */
1400 if (plat_info & 0x600000000) {
1401 u64 tdp_ctrl;
1402 u64 tdp_ratio;
1403 int tdp_msr;
1404 int err;
1405
1406 /* Get the TDP level (0, 1, 2) to get ratios */
1407 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1408 if (err)
1409 return err;
1410
1411 /* TDP MSR are continuous starting at 0x648 */
1412 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1413 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1414 if (err)
1415 return err;
1416
1417 /* For level 1 and 2, bits[23:16] contain the ratio */
1418 if (tdp_ctrl & 0x03)
1419 tdp_ratio >>= 16;
1420
1421 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1422 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1423
1424 return (int)tdp_ratio;
1425 }
1426
1427 return -ENXIO;
1428 }
1429
1430 static int core_get_max_pstate(void)
1431 {
1432 u64 tar;
1433 u64 plat_info;
1434 int max_pstate;
1435 int tdp_ratio;
1436 int err;
1437
1438 rdmsrl(MSR_PLATFORM_INFO, plat_info);
1439 max_pstate = (plat_info >> 8) & 0xFF;
1440
1441 tdp_ratio = core_get_tdp_ratio(plat_info);
1442 if (tdp_ratio <= 0)
1443 return max_pstate;
1444
1445 if (hwp_active) {
1446 /* Turbo activation ratio is not used on HWP platforms */
1447 return tdp_ratio;
1448 }
1449
1450 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1451 if (!err) {
1452 int tar_levels;
1453
1454 /* Do some sanity checking for safety */
1455 tar_levels = tar & 0xff;
1456 if (tdp_ratio - 1 == tar_levels) {
1457 max_pstate = tar_levels;
1458 pr_debug("max_pstate=TAC %x\n", max_pstate);
1459 }
1460 }
1461
1462 return max_pstate;
1463 }
1464
1465 static int core_get_turbo_pstate(void)
1466 {
1467 u64 value;
1468 int nont, ret;
1469
1470 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1471 nont = core_get_max_pstate();
1472 ret = (value) & 255;
1473 if (ret <= nont)
1474 ret = nont;
1475 return ret;
1476 }
1477
1478 static inline int core_get_scaling(void)
1479 {
1480 return 100000;
1481 }
1482
1483 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1484 {
1485 u64 val;
1486
1487 val = (u64)pstate << 8;
1488 if (global.no_turbo && !global.turbo_disabled)
1489 val |= (u64)1 << 32;
1490
1491 return val;
1492 }
1493
1494 static int knl_get_aperf_mperf_shift(void)
1495 {
1496 return 10;
1497 }
1498
1499 static int knl_get_turbo_pstate(void)
1500 {
1501 u64 value;
1502 int nont, ret;
1503
1504 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1505 nont = core_get_max_pstate();
1506 ret = (((value) >> 8) & 0xFF);
1507 if (ret <= nont)
1508 ret = nont;
1509 return ret;
1510 }
1511
1512 static int intel_pstate_get_base_pstate(struct cpudata *cpu)
1513 {
1514 return global.no_turbo || global.turbo_disabled ?
1515 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1516 }
1517
1518 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1519 {
1520 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1521 cpu->pstate.current_pstate = pstate;
1522 /*
1523 * Generally, there is no guarantee that this code will always run on
1524 * the CPU being updated, so force the register update to run on the
1525 * right CPU.
1526 */
1527 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1528 pstate_funcs.get_val(cpu, pstate));
1529 }
1530
1531 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1532 {
1533 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1534 }
1535
1536 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1537 {
1538 int pstate;
1539
1540 update_turbo_state();
1541 pstate = intel_pstate_get_base_pstate(cpu);
1542 pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
1543 intel_pstate_set_pstate(cpu, pstate);
1544 }
1545
1546 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1547 {
1548 cpu->pstate.min_pstate = pstate_funcs.get_min();
1549 cpu->pstate.max_pstate = pstate_funcs.get_max();
1550 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1551 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1552 cpu->pstate.scaling = pstate_funcs.get_scaling();
1553 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1554 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1555
1556 if (pstate_funcs.get_aperf_mperf_shift)
1557 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
1558
1559 if (pstate_funcs.get_vid)
1560 pstate_funcs.get_vid(cpu);
1561
1562 intel_pstate_set_min_pstate(cpu);
1563 }
1564
1565 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1566 {
1567 struct sample *sample = &cpu->sample;
1568
1569 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1570 }
1571
1572 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1573 {
1574 u64 aperf, mperf;
1575 unsigned long flags;
1576 u64 tsc;
1577
1578 local_irq_save(flags);
1579 rdmsrl(MSR_IA32_APERF, aperf);
1580 rdmsrl(MSR_IA32_MPERF, mperf);
1581 tsc = rdtsc();
1582 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1583 local_irq_restore(flags);
1584 return false;
1585 }
1586 local_irq_restore(flags);
1587
1588 cpu->last_sample_time = cpu->sample.time;
1589 cpu->sample.time = time;
1590 cpu->sample.aperf = aperf;
1591 cpu->sample.mperf = mperf;
1592 cpu->sample.tsc = tsc;
1593 cpu->sample.aperf -= cpu->prev_aperf;
1594 cpu->sample.mperf -= cpu->prev_mperf;
1595 cpu->sample.tsc -= cpu->prev_tsc;
1596
1597 cpu->prev_aperf = aperf;
1598 cpu->prev_mperf = mperf;
1599 cpu->prev_tsc = tsc;
1600 /*
1601 * First time this function is invoked in a given cycle, all of the
1602 * previous sample data fields are equal to zero or stale and they must
1603 * be populated with meaningful numbers for things to work, so assume
1604 * that sample.time will always be reset before setting the utilization
1605 * update hook and make the caller skip the sample then.
1606 */
1607 if (cpu->last_sample_time) {
1608 intel_pstate_calc_avg_perf(cpu);
1609 return true;
1610 }
1611 return false;
1612 }
1613
1614 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1615 {
1616 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
1617 }
1618
1619 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1620 {
1621 return mul_ext_fp(cpu->pstate.max_pstate_physical,
1622 cpu->sample.core_avg_perf);
1623 }
1624
1625 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu)
1626 {
1627 struct sample *sample = &cpu->sample;
1628 int32_t busy_frac, boost;
1629 int target, avg_pstate;
1630
1631 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
1632 sample->tsc);
1633
1634 boost = cpu->iowait_boost;
1635 cpu->iowait_boost >>= 1;
1636
1637 if (busy_frac < boost)
1638 busy_frac = boost;
1639
1640 sample->busy_scaled = busy_frac * 100;
1641
1642 target = global.no_turbo || global.turbo_disabled ?
1643 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1644 target += target >> 2;
1645 target = mul_fp(target, busy_frac);
1646 if (target < cpu->pstate.min_pstate)
1647 target = cpu->pstate.min_pstate;
1648
1649 /*
1650 * If the average P-state during the previous cycle was higher than the
1651 * current target, add 50% of the difference to the target to reduce
1652 * possible performance oscillations and offset possible performance
1653 * loss related to moving the workload from one CPU to another within
1654 * a package/module.
1655 */
1656 avg_pstate = get_avg_pstate(cpu);
1657 if (avg_pstate > target)
1658 target += (avg_pstate - target) >> 1;
1659
1660 return target;
1661 }
1662
1663 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
1664 {
1665 int32_t perf_scaled, max_pstate, current_pstate, sample_ratio;
1666 u64 duration_ns;
1667
1668 /*
1669 * perf_scaled is the ratio of the average P-state during the last
1670 * sampling period to the P-state requested last time (in percent).
1671 *
1672 * That measures the system's response to the previous P-state
1673 * selection.
1674 */
1675 max_pstate = cpu->pstate.max_pstate_physical;
1676 current_pstate = cpu->pstate.current_pstate;
1677 perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf,
1678 div_fp(100 * max_pstate, current_pstate));
1679
1680 /*
1681 * Since our utilization update callback will not run unless we are
1682 * in C0, check if the actual elapsed time is significantly greater (3x)
1683 * than our sample interval. If it is, then we were idle for a long
1684 * enough period of time to adjust our performance metric.
1685 */
1686 duration_ns = cpu->sample.time - cpu->last_sample_time;
1687 if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
1688 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns);
1689 perf_scaled = mul_fp(perf_scaled, sample_ratio);
1690 } else {
1691 sample_ratio = div_fp(100 * (cpu->sample.mperf << cpu->aperf_mperf_shift),
1692 cpu->sample.tsc);
1693 if (sample_ratio < int_tofp(1))
1694 perf_scaled = 0;
1695 }
1696
1697 cpu->sample.busy_scaled = perf_scaled;
1698 return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled);
1699 }
1700
1701 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1702 {
1703 int max_pstate = intel_pstate_get_base_pstate(cpu);
1704 int min_pstate;
1705
1706 min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
1707 max_pstate = max(min_pstate, cpu->max_perf_ratio);
1708 return clamp_t(int, pstate, min_pstate, max_pstate);
1709 }
1710
1711 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1712 {
1713 if (pstate == cpu->pstate.current_pstate)
1714 return;
1715
1716 cpu->pstate.current_pstate = pstate;
1717 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1718 }
1719
1720 static void intel_pstate_adjust_pstate(struct cpudata *cpu, int target_pstate)
1721 {
1722 int from = cpu->pstate.current_pstate;
1723 struct sample *sample;
1724
1725 update_turbo_state();
1726
1727 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1728 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1729 intel_pstate_update_pstate(cpu, target_pstate);
1730
1731 sample = &cpu->sample;
1732 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1733 fp_toint(sample->busy_scaled),
1734 from,
1735 cpu->pstate.current_pstate,
1736 sample->mperf,
1737 sample->aperf,
1738 sample->tsc,
1739 get_avg_frequency(cpu),
1740 fp_toint(cpu->iowait_boost * 100));
1741 }
1742
1743 static void intel_pstate_update_util_pid(struct update_util_data *data,
1744 u64 time, unsigned int flags)
1745 {
1746 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1747 u64 delta_ns = time - cpu->sample.time;
1748
1749 if ((s64)delta_ns < pid_params.sample_rate_ns)
1750 return;
1751
1752 if (intel_pstate_sample(cpu, time)) {
1753 int target_pstate;
1754
1755 target_pstate = get_target_pstate_use_performance(cpu);
1756 intel_pstate_adjust_pstate(cpu, target_pstate);
1757 }
1758 }
1759
1760 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1761 unsigned int flags)
1762 {
1763 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1764 u64 delta_ns;
1765
1766 if (flags & SCHED_CPUFREQ_IOWAIT) {
1767 cpu->iowait_boost = int_tofp(1);
1768 } else if (cpu->iowait_boost) {
1769 /* Clear iowait_boost if the CPU may have been idle. */
1770 delta_ns = time - cpu->last_update;
1771 if (delta_ns > TICK_NSEC)
1772 cpu->iowait_boost = 0;
1773 }
1774 cpu->last_update = time;
1775 delta_ns = time - cpu->sample.time;
1776 if ((s64)delta_ns < INTEL_PSTATE_DEFAULT_SAMPLING_INTERVAL)
1777 return;
1778
1779 if (intel_pstate_sample(cpu, time)) {
1780 int target_pstate;
1781
1782 target_pstate = get_target_pstate_use_cpu_load(cpu);
1783 intel_pstate_adjust_pstate(cpu, target_pstate);
1784 }
1785 }
1786
1787 static struct pstate_funcs core_funcs = {
1788 .get_max = core_get_max_pstate,
1789 .get_max_physical = core_get_max_pstate_physical,
1790 .get_min = core_get_min_pstate,
1791 .get_turbo = core_get_turbo_pstate,
1792 .get_scaling = core_get_scaling,
1793 .get_val = core_get_val,
1794 .update_util = intel_pstate_update_util_pid,
1795 };
1796
1797 static const struct pstate_funcs silvermont_funcs = {
1798 .get_max = atom_get_max_pstate,
1799 .get_max_physical = atom_get_max_pstate,
1800 .get_min = atom_get_min_pstate,
1801 .get_turbo = atom_get_turbo_pstate,
1802 .get_val = atom_get_val,
1803 .get_scaling = silvermont_get_scaling,
1804 .get_vid = atom_get_vid,
1805 .update_util = intel_pstate_update_util,
1806 };
1807
1808 static const struct pstate_funcs airmont_funcs = {
1809 .get_max = atom_get_max_pstate,
1810 .get_max_physical = atom_get_max_pstate,
1811 .get_min = atom_get_min_pstate,
1812 .get_turbo = atom_get_turbo_pstate,
1813 .get_val = atom_get_val,
1814 .get_scaling = airmont_get_scaling,
1815 .get_vid = atom_get_vid,
1816 .update_util = intel_pstate_update_util,
1817 };
1818
1819 static const struct pstate_funcs knl_funcs = {
1820 .get_max = core_get_max_pstate,
1821 .get_max_physical = core_get_max_pstate_physical,
1822 .get_min = core_get_min_pstate,
1823 .get_turbo = knl_get_turbo_pstate,
1824 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
1825 .get_scaling = core_get_scaling,
1826 .get_val = core_get_val,
1827 .update_util = intel_pstate_update_util_pid,
1828 };
1829
1830 static const struct pstate_funcs bxt_funcs = {
1831 .get_max = core_get_max_pstate,
1832 .get_max_physical = core_get_max_pstate_physical,
1833 .get_min = core_get_min_pstate,
1834 .get_turbo = core_get_turbo_pstate,
1835 .get_scaling = core_get_scaling,
1836 .get_val = core_get_val,
1837 .update_util = intel_pstate_update_util,
1838 };
1839
1840 #define ICPU(model, policy) \
1841 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1842 (unsigned long)&policy }
1843
1844 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1845 ICPU(INTEL_FAM6_SANDYBRIDGE, core_funcs),
1846 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_funcs),
1847 ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_funcs),
1848 ICPU(INTEL_FAM6_IVYBRIDGE, core_funcs),
1849 ICPU(INTEL_FAM6_HASWELL_CORE, core_funcs),
1850 ICPU(INTEL_FAM6_BROADWELL_CORE, core_funcs),
1851 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_funcs),
1852 ICPU(INTEL_FAM6_HASWELL_X, core_funcs),
1853 ICPU(INTEL_FAM6_HASWELL_ULT, core_funcs),
1854 ICPU(INTEL_FAM6_HASWELL_GT3E, core_funcs),
1855 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_funcs),
1856 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_funcs),
1857 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_funcs),
1858 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1859 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
1860 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1861 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_funcs),
1862 ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_funcs),
1863 ICPU(INTEL_FAM6_ATOM_GOLDMONT, bxt_funcs),
1864 ICPU(INTEL_FAM6_ATOM_GEMINI_LAKE, bxt_funcs),
1865 {}
1866 };
1867 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1868
1869 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1870 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1871 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1872 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1873 {}
1874 };
1875
1876 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1877 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_funcs),
1878 {}
1879 };
1880
1881 static bool pid_in_use(void);
1882
1883 static int intel_pstate_init_cpu(unsigned int cpunum)
1884 {
1885 struct cpudata *cpu;
1886
1887 cpu = all_cpu_data[cpunum];
1888
1889 if (!cpu) {
1890 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
1891 if (!cpu)
1892 return -ENOMEM;
1893
1894 all_cpu_data[cpunum] = cpu;
1895
1896 cpu->epp_default = -EINVAL;
1897 cpu->epp_powersave = -EINVAL;
1898 cpu->epp_saved = -EINVAL;
1899 }
1900
1901 cpu = all_cpu_data[cpunum];
1902
1903 cpu->cpu = cpunum;
1904
1905 if (hwp_active) {
1906 const struct x86_cpu_id *id;
1907
1908 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
1909 if (id)
1910 intel_pstate_disable_ee(cpunum);
1911
1912 intel_pstate_hwp_enable(cpu);
1913 } else if (pid_in_use()) {
1914 intel_pstate_pid_reset(cpu);
1915 }
1916
1917 intel_pstate_get_cpu_pstates(cpu);
1918
1919 pr_debug("controlling: cpu %d\n", cpunum);
1920
1921 return 0;
1922 }
1923
1924 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
1925 {
1926 struct cpudata *cpu = all_cpu_data[cpu_num];
1927
1928 if (hwp_active)
1929 return;
1930
1931 if (cpu->update_util_set)
1932 return;
1933
1934 /* Prevent intel_pstate_update_util() from using stale data. */
1935 cpu->sample.time = 0;
1936 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1937 pstate_funcs.update_util);
1938 cpu->update_util_set = true;
1939 }
1940
1941 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1942 {
1943 struct cpudata *cpu_data = all_cpu_data[cpu];
1944
1945 if (!cpu_data->update_util_set)
1946 return;
1947
1948 cpufreq_remove_update_util_hook(cpu);
1949 cpu_data->update_util_set = false;
1950 synchronize_sched();
1951 }
1952
1953 static int intel_pstate_get_max_freq(struct cpudata *cpu)
1954 {
1955 return global.turbo_disabled || global.no_turbo ?
1956 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
1957 }
1958
1959 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
1960 struct cpudata *cpu)
1961 {
1962 int max_freq = intel_pstate_get_max_freq(cpu);
1963 int32_t max_policy_perf, min_policy_perf;
1964 int max_state, turbo_max;
1965
1966 /*
1967 * HWP needs some special consideration, because on BDX the
1968 * HWP_REQUEST uses abstract value to represent performance
1969 * rather than pure ratios.
1970 */
1971 if (hwp_active) {
1972 intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state);
1973 } else {
1974 max_state = intel_pstate_get_base_pstate(cpu);
1975 turbo_max = cpu->pstate.turbo_pstate;
1976 }
1977
1978 max_policy_perf = max_state * policy->max / max_freq;
1979 if (policy->max == policy->min) {
1980 min_policy_perf = max_policy_perf;
1981 } else {
1982 min_policy_perf = max_state * policy->min / max_freq;
1983 min_policy_perf = clamp_t(int32_t, min_policy_perf,
1984 0, max_policy_perf);
1985 }
1986
1987 pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n",
1988 policy->cpu, max_state,
1989 min_policy_perf, max_policy_perf);
1990
1991 /* Normalize user input to [min_perf, max_perf] */
1992 if (per_cpu_limits) {
1993 cpu->min_perf_ratio = min_policy_perf;
1994 cpu->max_perf_ratio = max_policy_perf;
1995 } else {
1996 int32_t global_min, global_max;
1997
1998 /* Global limits are in percent of the maximum turbo P-state. */
1999 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2000 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2001 global_min = clamp_t(int32_t, global_min, 0, global_max);
2002
2003 pr_debug("cpu:%d global_min:%d global_max:%d\n", policy->cpu,
2004 global_min, global_max);
2005
2006 cpu->min_perf_ratio = max(min_policy_perf, global_min);
2007 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2008 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2009 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2010
2011 /* Make sure min_perf <= max_perf */
2012 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2013 cpu->max_perf_ratio);
2014
2015 }
2016 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", policy->cpu,
2017 cpu->max_perf_ratio,
2018 cpu->min_perf_ratio);
2019 }
2020
2021 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2022 {
2023 struct cpudata *cpu;
2024
2025 if (!policy->cpuinfo.max_freq)
2026 return -ENODEV;
2027
2028 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2029 policy->cpuinfo.max_freq, policy->max);
2030
2031 cpu = all_cpu_data[policy->cpu];
2032 cpu->policy = policy->policy;
2033
2034 mutex_lock(&intel_pstate_limits_lock);
2035
2036 intel_pstate_update_perf_limits(policy, cpu);
2037
2038 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2039 /*
2040 * NOHZ_FULL CPUs need this as the governor callback may not
2041 * be invoked on them.
2042 */
2043 intel_pstate_clear_update_util_hook(policy->cpu);
2044 intel_pstate_max_within_limits(cpu);
2045 } else {
2046 intel_pstate_set_update_util_hook(policy->cpu);
2047 }
2048
2049 if (hwp_active)
2050 intel_pstate_hwp_set(policy->cpu);
2051
2052 mutex_unlock(&intel_pstate_limits_lock);
2053
2054 return 0;
2055 }
2056
2057 static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy,
2058 struct cpudata *cpu)
2059 {
2060 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2061 policy->max < policy->cpuinfo.max_freq &&
2062 policy->max > cpu->pstate.max_freq) {
2063 pr_debug("policy->max > max non turbo frequency\n");
2064 policy->max = policy->cpuinfo.max_freq;
2065 }
2066 }
2067
2068 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
2069 {
2070 struct cpudata *cpu = all_cpu_data[policy->cpu];
2071
2072 update_turbo_state();
2073 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2074 intel_pstate_get_max_freq(cpu));
2075
2076 if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
2077 policy->policy != CPUFREQ_POLICY_PERFORMANCE)
2078 return -EINVAL;
2079
2080 intel_pstate_adjust_policy_max(policy, cpu);
2081
2082 return 0;
2083 }
2084
2085 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2086 {
2087 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2088 }
2089
2090 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2091 {
2092 pr_debug("CPU %d exiting\n", policy->cpu);
2093
2094 intel_pstate_clear_update_util_hook(policy->cpu);
2095 if (hwp_active)
2096 intel_pstate_hwp_save_state(policy);
2097 else
2098 intel_cpufreq_stop_cpu(policy);
2099 }
2100
2101 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2102 {
2103 intel_pstate_exit_perf_limits(policy);
2104
2105 policy->fast_switch_possible = false;
2106
2107 return 0;
2108 }
2109
2110 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2111 {
2112 struct cpudata *cpu;
2113 int rc;
2114
2115 rc = intel_pstate_init_cpu(policy->cpu);
2116 if (rc)
2117 return rc;
2118
2119 cpu = all_cpu_data[policy->cpu];
2120
2121 cpu->max_perf_ratio = 0xFF;
2122 cpu->min_perf_ratio = 0;
2123
2124 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2125 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2126
2127 /* cpuinfo and default policy values */
2128 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2129 update_turbo_state();
2130 policy->cpuinfo.max_freq = global.turbo_disabled ?
2131 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2132 policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2133
2134 intel_pstate_init_acpi_perf_limits(policy);
2135 cpumask_set_cpu(policy->cpu, policy->cpus);
2136
2137 policy->fast_switch_possible = true;
2138
2139 return 0;
2140 }
2141
2142 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2143 {
2144 int ret = __intel_pstate_cpu_init(policy);
2145
2146 if (ret)
2147 return ret;
2148
2149 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
2150 if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
2151 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2152 else
2153 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2154
2155 return 0;
2156 }
2157
2158 static struct cpufreq_driver intel_pstate = {
2159 .flags = CPUFREQ_CONST_LOOPS,
2160 .verify = intel_pstate_verify_policy,
2161 .setpolicy = intel_pstate_set_policy,
2162 .suspend = intel_pstate_hwp_save_state,
2163 .resume = intel_pstate_resume,
2164 .init = intel_pstate_cpu_init,
2165 .exit = intel_pstate_cpu_exit,
2166 .stop_cpu = intel_pstate_stop_cpu,
2167 .name = "intel_pstate",
2168 };
2169
2170 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2171 {
2172 struct cpudata *cpu = all_cpu_data[policy->cpu];
2173
2174 update_turbo_state();
2175 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2176 intel_pstate_get_max_freq(cpu));
2177
2178 intel_pstate_adjust_policy_max(policy, cpu);
2179
2180 intel_pstate_update_perf_limits(policy, cpu);
2181
2182 return 0;
2183 }
2184
2185 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2186 unsigned int target_freq,
2187 unsigned int relation)
2188 {
2189 struct cpudata *cpu = all_cpu_data[policy->cpu];
2190 struct cpufreq_freqs freqs;
2191 int target_pstate;
2192
2193 update_turbo_state();
2194
2195 freqs.old = policy->cur;
2196 freqs.new = target_freq;
2197
2198 cpufreq_freq_transition_begin(policy, &freqs);
2199 switch (relation) {
2200 case CPUFREQ_RELATION_L:
2201 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2202 break;
2203 case CPUFREQ_RELATION_H:
2204 target_pstate = freqs.new / cpu->pstate.scaling;
2205 break;
2206 default:
2207 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2208 break;
2209 }
2210 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2211 if (target_pstate != cpu->pstate.current_pstate) {
2212 cpu->pstate.current_pstate = target_pstate;
2213 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2214 pstate_funcs.get_val(cpu, target_pstate));
2215 }
2216 freqs.new = target_pstate * cpu->pstate.scaling;
2217 cpufreq_freq_transition_end(policy, &freqs, false);
2218
2219 return 0;
2220 }
2221
2222 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2223 unsigned int target_freq)
2224 {
2225 struct cpudata *cpu = all_cpu_data[policy->cpu];
2226 int target_pstate;
2227
2228 update_turbo_state();
2229
2230 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2231 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2232 intel_pstate_update_pstate(cpu, target_pstate);
2233 return target_pstate * cpu->pstate.scaling;
2234 }
2235
2236 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2237 {
2238 int ret = __intel_pstate_cpu_init(policy);
2239
2240 if (ret)
2241 return ret;
2242
2243 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2244 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
2245 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2246 policy->cur = policy->cpuinfo.min_freq;
2247
2248 return 0;
2249 }
2250
2251 static struct cpufreq_driver intel_cpufreq = {
2252 .flags = CPUFREQ_CONST_LOOPS,
2253 .verify = intel_cpufreq_verify_policy,
2254 .target = intel_cpufreq_target,
2255 .fast_switch = intel_cpufreq_fast_switch,
2256 .init = intel_cpufreq_cpu_init,
2257 .exit = intel_pstate_cpu_exit,
2258 .stop_cpu = intel_cpufreq_stop_cpu,
2259 .name = "intel_cpufreq",
2260 };
2261
2262 static struct cpufreq_driver *default_driver = &intel_pstate;
2263
2264 static bool pid_in_use(void)
2265 {
2266 return intel_pstate_driver == &intel_pstate &&
2267 pstate_funcs.update_util == intel_pstate_update_util_pid;
2268 }
2269
2270 static void intel_pstate_driver_cleanup(void)
2271 {
2272 unsigned int cpu;
2273
2274 get_online_cpus();
2275 for_each_online_cpu(cpu) {
2276 if (all_cpu_data[cpu]) {
2277 if (intel_pstate_driver == &intel_pstate)
2278 intel_pstate_clear_update_util_hook(cpu);
2279
2280 kfree(all_cpu_data[cpu]);
2281 all_cpu_data[cpu] = NULL;
2282 }
2283 }
2284 put_online_cpus();
2285 intel_pstate_driver = NULL;
2286 }
2287
2288 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
2289 {
2290 int ret;
2291
2292 memset(&global, 0, sizeof(global));
2293 global.max_perf_pct = 100;
2294
2295 intel_pstate_driver = driver;
2296 ret = cpufreq_register_driver(intel_pstate_driver);
2297 if (ret) {
2298 intel_pstate_driver_cleanup();
2299 return ret;
2300 }
2301
2302 global.min_perf_pct = min_perf_pct_min();
2303
2304 if (pid_in_use())
2305 intel_pstate_debug_expose_params();
2306
2307 return 0;
2308 }
2309
2310 static int intel_pstate_unregister_driver(void)
2311 {
2312 if (hwp_active)
2313 return -EBUSY;
2314
2315 if (pid_in_use())
2316 intel_pstate_debug_hide_params();
2317
2318 cpufreq_unregister_driver(intel_pstate_driver);
2319 intel_pstate_driver_cleanup();
2320
2321 return 0;
2322 }
2323
2324 static ssize_t intel_pstate_show_status(char *buf)
2325 {
2326 if (!intel_pstate_driver)
2327 return sprintf(buf, "off\n");
2328
2329 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2330 "active" : "passive");
2331 }
2332
2333 static int intel_pstate_update_status(const char *buf, size_t size)
2334 {
2335 int ret;
2336
2337 if (size == 3 && !strncmp(buf, "off", size))
2338 return intel_pstate_driver ?
2339 intel_pstate_unregister_driver() : -EINVAL;
2340
2341 if (size == 6 && !strncmp(buf, "active", size)) {
2342 if (intel_pstate_driver) {
2343 if (intel_pstate_driver == &intel_pstate)
2344 return 0;
2345
2346 ret = intel_pstate_unregister_driver();
2347 if (ret)
2348 return ret;
2349 }
2350
2351 return intel_pstate_register_driver(&intel_pstate);
2352 }
2353
2354 if (size == 7 && !strncmp(buf, "passive", size)) {
2355 if (intel_pstate_driver) {
2356 if (intel_pstate_driver == &intel_cpufreq)
2357 return 0;
2358
2359 ret = intel_pstate_unregister_driver();
2360 if (ret)
2361 return ret;
2362 }
2363
2364 return intel_pstate_register_driver(&intel_cpufreq);
2365 }
2366
2367 return -EINVAL;
2368 }
2369
2370 static int no_load __initdata;
2371 static int no_hwp __initdata;
2372 static int hwp_only __initdata;
2373 static unsigned int force_load __initdata;
2374
2375 static int __init intel_pstate_msrs_not_valid(void)
2376 {
2377 if (!pstate_funcs.get_max() ||
2378 !pstate_funcs.get_min() ||
2379 !pstate_funcs.get_turbo())
2380 return -ENODEV;
2381
2382 return 0;
2383 }
2384
2385 #ifdef CONFIG_ACPI
2386 static void intel_pstate_use_acpi_profile(void)
2387 {
2388 switch (acpi_gbl_FADT.preferred_profile) {
2389 case PM_MOBILE:
2390 case PM_TABLET:
2391 case PM_APPLIANCE_PC:
2392 case PM_DESKTOP:
2393 case PM_WORKSTATION:
2394 pstate_funcs.update_util = intel_pstate_update_util;
2395 }
2396 }
2397 #else
2398 static void intel_pstate_use_acpi_profile(void)
2399 {
2400 }
2401 #endif
2402
2403 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2404 {
2405 pstate_funcs.get_max = funcs->get_max;
2406 pstate_funcs.get_max_physical = funcs->get_max_physical;
2407 pstate_funcs.get_min = funcs->get_min;
2408 pstate_funcs.get_turbo = funcs->get_turbo;
2409 pstate_funcs.get_scaling = funcs->get_scaling;
2410 pstate_funcs.get_val = funcs->get_val;
2411 pstate_funcs.get_vid = funcs->get_vid;
2412 pstate_funcs.update_util = funcs->update_util;
2413 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
2414
2415 intel_pstate_use_acpi_profile();
2416 }
2417
2418 #ifdef CONFIG_ACPI
2419
2420 static bool __init intel_pstate_no_acpi_pss(void)
2421 {
2422 int i;
2423
2424 for_each_possible_cpu(i) {
2425 acpi_status status;
2426 union acpi_object *pss;
2427 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2428 struct acpi_processor *pr = per_cpu(processors, i);
2429
2430 if (!pr)
2431 continue;
2432
2433 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2434 if (ACPI_FAILURE(status))
2435 continue;
2436
2437 pss = buffer.pointer;
2438 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2439 kfree(pss);
2440 return false;
2441 }
2442
2443 kfree(pss);
2444 }
2445
2446 return true;
2447 }
2448
2449 static bool __init intel_pstate_has_acpi_ppc(void)
2450 {
2451 int i;
2452
2453 for_each_possible_cpu(i) {
2454 struct acpi_processor *pr = per_cpu(processors, i);
2455
2456 if (!pr)
2457 continue;
2458 if (acpi_has_method(pr->handle, "_PPC"))
2459 return true;
2460 }
2461 return false;
2462 }
2463
2464 enum {
2465 PSS,
2466 PPC,
2467 };
2468
2469 struct hw_vendor_info {
2470 u16 valid;
2471 char oem_id[ACPI_OEM_ID_SIZE];
2472 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
2473 int oem_pwr_table;
2474 };
2475
2476 /* Hardware vendor-specific info that has its own power management modes */
2477 static struct hw_vendor_info vendor_info[] __initdata = {
2478 {1, "HP ", "ProLiant", PSS},
2479 {1, "ORACLE", "X4-2 ", PPC},
2480 {1, "ORACLE", "X4-2L ", PPC},
2481 {1, "ORACLE", "X4-2B ", PPC},
2482 {1, "ORACLE", "X3-2 ", PPC},
2483 {1, "ORACLE", "X3-2L ", PPC},
2484 {1, "ORACLE", "X3-2B ", PPC},
2485 {1, "ORACLE", "X4470M2 ", PPC},
2486 {1, "ORACLE", "X4270M3 ", PPC},
2487 {1, "ORACLE", "X4270M2 ", PPC},
2488 {1, "ORACLE", "X4170M2 ", PPC},
2489 {1, "ORACLE", "X4170 M3", PPC},
2490 {1, "ORACLE", "X4275 M3", PPC},
2491 {1, "ORACLE", "X6-2 ", PPC},
2492 {1, "ORACLE", "Sudbury ", PPC},
2493 {0, "", ""},
2494 };
2495
2496 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2497 {
2498 struct acpi_table_header hdr;
2499 struct hw_vendor_info *v_info;
2500 const struct x86_cpu_id *id;
2501 u64 misc_pwr;
2502
2503 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2504 if (id) {
2505 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2506 if ( misc_pwr & (1 << 8))
2507 return true;
2508 }
2509
2510 if (acpi_disabled ||
2511 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
2512 return false;
2513
2514 for (v_info = vendor_info; v_info->valid; v_info++) {
2515 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
2516 !strncmp(hdr.oem_table_id, v_info->oem_table_id,
2517 ACPI_OEM_TABLE_ID_SIZE))
2518 switch (v_info->oem_pwr_table) {
2519 case PSS:
2520 return intel_pstate_no_acpi_pss();
2521 case PPC:
2522 return intel_pstate_has_acpi_ppc() &&
2523 (!force_load);
2524 }
2525 }
2526
2527 return false;
2528 }
2529
2530 static void intel_pstate_request_control_from_smm(void)
2531 {
2532 /*
2533 * It may be unsafe to request P-states control from SMM if _PPC support
2534 * has not been enabled.
2535 */
2536 if (acpi_ppc)
2537 acpi_processor_pstate_control();
2538 }
2539 #else /* CONFIG_ACPI not enabled */
2540 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2541 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2542 static inline void intel_pstate_request_control_from_smm(void) {}
2543 #endif /* CONFIG_ACPI */
2544
2545 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2546 { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
2547 {}
2548 };
2549
2550 static int __init intel_pstate_init(void)
2551 {
2552 int rc;
2553
2554 if (no_load)
2555 return -ENODEV;
2556
2557 if (x86_match_cpu(hwp_support_ids)) {
2558 copy_cpu_funcs(&core_funcs);
2559 if (no_hwp) {
2560 pstate_funcs.update_util = intel_pstate_update_util;
2561 } else {
2562 hwp_active++;
2563 intel_pstate.attr = hwp_cpufreq_attrs;
2564 goto hwp_cpu_matched;
2565 }
2566 } else {
2567 const struct x86_cpu_id *id;
2568
2569 id = x86_match_cpu(intel_pstate_cpu_ids);
2570 if (!id)
2571 return -ENODEV;
2572
2573 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
2574 }
2575
2576 if (intel_pstate_msrs_not_valid())
2577 return -ENODEV;
2578
2579 hwp_cpu_matched:
2580 /*
2581 * The Intel pstate driver will be ignored if the platform
2582 * firmware has its own power management modes.
2583 */
2584 if (intel_pstate_platform_pwr_mgmt_exists())
2585 return -ENODEV;
2586
2587 if (!hwp_active && hwp_only)
2588 return -ENOTSUPP;
2589
2590 pr_info("Intel P-state driver initializing\n");
2591
2592 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
2593 if (!all_cpu_data)
2594 return -ENOMEM;
2595
2596 intel_pstate_request_control_from_smm();
2597
2598 intel_pstate_sysfs_expose_params();
2599
2600 mutex_lock(&intel_pstate_driver_lock);
2601 rc = intel_pstate_register_driver(default_driver);
2602 mutex_unlock(&intel_pstate_driver_lock);
2603 if (rc)
2604 return rc;
2605
2606 if (hwp_active)
2607 pr_info("HWP enabled\n");
2608
2609 return 0;
2610 }
2611 device_initcall(intel_pstate_init);
2612
2613 static int __init intel_pstate_setup(char *str)
2614 {
2615 if (!str)
2616 return -EINVAL;
2617
2618 if (!strcmp(str, "disable")) {
2619 no_load = 1;
2620 } else if (!strcmp(str, "passive")) {
2621 pr_info("Passive mode enabled\n");
2622 default_driver = &intel_cpufreq;
2623 no_hwp = 1;
2624 }
2625 if (!strcmp(str, "no_hwp")) {
2626 pr_info("HWP disabled\n");
2627 no_hwp = 1;
2628 }
2629 if (!strcmp(str, "force"))
2630 force_load = 1;
2631 if (!strcmp(str, "hwp_only"))
2632 hwp_only = 1;
2633 if (!strcmp(str, "per_cpu_perf_limits"))
2634 per_cpu_limits = true;
2635
2636 #ifdef CONFIG_ACPI
2637 if (!strcmp(str, "support_acpi_ppc"))
2638 acpi_ppc = true;
2639 #endif
2640
2641 return 0;
2642 }
2643 early_param("intel_pstate", intel_pstate_setup);
2644
2645 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2646 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2647 MODULE_LICENSE("GPL");
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