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[mirror_ubuntu-artful-kernel.git] / drivers / cpufreq / intel_pstate.c
1 /*
2 * intel_pstate.c: Native P state management for Intel processors
3 *
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 */
12
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15 #include <linux/kernel.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/ktime.h>
19 #include <linux/hrtimer.h>
20 #include <linux/tick.h>
21 #include <linux/slab.h>
22 #include <linux/sched/cpufreq.h>
23 #include <linux/list.h>
24 #include <linux/cpu.h>
25 #include <linux/cpufreq.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
28 #include <linux/fs.h>
29 #include <linux/debugfs.h>
30 #include <linux/acpi.h>
31 #include <linux/vmalloc.h>
32 #include <trace/events/power.h>
33
34 #include <asm/div64.h>
35 #include <asm/msr.h>
36 #include <asm/cpu_device_id.h>
37 #include <asm/cpufeature.h>
38 #include <asm/intel-family.h>
39
40 #define INTEL_PSTATE_DEFAULT_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
41 #define INTEL_PSTATE_HWP_SAMPLING_INTERVAL (50 * NSEC_PER_MSEC)
42
43 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
44 #define INTEL_CPUFREQ_TRANSITION_DELAY 500
45
46 #ifdef CONFIG_ACPI
47 #include <acpi/processor.h>
48 #include <acpi/cppc_acpi.h>
49 #endif
50
51 #define FRAC_BITS 8
52 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
53 #define fp_toint(X) ((X) >> FRAC_BITS)
54
55 #define EXT_BITS 6
56 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
57 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
58 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
59
60 static inline int32_t mul_fp(int32_t x, int32_t y)
61 {
62 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
63 }
64
65 static inline int32_t div_fp(s64 x, s64 y)
66 {
67 return div64_s64((int64_t)x << FRAC_BITS, y);
68 }
69
70 static inline int ceiling_fp(int32_t x)
71 {
72 int mask, ret;
73
74 ret = fp_toint(x);
75 mask = (1 << FRAC_BITS) - 1;
76 if (x & mask)
77 ret += 1;
78 return ret;
79 }
80
81 static inline int32_t percent_fp(int percent)
82 {
83 return div_fp(percent, 100);
84 }
85
86 static inline u64 mul_ext_fp(u64 x, u64 y)
87 {
88 return (x * y) >> EXT_FRAC_BITS;
89 }
90
91 static inline u64 div_ext_fp(u64 x, u64 y)
92 {
93 return div64_u64(x << EXT_FRAC_BITS, y);
94 }
95
96 static inline int32_t percent_ext_fp(int percent)
97 {
98 return div_ext_fp(percent, 100);
99 }
100
101 /**
102 * struct sample - Store performance sample
103 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
104 * performance during last sample period
105 * @busy_scaled: Scaled busy value which is used to calculate next
106 * P state. This can be different than core_avg_perf
107 * to account for cpu idle period
108 * @aperf: Difference of actual performance frequency clock count
109 * read from APERF MSR between last and current sample
110 * @mperf: Difference of maximum performance frequency clock count
111 * read from MPERF MSR between last and current sample
112 * @tsc: Difference of time stamp counter between last and
113 * current sample
114 * @time: Current time from scheduler
115 *
116 * This structure is used in the cpudata structure to store performance sample
117 * data for choosing next P State.
118 */
119 struct sample {
120 int32_t core_avg_perf;
121 int32_t busy_scaled;
122 u64 aperf;
123 u64 mperf;
124 u64 tsc;
125 u64 time;
126 };
127
128 /**
129 * struct pstate_data - Store P state data
130 * @current_pstate: Current requested P state
131 * @min_pstate: Min P state possible for this platform
132 * @max_pstate: Max P state possible for this platform
133 * @max_pstate_physical:This is physical Max P state for a processor
134 * This can be higher than the max_pstate which can
135 * be limited by platform thermal design power limits
136 * @scaling: Scaling factor to convert frequency to cpufreq
137 * frequency units
138 * @turbo_pstate: Max Turbo P state possible for this platform
139 * @max_freq: @max_pstate frequency in cpufreq units
140 * @turbo_freq: @turbo_pstate frequency in cpufreq units
141 *
142 * Stores the per cpu model P state limits and current P state.
143 */
144 struct pstate_data {
145 int current_pstate;
146 int min_pstate;
147 int max_pstate;
148 int max_pstate_physical;
149 int scaling;
150 int turbo_pstate;
151 unsigned int max_freq;
152 unsigned int turbo_freq;
153 };
154
155 /**
156 * struct vid_data - Stores voltage information data
157 * @min: VID data for this platform corresponding to
158 * the lowest P state
159 * @max: VID data corresponding to the highest P State.
160 * @turbo: VID data for turbo P state
161 * @ratio: Ratio of (vid max - vid min) /
162 * (max P state - Min P State)
163 *
164 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
165 * This data is used in Atom platforms, where in addition to target P state,
166 * the voltage data needs to be specified to select next P State.
167 */
168 struct vid_data {
169 int min;
170 int max;
171 int turbo;
172 int32_t ratio;
173 };
174
175 /**
176 * struct _pid - Stores PID data
177 * @setpoint: Target set point for busyness or performance
178 * @integral: Storage for accumulated error values
179 * @p_gain: PID proportional gain
180 * @i_gain: PID integral gain
181 * @d_gain: PID derivative gain
182 * @deadband: PID deadband
183 * @last_err: Last error storage for integral part of PID calculation
184 *
185 * Stores PID coefficients and last error for PID controller.
186 */
187 struct _pid {
188 int setpoint;
189 int32_t integral;
190 int32_t p_gain;
191 int32_t i_gain;
192 int32_t d_gain;
193 int deadband;
194 int32_t last_err;
195 };
196
197 /**
198 * struct global_params - Global parameters, mostly tunable via sysfs.
199 * @no_turbo: Whether or not to use turbo P-states.
200 * @turbo_disabled: Whethet or not turbo P-states are available at all,
201 * based on the MSR_IA32_MISC_ENABLE value and whether or
202 * not the maximum reported turbo P-state is different from
203 * the maximum reported non-turbo one.
204 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
205 * P-state capacity.
206 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
207 * P-state capacity.
208 */
209 struct global_params {
210 bool no_turbo;
211 bool turbo_disabled;
212 int max_perf_pct;
213 int min_perf_pct;
214 };
215
216 /**
217 * struct cpudata - Per CPU instance data storage
218 * @cpu: CPU number for this instance data
219 * @policy: CPUFreq policy value
220 * @update_util: CPUFreq utility callback information
221 * @update_util_set: CPUFreq utility callback is set
222 * @iowait_boost: iowait-related boost fraction
223 * @last_update: Time of the last update.
224 * @pstate: Stores P state limits for this CPU
225 * @vid: Stores VID limits for this CPU
226 * @pid: Stores PID parameters for this CPU
227 * @last_sample_time: Last Sample time
228 * @prev_aperf: Last APERF value read from APERF MSR
229 * @prev_mperf: Last MPERF value read from MPERF MSR
230 * @prev_tsc: Last timestamp counter (TSC) value
231 * @prev_cummulative_iowait: IO Wait time difference from last and
232 * current sample
233 * @sample: Storage for storing last Sample data
234 * @min_perf: Minimum capacity limit as a fraction of the maximum
235 * turbo P-state capacity.
236 * @max_perf: Maximum capacity limit as a fraction of the maximum
237 * turbo P-state capacity.
238 * @acpi_perf_data: Stores ACPI perf information read from _PSS
239 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
240 * @epp_powersave: Last saved HWP energy performance preference
241 * (EPP) or energy performance bias (EPB),
242 * when policy switched to performance
243 * @epp_policy: Last saved policy used to set EPP/EPB
244 * @epp_default: Power on default HWP energy performance
245 * preference/bias
246 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
247 * operation
248 *
249 * This structure stores per CPU instance data for all CPUs.
250 */
251 struct cpudata {
252 int cpu;
253
254 unsigned int policy;
255 struct update_util_data update_util;
256 bool update_util_set;
257
258 struct pstate_data pstate;
259 struct vid_data vid;
260 struct _pid pid;
261
262 u64 last_update;
263 u64 last_sample_time;
264 u64 prev_aperf;
265 u64 prev_mperf;
266 u64 prev_tsc;
267 u64 prev_cummulative_iowait;
268 struct sample sample;
269 int32_t min_perf;
270 int32_t max_perf;
271 #ifdef CONFIG_ACPI
272 struct acpi_processor_performance acpi_perf_data;
273 bool valid_pss_table;
274 #endif
275 unsigned int iowait_boost;
276 s16 epp_powersave;
277 s16 epp_policy;
278 s16 epp_default;
279 s16 epp_saved;
280 };
281
282 static struct cpudata **all_cpu_data;
283
284 /**
285 * struct pstate_adjust_policy - Stores static PID configuration data
286 * @sample_rate_ms: PID calculation sample rate in ms
287 * @sample_rate_ns: Sample rate calculation in ns
288 * @deadband: PID deadband
289 * @setpoint: PID Setpoint
290 * @p_gain_pct: PID proportional gain
291 * @i_gain_pct: PID integral gain
292 * @d_gain_pct: PID derivative gain
293 *
294 * Stores per CPU model static PID configuration data.
295 */
296 struct pstate_adjust_policy {
297 int sample_rate_ms;
298 s64 sample_rate_ns;
299 int deadband;
300 int setpoint;
301 int p_gain_pct;
302 int d_gain_pct;
303 int i_gain_pct;
304 };
305
306 /**
307 * struct pstate_funcs - Per CPU model specific callbacks
308 * @get_max: Callback to get maximum non turbo effective P state
309 * @get_max_physical: Callback to get maximum non turbo physical P state
310 * @get_min: Callback to get minimum P state
311 * @get_turbo: Callback to get turbo P state
312 * @get_scaling: Callback to get frequency scaling factor
313 * @get_val: Callback to convert P state to actual MSR write value
314 * @get_vid: Callback to get VID data for Atom platforms
315 * @update_util: Active mode utilization update callback.
316 *
317 * Core and Atom CPU models have different way to get P State limits. This
318 * structure is used to store those callbacks.
319 */
320 struct pstate_funcs {
321 int (*get_max)(void);
322 int (*get_max_physical)(void);
323 int (*get_min)(void);
324 int (*get_turbo)(void);
325 int (*get_scaling)(void);
326 u64 (*get_val)(struct cpudata*, int pstate);
327 void (*get_vid)(struct cpudata *);
328 void (*update_util)(struct update_util_data *data, u64 time,
329 unsigned int flags);
330 };
331
332 static struct pstate_funcs pstate_funcs __read_mostly;
333 static struct pstate_adjust_policy pid_params __read_mostly = {
334 .sample_rate_ms = 10,
335 .sample_rate_ns = 10 * NSEC_PER_MSEC,
336 .deadband = 0,
337 .setpoint = 97,
338 .p_gain_pct = 20,
339 .d_gain_pct = 0,
340 .i_gain_pct = 0,
341 };
342
343 static int hwp_active __read_mostly;
344 static bool per_cpu_limits __read_mostly;
345
346 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
347
348 #ifdef CONFIG_ACPI
349 static bool acpi_ppc;
350 #endif
351
352 static struct global_params global;
353
354 static DEFINE_MUTEX(intel_pstate_driver_lock);
355 static DEFINE_MUTEX(intel_pstate_limits_lock);
356
357 #ifdef CONFIG_ACPI
358
359 static bool intel_pstate_get_ppc_enable_status(void)
360 {
361 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
362 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
363 return true;
364
365 return acpi_ppc;
366 }
367
368 #ifdef CONFIG_ACPI_CPPC_LIB
369
370 /* The work item is needed to avoid CPU hotplug locking issues */
371 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
372 {
373 sched_set_itmt_support();
374 }
375
376 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
377
378 static void intel_pstate_set_itmt_prio(int cpu)
379 {
380 struct cppc_perf_caps cppc_perf;
381 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
382 int ret;
383
384 ret = cppc_get_perf_caps(cpu, &cppc_perf);
385 if (ret)
386 return;
387
388 /*
389 * The priorities can be set regardless of whether or not
390 * sched_set_itmt_support(true) has been called and it is valid to
391 * update them at any time after it has been called.
392 */
393 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
394
395 if (max_highest_perf <= min_highest_perf) {
396 if (cppc_perf.highest_perf > max_highest_perf)
397 max_highest_perf = cppc_perf.highest_perf;
398
399 if (cppc_perf.highest_perf < min_highest_perf)
400 min_highest_perf = cppc_perf.highest_perf;
401
402 if (max_highest_perf > min_highest_perf) {
403 /*
404 * This code can be run during CPU online under the
405 * CPU hotplug locks, so sched_set_itmt_support()
406 * cannot be called from here. Queue up a work item
407 * to invoke it.
408 */
409 schedule_work(&sched_itmt_work);
410 }
411 }
412 }
413 #else
414 static void intel_pstate_set_itmt_prio(int cpu)
415 {
416 }
417 #endif
418
419 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
420 {
421 struct cpudata *cpu;
422 int ret;
423 int i;
424
425 if (hwp_active) {
426 intel_pstate_set_itmt_prio(policy->cpu);
427 return;
428 }
429
430 if (!intel_pstate_get_ppc_enable_status())
431 return;
432
433 cpu = all_cpu_data[policy->cpu];
434
435 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
436 policy->cpu);
437 if (ret)
438 return;
439
440 /*
441 * Check if the control value in _PSS is for PERF_CTL MSR, which should
442 * guarantee that the states returned by it map to the states in our
443 * list directly.
444 */
445 if (cpu->acpi_perf_data.control_register.space_id !=
446 ACPI_ADR_SPACE_FIXED_HARDWARE)
447 goto err;
448
449 /*
450 * If there is only one entry _PSS, simply ignore _PSS and continue as
451 * usual without taking _PSS into account
452 */
453 if (cpu->acpi_perf_data.state_count < 2)
454 goto err;
455
456 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
457 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
458 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
459 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
460 (u32) cpu->acpi_perf_data.states[i].core_frequency,
461 (u32) cpu->acpi_perf_data.states[i].power,
462 (u32) cpu->acpi_perf_data.states[i].control);
463 }
464
465 /*
466 * The _PSS table doesn't contain whole turbo frequency range.
467 * This just contains +1 MHZ above the max non turbo frequency,
468 * with control value corresponding to max turbo ratio. But
469 * when cpufreq set policy is called, it will call with this
470 * max frequency, which will cause a reduced performance as
471 * this driver uses real max turbo frequency as the max
472 * frequency. So correct this frequency in _PSS table to
473 * correct max turbo frequency based on the turbo state.
474 * Also need to convert to MHz as _PSS freq is in MHz.
475 */
476 if (!global.turbo_disabled)
477 cpu->acpi_perf_data.states[0].core_frequency =
478 policy->cpuinfo.max_freq / 1000;
479 cpu->valid_pss_table = true;
480 pr_debug("_PPC limits will be enforced\n");
481
482 return;
483
484 err:
485 cpu->valid_pss_table = false;
486 acpi_processor_unregister_performance(policy->cpu);
487 }
488
489 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
490 {
491 struct cpudata *cpu;
492
493 cpu = all_cpu_data[policy->cpu];
494 if (!cpu->valid_pss_table)
495 return;
496
497 acpi_processor_unregister_performance(policy->cpu);
498 }
499 #else
500 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
501 {
502 }
503
504 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
505 {
506 }
507 #endif
508
509 static signed int pid_calc(struct _pid *pid, int32_t busy)
510 {
511 signed int result;
512 int32_t pterm, dterm, fp_error;
513 int32_t integral_limit;
514
515 fp_error = pid->setpoint - busy;
516
517 if (abs(fp_error) <= pid->deadband)
518 return 0;
519
520 pterm = mul_fp(pid->p_gain, fp_error);
521
522 pid->integral += fp_error;
523
524 /*
525 * We limit the integral here so that it will never
526 * get higher than 30. This prevents it from becoming
527 * too large an input over long periods of time and allows
528 * it to get factored out sooner.
529 *
530 * The value of 30 was chosen through experimentation.
531 */
532 integral_limit = int_tofp(30);
533 if (pid->integral > integral_limit)
534 pid->integral = integral_limit;
535 if (pid->integral < -integral_limit)
536 pid->integral = -integral_limit;
537
538 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
539 pid->last_err = fp_error;
540
541 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
542 result = result + (1 << (FRAC_BITS-1));
543 return (signed int)fp_toint(result);
544 }
545
546 static inline void intel_pstate_pid_reset(struct cpudata *cpu)
547 {
548 struct _pid *pid = &cpu->pid;
549
550 pid->p_gain = percent_fp(pid_params.p_gain_pct);
551 pid->d_gain = percent_fp(pid_params.d_gain_pct);
552 pid->i_gain = percent_fp(pid_params.i_gain_pct);
553 pid->setpoint = int_tofp(pid_params.setpoint);
554 pid->last_err = pid->setpoint - int_tofp(100);
555 pid->deadband = int_tofp(pid_params.deadband);
556 pid->integral = 0;
557 }
558
559 static inline void update_turbo_state(void)
560 {
561 u64 misc_en;
562 struct cpudata *cpu;
563
564 cpu = all_cpu_data[0];
565 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
566 global.turbo_disabled =
567 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
568 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
569 }
570
571 static int min_perf_pct_min(void)
572 {
573 struct cpudata *cpu = all_cpu_data[0];
574
575 return DIV_ROUND_UP(cpu->pstate.min_pstate * 100,
576 cpu->pstate.turbo_pstate);
577 }
578
579 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
580 {
581 u64 epb;
582 int ret;
583
584 if (!static_cpu_has(X86_FEATURE_EPB))
585 return -ENXIO;
586
587 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
588 if (ret)
589 return (s16)ret;
590
591 return (s16)(epb & 0x0f);
592 }
593
594 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
595 {
596 s16 epp;
597
598 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
599 /*
600 * When hwp_req_data is 0, means that caller didn't read
601 * MSR_HWP_REQUEST, so need to read and get EPP.
602 */
603 if (!hwp_req_data) {
604 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
605 &hwp_req_data);
606 if (epp)
607 return epp;
608 }
609 epp = (hwp_req_data >> 24) & 0xff;
610 } else {
611 /* When there is no EPP present, HWP uses EPB settings */
612 epp = intel_pstate_get_epb(cpu_data);
613 }
614
615 return epp;
616 }
617
618 static int intel_pstate_set_epb(int cpu, s16 pref)
619 {
620 u64 epb;
621 int ret;
622
623 if (!static_cpu_has(X86_FEATURE_EPB))
624 return -ENXIO;
625
626 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
627 if (ret)
628 return ret;
629
630 epb = (epb & ~0x0f) | pref;
631 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
632
633 return 0;
634 }
635
636 /*
637 * EPP/EPB display strings corresponding to EPP index in the
638 * energy_perf_strings[]
639 * index String
640 *-------------------------------------
641 * 0 default
642 * 1 performance
643 * 2 balance_performance
644 * 3 balance_power
645 * 4 power
646 */
647 static const char * const energy_perf_strings[] = {
648 "default",
649 "performance",
650 "balance_performance",
651 "balance_power",
652 "power",
653 NULL
654 };
655
656 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
657 {
658 s16 epp;
659 int index = -EINVAL;
660
661 epp = intel_pstate_get_epp(cpu_data, 0);
662 if (epp < 0)
663 return epp;
664
665 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
666 /*
667 * Range:
668 * 0x00-0x3F : Performance
669 * 0x40-0x7F : Balance performance
670 * 0x80-0xBF : Balance power
671 * 0xC0-0xFF : Power
672 * The EPP is a 8 bit value, but our ranges restrict the
673 * value which can be set. Here only using top two bits
674 * effectively.
675 */
676 index = (epp >> 6) + 1;
677 } else if (static_cpu_has(X86_FEATURE_EPB)) {
678 /*
679 * Range:
680 * 0x00-0x03 : Performance
681 * 0x04-0x07 : Balance performance
682 * 0x08-0x0B : Balance power
683 * 0x0C-0x0F : Power
684 * The EPB is a 4 bit value, but our ranges restrict the
685 * value which can be set. Here only using top two bits
686 * effectively.
687 */
688 index = (epp >> 2) + 1;
689 }
690
691 return index;
692 }
693
694 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
695 int pref_index)
696 {
697 int epp = -EINVAL;
698 int ret;
699
700 if (!pref_index)
701 epp = cpu_data->epp_default;
702
703 mutex_lock(&intel_pstate_limits_lock);
704
705 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
706 u64 value;
707
708 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
709 if (ret)
710 goto return_pref;
711
712 value &= ~GENMASK_ULL(31, 24);
713
714 /*
715 * If epp is not default, convert from index into
716 * energy_perf_strings to epp value, by shifting 6
717 * bits left to use only top two bits in epp.
718 * The resultant epp need to shifted by 24 bits to
719 * epp position in MSR_HWP_REQUEST.
720 */
721 if (epp == -EINVAL)
722 epp = (pref_index - 1) << 6;
723
724 value |= (u64)epp << 24;
725 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
726 } else {
727 if (epp == -EINVAL)
728 epp = (pref_index - 1) << 2;
729 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
730 }
731 return_pref:
732 mutex_unlock(&intel_pstate_limits_lock);
733
734 return ret;
735 }
736
737 static ssize_t show_energy_performance_available_preferences(
738 struct cpufreq_policy *policy, char *buf)
739 {
740 int i = 0;
741 int ret = 0;
742
743 while (energy_perf_strings[i] != NULL)
744 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
745
746 ret += sprintf(&buf[ret], "\n");
747
748 return ret;
749 }
750
751 cpufreq_freq_attr_ro(energy_performance_available_preferences);
752
753 static ssize_t store_energy_performance_preference(
754 struct cpufreq_policy *policy, const char *buf, size_t count)
755 {
756 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
757 char str_preference[21];
758 int ret, i = 0;
759
760 ret = sscanf(buf, "%20s", str_preference);
761 if (ret != 1)
762 return -EINVAL;
763
764 while (energy_perf_strings[i] != NULL) {
765 if (!strcmp(str_preference, energy_perf_strings[i])) {
766 intel_pstate_set_energy_pref_index(cpu_data, i);
767 return count;
768 }
769 ++i;
770 }
771
772 return -EINVAL;
773 }
774
775 static ssize_t show_energy_performance_preference(
776 struct cpufreq_policy *policy, char *buf)
777 {
778 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
779 int preference;
780
781 preference = intel_pstate_get_energy_pref_index(cpu_data);
782 if (preference < 0)
783 return preference;
784
785 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
786 }
787
788 cpufreq_freq_attr_rw(energy_performance_preference);
789
790 static struct freq_attr *hwp_cpufreq_attrs[] = {
791 &energy_performance_preference,
792 &energy_performance_available_preferences,
793 NULL,
794 };
795
796 static void intel_pstate_hwp_set(unsigned int cpu)
797 {
798 struct cpudata *cpu_data = all_cpu_data[cpu];
799 int min, hw_min, max, hw_max;
800 u64 value, cap;
801 s16 epp;
802
803 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
804 hw_min = HWP_LOWEST_PERF(cap);
805 if (global.no_turbo)
806 hw_max = HWP_GUARANTEED_PERF(cap);
807 else
808 hw_max = HWP_HIGHEST_PERF(cap);
809
810 max = fp_ext_toint(hw_max * cpu_data->max_perf);
811 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
812 min = max;
813 else
814 min = fp_ext_toint(hw_max * cpu_data->min_perf);
815
816 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
817
818 value &= ~HWP_MIN_PERF(~0L);
819 value |= HWP_MIN_PERF(min);
820
821 value &= ~HWP_MAX_PERF(~0L);
822 value |= HWP_MAX_PERF(max);
823
824 if (cpu_data->epp_policy == cpu_data->policy)
825 goto skip_epp;
826
827 cpu_data->epp_policy = cpu_data->policy;
828
829 if (cpu_data->epp_saved >= 0) {
830 epp = cpu_data->epp_saved;
831 cpu_data->epp_saved = -EINVAL;
832 goto update_epp;
833 }
834
835 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
836 epp = intel_pstate_get_epp(cpu_data, value);
837 cpu_data->epp_powersave = epp;
838 /* If EPP read was failed, then don't try to write */
839 if (epp < 0)
840 goto skip_epp;
841
842 epp = 0;
843 } else {
844 /* skip setting EPP, when saved value is invalid */
845 if (cpu_data->epp_powersave < 0)
846 goto skip_epp;
847
848 /*
849 * No need to restore EPP when it is not zero. This
850 * means:
851 * - Policy is not changed
852 * - user has manually changed
853 * - Error reading EPB
854 */
855 epp = intel_pstate_get_epp(cpu_data, value);
856 if (epp)
857 goto skip_epp;
858
859 epp = cpu_data->epp_powersave;
860 }
861 update_epp:
862 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
863 value &= ~GENMASK_ULL(31, 24);
864 value |= (u64)epp << 24;
865 } else {
866 intel_pstate_set_epb(cpu, epp);
867 }
868 skip_epp:
869 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
870 }
871
872 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
873 {
874 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
875
876 if (!hwp_active)
877 return 0;
878
879 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
880
881 return 0;
882 }
883
884 static int intel_pstate_resume(struct cpufreq_policy *policy)
885 {
886 if (!hwp_active)
887 return 0;
888
889 mutex_lock(&intel_pstate_limits_lock);
890
891 all_cpu_data[policy->cpu]->epp_policy = 0;
892 intel_pstate_hwp_set(policy->cpu);
893
894 mutex_unlock(&intel_pstate_limits_lock);
895
896 return 0;
897 }
898
899 static void intel_pstate_update_policies(void)
900 {
901 int cpu;
902
903 for_each_possible_cpu(cpu)
904 cpufreq_update_policy(cpu);
905 }
906
907 /************************** debugfs begin ************************/
908 static int pid_param_set(void *data, u64 val)
909 {
910 unsigned int cpu;
911
912 *(u32 *)data = val;
913 pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
914 for_each_possible_cpu(cpu)
915 if (all_cpu_data[cpu])
916 intel_pstate_pid_reset(all_cpu_data[cpu]);
917
918 return 0;
919 }
920
921 static int pid_param_get(void *data, u64 *val)
922 {
923 *val = *(u32 *)data;
924 return 0;
925 }
926 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
927
928 static struct dentry *debugfs_parent;
929
930 struct pid_param {
931 char *name;
932 void *value;
933 struct dentry *dentry;
934 };
935
936 static struct pid_param pid_files[] = {
937 {"sample_rate_ms", &pid_params.sample_rate_ms, },
938 {"d_gain_pct", &pid_params.d_gain_pct, },
939 {"i_gain_pct", &pid_params.i_gain_pct, },
940 {"deadband", &pid_params.deadband, },
941 {"setpoint", &pid_params.setpoint, },
942 {"p_gain_pct", &pid_params.p_gain_pct, },
943 {NULL, NULL, }
944 };
945
946 static void intel_pstate_debug_expose_params(void)
947 {
948 int i;
949
950 debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
951 if (IS_ERR_OR_NULL(debugfs_parent))
952 return;
953
954 for (i = 0; pid_files[i].name; i++) {
955 struct dentry *dentry;
956
957 dentry = debugfs_create_file(pid_files[i].name, 0660,
958 debugfs_parent, pid_files[i].value,
959 &fops_pid_param);
960 if (!IS_ERR(dentry))
961 pid_files[i].dentry = dentry;
962 }
963 }
964
965 static void intel_pstate_debug_hide_params(void)
966 {
967 int i;
968
969 if (IS_ERR_OR_NULL(debugfs_parent))
970 return;
971
972 for (i = 0; pid_files[i].name; i++) {
973 debugfs_remove(pid_files[i].dentry);
974 pid_files[i].dentry = NULL;
975 }
976
977 debugfs_remove(debugfs_parent);
978 debugfs_parent = NULL;
979 }
980
981 /************************** debugfs end ************************/
982
983 /************************** sysfs begin ************************/
984 #define show_one(file_name, object) \
985 static ssize_t show_##file_name \
986 (struct kobject *kobj, struct attribute *attr, char *buf) \
987 { \
988 return sprintf(buf, "%u\n", global.object); \
989 }
990
991 static ssize_t intel_pstate_show_status(char *buf);
992 static int intel_pstate_update_status(const char *buf, size_t size);
993
994 static ssize_t show_status(struct kobject *kobj,
995 struct attribute *attr, char *buf)
996 {
997 ssize_t ret;
998
999 mutex_lock(&intel_pstate_driver_lock);
1000 ret = intel_pstate_show_status(buf);
1001 mutex_unlock(&intel_pstate_driver_lock);
1002
1003 return ret;
1004 }
1005
1006 static ssize_t store_status(struct kobject *a, struct attribute *b,
1007 const char *buf, size_t count)
1008 {
1009 char *p = memchr(buf, '\n', count);
1010 int ret;
1011
1012 mutex_lock(&intel_pstate_driver_lock);
1013 ret = intel_pstate_update_status(buf, p ? p - buf : count);
1014 mutex_unlock(&intel_pstate_driver_lock);
1015
1016 return ret < 0 ? ret : count;
1017 }
1018
1019 static ssize_t show_turbo_pct(struct kobject *kobj,
1020 struct attribute *attr, char *buf)
1021 {
1022 struct cpudata *cpu;
1023 int total, no_turbo, turbo_pct;
1024 uint32_t turbo_fp;
1025
1026 mutex_lock(&intel_pstate_driver_lock);
1027
1028 if (!intel_pstate_driver) {
1029 mutex_unlock(&intel_pstate_driver_lock);
1030 return -EAGAIN;
1031 }
1032
1033 cpu = all_cpu_data[0];
1034
1035 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1036 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1037 turbo_fp = div_fp(no_turbo, total);
1038 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1039
1040 mutex_unlock(&intel_pstate_driver_lock);
1041
1042 return sprintf(buf, "%u\n", turbo_pct);
1043 }
1044
1045 static ssize_t show_num_pstates(struct kobject *kobj,
1046 struct attribute *attr, char *buf)
1047 {
1048 struct cpudata *cpu;
1049 int total;
1050
1051 mutex_lock(&intel_pstate_driver_lock);
1052
1053 if (!intel_pstate_driver) {
1054 mutex_unlock(&intel_pstate_driver_lock);
1055 return -EAGAIN;
1056 }
1057
1058 cpu = all_cpu_data[0];
1059 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1060
1061 mutex_unlock(&intel_pstate_driver_lock);
1062
1063 return sprintf(buf, "%u\n", total);
1064 }
1065
1066 static ssize_t show_no_turbo(struct kobject *kobj,
1067 struct attribute *attr, char *buf)
1068 {
1069 ssize_t ret;
1070
1071 mutex_lock(&intel_pstate_driver_lock);
1072
1073 if (!intel_pstate_driver) {
1074 mutex_unlock(&intel_pstate_driver_lock);
1075 return -EAGAIN;
1076 }
1077
1078 update_turbo_state();
1079 if (global.turbo_disabled)
1080 ret = sprintf(buf, "%u\n", global.turbo_disabled);
1081 else
1082 ret = sprintf(buf, "%u\n", global.no_turbo);
1083
1084 mutex_unlock(&intel_pstate_driver_lock);
1085
1086 return ret;
1087 }
1088
1089 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
1090 const char *buf, size_t count)
1091 {
1092 unsigned int input;
1093 int ret;
1094
1095 ret = sscanf(buf, "%u", &input);
1096 if (ret != 1)
1097 return -EINVAL;
1098
1099 mutex_lock(&intel_pstate_driver_lock);
1100
1101 if (!intel_pstate_driver) {
1102 mutex_unlock(&intel_pstate_driver_lock);
1103 return -EAGAIN;
1104 }
1105
1106 mutex_lock(&intel_pstate_limits_lock);
1107
1108 update_turbo_state();
1109 if (global.turbo_disabled) {
1110 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1111 mutex_unlock(&intel_pstate_limits_lock);
1112 mutex_unlock(&intel_pstate_driver_lock);
1113 return -EPERM;
1114 }
1115
1116 global.no_turbo = clamp_t(int, input, 0, 1);
1117
1118 if (global.no_turbo) {
1119 struct cpudata *cpu = all_cpu_data[0];
1120 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1121
1122 /* Squash the global minimum into the permitted range. */
1123 if (global.min_perf_pct > pct)
1124 global.min_perf_pct = pct;
1125 }
1126
1127 mutex_unlock(&intel_pstate_limits_lock);
1128
1129 intel_pstate_update_policies();
1130
1131 mutex_unlock(&intel_pstate_driver_lock);
1132
1133 return count;
1134 }
1135
1136 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
1137 const char *buf, size_t count)
1138 {
1139 unsigned int input;
1140 int ret;
1141
1142 ret = sscanf(buf, "%u", &input);
1143 if (ret != 1)
1144 return -EINVAL;
1145
1146 mutex_lock(&intel_pstate_driver_lock);
1147
1148 if (!intel_pstate_driver) {
1149 mutex_unlock(&intel_pstate_driver_lock);
1150 return -EAGAIN;
1151 }
1152
1153 mutex_lock(&intel_pstate_limits_lock);
1154
1155 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1156
1157 mutex_unlock(&intel_pstate_limits_lock);
1158
1159 intel_pstate_update_policies();
1160
1161 mutex_unlock(&intel_pstate_driver_lock);
1162
1163 return count;
1164 }
1165
1166 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
1167 const char *buf, size_t count)
1168 {
1169 unsigned int input;
1170 int ret;
1171
1172 ret = sscanf(buf, "%u", &input);
1173 if (ret != 1)
1174 return -EINVAL;
1175
1176 mutex_lock(&intel_pstate_driver_lock);
1177
1178 if (!intel_pstate_driver) {
1179 mutex_unlock(&intel_pstate_driver_lock);
1180 return -EAGAIN;
1181 }
1182
1183 mutex_lock(&intel_pstate_limits_lock);
1184
1185 global.min_perf_pct = clamp_t(int, input,
1186 min_perf_pct_min(), global.max_perf_pct);
1187
1188 mutex_unlock(&intel_pstate_limits_lock);
1189
1190 intel_pstate_update_policies();
1191
1192 mutex_unlock(&intel_pstate_driver_lock);
1193
1194 return count;
1195 }
1196
1197 show_one(max_perf_pct, max_perf_pct);
1198 show_one(min_perf_pct, min_perf_pct);
1199
1200 define_one_global_rw(status);
1201 define_one_global_rw(no_turbo);
1202 define_one_global_rw(max_perf_pct);
1203 define_one_global_rw(min_perf_pct);
1204 define_one_global_ro(turbo_pct);
1205 define_one_global_ro(num_pstates);
1206
1207 static struct attribute *intel_pstate_attributes[] = {
1208 &status.attr,
1209 &no_turbo.attr,
1210 &turbo_pct.attr,
1211 &num_pstates.attr,
1212 NULL
1213 };
1214
1215 static struct attribute_group intel_pstate_attr_group = {
1216 .attrs = intel_pstate_attributes,
1217 };
1218
1219 static void __init intel_pstate_sysfs_expose_params(void)
1220 {
1221 struct kobject *intel_pstate_kobject;
1222 int rc;
1223
1224 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1225 &cpu_subsys.dev_root->kobj);
1226 if (WARN_ON(!intel_pstate_kobject))
1227 return;
1228
1229 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1230 if (WARN_ON(rc))
1231 return;
1232
1233 /*
1234 * If per cpu limits are enforced there are no global limits, so
1235 * return without creating max/min_perf_pct attributes
1236 */
1237 if (per_cpu_limits)
1238 return;
1239
1240 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1241 WARN_ON(rc);
1242
1243 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1244 WARN_ON(rc);
1245
1246 }
1247 /************************** sysfs end ************************/
1248
1249 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1250 {
1251 /* First disable HWP notification interrupt as we don't process them */
1252 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1253 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1254
1255 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1256 cpudata->epp_policy = 0;
1257 if (cpudata->epp_default == -EINVAL)
1258 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1259 }
1260
1261 #define MSR_IA32_POWER_CTL_BIT_EE 19
1262
1263 /* Disable energy efficiency optimization */
1264 static void intel_pstate_disable_ee(int cpu)
1265 {
1266 u64 power_ctl;
1267 int ret;
1268
1269 ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1270 if (ret)
1271 return;
1272
1273 if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1274 pr_info("Disabling energy efficiency optimization\n");
1275 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1276 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1277 }
1278 }
1279
1280 static int atom_get_min_pstate(void)
1281 {
1282 u64 value;
1283
1284 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1285 return (value >> 8) & 0x7F;
1286 }
1287
1288 static int atom_get_max_pstate(void)
1289 {
1290 u64 value;
1291
1292 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1293 return (value >> 16) & 0x7F;
1294 }
1295
1296 static int atom_get_turbo_pstate(void)
1297 {
1298 u64 value;
1299
1300 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1301 return value & 0x7F;
1302 }
1303
1304 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1305 {
1306 u64 val;
1307 int32_t vid_fp;
1308 u32 vid;
1309
1310 val = (u64)pstate << 8;
1311 if (global.no_turbo && !global.turbo_disabled)
1312 val |= (u64)1 << 32;
1313
1314 vid_fp = cpudata->vid.min + mul_fp(
1315 int_tofp(pstate - cpudata->pstate.min_pstate),
1316 cpudata->vid.ratio);
1317
1318 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1319 vid = ceiling_fp(vid_fp);
1320
1321 if (pstate > cpudata->pstate.max_pstate)
1322 vid = cpudata->vid.turbo;
1323
1324 return val | vid;
1325 }
1326
1327 static int silvermont_get_scaling(void)
1328 {
1329 u64 value;
1330 int i;
1331 /* Defined in Table 35-6 from SDM (Sept 2015) */
1332 static int silvermont_freq_table[] = {
1333 83300, 100000, 133300, 116700, 80000};
1334
1335 rdmsrl(MSR_FSB_FREQ, value);
1336 i = value & 0x7;
1337 WARN_ON(i > 4);
1338
1339 return silvermont_freq_table[i];
1340 }
1341
1342 static int airmont_get_scaling(void)
1343 {
1344 u64 value;
1345 int i;
1346 /* Defined in Table 35-10 from SDM (Sept 2015) */
1347 static int airmont_freq_table[] = {
1348 83300, 100000, 133300, 116700, 80000,
1349 93300, 90000, 88900, 87500};
1350
1351 rdmsrl(MSR_FSB_FREQ, value);
1352 i = value & 0xF;
1353 WARN_ON(i > 8);
1354
1355 return airmont_freq_table[i];
1356 }
1357
1358 static void atom_get_vid(struct cpudata *cpudata)
1359 {
1360 u64 value;
1361
1362 rdmsrl(MSR_ATOM_CORE_VIDS, value);
1363 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1364 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1365 cpudata->vid.ratio = div_fp(
1366 cpudata->vid.max - cpudata->vid.min,
1367 int_tofp(cpudata->pstate.max_pstate -
1368 cpudata->pstate.min_pstate));
1369
1370 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1371 cpudata->vid.turbo = value & 0x7f;
1372 }
1373
1374 static int core_get_min_pstate(void)
1375 {
1376 u64 value;
1377
1378 rdmsrl(MSR_PLATFORM_INFO, value);
1379 return (value >> 40) & 0xFF;
1380 }
1381
1382 static int core_get_max_pstate_physical(void)
1383 {
1384 u64 value;
1385
1386 rdmsrl(MSR_PLATFORM_INFO, value);
1387 return (value >> 8) & 0xFF;
1388 }
1389
1390 static int core_get_tdp_ratio(u64 plat_info)
1391 {
1392 /* Check how many TDP levels present */
1393 if (plat_info & 0x600000000) {
1394 u64 tdp_ctrl;
1395 u64 tdp_ratio;
1396 int tdp_msr;
1397 int err;
1398
1399 /* Get the TDP level (0, 1, 2) to get ratios */
1400 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1401 if (err)
1402 return err;
1403
1404 /* TDP MSR are continuous starting at 0x648 */
1405 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1406 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1407 if (err)
1408 return err;
1409
1410 /* For level 1 and 2, bits[23:16] contain the ratio */
1411 if (tdp_ctrl & 0x03)
1412 tdp_ratio >>= 16;
1413
1414 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1415 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1416
1417 return (int)tdp_ratio;
1418 }
1419
1420 return -ENXIO;
1421 }
1422
1423 static int core_get_max_pstate(void)
1424 {
1425 u64 tar;
1426 u64 plat_info;
1427 int max_pstate;
1428 int tdp_ratio;
1429 int err;
1430
1431 rdmsrl(MSR_PLATFORM_INFO, plat_info);
1432 max_pstate = (plat_info >> 8) & 0xFF;
1433
1434 tdp_ratio = core_get_tdp_ratio(plat_info);
1435 if (tdp_ratio <= 0)
1436 return max_pstate;
1437
1438 if (hwp_active) {
1439 /* Turbo activation ratio is not used on HWP platforms */
1440 return tdp_ratio;
1441 }
1442
1443 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1444 if (!err) {
1445 int tar_levels;
1446
1447 /* Do some sanity checking for safety */
1448 tar_levels = tar & 0xff;
1449 if (tdp_ratio - 1 == tar_levels) {
1450 max_pstate = tar_levels;
1451 pr_debug("max_pstate=TAC %x\n", max_pstate);
1452 }
1453 }
1454
1455 return max_pstate;
1456 }
1457
1458 static int core_get_turbo_pstate(void)
1459 {
1460 u64 value;
1461 int nont, ret;
1462
1463 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1464 nont = core_get_max_pstate();
1465 ret = (value) & 255;
1466 if (ret <= nont)
1467 ret = nont;
1468 return ret;
1469 }
1470
1471 static inline int core_get_scaling(void)
1472 {
1473 return 100000;
1474 }
1475
1476 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1477 {
1478 u64 val;
1479
1480 val = (u64)pstate << 8;
1481 if (global.no_turbo && !global.turbo_disabled)
1482 val |= (u64)1 << 32;
1483
1484 return val;
1485 }
1486
1487 static int knl_get_turbo_pstate(void)
1488 {
1489 u64 value;
1490 int nont, ret;
1491
1492 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1493 nont = core_get_max_pstate();
1494 ret = (((value) >> 8) & 0xFF);
1495 if (ret <= nont)
1496 ret = nont;
1497 return ret;
1498 }
1499
1500 static int intel_pstate_get_base_pstate(struct cpudata *cpu)
1501 {
1502 return global.no_turbo || global.turbo_disabled ?
1503 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1504 }
1505
1506 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1507 {
1508 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1509 cpu->pstate.current_pstate = pstate;
1510 /*
1511 * Generally, there is no guarantee that this code will always run on
1512 * the CPU being updated, so force the register update to run on the
1513 * right CPU.
1514 */
1515 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1516 pstate_funcs.get_val(cpu, pstate));
1517 }
1518
1519 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1520 {
1521 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1522 }
1523
1524 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1525 {
1526 int pstate;
1527
1528 update_turbo_state();
1529 pstate = intel_pstate_get_base_pstate(cpu);
1530 pstate = max(cpu->pstate.min_pstate,
1531 fp_ext_toint(pstate * cpu->max_perf));
1532 intel_pstate_set_pstate(cpu, pstate);
1533 }
1534
1535 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1536 {
1537 cpu->pstate.min_pstate = pstate_funcs.get_min();
1538 cpu->pstate.max_pstate = pstate_funcs.get_max();
1539 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1540 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1541 cpu->pstate.scaling = pstate_funcs.get_scaling();
1542 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1543 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1544
1545 if (pstate_funcs.get_vid)
1546 pstate_funcs.get_vid(cpu);
1547
1548 intel_pstate_set_min_pstate(cpu);
1549 }
1550
1551 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1552 {
1553 struct sample *sample = &cpu->sample;
1554
1555 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1556 }
1557
1558 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1559 {
1560 u64 aperf, mperf;
1561 unsigned long flags;
1562 u64 tsc;
1563
1564 local_irq_save(flags);
1565 rdmsrl(MSR_IA32_APERF, aperf);
1566 rdmsrl(MSR_IA32_MPERF, mperf);
1567 tsc = rdtsc();
1568 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1569 local_irq_restore(flags);
1570 return false;
1571 }
1572 local_irq_restore(flags);
1573
1574 cpu->last_sample_time = cpu->sample.time;
1575 cpu->sample.time = time;
1576 cpu->sample.aperf = aperf;
1577 cpu->sample.mperf = mperf;
1578 cpu->sample.tsc = tsc;
1579 cpu->sample.aperf -= cpu->prev_aperf;
1580 cpu->sample.mperf -= cpu->prev_mperf;
1581 cpu->sample.tsc -= cpu->prev_tsc;
1582
1583 cpu->prev_aperf = aperf;
1584 cpu->prev_mperf = mperf;
1585 cpu->prev_tsc = tsc;
1586 /*
1587 * First time this function is invoked in a given cycle, all of the
1588 * previous sample data fields are equal to zero or stale and they must
1589 * be populated with meaningful numbers for things to work, so assume
1590 * that sample.time will always be reset before setting the utilization
1591 * update hook and make the caller skip the sample then.
1592 */
1593 if (cpu->last_sample_time) {
1594 intel_pstate_calc_avg_perf(cpu);
1595 return true;
1596 }
1597 return false;
1598 }
1599
1600 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1601 {
1602 return mul_ext_fp(cpu->sample.core_avg_perf,
1603 cpu->pstate.max_pstate_physical * cpu->pstate.scaling);
1604 }
1605
1606 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1607 {
1608 return mul_ext_fp(cpu->pstate.max_pstate_physical,
1609 cpu->sample.core_avg_perf);
1610 }
1611
1612 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu)
1613 {
1614 struct sample *sample = &cpu->sample;
1615 int32_t busy_frac, boost;
1616 int target, avg_pstate;
1617
1618 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE)
1619 return cpu->pstate.turbo_pstate;
1620
1621 busy_frac = div_fp(sample->mperf, sample->tsc);
1622
1623 boost = cpu->iowait_boost;
1624 cpu->iowait_boost >>= 1;
1625
1626 if (busy_frac < boost)
1627 busy_frac = boost;
1628
1629 sample->busy_scaled = busy_frac * 100;
1630
1631 target = global.no_turbo || global.turbo_disabled ?
1632 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1633 target += target >> 2;
1634 target = mul_fp(target, busy_frac);
1635 if (target < cpu->pstate.min_pstate)
1636 target = cpu->pstate.min_pstate;
1637
1638 /*
1639 * If the average P-state during the previous cycle was higher than the
1640 * current target, add 50% of the difference to the target to reduce
1641 * possible performance oscillations and offset possible performance
1642 * loss related to moving the workload from one CPU to another within
1643 * a package/module.
1644 */
1645 avg_pstate = get_avg_pstate(cpu);
1646 if (avg_pstate > target)
1647 target += (avg_pstate - target) >> 1;
1648
1649 return target;
1650 }
1651
1652 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
1653 {
1654 int32_t perf_scaled, max_pstate, current_pstate, sample_ratio;
1655 u64 duration_ns;
1656
1657 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE)
1658 return cpu->pstate.turbo_pstate;
1659
1660 /*
1661 * perf_scaled is the ratio of the average P-state during the last
1662 * sampling period to the P-state requested last time (in percent).
1663 *
1664 * That measures the system's response to the previous P-state
1665 * selection.
1666 */
1667 max_pstate = cpu->pstate.max_pstate_physical;
1668 current_pstate = cpu->pstate.current_pstate;
1669 perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf,
1670 div_fp(100 * max_pstate, current_pstate));
1671
1672 /*
1673 * Since our utilization update callback will not run unless we are
1674 * in C0, check if the actual elapsed time is significantly greater (3x)
1675 * than our sample interval. If it is, then we were idle for a long
1676 * enough period of time to adjust our performance metric.
1677 */
1678 duration_ns = cpu->sample.time - cpu->last_sample_time;
1679 if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
1680 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns);
1681 perf_scaled = mul_fp(perf_scaled, sample_ratio);
1682 } else {
1683 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc);
1684 if (sample_ratio < int_tofp(1))
1685 perf_scaled = 0;
1686 }
1687
1688 cpu->sample.busy_scaled = perf_scaled;
1689 return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled);
1690 }
1691
1692 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1693 {
1694 int max_pstate = intel_pstate_get_base_pstate(cpu);
1695 int min_pstate;
1696
1697 min_pstate = max(cpu->pstate.min_pstate,
1698 fp_ext_toint(max_pstate * cpu->min_perf));
1699 max_pstate = max(min_pstate, fp_ext_toint(max_pstate * cpu->max_perf));
1700 return clamp_t(int, pstate, min_pstate, max_pstate);
1701 }
1702
1703 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1704 {
1705 if (pstate == cpu->pstate.current_pstate)
1706 return;
1707
1708 cpu->pstate.current_pstate = pstate;
1709 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1710 }
1711
1712 static void intel_pstate_adjust_pstate(struct cpudata *cpu, int target_pstate)
1713 {
1714 int from = cpu->pstate.current_pstate;
1715 struct sample *sample;
1716
1717 update_turbo_state();
1718
1719 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1720 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1721 intel_pstate_update_pstate(cpu, target_pstate);
1722
1723 sample = &cpu->sample;
1724 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1725 fp_toint(sample->busy_scaled),
1726 from,
1727 cpu->pstate.current_pstate,
1728 sample->mperf,
1729 sample->aperf,
1730 sample->tsc,
1731 get_avg_frequency(cpu),
1732 fp_toint(cpu->iowait_boost * 100));
1733 }
1734
1735 static void intel_pstate_update_util_hwp(struct update_util_data *data,
1736 u64 time, unsigned int flags)
1737 {
1738 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1739 u64 delta_ns = time - cpu->sample.time;
1740
1741 if ((s64)delta_ns >= INTEL_PSTATE_HWP_SAMPLING_INTERVAL)
1742 intel_pstate_sample(cpu, time);
1743 }
1744
1745 static void intel_pstate_update_util_pid(struct update_util_data *data,
1746 u64 time, unsigned int flags)
1747 {
1748 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1749 u64 delta_ns = time - cpu->sample.time;
1750
1751 if ((s64)delta_ns < pid_params.sample_rate_ns)
1752 return;
1753
1754 if (intel_pstate_sample(cpu, time)) {
1755 int target_pstate;
1756
1757 target_pstate = get_target_pstate_use_performance(cpu);
1758 intel_pstate_adjust_pstate(cpu, target_pstate);
1759 }
1760 }
1761
1762 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1763 unsigned int flags)
1764 {
1765 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1766 u64 delta_ns;
1767
1768 if (flags & SCHED_CPUFREQ_IOWAIT) {
1769 cpu->iowait_boost = int_tofp(1);
1770 } else if (cpu->iowait_boost) {
1771 /* Clear iowait_boost if the CPU may have been idle. */
1772 delta_ns = time - cpu->last_update;
1773 if (delta_ns > TICK_NSEC)
1774 cpu->iowait_boost = 0;
1775 }
1776 cpu->last_update = time;
1777 delta_ns = time - cpu->sample.time;
1778 if ((s64)delta_ns < INTEL_PSTATE_DEFAULT_SAMPLING_INTERVAL)
1779 return;
1780
1781 if (intel_pstate_sample(cpu, time)) {
1782 int target_pstate;
1783
1784 target_pstate = get_target_pstate_use_cpu_load(cpu);
1785 intel_pstate_adjust_pstate(cpu, target_pstate);
1786 }
1787 }
1788
1789 static struct pstate_funcs core_funcs = {
1790 .get_max = core_get_max_pstate,
1791 .get_max_physical = core_get_max_pstate_physical,
1792 .get_min = core_get_min_pstate,
1793 .get_turbo = core_get_turbo_pstate,
1794 .get_scaling = core_get_scaling,
1795 .get_val = core_get_val,
1796 .update_util = intel_pstate_update_util_pid,
1797 };
1798
1799 static const struct pstate_funcs silvermont_funcs = {
1800 .get_max = atom_get_max_pstate,
1801 .get_max_physical = atom_get_max_pstate,
1802 .get_min = atom_get_min_pstate,
1803 .get_turbo = atom_get_turbo_pstate,
1804 .get_val = atom_get_val,
1805 .get_scaling = silvermont_get_scaling,
1806 .get_vid = atom_get_vid,
1807 .update_util = intel_pstate_update_util,
1808 };
1809
1810 static const struct pstate_funcs airmont_funcs = {
1811 .get_max = atom_get_max_pstate,
1812 .get_max_physical = atom_get_max_pstate,
1813 .get_min = atom_get_min_pstate,
1814 .get_turbo = atom_get_turbo_pstate,
1815 .get_val = atom_get_val,
1816 .get_scaling = airmont_get_scaling,
1817 .get_vid = atom_get_vid,
1818 .update_util = intel_pstate_update_util,
1819 };
1820
1821 static const struct pstate_funcs knl_funcs = {
1822 .get_max = core_get_max_pstate,
1823 .get_max_physical = core_get_max_pstate_physical,
1824 .get_min = core_get_min_pstate,
1825 .get_turbo = knl_get_turbo_pstate,
1826 .get_scaling = core_get_scaling,
1827 .get_val = core_get_val,
1828 .update_util = intel_pstate_update_util_pid,
1829 };
1830
1831 static const struct pstate_funcs bxt_funcs = {
1832 .get_max = core_get_max_pstate,
1833 .get_max_physical = core_get_max_pstate_physical,
1834 .get_min = core_get_min_pstate,
1835 .get_turbo = core_get_turbo_pstate,
1836 .get_scaling = core_get_scaling,
1837 .get_val = core_get_val,
1838 .update_util = intel_pstate_update_util,
1839 };
1840
1841 #define ICPU(model, policy) \
1842 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1843 (unsigned long)&policy }
1844
1845 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1846 ICPU(INTEL_FAM6_SANDYBRIDGE, core_funcs),
1847 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_funcs),
1848 ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_funcs),
1849 ICPU(INTEL_FAM6_IVYBRIDGE, core_funcs),
1850 ICPU(INTEL_FAM6_HASWELL_CORE, core_funcs),
1851 ICPU(INTEL_FAM6_BROADWELL_CORE, core_funcs),
1852 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_funcs),
1853 ICPU(INTEL_FAM6_HASWELL_X, core_funcs),
1854 ICPU(INTEL_FAM6_HASWELL_ULT, core_funcs),
1855 ICPU(INTEL_FAM6_HASWELL_GT3E, core_funcs),
1856 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_funcs),
1857 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_funcs),
1858 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_funcs),
1859 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1860 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
1861 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1862 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_funcs),
1863 ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_funcs),
1864 ICPU(INTEL_FAM6_ATOM_GOLDMONT, bxt_funcs),
1865 ICPU(INTEL_FAM6_ATOM_GEMINI_LAKE, bxt_funcs),
1866 {}
1867 };
1868 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1869
1870 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1871 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1872 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1873 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1874 {}
1875 };
1876
1877 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1878 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_funcs),
1879 {}
1880 };
1881
1882 static bool pid_in_use(void);
1883
1884 static int intel_pstate_init_cpu(unsigned int cpunum)
1885 {
1886 struct cpudata *cpu;
1887
1888 cpu = all_cpu_data[cpunum];
1889
1890 if (!cpu) {
1891 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
1892 if (!cpu)
1893 return -ENOMEM;
1894
1895 all_cpu_data[cpunum] = cpu;
1896
1897 cpu->epp_default = -EINVAL;
1898 cpu->epp_powersave = -EINVAL;
1899 cpu->epp_saved = -EINVAL;
1900 }
1901
1902 cpu = all_cpu_data[cpunum];
1903
1904 cpu->cpu = cpunum;
1905
1906 if (hwp_active) {
1907 const struct x86_cpu_id *id;
1908
1909 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
1910 if (id)
1911 intel_pstate_disable_ee(cpunum);
1912
1913 intel_pstate_hwp_enable(cpu);
1914 } else if (pid_in_use()) {
1915 intel_pstate_pid_reset(cpu);
1916 }
1917
1918 intel_pstate_get_cpu_pstates(cpu);
1919
1920 pr_debug("controlling: cpu %d\n", cpunum);
1921
1922 return 0;
1923 }
1924
1925 static unsigned int intel_pstate_get(unsigned int cpu_num)
1926 {
1927 struct cpudata *cpu = all_cpu_data[cpu_num];
1928
1929 return cpu ? get_avg_frequency(cpu) : 0;
1930 }
1931
1932 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
1933 {
1934 struct cpudata *cpu = all_cpu_data[cpu_num];
1935
1936 if (cpu->update_util_set)
1937 return;
1938
1939 /* Prevent intel_pstate_update_util() from using stale data. */
1940 cpu->sample.time = 0;
1941 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1942 pstate_funcs.update_util);
1943 cpu->update_util_set = true;
1944 }
1945
1946 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1947 {
1948 struct cpudata *cpu_data = all_cpu_data[cpu];
1949
1950 if (!cpu_data->update_util_set)
1951 return;
1952
1953 cpufreq_remove_update_util_hook(cpu);
1954 cpu_data->update_util_set = false;
1955 synchronize_sched();
1956 }
1957
1958 static int intel_pstate_get_max_freq(struct cpudata *cpu)
1959 {
1960 return global.turbo_disabled || global.no_turbo ?
1961 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
1962 }
1963
1964 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
1965 struct cpudata *cpu)
1966 {
1967 int max_freq = intel_pstate_get_max_freq(cpu);
1968 int32_t max_policy_perf, min_policy_perf;
1969
1970 max_policy_perf = div_ext_fp(policy->max, max_freq);
1971 max_policy_perf = clamp_t(int32_t, max_policy_perf, 0, int_ext_tofp(1));
1972 if (policy->max == policy->min) {
1973 min_policy_perf = max_policy_perf;
1974 } else {
1975 min_policy_perf = div_ext_fp(policy->min, max_freq);
1976 min_policy_perf = clamp_t(int32_t, min_policy_perf,
1977 0, max_policy_perf);
1978 }
1979
1980 /* Normalize user input to [min_perf, max_perf] */
1981 if (per_cpu_limits) {
1982 cpu->min_perf = min_policy_perf;
1983 cpu->max_perf = max_policy_perf;
1984 } else {
1985 int32_t global_min, global_max;
1986
1987 /* Global limits are in percent of the maximum turbo P-state. */
1988 global_max = percent_ext_fp(global.max_perf_pct);
1989 global_min = percent_ext_fp(global.min_perf_pct);
1990 if (max_freq != cpu->pstate.turbo_freq) {
1991 int32_t turbo_factor;
1992
1993 turbo_factor = div_ext_fp(cpu->pstate.turbo_pstate,
1994 cpu->pstate.max_pstate);
1995 global_min = mul_ext_fp(global_min, turbo_factor);
1996 global_max = mul_ext_fp(global_max, turbo_factor);
1997 }
1998 global_min = clamp_t(int32_t, global_min, 0, global_max);
1999
2000 cpu->min_perf = max(min_policy_perf, global_min);
2001 cpu->min_perf = min(cpu->min_perf, max_policy_perf);
2002 cpu->max_perf = min(max_policy_perf, global_max);
2003 cpu->max_perf = max(min_policy_perf, cpu->max_perf);
2004
2005 /* Make sure min_perf <= max_perf */
2006 cpu->min_perf = min(cpu->min_perf, cpu->max_perf);
2007 }
2008
2009 cpu->max_perf = round_up(cpu->max_perf, EXT_FRAC_BITS);
2010 cpu->min_perf = round_up(cpu->min_perf, EXT_FRAC_BITS);
2011
2012 pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu,
2013 fp_ext_toint(cpu->max_perf * 100),
2014 fp_ext_toint(cpu->min_perf * 100));
2015 }
2016
2017 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2018 {
2019 struct cpudata *cpu;
2020
2021 if (!policy->cpuinfo.max_freq)
2022 return -ENODEV;
2023
2024 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2025 policy->cpuinfo.max_freq, policy->max);
2026
2027 cpu = all_cpu_data[policy->cpu];
2028 cpu->policy = policy->policy;
2029
2030 mutex_lock(&intel_pstate_limits_lock);
2031
2032 intel_pstate_update_perf_limits(policy, cpu);
2033
2034 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2035 /*
2036 * NOHZ_FULL CPUs need this as the governor callback may not
2037 * be invoked on them.
2038 */
2039 intel_pstate_clear_update_util_hook(policy->cpu);
2040 intel_pstate_max_within_limits(cpu);
2041 }
2042
2043 intel_pstate_set_update_util_hook(policy->cpu);
2044
2045 if (hwp_active)
2046 intel_pstate_hwp_set(policy->cpu);
2047
2048 mutex_unlock(&intel_pstate_limits_lock);
2049
2050 return 0;
2051 }
2052
2053 static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy,
2054 struct cpudata *cpu)
2055 {
2056 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2057 policy->max < policy->cpuinfo.max_freq &&
2058 policy->max > cpu->pstate.max_freq) {
2059 pr_debug("policy->max > max non turbo frequency\n");
2060 policy->max = policy->cpuinfo.max_freq;
2061 }
2062 }
2063
2064 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
2065 {
2066 struct cpudata *cpu = all_cpu_data[policy->cpu];
2067
2068 update_turbo_state();
2069 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2070 intel_pstate_get_max_freq(cpu));
2071
2072 if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
2073 policy->policy != CPUFREQ_POLICY_PERFORMANCE)
2074 return -EINVAL;
2075
2076 intel_pstate_adjust_policy_max(policy, cpu);
2077
2078 return 0;
2079 }
2080
2081 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2082 {
2083 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2084 }
2085
2086 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2087 {
2088 pr_debug("CPU %d exiting\n", policy->cpu);
2089
2090 intel_pstate_clear_update_util_hook(policy->cpu);
2091 if (hwp_active)
2092 intel_pstate_hwp_save_state(policy);
2093 else
2094 intel_cpufreq_stop_cpu(policy);
2095 }
2096
2097 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2098 {
2099 intel_pstate_exit_perf_limits(policy);
2100
2101 policy->fast_switch_possible = false;
2102
2103 return 0;
2104 }
2105
2106 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2107 {
2108 struct cpudata *cpu;
2109 int rc;
2110
2111 rc = intel_pstate_init_cpu(policy->cpu);
2112 if (rc)
2113 return rc;
2114
2115 cpu = all_cpu_data[policy->cpu];
2116
2117 cpu->max_perf = int_ext_tofp(1);
2118 cpu->min_perf = 0;
2119
2120 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2121 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2122
2123 /* cpuinfo and default policy values */
2124 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2125 update_turbo_state();
2126 policy->cpuinfo.max_freq = global.turbo_disabled ?
2127 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2128 policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2129
2130 intel_pstate_init_acpi_perf_limits(policy);
2131 cpumask_set_cpu(policy->cpu, policy->cpus);
2132
2133 policy->fast_switch_possible = true;
2134
2135 return 0;
2136 }
2137
2138 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2139 {
2140 int ret = __intel_pstate_cpu_init(policy);
2141
2142 if (ret)
2143 return ret;
2144
2145 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
2146 if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
2147 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2148 else
2149 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2150
2151 return 0;
2152 }
2153
2154 static struct cpufreq_driver intel_pstate = {
2155 .flags = CPUFREQ_CONST_LOOPS,
2156 .verify = intel_pstate_verify_policy,
2157 .setpolicy = intel_pstate_set_policy,
2158 .suspend = intel_pstate_hwp_save_state,
2159 .resume = intel_pstate_resume,
2160 .get = intel_pstate_get,
2161 .init = intel_pstate_cpu_init,
2162 .exit = intel_pstate_cpu_exit,
2163 .stop_cpu = intel_pstate_stop_cpu,
2164 .name = "intel_pstate",
2165 };
2166
2167 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2168 {
2169 struct cpudata *cpu = all_cpu_data[policy->cpu];
2170
2171 update_turbo_state();
2172 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2173 intel_pstate_get_max_freq(cpu));
2174
2175 intel_pstate_adjust_policy_max(policy, cpu);
2176
2177 intel_pstate_update_perf_limits(policy, cpu);
2178
2179 return 0;
2180 }
2181
2182 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2183 unsigned int target_freq,
2184 unsigned int relation)
2185 {
2186 struct cpudata *cpu = all_cpu_data[policy->cpu];
2187 struct cpufreq_freqs freqs;
2188 int target_pstate;
2189
2190 update_turbo_state();
2191
2192 freqs.old = policy->cur;
2193 freqs.new = target_freq;
2194
2195 cpufreq_freq_transition_begin(policy, &freqs);
2196 switch (relation) {
2197 case CPUFREQ_RELATION_L:
2198 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2199 break;
2200 case CPUFREQ_RELATION_H:
2201 target_pstate = freqs.new / cpu->pstate.scaling;
2202 break;
2203 default:
2204 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2205 break;
2206 }
2207 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2208 if (target_pstate != cpu->pstate.current_pstate) {
2209 cpu->pstate.current_pstate = target_pstate;
2210 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2211 pstate_funcs.get_val(cpu, target_pstate));
2212 }
2213 freqs.new = target_pstate * cpu->pstate.scaling;
2214 cpufreq_freq_transition_end(policy, &freqs, false);
2215
2216 return 0;
2217 }
2218
2219 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2220 unsigned int target_freq)
2221 {
2222 struct cpudata *cpu = all_cpu_data[policy->cpu];
2223 int target_pstate;
2224
2225 update_turbo_state();
2226
2227 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2228 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2229 intel_pstate_update_pstate(cpu, target_pstate);
2230 return target_pstate * cpu->pstate.scaling;
2231 }
2232
2233 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2234 {
2235 int ret = __intel_pstate_cpu_init(policy);
2236
2237 if (ret)
2238 return ret;
2239
2240 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2241 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
2242 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2243 policy->cur = policy->cpuinfo.min_freq;
2244
2245 return 0;
2246 }
2247
2248 static struct cpufreq_driver intel_cpufreq = {
2249 .flags = CPUFREQ_CONST_LOOPS,
2250 .verify = intel_cpufreq_verify_policy,
2251 .target = intel_cpufreq_target,
2252 .fast_switch = intel_cpufreq_fast_switch,
2253 .init = intel_cpufreq_cpu_init,
2254 .exit = intel_pstate_cpu_exit,
2255 .stop_cpu = intel_cpufreq_stop_cpu,
2256 .name = "intel_cpufreq",
2257 };
2258
2259 static struct cpufreq_driver *default_driver = &intel_pstate;
2260
2261 static bool pid_in_use(void)
2262 {
2263 return intel_pstate_driver == &intel_pstate &&
2264 pstate_funcs.update_util == intel_pstate_update_util_pid;
2265 }
2266
2267 static void intel_pstate_driver_cleanup(void)
2268 {
2269 unsigned int cpu;
2270
2271 get_online_cpus();
2272 for_each_online_cpu(cpu) {
2273 if (all_cpu_data[cpu]) {
2274 if (intel_pstate_driver == &intel_pstate)
2275 intel_pstate_clear_update_util_hook(cpu);
2276
2277 kfree(all_cpu_data[cpu]);
2278 all_cpu_data[cpu] = NULL;
2279 }
2280 }
2281 put_online_cpus();
2282 intel_pstate_driver = NULL;
2283 }
2284
2285 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
2286 {
2287 int ret;
2288
2289 memset(&global, 0, sizeof(global));
2290 global.max_perf_pct = 100;
2291
2292 intel_pstate_driver = driver;
2293 ret = cpufreq_register_driver(intel_pstate_driver);
2294 if (ret) {
2295 intel_pstate_driver_cleanup();
2296 return ret;
2297 }
2298
2299 global.min_perf_pct = min_perf_pct_min();
2300
2301 if (pid_in_use())
2302 intel_pstate_debug_expose_params();
2303
2304 return 0;
2305 }
2306
2307 static int intel_pstate_unregister_driver(void)
2308 {
2309 if (hwp_active)
2310 return -EBUSY;
2311
2312 if (pid_in_use())
2313 intel_pstate_debug_hide_params();
2314
2315 cpufreq_unregister_driver(intel_pstate_driver);
2316 intel_pstate_driver_cleanup();
2317
2318 return 0;
2319 }
2320
2321 static ssize_t intel_pstate_show_status(char *buf)
2322 {
2323 if (!intel_pstate_driver)
2324 return sprintf(buf, "off\n");
2325
2326 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2327 "active" : "passive");
2328 }
2329
2330 static int intel_pstate_update_status(const char *buf, size_t size)
2331 {
2332 int ret;
2333
2334 if (size == 3 && !strncmp(buf, "off", size))
2335 return intel_pstate_driver ?
2336 intel_pstate_unregister_driver() : -EINVAL;
2337
2338 if (size == 6 && !strncmp(buf, "active", size)) {
2339 if (intel_pstate_driver) {
2340 if (intel_pstate_driver == &intel_pstate)
2341 return 0;
2342
2343 ret = intel_pstate_unregister_driver();
2344 if (ret)
2345 return ret;
2346 }
2347
2348 return intel_pstate_register_driver(&intel_pstate);
2349 }
2350
2351 if (size == 7 && !strncmp(buf, "passive", size)) {
2352 if (intel_pstate_driver) {
2353 if (intel_pstate_driver == &intel_cpufreq)
2354 return 0;
2355
2356 ret = intel_pstate_unregister_driver();
2357 if (ret)
2358 return ret;
2359 }
2360
2361 return intel_pstate_register_driver(&intel_cpufreq);
2362 }
2363
2364 return -EINVAL;
2365 }
2366
2367 static int no_load __initdata;
2368 static int no_hwp __initdata;
2369 static int hwp_only __initdata;
2370 static unsigned int force_load __initdata;
2371
2372 static int __init intel_pstate_msrs_not_valid(void)
2373 {
2374 if (!pstate_funcs.get_max() ||
2375 !pstate_funcs.get_min() ||
2376 !pstate_funcs.get_turbo())
2377 return -ENODEV;
2378
2379 return 0;
2380 }
2381
2382 #ifdef CONFIG_ACPI
2383 static void intel_pstate_use_acpi_profile(void)
2384 {
2385 switch (acpi_gbl_FADT.preferred_profile) {
2386 case PM_MOBILE:
2387 case PM_TABLET:
2388 case PM_APPLIANCE_PC:
2389 case PM_DESKTOP:
2390 case PM_WORKSTATION:
2391 pstate_funcs.update_util = intel_pstate_update_util;
2392 }
2393 }
2394 #else
2395 static void intel_pstate_use_acpi_profile(void)
2396 {
2397 }
2398 #endif
2399
2400 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2401 {
2402 pstate_funcs.get_max = funcs->get_max;
2403 pstate_funcs.get_max_physical = funcs->get_max_physical;
2404 pstate_funcs.get_min = funcs->get_min;
2405 pstate_funcs.get_turbo = funcs->get_turbo;
2406 pstate_funcs.get_scaling = funcs->get_scaling;
2407 pstate_funcs.get_val = funcs->get_val;
2408 pstate_funcs.get_vid = funcs->get_vid;
2409 pstate_funcs.update_util = funcs->update_util;
2410
2411 intel_pstate_use_acpi_profile();
2412 }
2413
2414 #ifdef CONFIG_ACPI
2415
2416 static bool __init intel_pstate_no_acpi_pss(void)
2417 {
2418 int i;
2419
2420 for_each_possible_cpu(i) {
2421 acpi_status status;
2422 union acpi_object *pss;
2423 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2424 struct acpi_processor *pr = per_cpu(processors, i);
2425
2426 if (!pr)
2427 continue;
2428
2429 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2430 if (ACPI_FAILURE(status))
2431 continue;
2432
2433 pss = buffer.pointer;
2434 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2435 kfree(pss);
2436 return false;
2437 }
2438
2439 kfree(pss);
2440 }
2441
2442 return true;
2443 }
2444
2445 static bool __init intel_pstate_has_acpi_ppc(void)
2446 {
2447 int i;
2448
2449 for_each_possible_cpu(i) {
2450 struct acpi_processor *pr = per_cpu(processors, i);
2451
2452 if (!pr)
2453 continue;
2454 if (acpi_has_method(pr->handle, "_PPC"))
2455 return true;
2456 }
2457 return false;
2458 }
2459
2460 enum {
2461 PSS,
2462 PPC,
2463 };
2464
2465 struct hw_vendor_info {
2466 u16 valid;
2467 char oem_id[ACPI_OEM_ID_SIZE];
2468 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
2469 int oem_pwr_table;
2470 };
2471
2472 /* Hardware vendor-specific info that has its own power management modes */
2473 static struct hw_vendor_info vendor_info[] __initdata = {
2474 {1, "HP ", "ProLiant", PSS},
2475 {1, "ORACLE", "X4-2 ", PPC},
2476 {1, "ORACLE", "X4-2L ", PPC},
2477 {1, "ORACLE", "X4-2B ", PPC},
2478 {1, "ORACLE", "X3-2 ", PPC},
2479 {1, "ORACLE", "X3-2L ", PPC},
2480 {1, "ORACLE", "X3-2B ", PPC},
2481 {1, "ORACLE", "X4470M2 ", PPC},
2482 {1, "ORACLE", "X4270M3 ", PPC},
2483 {1, "ORACLE", "X4270M2 ", PPC},
2484 {1, "ORACLE", "X4170M2 ", PPC},
2485 {1, "ORACLE", "X4170 M3", PPC},
2486 {1, "ORACLE", "X4275 M3", PPC},
2487 {1, "ORACLE", "X6-2 ", PPC},
2488 {1, "ORACLE", "Sudbury ", PPC},
2489 {0, "", ""},
2490 };
2491
2492 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2493 {
2494 struct acpi_table_header hdr;
2495 struct hw_vendor_info *v_info;
2496 const struct x86_cpu_id *id;
2497 u64 misc_pwr;
2498
2499 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2500 if (id) {
2501 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2502 if ( misc_pwr & (1 << 8))
2503 return true;
2504 }
2505
2506 if (acpi_disabled ||
2507 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
2508 return false;
2509
2510 for (v_info = vendor_info; v_info->valid; v_info++) {
2511 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
2512 !strncmp(hdr.oem_table_id, v_info->oem_table_id,
2513 ACPI_OEM_TABLE_ID_SIZE))
2514 switch (v_info->oem_pwr_table) {
2515 case PSS:
2516 return intel_pstate_no_acpi_pss();
2517 case PPC:
2518 return intel_pstate_has_acpi_ppc() &&
2519 (!force_load);
2520 }
2521 }
2522
2523 return false;
2524 }
2525
2526 static void intel_pstate_request_control_from_smm(void)
2527 {
2528 /*
2529 * It may be unsafe to request P-states control from SMM if _PPC support
2530 * has not been enabled.
2531 */
2532 if (acpi_ppc)
2533 acpi_processor_pstate_control();
2534 }
2535 #else /* CONFIG_ACPI not enabled */
2536 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2537 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2538 static inline void intel_pstate_request_control_from_smm(void) {}
2539 #endif /* CONFIG_ACPI */
2540
2541 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2542 { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
2543 {}
2544 };
2545
2546 static int __init intel_pstate_init(void)
2547 {
2548 int rc;
2549
2550 if (no_load)
2551 return -ENODEV;
2552
2553 if (x86_match_cpu(hwp_support_ids)) {
2554 copy_cpu_funcs(&core_funcs);
2555 if (no_hwp) {
2556 pstate_funcs.update_util = intel_pstate_update_util;
2557 } else {
2558 hwp_active++;
2559 intel_pstate.attr = hwp_cpufreq_attrs;
2560 pstate_funcs.update_util = intel_pstate_update_util_hwp;
2561 goto hwp_cpu_matched;
2562 }
2563 } else {
2564 const struct x86_cpu_id *id;
2565
2566 id = x86_match_cpu(intel_pstate_cpu_ids);
2567 if (!id)
2568 return -ENODEV;
2569
2570 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
2571 }
2572
2573 if (intel_pstate_msrs_not_valid())
2574 return -ENODEV;
2575
2576 hwp_cpu_matched:
2577 /*
2578 * The Intel pstate driver will be ignored if the platform
2579 * firmware has its own power management modes.
2580 */
2581 if (intel_pstate_platform_pwr_mgmt_exists())
2582 return -ENODEV;
2583
2584 if (!hwp_active && hwp_only)
2585 return -ENOTSUPP;
2586
2587 pr_info("Intel P-state driver initializing\n");
2588
2589 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
2590 if (!all_cpu_data)
2591 return -ENOMEM;
2592
2593 intel_pstate_request_control_from_smm();
2594
2595 intel_pstate_sysfs_expose_params();
2596
2597 mutex_lock(&intel_pstate_driver_lock);
2598 rc = intel_pstate_register_driver(default_driver);
2599 mutex_unlock(&intel_pstate_driver_lock);
2600 if (rc)
2601 return rc;
2602
2603 if (hwp_active)
2604 pr_info("HWP enabled\n");
2605
2606 return 0;
2607 }
2608 device_initcall(intel_pstate_init);
2609
2610 static int __init intel_pstate_setup(char *str)
2611 {
2612 if (!str)
2613 return -EINVAL;
2614
2615 if (!strcmp(str, "disable")) {
2616 no_load = 1;
2617 } else if (!strcmp(str, "passive")) {
2618 pr_info("Passive mode enabled\n");
2619 default_driver = &intel_cpufreq;
2620 no_hwp = 1;
2621 }
2622 if (!strcmp(str, "no_hwp")) {
2623 pr_info("HWP disabled\n");
2624 no_hwp = 1;
2625 }
2626 if (!strcmp(str, "force"))
2627 force_load = 1;
2628 if (!strcmp(str, "hwp_only"))
2629 hwp_only = 1;
2630 if (!strcmp(str, "per_cpu_perf_limits"))
2631 per_cpu_limits = true;
2632
2633 #ifdef CONFIG_ACPI
2634 if (!strcmp(str, "support_acpi_ppc"))
2635 acpi_ppc = true;
2636 #endif
2637
2638 return 0;
2639 }
2640 early_param("intel_pstate", intel_pstate_setup);
2641
2642 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2643 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2644 MODULE_LICENSE("GPL");
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