2 * intel_pstate.c: Native P state management for Intel processors
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/kernel.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/ktime.h>
19 #include <linux/hrtimer.h>
20 #include <linux/tick.h>
21 #include <linux/slab.h>
22 #include <linux/sched/cpufreq.h>
23 #include <linux/list.h>
24 #include <linux/cpu.h>
25 #include <linux/cpufreq.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
29 #include <linux/debugfs.h>
30 #include <linux/acpi.h>
31 #include <linux/vmalloc.h>
32 #include <trace/events/power.h>
34 #include <asm/div64.h>
36 #include <asm/cpu_device_id.h>
37 #include <asm/cpufeature.h>
38 #include <asm/intel-family.h>
40 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
43 #include <acpi/processor.h>
44 #include <acpi/cppc_acpi.h>
48 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
49 #define fp_toint(X) ((X) >> FRAC_BITS)
52 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
53 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
54 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
56 static inline int32_t mul_fp(int32_t x
, int32_t y
)
58 return ((int64_t)x
* (int64_t)y
) >> FRAC_BITS
;
61 static inline int32_t div_fp(s64 x
, s64 y
)
63 return div64_s64((int64_t)x
<< FRAC_BITS
, y
);
66 static inline int ceiling_fp(int32_t x
)
71 mask
= (1 << FRAC_BITS
) - 1;
77 static inline u64
mul_ext_fp(u64 x
, u64 y
)
79 return (x
* y
) >> EXT_FRAC_BITS
;
82 static inline u64
div_ext_fp(u64 x
, u64 y
)
84 return div64_u64(x
<< EXT_FRAC_BITS
, y
);
87 static inline int32_t percent_ext_fp(int percent
)
89 return div_ext_fp(percent
, 100);
93 * struct sample - Store performance sample
94 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
95 * performance during last sample period
96 * @busy_scaled: Scaled busy value which is used to calculate next
97 * P state. This can be different than core_avg_perf
98 * to account for cpu idle period
99 * @aperf: Difference of actual performance frequency clock count
100 * read from APERF MSR between last and current sample
101 * @mperf: Difference of maximum performance frequency clock count
102 * read from MPERF MSR between last and current sample
103 * @tsc: Difference of time stamp counter between last and
105 * @time: Current time from scheduler
107 * This structure is used in the cpudata structure to store performance sample
108 * data for choosing next P State.
111 int32_t core_avg_perf
;
120 * struct pstate_data - Store P state data
121 * @current_pstate: Current requested P state
122 * @min_pstate: Min P state possible for this platform
123 * @max_pstate: Max P state possible for this platform
124 * @max_pstate_physical:This is physical Max P state for a processor
125 * This can be higher than the max_pstate which can
126 * be limited by platform thermal design power limits
127 * @scaling: Scaling factor to convert frequency to cpufreq
129 * @turbo_pstate: Max Turbo P state possible for this platform
130 * @max_freq: @max_pstate frequency in cpufreq units
131 * @turbo_freq: @turbo_pstate frequency in cpufreq units
133 * Stores the per cpu model P state limits and current P state.
139 int max_pstate_physical
;
142 unsigned int max_freq
;
143 unsigned int turbo_freq
;
147 * struct vid_data - Stores voltage information data
148 * @min: VID data for this platform corresponding to
150 * @max: VID data corresponding to the highest P State.
151 * @turbo: VID data for turbo P state
152 * @ratio: Ratio of (vid max - vid min) /
153 * (max P state - Min P State)
155 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
156 * This data is used in Atom platforms, where in addition to target P state,
157 * the voltage data needs to be specified to select next P State.
167 * struct _pid - Stores PID data
168 * @setpoint: Target set point for busyness or performance
169 * @integral: Storage for accumulated error values
170 * @p_gain: PID proportional gain
171 * @i_gain: PID integral gain
172 * @d_gain: PID derivative gain
173 * @deadband: PID deadband
174 * @last_err: Last error storage for integral part of PID calculation
176 * Stores PID coefficients and last error for PID controller.
189 * struct perf_limits - Store user and policy limits
190 * @no_turbo: User requested turbo state from intel_pstate sysfs
191 * @turbo_disabled: Platform turbo status either from msr
192 * MSR_IA32_MISC_ENABLE or when maximum available pstate
193 * matches the maximum turbo pstate
194 * @max_perf_pct: Effective maximum performance limit in percentage, this
195 * is minimum of either limits enforced by cpufreq policy
196 * or limits from user set limits via intel_pstate sysfs
197 * @min_perf_pct: Effective minimum performance limit in percentage, this
198 * is maximum of either limits enforced by cpufreq policy
199 * or limits from user set limits via intel_pstate sysfs
200 * @max_perf: This is a scaled value between 0 to 255 for max_perf_pct
201 * This value is used to limit max pstate
202 * @min_perf: This is a scaled value between 0 to 255 for min_perf_pct
203 * This value is used to limit min pstate
204 * @max_policy_pct: The maximum performance in percentage enforced by
205 * cpufreq setpolicy interface
206 * @max_sysfs_pct: The maximum performance in percentage enforced by
207 * intel pstate sysfs interface, unused when per cpu
208 * controls are enforced
209 * @min_policy_pct: The minimum performance in percentage enforced by
210 * cpufreq setpolicy interface
211 * @min_sysfs_pct: The minimum performance in percentage enforced by
212 * intel pstate sysfs interface, unused when per cpu
213 * controls are enforced
215 * Storage for user and policy defined limits.
231 * struct cpudata - Per CPU instance data storage
232 * @cpu: CPU number for this instance data
233 * @policy: CPUFreq policy value
234 * @update_util: CPUFreq utility callback information
235 * @update_util_set: CPUFreq utility callback is set
236 * @iowait_boost: iowait-related boost fraction
237 * @last_update: Time of the last update.
238 * @pstate: Stores P state limits for this CPU
239 * @vid: Stores VID limits for this CPU
240 * @pid: Stores PID parameters for this CPU
241 * @last_sample_time: Last Sample time
242 * @prev_aperf: Last APERF value read from APERF MSR
243 * @prev_mperf: Last MPERF value read from MPERF MSR
244 * @prev_tsc: Last timestamp counter (TSC) value
245 * @prev_cummulative_iowait: IO Wait time difference from last and
247 * @sample: Storage for storing last Sample data
248 * @perf_limits: Pointer to perf_limit unique to this CPU
249 * Not all field in the structure are applicable
250 * when per cpu controls are enforced
251 * @acpi_perf_data: Stores ACPI perf information read from _PSS
252 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
253 * @epp_powersave: Last saved HWP energy performance preference
254 * (EPP) or energy performance bias (EPB),
255 * when policy switched to performance
256 * @epp_policy: Last saved policy used to set EPP/EPB
257 * @epp_default: Power on default HWP energy performance
259 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
262 * This structure stores per CPU instance data for all CPUs.
268 struct update_util_data update_util
;
269 bool update_util_set
;
271 struct pstate_data pstate
;
276 u64 last_sample_time
;
280 u64 prev_cummulative_iowait
;
281 struct sample sample
;
282 struct perf_limits
*perf_limits
;
284 struct acpi_processor_performance acpi_perf_data
;
285 bool valid_pss_table
;
287 unsigned int iowait_boost
;
294 static struct cpudata
**all_cpu_data
;
297 * struct pstate_adjust_policy - Stores static PID configuration data
298 * @sample_rate_ms: PID calculation sample rate in ms
299 * @sample_rate_ns: Sample rate calculation in ns
300 * @deadband: PID deadband
301 * @setpoint: PID Setpoint
302 * @p_gain_pct: PID proportional gain
303 * @i_gain_pct: PID integral gain
304 * @d_gain_pct: PID derivative gain
306 * Stores per CPU model static PID configuration data.
308 struct pstate_adjust_policy
{
319 * struct pstate_funcs - Per CPU model specific callbacks
320 * @get_max: Callback to get maximum non turbo effective P state
321 * @get_max_physical: Callback to get maximum non turbo physical P state
322 * @get_min: Callback to get minimum P state
323 * @get_turbo: Callback to get turbo P state
324 * @get_scaling: Callback to get frequency scaling factor
325 * @get_val: Callback to convert P state to actual MSR write value
326 * @get_vid: Callback to get VID data for Atom platforms
327 * @get_target_pstate: Callback to a function to calculate next P state to use
329 * Core and Atom CPU models have different way to get P State limits. This
330 * structure is used to store those callbacks.
332 struct pstate_funcs
{
333 int (*get_max
)(void);
334 int (*get_max_physical
)(void);
335 int (*get_min
)(void);
336 int (*get_turbo
)(void);
337 int (*get_scaling
)(void);
338 u64 (*get_val
)(struct cpudata
*, int pstate
);
339 void (*get_vid
)(struct cpudata
*);
340 int32_t (*get_target_pstate
)(struct cpudata
*);
344 * struct cpu_defaults- Per CPU model default config data
345 * @pid_policy: PID config data
346 * @funcs: Callback function data
348 struct cpu_defaults
{
349 struct pstate_adjust_policy pid_policy
;
350 struct pstate_funcs funcs
;
353 static inline int32_t get_target_pstate_use_performance(struct cpudata
*cpu
);
354 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata
*cpu
);
356 static struct pstate_adjust_policy pid_params __read_mostly
;
357 static struct pstate_funcs pstate_funcs __read_mostly
;
358 static int hwp_active __read_mostly
;
359 static bool per_cpu_limits __read_mostly
;
361 static bool driver_registered __read_mostly
;
364 static bool acpi_ppc
;
367 static struct perf_limits global
;
369 static void intel_pstate_init_limits(struct perf_limits
*limits
)
371 memset(limits
, 0, sizeof(*limits
));
372 limits
->max_perf_pct
= 100;
373 limits
->max_perf
= int_ext_tofp(1);
374 limits
->max_policy_pct
= 100;
375 limits
->max_sysfs_pct
= 100;
378 static DEFINE_MUTEX(intel_pstate_driver_lock
);
379 static DEFINE_MUTEX(intel_pstate_limits_lock
);
383 static bool intel_pstate_get_ppc_enable_status(void)
385 if (acpi_gbl_FADT
.preferred_profile
== PM_ENTERPRISE_SERVER
||
386 acpi_gbl_FADT
.preferred_profile
== PM_PERFORMANCE_SERVER
)
392 #ifdef CONFIG_ACPI_CPPC_LIB
394 /* The work item is needed to avoid CPU hotplug locking issues */
395 static void intel_pstste_sched_itmt_work_fn(struct work_struct
*work
)
397 sched_set_itmt_support();
400 static DECLARE_WORK(sched_itmt_work
, intel_pstste_sched_itmt_work_fn
);
402 static void intel_pstate_set_itmt_prio(int cpu
)
404 struct cppc_perf_caps cppc_perf
;
405 static u32 max_highest_perf
= 0, min_highest_perf
= U32_MAX
;
408 ret
= cppc_get_perf_caps(cpu
, &cppc_perf
);
413 * The priorities can be set regardless of whether or not
414 * sched_set_itmt_support(true) has been called and it is valid to
415 * update them at any time after it has been called.
417 sched_set_itmt_core_prio(cppc_perf
.highest_perf
, cpu
);
419 if (max_highest_perf
<= min_highest_perf
) {
420 if (cppc_perf
.highest_perf
> max_highest_perf
)
421 max_highest_perf
= cppc_perf
.highest_perf
;
423 if (cppc_perf
.highest_perf
< min_highest_perf
)
424 min_highest_perf
= cppc_perf
.highest_perf
;
426 if (max_highest_perf
> min_highest_perf
) {
428 * This code can be run during CPU online under the
429 * CPU hotplug locks, so sched_set_itmt_support()
430 * cannot be called from here. Queue up a work item
433 schedule_work(&sched_itmt_work
);
438 static void intel_pstate_set_itmt_prio(int cpu
)
443 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy
*policy
)
450 intel_pstate_set_itmt_prio(policy
->cpu
);
454 if (!intel_pstate_get_ppc_enable_status())
457 cpu
= all_cpu_data
[policy
->cpu
];
459 ret
= acpi_processor_register_performance(&cpu
->acpi_perf_data
,
465 * Check if the control value in _PSS is for PERF_CTL MSR, which should
466 * guarantee that the states returned by it map to the states in our
469 if (cpu
->acpi_perf_data
.control_register
.space_id
!=
470 ACPI_ADR_SPACE_FIXED_HARDWARE
)
474 * If there is only one entry _PSS, simply ignore _PSS and continue as
475 * usual without taking _PSS into account
477 if (cpu
->acpi_perf_data
.state_count
< 2)
480 pr_debug("CPU%u - ACPI _PSS perf data\n", policy
->cpu
);
481 for (i
= 0; i
< cpu
->acpi_perf_data
.state_count
; i
++) {
482 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
483 (i
== cpu
->acpi_perf_data
.state
? '*' : ' '), i
,
484 (u32
) cpu
->acpi_perf_data
.states
[i
].core_frequency
,
485 (u32
) cpu
->acpi_perf_data
.states
[i
].power
,
486 (u32
) cpu
->acpi_perf_data
.states
[i
].control
);
490 * The _PSS table doesn't contain whole turbo frequency range.
491 * This just contains +1 MHZ above the max non turbo frequency,
492 * with control value corresponding to max turbo ratio. But
493 * when cpufreq set policy is called, it will call with this
494 * max frequency, which will cause a reduced performance as
495 * this driver uses real max turbo frequency as the max
496 * frequency. So correct this frequency in _PSS table to
497 * correct max turbo frequency based on the turbo state.
498 * Also need to convert to MHz as _PSS freq is in MHz.
500 if (!global
.turbo_disabled
)
501 cpu
->acpi_perf_data
.states
[0].core_frequency
=
502 policy
->cpuinfo
.max_freq
/ 1000;
503 cpu
->valid_pss_table
= true;
504 pr_debug("_PPC limits will be enforced\n");
509 cpu
->valid_pss_table
= false;
510 acpi_processor_unregister_performance(policy
->cpu
);
513 static void intel_pstate_exit_perf_limits(struct cpufreq_policy
*policy
)
517 cpu
= all_cpu_data
[policy
->cpu
];
518 if (!cpu
->valid_pss_table
)
521 acpi_processor_unregister_performance(policy
->cpu
);
524 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy
*policy
)
528 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy
*policy
)
533 static inline void pid_reset(struct _pid
*pid
, int setpoint
, int busy
,
534 int deadband
, int integral
) {
535 pid
->setpoint
= int_tofp(setpoint
);
536 pid
->deadband
= int_tofp(deadband
);
537 pid
->integral
= int_tofp(integral
);
538 pid
->last_err
= int_tofp(setpoint
) - int_tofp(busy
);
541 static inline void pid_p_gain_set(struct _pid
*pid
, int percent
)
543 pid
->p_gain
= div_fp(percent
, 100);
546 static inline void pid_i_gain_set(struct _pid
*pid
, int percent
)
548 pid
->i_gain
= div_fp(percent
, 100);
551 static inline void pid_d_gain_set(struct _pid
*pid
, int percent
)
553 pid
->d_gain
= div_fp(percent
, 100);
556 static signed int pid_calc(struct _pid
*pid
, int32_t busy
)
559 int32_t pterm
, dterm
, fp_error
;
560 int32_t integral_limit
;
562 fp_error
= pid
->setpoint
- busy
;
564 if (abs(fp_error
) <= pid
->deadband
)
567 pterm
= mul_fp(pid
->p_gain
, fp_error
);
569 pid
->integral
+= fp_error
;
572 * We limit the integral here so that it will never
573 * get higher than 30. This prevents it from becoming
574 * too large an input over long periods of time and allows
575 * it to get factored out sooner.
577 * The value of 30 was chosen through experimentation.
579 integral_limit
= int_tofp(30);
580 if (pid
->integral
> integral_limit
)
581 pid
->integral
= integral_limit
;
582 if (pid
->integral
< -integral_limit
)
583 pid
->integral
= -integral_limit
;
585 dterm
= mul_fp(pid
->d_gain
, fp_error
- pid
->last_err
);
586 pid
->last_err
= fp_error
;
588 result
= pterm
+ mul_fp(pid
->integral
, pid
->i_gain
) + dterm
;
589 result
= result
+ (1 << (FRAC_BITS
-1));
590 return (signed int)fp_toint(result
);
593 static inline void intel_pstate_busy_pid_reset(struct cpudata
*cpu
)
595 pid_p_gain_set(&cpu
->pid
, pid_params
.p_gain_pct
);
596 pid_d_gain_set(&cpu
->pid
, pid_params
.d_gain_pct
);
597 pid_i_gain_set(&cpu
->pid
, pid_params
.i_gain_pct
);
599 pid_reset(&cpu
->pid
, pid_params
.setpoint
, 100, pid_params
.deadband
, 0);
602 static inline void intel_pstate_reset_all_pid(void)
606 for_each_online_cpu(cpu
) {
607 if (all_cpu_data
[cpu
])
608 intel_pstate_busy_pid_reset(all_cpu_data
[cpu
]);
612 static inline void update_turbo_state(void)
617 cpu
= all_cpu_data
[0];
618 rdmsrl(MSR_IA32_MISC_ENABLE
, misc_en
);
619 global
.turbo_disabled
=
620 (misc_en
& MSR_IA32_MISC_ENABLE_TURBO_DISABLE
||
621 cpu
->pstate
.max_pstate
== cpu
->pstate
.turbo_pstate
);
624 static s16
intel_pstate_get_epb(struct cpudata
*cpu_data
)
629 if (!static_cpu_has(X86_FEATURE_EPB
))
632 ret
= rdmsrl_on_cpu(cpu_data
->cpu
, MSR_IA32_ENERGY_PERF_BIAS
, &epb
);
636 return (s16
)(epb
& 0x0f);
639 static s16
intel_pstate_get_epp(struct cpudata
*cpu_data
, u64 hwp_req_data
)
643 if (static_cpu_has(X86_FEATURE_HWP_EPP
)) {
645 * When hwp_req_data is 0, means that caller didn't read
646 * MSR_HWP_REQUEST, so need to read and get EPP.
649 epp
= rdmsrl_on_cpu(cpu_data
->cpu
, MSR_HWP_REQUEST
,
654 epp
= (hwp_req_data
>> 24) & 0xff;
656 /* When there is no EPP present, HWP uses EPB settings */
657 epp
= intel_pstate_get_epb(cpu_data
);
663 static int intel_pstate_set_epb(int cpu
, s16 pref
)
668 if (!static_cpu_has(X86_FEATURE_EPB
))
671 ret
= rdmsrl_on_cpu(cpu
, MSR_IA32_ENERGY_PERF_BIAS
, &epb
);
675 epb
= (epb
& ~0x0f) | pref
;
676 wrmsrl_on_cpu(cpu
, MSR_IA32_ENERGY_PERF_BIAS
, epb
);
682 * EPP/EPB display strings corresponding to EPP index in the
683 * energy_perf_strings[]
685 *-------------------------------------
688 * 2 balance_performance
692 static const char * const energy_perf_strings
[] = {
695 "balance_performance",
701 static int intel_pstate_get_energy_pref_index(struct cpudata
*cpu_data
)
706 epp
= intel_pstate_get_epp(cpu_data
, 0);
710 if (static_cpu_has(X86_FEATURE_HWP_EPP
)) {
713 * 0x00-0x3F : Performance
714 * 0x40-0x7F : Balance performance
715 * 0x80-0xBF : Balance power
717 * The EPP is a 8 bit value, but our ranges restrict the
718 * value which can be set. Here only using top two bits
721 index
= (epp
>> 6) + 1;
722 } else if (static_cpu_has(X86_FEATURE_EPB
)) {
725 * 0x00-0x03 : Performance
726 * 0x04-0x07 : Balance performance
727 * 0x08-0x0B : Balance power
729 * The EPB is a 4 bit value, but our ranges restrict the
730 * value which can be set. Here only using top two bits
733 index
= (epp
>> 2) + 1;
739 static int intel_pstate_set_energy_pref_index(struct cpudata
*cpu_data
,
746 epp
= cpu_data
->epp_default
;
748 mutex_lock(&intel_pstate_limits_lock
);
750 if (static_cpu_has(X86_FEATURE_HWP_EPP
)) {
753 ret
= rdmsrl_on_cpu(cpu_data
->cpu
, MSR_HWP_REQUEST
, &value
);
757 value
&= ~GENMASK_ULL(31, 24);
760 * If epp is not default, convert from index into
761 * energy_perf_strings to epp value, by shifting 6
762 * bits left to use only top two bits in epp.
763 * The resultant epp need to shifted by 24 bits to
764 * epp position in MSR_HWP_REQUEST.
767 epp
= (pref_index
- 1) << 6;
769 value
|= (u64
)epp
<< 24;
770 ret
= wrmsrl_on_cpu(cpu_data
->cpu
, MSR_HWP_REQUEST
, value
);
773 epp
= (pref_index
- 1) << 2;
774 ret
= intel_pstate_set_epb(cpu_data
->cpu
, epp
);
777 mutex_unlock(&intel_pstate_limits_lock
);
782 static ssize_t
show_energy_performance_available_preferences(
783 struct cpufreq_policy
*policy
, char *buf
)
788 while (energy_perf_strings
[i
] != NULL
)
789 ret
+= sprintf(&buf
[ret
], "%s ", energy_perf_strings
[i
++]);
791 ret
+= sprintf(&buf
[ret
], "\n");
796 cpufreq_freq_attr_ro(energy_performance_available_preferences
);
798 static ssize_t
store_energy_performance_preference(
799 struct cpufreq_policy
*policy
, const char *buf
, size_t count
)
801 struct cpudata
*cpu_data
= all_cpu_data
[policy
->cpu
];
802 char str_preference
[21];
805 ret
= sscanf(buf
, "%20s", str_preference
);
809 while (energy_perf_strings
[i
] != NULL
) {
810 if (!strcmp(str_preference
, energy_perf_strings
[i
])) {
811 intel_pstate_set_energy_pref_index(cpu_data
, i
);
820 static ssize_t
show_energy_performance_preference(
821 struct cpufreq_policy
*policy
, char *buf
)
823 struct cpudata
*cpu_data
= all_cpu_data
[policy
->cpu
];
826 preference
= intel_pstate_get_energy_pref_index(cpu_data
);
830 return sprintf(buf
, "%s\n", energy_perf_strings
[preference
]);
833 cpufreq_freq_attr_rw(energy_performance_preference
);
835 static struct freq_attr
*hwp_cpufreq_attrs
[] = {
836 &energy_performance_preference
,
837 &energy_performance_available_preferences
,
841 static void intel_pstate_hwp_set(struct cpufreq_policy
*policy
)
843 int min
, hw_min
, max
, hw_max
, cpu
;
844 struct perf_limits
*perf_limits
= &global
;
847 for_each_cpu(cpu
, policy
->cpus
) {
848 struct cpudata
*cpu_data
= all_cpu_data
[cpu
];
852 perf_limits
= all_cpu_data
[cpu
]->perf_limits
;
854 rdmsrl_on_cpu(cpu
, MSR_HWP_CAPABILITIES
, &cap
);
855 hw_min
= HWP_LOWEST_PERF(cap
);
857 hw_max
= HWP_GUARANTEED_PERF(cap
);
859 hw_max
= HWP_HIGHEST_PERF(cap
);
861 max
= fp_ext_toint(hw_max
* perf_limits
->max_perf
);
862 if (cpu_data
->policy
== CPUFREQ_POLICY_PERFORMANCE
)
865 min
= fp_ext_toint(hw_max
* perf_limits
->min_perf
);
867 rdmsrl_on_cpu(cpu
, MSR_HWP_REQUEST
, &value
);
869 value
&= ~HWP_MIN_PERF(~0L);
870 value
|= HWP_MIN_PERF(min
);
872 value
&= ~HWP_MAX_PERF(~0L);
873 value
|= HWP_MAX_PERF(max
);
875 if (cpu_data
->epp_policy
== cpu_data
->policy
)
878 cpu_data
->epp_policy
= cpu_data
->policy
;
880 if (cpu_data
->epp_saved
>= 0) {
881 epp
= cpu_data
->epp_saved
;
882 cpu_data
->epp_saved
= -EINVAL
;
886 if (cpu_data
->policy
== CPUFREQ_POLICY_PERFORMANCE
) {
887 epp
= intel_pstate_get_epp(cpu_data
, value
);
888 cpu_data
->epp_powersave
= epp
;
889 /* If EPP read was failed, then don't try to write */
896 /* skip setting EPP, when saved value is invalid */
897 if (cpu_data
->epp_powersave
< 0)
901 * No need to restore EPP when it is not zero. This
903 * - Policy is not changed
904 * - user has manually changed
905 * - Error reading EPB
907 epp
= intel_pstate_get_epp(cpu_data
, value
);
911 epp
= cpu_data
->epp_powersave
;
914 if (static_cpu_has(X86_FEATURE_HWP_EPP
)) {
915 value
&= ~GENMASK_ULL(31, 24);
916 value
|= (u64
)epp
<< 24;
918 intel_pstate_set_epb(cpu
, epp
);
921 wrmsrl_on_cpu(cpu
, MSR_HWP_REQUEST
, value
);
925 static int intel_pstate_hwp_set_policy(struct cpufreq_policy
*policy
)
928 intel_pstate_hwp_set(policy
);
933 static int intel_pstate_hwp_save_state(struct cpufreq_policy
*policy
)
935 struct cpudata
*cpu_data
= all_cpu_data
[policy
->cpu
];
940 cpu_data
->epp_saved
= intel_pstate_get_epp(cpu_data
, 0);
945 static int intel_pstate_resume(struct cpufreq_policy
*policy
)
952 mutex_lock(&intel_pstate_limits_lock
);
954 all_cpu_data
[policy
->cpu
]->epp_policy
= 0;
956 ret
= intel_pstate_hwp_set_policy(policy
);
958 mutex_unlock(&intel_pstate_limits_lock
);
963 static void intel_pstate_update_policies(void)
967 for_each_possible_cpu(cpu
)
968 cpufreq_update_policy(cpu
);
971 /************************** debugfs begin ************************/
972 static int pid_param_set(void *data
, u64 val
)
975 pid_params
.sample_rate_ns
= pid_params
.sample_rate_ms
* NSEC_PER_MSEC
;
976 intel_pstate_reset_all_pid();
980 static int pid_param_get(void *data
, u64
*val
)
985 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param
, pid_param_get
, pid_param_set
, "%llu\n");
987 static struct dentry
*debugfs_parent
;
992 struct dentry
*dentry
;
995 static struct pid_param pid_files
[] = {
996 {"sample_rate_ms", &pid_params
.sample_rate_ms
, },
997 {"d_gain_pct", &pid_params
.d_gain_pct
, },
998 {"i_gain_pct", &pid_params
.i_gain_pct
, },
999 {"deadband", &pid_params
.deadband
, },
1000 {"setpoint", &pid_params
.setpoint
, },
1001 {"p_gain_pct", &pid_params
.p_gain_pct
, },
1005 static void intel_pstate_debug_expose_params(void)
1009 debugfs_parent
= debugfs_create_dir("pstate_snb", NULL
);
1010 if (IS_ERR_OR_NULL(debugfs_parent
))
1013 for (i
= 0; pid_files
[i
].name
; i
++) {
1014 struct dentry
*dentry
;
1016 dentry
= debugfs_create_file(pid_files
[i
].name
, 0660,
1017 debugfs_parent
, pid_files
[i
].value
,
1019 if (!IS_ERR(dentry
))
1020 pid_files
[i
].dentry
= dentry
;
1024 static void intel_pstate_debug_hide_params(void)
1028 if (IS_ERR_OR_NULL(debugfs_parent
))
1031 for (i
= 0; pid_files
[i
].name
; i
++) {
1032 debugfs_remove(pid_files
[i
].dentry
);
1033 pid_files
[i
].dentry
= NULL
;
1036 debugfs_remove(debugfs_parent
);
1037 debugfs_parent
= NULL
;
1040 /************************** debugfs end ************************/
1042 /************************** sysfs begin ************************/
1043 #define show_one(file_name, object) \
1044 static ssize_t show_##file_name \
1045 (struct kobject *kobj, struct attribute *attr, char *buf) \
1047 return sprintf(buf, "%u\n", global.object); \
1050 static ssize_t
intel_pstate_show_status(char *buf
);
1051 static int intel_pstate_update_status(const char *buf
, size_t size
);
1053 static ssize_t
show_status(struct kobject
*kobj
,
1054 struct attribute
*attr
, char *buf
)
1058 mutex_lock(&intel_pstate_driver_lock
);
1059 ret
= intel_pstate_show_status(buf
);
1060 mutex_unlock(&intel_pstate_driver_lock
);
1065 static ssize_t
store_status(struct kobject
*a
, struct attribute
*b
,
1066 const char *buf
, size_t count
)
1068 char *p
= memchr(buf
, '\n', count
);
1071 mutex_lock(&intel_pstate_driver_lock
);
1072 ret
= intel_pstate_update_status(buf
, p
? p
- buf
: count
);
1073 mutex_unlock(&intel_pstate_driver_lock
);
1075 return ret
< 0 ? ret
: count
;
1078 static ssize_t
show_turbo_pct(struct kobject
*kobj
,
1079 struct attribute
*attr
, char *buf
)
1081 struct cpudata
*cpu
;
1082 int total
, no_turbo
, turbo_pct
;
1085 mutex_lock(&intel_pstate_driver_lock
);
1087 if (!driver_registered
) {
1088 mutex_unlock(&intel_pstate_driver_lock
);
1092 cpu
= all_cpu_data
[0];
1094 total
= cpu
->pstate
.turbo_pstate
- cpu
->pstate
.min_pstate
+ 1;
1095 no_turbo
= cpu
->pstate
.max_pstate
- cpu
->pstate
.min_pstate
+ 1;
1096 turbo_fp
= div_fp(no_turbo
, total
);
1097 turbo_pct
= 100 - fp_toint(mul_fp(turbo_fp
, int_tofp(100)));
1099 mutex_unlock(&intel_pstate_driver_lock
);
1101 return sprintf(buf
, "%u\n", turbo_pct
);
1104 static ssize_t
show_num_pstates(struct kobject
*kobj
,
1105 struct attribute
*attr
, char *buf
)
1107 struct cpudata
*cpu
;
1110 mutex_lock(&intel_pstate_driver_lock
);
1112 if (!driver_registered
) {
1113 mutex_unlock(&intel_pstate_driver_lock
);
1117 cpu
= all_cpu_data
[0];
1118 total
= cpu
->pstate
.turbo_pstate
- cpu
->pstate
.min_pstate
+ 1;
1120 mutex_unlock(&intel_pstate_driver_lock
);
1122 return sprintf(buf
, "%u\n", total
);
1125 static ssize_t
show_no_turbo(struct kobject
*kobj
,
1126 struct attribute
*attr
, char *buf
)
1130 mutex_lock(&intel_pstate_driver_lock
);
1132 if (!driver_registered
) {
1133 mutex_unlock(&intel_pstate_driver_lock
);
1137 update_turbo_state();
1138 if (global
.turbo_disabled
)
1139 ret
= sprintf(buf
, "%u\n", global
.turbo_disabled
);
1141 ret
= sprintf(buf
, "%u\n", global
.no_turbo
);
1143 mutex_unlock(&intel_pstate_driver_lock
);
1148 static ssize_t
store_no_turbo(struct kobject
*a
, struct attribute
*b
,
1149 const char *buf
, size_t count
)
1154 ret
= sscanf(buf
, "%u", &input
);
1158 mutex_lock(&intel_pstate_driver_lock
);
1160 if (!driver_registered
) {
1161 mutex_unlock(&intel_pstate_driver_lock
);
1165 mutex_lock(&intel_pstate_limits_lock
);
1167 update_turbo_state();
1168 if (global
.turbo_disabled
) {
1169 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1170 mutex_unlock(&intel_pstate_limits_lock
);
1171 mutex_unlock(&intel_pstate_driver_lock
);
1175 global
.no_turbo
= clamp_t(int, input
, 0, 1);
1177 mutex_unlock(&intel_pstate_limits_lock
);
1179 intel_pstate_update_policies();
1181 mutex_unlock(&intel_pstate_driver_lock
);
1186 static ssize_t
store_max_perf_pct(struct kobject
*a
, struct attribute
*b
,
1187 const char *buf
, size_t count
)
1192 ret
= sscanf(buf
, "%u", &input
);
1196 mutex_lock(&intel_pstate_driver_lock
);
1198 if (!driver_registered
) {
1199 mutex_unlock(&intel_pstate_driver_lock
);
1203 mutex_lock(&intel_pstate_limits_lock
);
1205 global
.max_sysfs_pct
= clamp_t(int, input
, 0 , 100);
1206 global
.max_perf_pct
= min(global
.max_policy_pct
, global
.max_sysfs_pct
);
1207 global
.max_perf_pct
= max(global
.min_policy_pct
, global
.max_perf_pct
);
1208 global
.max_perf_pct
= max(global
.min_perf_pct
, global
.max_perf_pct
);
1209 global
.max_perf
= percent_ext_fp(global
.max_perf_pct
);
1211 mutex_unlock(&intel_pstate_limits_lock
);
1213 intel_pstate_update_policies();
1215 mutex_unlock(&intel_pstate_driver_lock
);
1220 static ssize_t
store_min_perf_pct(struct kobject
*a
, struct attribute
*b
,
1221 const char *buf
, size_t count
)
1226 ret
= sscanf(buf
, "%u", &input
);
1230 mutex_lock(&intel_pstate_driver_lock
);
1232 if (!driver_registered
) {
1233 mutex_unlock(&intel_pstate_driver_lock
);
1237 mutex_lock(&intel_pstate_limits_lock
);
1239 global
.min_sysfs_pct
= clamp_t(int, input
, 0 , 100);
1240 global
.min_perf_pct
= max(global
.min_policy_pct
, global
.min_sysfs_pct
);
1241 global
.min_perf_pct
= min(global
.max_policy_pct
, global
.min_perf_pct
);
1242 global
.min_perf_pct
= min(global
.max_perf_pct
, global
.min_perf_pct
);
1243 global
.min_perf
= percent_ext_fp(global
.min_perf_pct
);
1245 mutex_unlock(&intel_pstate_limits_lock
);
1247 intel_pstate_update_policies();
1249 mutex_unlock(&intel_pstate_driver_lock
);
1254 show_one(max_perf_pct
, max_perf_pct
);
1255 show_one(min_perf_pct
, min_perf_pct
);
1257 define_one_global_rw(status
);
1258 define_one_global_rw(no_turbo
);
1259 define_one_global_rw(max_perf_pct
);
1260 define_one_global_rw(min_perf_pct
);
1261 define_one_global_ro(turbo_pct
);
1262 define_one_global_ro(num_pstates
);
1264 static struct attribute
*intel_pstate_attributes
[] = {
1272 static struct attribute_group intel_pstate_attr_group
= {
1273 .attrs
= intel_pstate_attributes
,
1276 static void __init
intel_pstate_sysfs_expose_params(void)
1278 struct kobject
*intel_pstate_kobject
;
1281 intel_pstate_kobject
= kobject_create_and_add("intel_pstate",
1282 &cpu_subsys
.dev_root
->kobj
);
1283 if (WARN_ON(!intel_pstate_kobject
))
1286 rc
= sysfs_create_group(intel_pstate_kobject
, &intel_pstate_attr_group
);
1291 * If per cpu limits are enforced there are no global limits, so
1292 * return without creating max/min_perf_pct attributes
1297 rc
= sysfs_create_file(intel_pstate_kobject
, &max_perf_pct
.attr
);
1300 rc
= sysfs_create_file(intel_pstate_kobject
, &min_perf_pct
.attr
);
1304 /************************** sysfs end ************************/
1306 static void intel_pstate_hwp_enable(struct cpudata
*cpudata
)
1308 /* First disable HWP notification interrupt as we don't process them */
1309 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY
))
1310 wrmsrl_on_cpu(cpudata
->cpu
, MSR_HWP_INTERRUPT
, 0x00);
1312 wrmsrl_on_cpu(cpudata
->cpu
, MSR_PM_ENABLE
, 0x1);
1313 cpudata
->epp_policy
= 0;
1314 if (cpudata
->epp_default
== -EINVAL
)
1315 cpudata
->epp_default
= intel_pstate_get_epp(cpudata
, 0);
1318 #define MSR_IA32_POWER_CTL_BIT_EE 19
1320 /* Disable energy efficiency optimization */
1321 static void intel_pstate_disable_ee(int cpu
)
1326 ret
= rdmsrl_on_cpu(cpu
, MSR_IA32_POWER_CTL
, &power_ctl
);
1330 if (!(power_ctl
& BIT(MSR_IA32_POWER_CTL_BIT_EE
))) {
1331 pr_info("Disabling energy efficiency optimization\n");
1332 power_ctl
|= BIT(MSR_IA32_POWER_CTL_BIT_EE
);
1333 wrmsrl_on_cpu(cpu
, MSR_IA32_POWER_CTL
, power_ctl
);
1337 static int atom_get_min_pstate(void)
1341 rdmsrl(MSR_ATOM_CORE_RATIOS
, value
);
1342 return (value
>> 8) & 0x7F;
1345 static int atom_get_max_pstate(void)
1349 rdmsrl(MSR_ATOM_CORE_RATIOS
, value
);
1350 return (value
>> 16) & 0x7F;
1353 static int atom_get_turbo_pstate(void)
1357 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS
, value
);
1358 return value
& 0x7F;
1361 static u64
atom_get_val(struct cpudata
*cpudata
, int pstate
)
1367 val
= (u64
)pstate
<< 8;
1368 if (global
.no_turbo
&& !global
.turbo_disabled
)
1369 val
|= (u64
)1 << 32;
1371 vid_fp
= cpudata
->vid
.min
+ mul_fp(
1372 int_tofp(pstate
- cpudata
->pstate
.min_pstate
),
1373 cpudata
->vid
.ratio
);
1375 vid_fp
= clamp_t(int32_t, vid_fp
, cpudata
->vid
.min
, cpudata
->vid
.max
);
1376 vid
= ceiling_fp(vid_fp
);
1378 if (pstate
> cpudata
->pstate
.max_pstate
)
1379 vid
= cpudata
->vid
.turbo
;
1384 static int silvermont_get_scaling(void)
1388 /* Defined in Table 35-6 from SDM (Sept 2015) */
1389 static int silvermont_freq_table
[] = {
1390 83300, 100000, 133300, 116700, 80000};
1392 rdmsrl(MSR_FSB_FREQ
, value
);
1396 return silvermont_freq_table
[i
];
1399 static int airmont_get_scaling(void)
1403 /* Defined in Table 35-10 from SDM (Sept 2015) */
1404 static int airmont_freq_table
[] = {
1405 83300, 100000, 133300, 116700, 80000,
1406 93300, 90000, 88900, 87500};
1408 rdmsrl(MSR_FSB_FREQ
, value
);
1412 return airmont_freq_table
[i
];
1415 static void atom_get_vid(struct cpudata
*cpudata
)
1419 rdmsrl(MSR_ATOM_CORE_VIDS
, value
);
1420 cpudata
->vid
.min
= int_tofp((value
>> 8) & 0x7f);
1421 cpudata
->vid
.max
= int_tofp((value
>> 16) & 0x7f);
1422 cpudata
->vid
.ratio
= div_fp(
1423 cpudata
->vid
.max
- cpudata
->vid
.min
,
1424 int_tofp(cpudata
->pstate
.max_pstate
-
1425 cpudata
->pstate
.min_pstate
));
1427 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS
, value
);
1428 cpudata
->vid
.turbo
= value
& 0x7f;
1431 static int core_get_min_pstate(void)
1435 rdmsrl(MSR_PLATFORM_INFO
, value
);
1436 return (value
>> 40) & 0xFF;
1439 static int core_get_max_pstate_physical(void)
1443 rdmsrl(MSR_PLATFORM_INFO
, value
);
1444 return (value
>> 8) & 0xFF;
1447 static int core_get_tdp_ratio(u64 plat_info
)
1449 /* Check how many TDP levels present */
1450 if (plat_info
& 0x600000000) {
1456 /* Get the TDP level (0, 1, 2) to get ratios */
1457 err
= rdmsrl_safe(MSR_CONFIG_TDP_CONTROL
, &tdp_ctrl
);
1461 /* TDP MSR are continuous starting at 0x648 */
1462 tdp_msr
= MSR_CONFIG_TDP_NOMINAL
+ (tdp_ctrl
& 0x03);
1463 err
= rdmsrl_safe(tdp_msr
, &tdp_ratio
);
1467 /* For level 1 and 2, bits[23:16] contain the ratio */
1468 if (tdp_ctrl
& 0x03)
1471 tdp_ratio
&= 0xff; /* ratios are only 8 bits long */
1472 pr_debug("tdp_ratio %x\n", (int)tdp_ratio
);
1474 return (int)tdp_ratio
;
1480 static int core_get_max_pstate(void)
1488 rdmsrl(MSR_PLATFORM_INFO
, plat_info
);
1489 max_pstate
= (plat_info
>> 8) & 0xFF;
1491 tdp_ratio
= core_get_tdp_ratio(plat_info
);
1496 /* Turbo activation ratio is not used on HWP platforms */
1500 err
= rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO
, &tar
);
1504 /* Do some sanity checking for safety */
1505 tar_levels
= tar
& 0xff;
1506 if (tdp_ratio
- 1 == tar_levels
) {
1507 max_pstate
= tar_levels
;
1508 pr_debug("max_pstate=TAC %x\n", max_pstate
);
1515 static int core_get_turbo_pstate(void)
1520 rdmsrl(MSR_TURBO_RATIO_LIMIT
, value
);
1521 nont
= core_get_max_pstate();
1522 ret
= (value
) & 255;
1528 static inline int core_get_scaling(void)
1533 static u64
core_get_val(struct cpudata
*cpudata
, int pstate
)
1537 val
= (u64
)pstate
<< 8;
1538 if (global
.no_turbo
&& !global
.turbo_disabled
)
1539 val
|= (u64
)1 << 32;
1544 static int knl_get_turbo_pstate(void)
1549 rdmsrl(MSR_TURBO_RATIO_LIMIT
, value
);
1550 nont
= core_get_max_pstate();
1551 ret
= (((value
) >> 8) & 0xFF);
1557 static struct cpu_defaults core_params
= {
1559 .sample_rate_ms
= 10,
1567 .get_max
= core_get_max_pstate
,
1568 .get_max_physical
= core_get_max_pstate_physical
,
1569 .get_min
= core_get_min_pstate
,
1570 .get_turbo
= core_get_turbo_pstate
,
1571 .get_scaling
= core_get_scaling
,
1572 .get_val
= core_get_val
,
1573 .get_target_pstate
= get_target_pstate_use_performance
,
1577 static const struct cpu_defaults silvermont_params
= {
1579 .sample_rate_ms
= 10,
1587 .get_max
= atom_get_max_pstate
,
1588 .get_max_physical
= atom_get_max_pstate
,
1589 .get_min
= atom_get_min_pstate
,
1590 .get_turbo
= atom_get_turbo_pstate
,
1591 .get_val
= atom_get_val
,
1592 .get_scaling
= silvermont_get_scaling
,
1593 .get_vid
= atom_get_vid
,
1594 .get_target_pstate
= get_target_pstate_use_cpu_load
,
1598 static const struct cpu_defaults airmont_params
= {
1600 .sample_rate_ms
= 10,
1608 .get_max
= atom_get_max_pstate
,
1609 .get_max_physical
= atom_get_max_pstate
,
1610 .get_min
= atom_get_min_pstate
,
1611 .get_turbo
= atom_get_turbo_pstate
,
1612 .get_val
= atom_get_val
,
1613 .get_scaling
= airmont_get_scaling
,
1614 .get_vid
= atom_get_vid
,
1615 .get_target_pstate
= get_target_pstate_use_cpu_load
,
1619 static const struct cpu_defaults knl_params
= {
1621 .sample_rate_ms
= 10,
1629 .get_max
= core_get_max_pstate
,
1630 .get_max_physical
= core_get_max_pstate_physical
,
1631 .get_min
= core_get_min_pstate
,
1632 .get_turbo
= knl_get_turbo_pstate
,
1633 .get_scaling
= core_get_scaling
,
1634 .get_val
= core_get_val
,
1635 .get_target_pstate
= get_target_pstate_use_performance
,
1639 static const struct cpu_defaults bxt_params
= {
1641 .sample_rate_ms
= 10,
1649 .get_max
= core_get_max_pstate
,
1650 .get_max_physical
= core_get_max_pstate_physical
,
1651 .get_min
= core_get_min_pstate
,
1652 .get_turbo
= core_get_turbo_pstate
,
1653 .get_scaling
= core_get_scaling
,
1654 .get_val
= core_get_val
,
1655 .get_target_pstate
= get_target_pstate_use_cpu_load
,
1659 static void intel_pstate_get_min_max(struct cpudata
*cpu
, int *min
, int *max
)
1661 int max_perf
= cpu
->pstate
.turbo_pstate
;
1664 struct perf_limits
*perf_limits
= &global
;
1666 if (global
.no_turbo
|| global
.turbo_disabled
)
1667 max_perf
= cpu
->pstate
.max_pstate
;
1670 perf_limits
= cpu
->perf_limits
;
1673 * performance can be limited by user through sysfs, by cpufreq
1674 * policy, or by cpu specific default values determined through
1677 max_perf_adj
= fp_ext_toint(max_perf
* perf_limits
->max_perf
);
1678 *max
= clamp_t(int, max_perf_adj
,
1679 cpu
->pstate
.min_pstate
, cpu
->pstate
.turbo_pstate
);
1681 min_perf
= fp_ext_toint(max_perf
* perf_limits
->min_perf
);
1682 *min
= clamp_t(int, min_perf
, cpu
->pstate
.min_pstate
, max_perf
);
1685 static void intel_pstate_set_pstate(struct cpudata
*cpu
, int pstate
)
1687 trace_cpu_frequency(pstate
* cpu
->pstate
.scaling
, cpu
->cpu
);
1688 cpu
->pstate
.current_pstate
= pstate
;
1690 * Generally, there is no guarantee that this code will always run on
1691 * the CPU being updated, so force the register update to run on the
1694 wrmsrl_on_cpu(cpu
->cpu
, MSR_IA32_PERF_CTL
,
1695 pstate_funcs
.get_val(cpu
, pstate
));
1698 static void intel_pstate_set_min_pstate(struct cpudata
*cpu
)
1700 intel_pstate_set_pstate(cpu
, cpu
->pstate
.min_pstate
);
1703 static void intel_pstate_max_within_limits(struct cpudata
*cpu
)
1705 int min_pstate
, max_pstate
;
1707 update_turbo_state();
1708 intel_pstate_get_min_max(cpu
, &min_pstate
, &max_pstate
);
1709 intel_pstate_set_pstate(cpu
, max_pstate
);
1712 static void intel_pstate_get_cpu_pstates(struct cpudata
*cpu
)
1714 cpu
->pstate
.min_pstate
= pstate_funcs
.get_min();
1715 cpu
->pstate
.max_pstate
= pstate_funcs
.get_max();
1716 cpu
->pstate
.max_pstate_physical
= pstate_funcs
.get_max_physical();
1717 cpu
->pstate
.turbo_pstate
= pstate_funcs
.get_turbo();
1718 cpu
->pstate
.scaling
= pstate_funcs
.get_scaling();
1719 cpu
->pstate
.max_freq
= cpu
->pstate
.max_pstate
* cpu
->pstate
.scaling
;
1720 cpu
->pstate
.turbo_freq
= cpu
->pstate
.turbo_pstate
* cpu
->pstate
.scaling
;
1722 if (pstate_funcs
.get_vid
)
1723 pstate_funcs
.get_vid(cpu
);
1725 intel_pstate_set_min_pstate(cpu
);
1728 static inline void intel_pstate_calc_avg_perf(struct cpudata
*cpu
)
1730 struct sample
*sample
= &cpu
->sample
;
1732 sample
->core_avg_perf
= div_ext_fp(sample
->aperf
, sample
->mperf
);
1735 static inline bool intel_pstate_sample(struct cpudata
*cpu
, u64 time
)
1738 unsigned long flags
;
1741 local_irq_save(flags
);
1742 rdmsrl(MSR_IA32_APERF
, aperf
);
1743 rdmsrl(MSR_IA32_MPERF
, mperf
);
1745 if (cpu
->prev_mperf
== mperf
|| cpu
->prev_tsc
== tsc
) {
1746 local_irq_restore(flags
);
1749 local_irq_restore(flags
);
1751 cpu
->last_sample_time
= cpu
->sample
.time
;
1752 cpu
->sample
.time
= time
;
1753 cpu
->sample
.aperf
= aperf
;
1754 cpu
->sample
.mperf
= mperf
;
1755 cpu
->sample
.tsc
= tsc
;
1756 cpu
->sample
.aperf
-= cpu
->prev_aperf
;
1757 cpu
->sample
.mperf
-= cpu
->prev_mperf
;
1758 cpu
->sample
.tsc
-= cpu
->prev_tsc
;
1760 cpu
->prev_aperf
= aperf
;
1761 cpu
->prev_mperf
= mperf
;
1762 cpu
->prev_tsc
= tsc
;
1764 * First time this function is invoked in a given cycle, all of the
1765 * previous sample data fields are equal to zero or stale and they must
1766 * be populated with meaningful numbers for things to work, so assume
1767 * that sample.time will always be reset before setting the utilization
1768 * update hook and make the caller skip the sample then.
1770 return !!cpu
->last_sample_time
;
1773 static inline int32_t get_avg_frequency(struct cpudata
*cpu
)
1775 return mul_ext_fp(cpu
->sample
.core_avg_perf
,
1776 cpu
->pstate
.max_pstate_physical
* cpu
->pstate
.scaling
);
1779 static inline int32_t get_avg_pstate(struct cpudata
*cpu
)
1781 return mul_ext_fp(cpu
->pstate
.max_pstate_physical
,
1782 cpu
->sample
.core_avg_perf
);
1785 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata
*cpu
)
1787 struct sample
*sample
= &cpu
->sample
;
1788 int32_t busy_frac
, boost
;
1789 int target
, avg_pstate
;
1791 busy_frac
= div_fp(sample
->mperf
, sample
->tsc
);
1793 boost
= cpu
->iowait_boost
;
1794 cpu
->iowait_boost
>>= 1;
1796 if (busy_frac
< boost
)
1799 sample
->busy_scaled
= busy_frac
* 100;
1801 target
= global
.no_turbo
|| global
.turbo_disabled
?
1802 cpu
->pstate
.max_pstate
: cpu
->pstate
.turbo_pstate
;
1803 target
+= target
>> 2;
1804 target
= mul_fp(target
, busy_frac
);
1805 if (target
< cpu
->pstate
.min_pstate
)
1806 target
= cpu
->pstate
.min_pstate
;
1809 * If the average P-state during the previous cycle was higher than the
1810 * current target, add 50% of the difference to the target to reduce
1811 * possible performance oscillations and offset possible performance
1812 * loss related to moving the workload from one CPU to another within
1815 avg_pstate
= get_avg_pstate(cpu
);
1816 if (avg_pstate
> target
)
1817 target
+= (avg_pstate
- target
) >> 1;
1822 static inline int32_t get_target_pstate_use_performance(struct cpudata
*cpu
)
1824 int32_t perf_scaled
, max_pstate
, current_pstate
, sample_ratio
;
1828 * perf_scaled is the ratio of the average P-state during the last
1829 * sampling period to the P-state requested last time (in percent).
1831 * That measures the system's response to the previous P-state
1834 max_pstate
= cpu
->pstate
.max_pstate_physical
;
1835 current_pstate
= cpu
->pstate
.current_pstate
;
1836 perf_scaled
= mul_ext_fp(cpu
->sample
.core_avg_perf
,
1837 div_fp(100 * max_pstate
, current_pstate
));
1840 * Since our utilization update callback will not run unless we are
1841 * in C0, check if the actual elapsed time is significantly greater (3x)
1842 * than our sample interval. If it is, then we were idle for a long
1843 * enough period of time to adjust our performance metric.
1845 duration_ns
= cpu
->sample
.time
- cpu
->last_sample_time
;
1846 if ((s64
)duration_ns
> pid_params
.sample_rate_ns
* 3) {
1847 sample_ratio
= div_fp(pid_params
.sample_rate_ns
, duration_ns
);
1848 perf_scaled
= mul_fp(perf_scaled
, sample_ratio
);
1850 sample_ratio
= div_fp(100 * cpu
->sample
.mperf
, cpu
->sample
.tsc
);
1851 if (sample_ratio
< int_tofp(1))
1855 cpu
->sample
.busy_scaled
= perf_scaled
;
1856 return cpu
->pstate
.current_pstate
- pid_calc(&cpu
->pid
, perf_scaled
);
1859 static int intel_pstate_prepare_request(struct cpudata
*cpu
, int pstate
)
1861 int max_perf
, min_perf
;
1863 intel_pstate_get_min_max(cpu
, &min_perf
, &max_perf
);
1864 pstate
= clamp_t(int, pstate
, min_perf
, max_perf
);
1868 static void intel_pstate_update_pstate(struct cpudata
*cpu
, int pstate
)
1870 if (pstate
== cpu
->pstate
.current_pstate
)
1873 cpu
->pstate
.current_pstate
= pstate
;
1874 wrmsrl(MSR_IA32_PERF_CTL
, pstate_funcs
.get_val(cpu
, pstate
));
1877 static inline void intel_pstate_adjust_busy_pstate(struct cpudata
*cpu
)
1879 int from
, target_pstate
;
1880 struct sample
*sample
;
1882 from
= cpu
->pstate
.current_pstate
;
1884 target_pstate
= cpu
->policy
== CPUFREQ_POLICY_PERFORMANCE
?
1885 cpu
->pstate
.turbo_pstate
: pstate_funcs
.get_target_pstate(cpu
);
1887 update_turbo_state();
1889 target_pstate
= intel_pstate_prepare_request(cpu
, target_pstate
);
1890 trace_cpu_frequency(target_pstate
* cpu
->pstate
.scaling
, cpu
->cpu
);
1891 intel_pstate_update_pstate(cpu
, target_pstate
);
1893 sample
= &cpu
->sample
;
1894 trace_pstate_sample(mul_ext_fp(100, sample
->core_avg_perf
),
1895 fp_toint(sample
->busy_scaled
),
1897 cpu
->pstate
.current_pstate
,
1901 get_avg_frequency(cpu
),
1902 fp_toint(cpu
->iowait_boost
* 100));
1905 static void intel_pstate_update_util(struct update_util_data
*data
, u64 time
,
1908 struct cpudata
*cpu
= container_of(data
, struct cpudata
, update_util
);
1911 if (pstate_funcs
.get_target_pstate
== get_target_pstate_use_cpu_load
) {
1912 if (flags
& SCHED_CPUFREQ_IOWAIT
) {
1913 cpu
->iowait_boost
= int_tofp(1);
1914 } else if (cpu
->iowait_boost
) {
1915 /* Clear iowait_boost if the CPU may have been idle. */
1916 delta_ns
= time
- cpu
->last_update
;
1917 if (delta_ns
> TICK_NSEC
)
1918 cpu
->iowait_boost
= 0;
1920 cpu
->last_update
= time
;
1923 delta_ns
= time
- cpu
->sample
.time
;
1924 if ((s64
)delta_ns
>= pid_params
.sample_rate_ns
) {
1925 bool sample_taken
= intel_pstate_sample(cpu
, time
);
1928 intel_pstate_calc_avg_perf(cpu
);
1930 intel_pstate_adjust_busy_pstate(cpu
);
1935 #define ICPU(model, policy) \
1936 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1937 (unsigned long)&policy }
1939 static const struct x86_cpu_id intel_pstate_cpu_ids
[] = {
1940 ICPU(INTEL_FAM6_SANDYBRIDGE
, core_params
),
1941 ICPU(INTEL_FAM6_SANDYBRIDGE_X
, core_params
),
1942 ICPU(INTEL_FAM6_ATOM_SILVERMONT1
, silvermont_params
),
1943 ICPU(INTEL_FAM6_IVYBRIDGE
, core_params
),
1944 ICPU(INTEL_FAM6_HASWELL_CORE
, core_params
),
1945 ICPU(INTEL_FAM6_BROADWELL_CORE
, core_params
),
1946 ICPU(INTEL_FAM6_IVYBRIDGE_X
, core_params
),
1947 ICPU(INTEL_FAM6_HASWELL_X
, core_params
),
1948 ICPU(INTEL_FAM6_HASWELL_ULT
, core_params
),
1949 ICPU(INTEL_FAM6_HASWELL_GT3E
, core_params
),
1950 ICPU(INTEL_FAM6_BROADWELL_GT3E
, core_params
),
1951 ICPU(INTEL_FAM6_ATOM_AIRMONT
, airmont_params
),
1952 ICPU(INTEL_FAM6_SKYLAKE_MOBILE
, core_params
),
1953 ICPU(INTEL_FAM6_BROADWELL_X
, core_params
),
1954 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP
, core_params
),
1955 ICPU(INTEL_FAM6_BROADWELL_XEON_D
, core_params
),
1956 ICPU(INTEL_FAM6_XEON_PHI_KNL
, knl_params
),
1957 ICPU(INTEL_FAM6_XEON_PHI_KNM
, knl_params
),
1958 ICPU(INTEL_FAM6_ATOM_GOLDMONT
, bxt_params
),
1961 MODULE_DEVICE_TABLE(x86cpu
, intel_pstate_cpu_ids
);
1963 static const struct x86_cpu_id intel_pstate_cpu_oob_ids
[] __initconst
= {
1964 ICPU(INTEL_FAM6_BROADWELL_XEON_D
, core_params
),
1965 ICPU(INTEL_FAM6_BROADWELL_X
, core_params
),
1966 ICPU(INTEL_FAM6_SKYLAKE_X
, core_params
),
1970 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids
[] = {
1971 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP
, core_params
),
1975 static int intel_pstate_init_cpu(unsigned int cpunum
)
1977 struct cpudata
*cpu
;
1979 cpu
= all_cpu_data
[cpunum
];
1982 unsigned int size
= sizeof(struct cpudata
);
1985 size
+= sizeof(struct perf_limits
);
1987 cpu
= kzalloc(size
, GFP_KERNEL
);
1991 all_cpu_data
[cpunum
] = cpu
;
1993 cpu
->perf_limits
= (struct perf_limits
*)(cpu
+ 1);
1995 cpu
->epp_default
= -EINVAL
;
1996 cpu
->epp_powersave
= -EINVAL
;
1997 cpu
->epp_saved
= -EINVAL
;
2000 cpu
= all_cpu_data
[cpunum
];
2005 const struct x86_cpu_id
*id
;
2007 id
= x86_match_cpu(intel_pstate_cpu_ee_disable_ids
);
2009 intel_pstate_disable_ee(cpunum
);
2011 intel_pstate_hwp_enable(cpu
);
2012 pid_params
.sample_rate_ms
= 50;
2013 pid_params
.sample_rate_ns
= 50 * NSEC_PER_MSEC
;
2016 intel_pstate_get_cpu_pstates(cpu
);
2018 intel_pstate_busy_pid_reset(cpu
);
2020 pr_debug("controlling: cpu %d\n", cpunum
);
2025 static unsigned int intel_pstate_get(unsigned int cpu_num
)
2027 struct cpudata
*cpu
= all_cpu_data
[cpu_num
];
2029 return cpu
? get_avg_frequency(cpu
) : 0;
2032 static void intel_pstate_set_update_util_hook(unsigned int cpu_num
)
2034 struct cpudata
*cpu
= all_cpu_data
[cpu_num
];
2036 if (cpu
->update_util_set
)
2039 /* Prevent intel_pstate_update_util() from using stale data. */
2040 cpu
->sample
.time
= 0;
2041 cpufreq_add_update_util_hook(cpu_num
, &cpu
->update_util
,
2042 intel_pstate_update_util
);
2043 cpu
->update_util_set
= true;
2046 static void intel_pstate_clear_update_util_hook(unsigned int cpu
)
2048 struct cpudata
*cpu_data
= all_cpu_data
[cpu
];
2050 if (!cpu_data
->update_util_set
)
2053 cpufreq_remove_update_util_hook(cpu
);
2054 cpu_data
->update_util_set
= false;
2055 synchronize_sched();
2058 static void intel_pstate_update_perf_limits(struct cpufreq_policy
*policy
,
2059 struct perf_limits
*limits
)
2061 int32_t max_policy_perf
, min_policy_perf
;
2063 max_policy_perf
= div_ext_fp(policy
->max
, policy
->cpuinfo
.max_freq
);
2064 max_policy_perf
= clamp_t(int32_t, max_policy_perf
, 0, int_ext_tofp(1));
2065 if (policy
->max
== policy
->min
) {
2066 min_policy_perf
= max_policy_perf
;
2068 min_policy_perf
= div_ext_fp(policy
->min
,
2069 policy
->cpuinfo
.max_freq
);
2070 min_policy_perf
= clamp_t(int32_t, min_policy_perf
,
2071 0, max_policy_perf
);
2074 /* Normalize user input to [min_perf, max_perf] */
2075 limits
->min_perf
= max(min_policy_perf
,
2076 percent_ext_fp(limits
->min_sysfs_pct
));
2077 limits
->min_perf
= min(limits
->min_perf
, max_policy_perf
);
2078 limits
->max_perf
= min(max_policy_perf
,
2079 percent_ext_fp(limits
->max_sysfs_pct
));
2080 limits
->max_perf
= max(min_policy_perf
, limits
->max_perf
);
2082 /* Make sure min_perf <= max_perf */
2083 limits
->min_perf
= min(limits
->min_perf
, limits
->max_perf
);
2085 limits
->max_perf
= round_up(limits
->max_perf
, EXT_FRAC_BITS
);
2086 limits
->min_perf
= round_up(limits
->min_perf
, EXT_FRAC_BITS
);
2087 limits
->max_perf_pct
= fp_ext_toint(limits
->max_perf
* 100);
2088 limits
->min_perf_pct
= fp_ext_toint(limits
->min_perf
* 100);
2090 pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy
->cpu
,
2091 limits
->max_perf_pct
, limits
->min_perf_pct
);
2094 static int intel_pstate_set_policy(struct cpufreq_policy
*policy
)
2096 struct cpudata
*cpu
;
2097 struct perf_limits
*perf_limits
= &global
;
2099 if (!policy
->cpuinfo
.max_freq
)
2102 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2103 policy
->cpuinfo
.max_freq
, policy
->max
);
2105 cpu
= all_cpu_data
[policy
->cpu
];
2106 cpu
->policy
= policy
->policy
;
2108 if (cpu
->pstate
.max_pstate_physical
> cpu
->pstate
.max_pstate
&&
2109 policy
->max
< policy
->cpuinfo
.max_freq
&&
2110 policy
->max
> cpu
->pstate
.max_pstate
* cpu
->pstate
.scaling
) {
2111 pr_debug("policy->max > max non turbo frequency\n");
2112 policy
->max
= policy
->cpuinfo
.max_freq
;
2116 perf_limits
= cpu
->perf_limits
;
2118 mutex_lock(&intel_pstate_limits_lock
);
2120 intel_pstate_update_perf_limits(policy
, perf_limits
);
2122 if (cpu
->policy
== CPUFREQ_POLICY_PERFORMANCE
) {
2124 * NOHZ_FULL CPUs need this as the governor callback may not
2125 * be invoked on them.
2127 intel_pstate_clear_update_util_hook(policy
->cpu
);
2128 intel_pstate_max_within_limits(cpu
);
2131 intel_pstate_set_update_util_hook(policy
->cpu
);
2133 intel_pstate_hwp_set_policy(policy
);
2135 mutex_unlock(&intel_pstate_limits_lock
);
2140 static int intel_pstate_verify_policy(struct cpufreq_policy
*policy
)
2142 struct cpudata
*cpu
= all_cpu_data
[policy
->cpu
];
2144 update_turbo_state();
2145 policy
->cpuinfo
.max_freq
= global
.turbo_disabled
|| global
.no_turbo
?
2146 cpu
->pstate
.max_freq
:
2147 cpu
->pstate
.turbo_freq
;
2149 cpufreq_verify_within_cpu_limits(policy
);
2151 if (policy
->policy
!= CPUFREQ_POLICY_POWERSAVE
&&
2152 policy
->policy
!= CPUFREQ_POLICY_PERFORMANCE
)
2155 /* When per-CPU limits are used, sysfs limits are not used */
2156 if (!per_cpu_limits
) {
2157 unsigned int max_freq
, min_freq
;
2159 max_freq
= policy
->cpuinfo
.max_freq
*
2160 global
.max_sysfs_pct
/ 100;
2161 min_freq
= policy
->cpuinfo
.max_freq
*
2162 global
.min_sysfs_pct
/ 100;
2163 cpufreq_verify_within_limits(policy
, min_freq
, max_freq
);
2169 static void intel_cpufreq_stop_cpu(struct cpufreq_policy
*policy
)
2171 intel_pstate_set_min_pstate(all_cpu_data
[policy
->cpu
]);
2174 static void intel_pstate_stop_cpu(struct cpufreq_policy
*policy
)
2176 pr_debug("CPU %d exiting\n", policy
->cpu
);
2178 intel_pstate_clear_update_util_hook(policy
->cpu
);
2180 intel_pstate_hwp_save_state(policy
);
2182 intel_cpufreq_stop_cpu(policy
);
2185 static int intel_pstate_cpu_exit(struct cpufreq_policy
*policy
)
2187 intel_pstate_exit_perf_limits(policy
);
2189 policy
->fast_switch_possible
= false;
2194 static int __intel_pstate_cpu_init(struct cpufreq_policy
*policy
)
2196 struct cpudata
*cpu
;
2199 rc
= intel_pstate_init_cpu(policy
->cpu
);
2203 cpu
= all_cpu_data
[policy
->cpu
];
2206 intel_pstate_init_limits(cpu
->perf_limits
);
2208 policy
->min
= cpu
->pstate
.min_pstate
* cpu
->pstate
.scaling
;
2209 policy
->max
= cpu
->pstate
.turbo_pstate
* cpu
->pstate
.scaling
;
2211 /* cpuinfo and default policy values */
2212 policy
->cpuinfo
.min_freq
= cpu
->pstate
.min_pstate
* cpu
->pstate
.scaling
;
2213 update_turbo_state();
2214 policy
->cpuinfo
.max_freq
= global
.turbo_disabled
?
2215 cpu
->pstate
.max_pstate
: cpu
->pstate
.turbo_pstate
;
2216 policy
->cpuinfo
.max_freq
*= cpu
->pstate
.scaling
;
2218 intel_pstate_init_acpi_perf_limits(policy
);
2219 cpumask_set_cpu(policy
->cpu
, policy
->cpus
);
2221 policy
->fast_switch_possible
= true;
2226 static int intel_pstate_cpu_init(struct cpufreq_policy
*policy
)
2228 int ret
= __intel_pstate_cpu_init(policy
);
2233 policy
->cpuinfo
.transition_latency
= CPUFREQ_ETERNAL
;
2234 if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE
))
2235 policy
->policy
= CPUFREQ_POLICY_PERFORMANCE
;
2237 policy
->policy
= CPUFREQ_POLICY_POWERSAVE
;
2242 static struct cpufreq_driver intel_pstate
= {
2243 .flags
= CPUFREQ_CONST_LOOPS
,
2244 .verify
= intel_pstate_verify_policy
,
2245 .setpolicy
= intel_pstate_set_policy
,
2246 .suspend
= intel_pstate_hwp_save_state
,
2247 .resume
= intel_pstate_resume
,
2248 .get
= intel_pstate_get
,
2249 .init
= intel_pstate_cpu_init
,
2250 .exit
= intel_pstate_cpu_exit
,
2251 .stop_cpu
= intel_pstate_stop_cpu
,
2252 .name
= "intel_pstate",
2255 static int intel_cpufreq_verify_policy(struct cpufreq_policy
*policy
)
2257 struct cpudata
*cpu
= all_cpu_data
[policy
->cpu
];
2259 update_turbo_state();
2260 policy
->cpuinfo
.max_freq
= global
.no_turbo
|| global
.turbo_disabled
?
2261 cpu
->pstate
.max_freq
: cpu
->pstate
.turbo_freq
;
2263 cpufreq_verify_within_cpu_limits(policy
);
2268 static int intel_cpufreq_target(struct cpufreq_policy
*policy
,
2269 unsigned int target_freq
,
2270 unsigned int relation
)
2272 struct cpudata
*cpu
= all_cpu_data
[policy
->cpu
];
2273 struct cpufreq_freqs freqs
;
2276 update_turbo_state();
2278 freqs
.old
= policy
->cur
;
2279 freqs
.new = target_freq
;
2281 cpufreq_freq_transition_begin(policy
, &freqs
);
2283 case CPUFREQ_RELATION_L
:
2284 target_pstate
= DIV_ROUND_UP(freqs
.new, cpu
->pstate
.scaling
);
2286 case CPUFREQ_RELATION_H
:
2287 target_pstate
= freqs
.new / cpu
->pstate
.scaling
;
2290 target_pstate
= DIV_ROUND_CLOSEST(freqs
.new, cpu
->pstate
.scaling
);
2293 target_pstate
= intel_pstate_prepare_request(cpu
, target_pstate
);
2294 if (target_pstate
!= cpu
->pstate
.current_pstate
) {
2295 cpu
->pstate
.current_pstate
= target_pstate
;
2296 wrmsrl_on_cpu(policy
->cpu
, MSR_IA32_PERF_CTL
,
2297 pstate_funcs
.get_val(cpu
, target_pstate
));
2299 freqs
.new = target_pstate
* cpu
->pstate
.scaling
;
2300 cpufreq_freq_transition_end(policy
, &freqs
, false);
2305 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy
*policy
,
2306 unsigned int target_freq
)
2308 struct cpudata
*cpu
= all_cpu_data
[policy
->cpu
];
2311 update_turbo_state();
2313 target_pstate
= DIV_ROUND_UP(target_freq
, cpu
->pstate
.scaling
);
2314 target_pstate
= intel_pstate_prepare_request(cpu
, target_pstate
);
2315 intel_pstate_update_pstate(cpu
, target_pstate
);
2316 return target_pstate
* cpu
->pstate
.scaling
;
2319 static int intel_cpufreq_cpu_init(struct cpufreq_policy
*policy
)
2321 int ret
= __intel_pstate_cpu_init(policy
);
2326 policy
->cpuinfo
.transition_latency
= INTEL_CPUFREQ_TRANSITION_LATENCY
;
2327 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2328 policy
->cur
= policy
->cpuinfo
.min_freq
;
2333 static struct cpufreq_driver intel_cpufreq
= {
2334 .flags
= CPUFREQ_CONST_LOOPS
,
2335 .verify
= intel_cpufreq_verify_policy
,
2336 .target
= intel_cpufreq_target
,
2337 .fast_switch
= intel_cpufreq_fast_switch
,
2338 .init
= intel_cpufreq_cpu_init
,
2339 .exit
= intel_pstate_cpu_exit
,
2340 .stop_cpu
= intel_cpufreq_stop_cpu
,
2341 .name
= "intel_cpufreq",
2344 static struct cpufreq_driver
*intel_pstate_driver
= &intel_pstate
;
2346 static void intel_pstate_driver_cleanup(void)
2351 for_each_online_cpu(cpu
) {
2352 if (all_cpu_data
[cpu
]) {
2353 if (intel_pstate_driver
== &intel_pstate
)
2354 intel_pstate_clear_update_util_hook(cpu
);
2356 kfree(all_cpu_data
[cpu
]);
2357 all_cpu_data
[cpu
] = NULL
;
2363 static int intel_pstate_register_driver(void)
2367 intel_pstate_init_limits(&global
);
2369 ret
= cpufreq_register_driver(intel_pstate_driver
);
2371 intel_pstate_driver_cleanup();
2375 mutex_lock(&intel_pstate_limits_lock
);
2376 driver_registered
= true;
2377 mutex_unlock(&intel_pstate_limits_lock
);
2379 if (intel_pstate_driver
== &intel_pstate
&& !hwp_active
&&
2380 pstate_funcs
.get_target_pstate
!= get_target_pstate_use_cpu_load
)
2381 intel_pstate_debug_expose_params();
2386 static int intel_pstate_unregister_driver(void)
2391 if (intel_pstate_driver
== &intel_pstate
&& !hwp_active
&&
2392 pstate_funcs
.get_target_pstate
!= get_target_pstate_use_cpu_load
)
2393 intel_pstate_debug_hide_params();
2395 mutex_lock(&intel_pstate_limits_lock
);
2396 driver_registered
= false;
2397 mutex_unlock(&intel_pstate_limits_lock
);
2399 cpufreq_unregister_driver(intel_pstate_driver
);
2400 intel_pstate_driver_cleanup();
2405 static ssize_t
intel_pstate_show_status(char *buf
)
2407 if (!driver_registered
)
2408 return sprintf(buf
, "off\n");
2410 return sprintf(buf
, "%s\n", intel_pstate_driver
== &intel_pstate
?
2411 "active" : "passive");
2414 static int intel_pstate_update_status(const char *buf
, size_t size
)
2418 if (size
== 3 && !strncmp(buf
, "off", size
))
2419 return driver_registered
?
2420 intel_pstate_unregister_driver() : -EINVAL
;
2422 if (size
== 6 && !strncmp(buf
, "active", size
)) {
2423 if (driver_registered
) {
2424 if (intel_pstate_driver
== &intel_pstate
)
2427 ret
= intel_pstate_unregister_driver();
2432 intel_pstate_driver
= &intel_pstate
;
2433 return intel_pstate_register_driver();
2436 if (size
== 7 && !strncmp(buf
, "passive", size
)) {
2437 if (driver_registered
) {
2438 if (intel_pstate_driver
!= &intel_pstate
)
2441 ret
= intel_pstate_unregister_driver();
2446 intel_pstate_driver
= &intel_cpufreq
;
2447 return intel_pstate_register_driver();
2453 static int no_load __initdata
;
2454 static int no_hwp __initdata
;
2455 static int hwp_only __initdata
;
2456 static unsigned int force_load __initdata
;
2458 static int __init
intel_pstate_msrs_not_valid(void)
2460 if (!pstate_funcs
.get_max() ||
2461 !pstate_funcs
.get_min() ||
2462 !pstate_funcs
.get_turbo())
2468 static void __init
copy_pid_params(struct pstate_adjust_policy
*policy
)
2470 pid_params
.sample_rate_ms
= policy
->sample_rate_ms
;
2471 pid_params
.sample_rate_ns
= pid_params
.sample_rate_ms
* NSEC_PER_MSEC
;
2472 pid_params
.p_gain_pct
= policy
->p_gain_pct
;
2473 pid_params
.i_gain_pct
= policy
->i_gain_pct
;
2474 pid_params
.d_gain_pct
= policy
->d_gain_pct
;
2475 pid_params
.deadband
= policy
->deadband
;
2476 pid_params
.setpoint
= policy
->setpoint
;
2480 static void intel_pstate_use_acpi_profile(void)
2482 if (acpi_gbl_FADT
.preferred_profile
== PM_MOBILE
)
2483 pstate_funcs
.get_target_pstate
=
2484 get_target_pstate_use_cpu_load
;
2487 static void intel_pstate_use_acpi_profile(void)
2492 static void __init
copy_cpu_funcs(struct pstate_funcs
*funcs
)
2494 pstate_funcs
.get_max
= funcs
->get_max
;
2495 pstate_funcs
.get_max_physical
= funcs
->get_max_physical
;
2496 pstate_funcs
.get_min
= funcs
->get_min
;
2497 pstate_funcs
.get_turbo
= funcs
->get_turbo
;
2498 pstate_funcs
.get_scaling
= funcs
->get_scaling
;
2499 pstate_funcs
.get_val
= funcs
->get_val
;
2500 pstate_funcs
.get_vid
= funcs
->get_vid
;
2501 pstate_funcs
.get_target_pstate
= funcs
->get_target_pstate
;
2503 intel_pstate_use_acpi_profile();
2508 static bool __init
intel_pstate_no_acpi_pss(void)
2512 for_each_possible_cpu(i
) {
2514 union acpi_object
*pss
;
2515 struct acpi_buffer buffer
= { ACPI_ALLOCATE_BUFFER
, NULL
};
2516 struct acpi_processor
*pr
= per_cpu(processors
, i
);
2521 status
= acpi_evaluate_object(pr
->handle
, "_PSS", NULL
, &buffer
);
2522 if (ACPI_FAILURE(status
))
2525 pss
= buffer
.pointer
;
2526 if (pss
&& pss
->type
== ACPI_TYPE_PACKAGE
) {
2537 static bool __init
intel_pstate_has_acpi_ppc(void)
2541 for_each_possible_cpu(i
) {
2542 struct acpi_processor
*pr
= per_cpu(processors
, i
);
2546 if (acpi_has_method(pr
->handle
, "_PPC"))
2557 struct hw_vendor_info
{
2559 char oem_id
[ACPI_OEM_ID_SIZE
];
2560 char oem_table_id
[ACPI_OEM_TABLE_ID_SIZE
];
2564 /* Hardware vendor-specific info that has its own power management modes */
2565 static struct hw_vendor_info vendor_info
[] __initdata
= {
2566 {1, "HP ", "ProLiant", PSS
},
2567 {1, "ORACLE", "X4-2 ", PPC
},
2568 {1, "ORACLE", "X4-2L ", PPC
},
2569 {1, "ORACLE", "X4-2B ", PPC
},
2570 {1, "ORACLE", "X3-2 ", PPC
},
2571 {1, "ORACLE", "X3-2L ", PPC
},
2572 {1, "ORACLE", "X3-2B ", PPC
},
2573 {1, "ORACLE", "X4470M2 ", PPC
},
2574 {1, "ORACLE", "X4270M3 ", PPC
},
2575 {1, "ORACLE", "X4270M2 ", PPC
},
2576 {1, "ORACLE", "X4170M2 ", PPC
},
2577 {1, "ORACLE", "X4170 M3", PPC
},
2578 {1, "ORACLE", "X4275 M3", PPC
},
2579 {1, "ORACLE", "X6-2 ", PPC
},
2580 {1, "ORACLE", "Sudbury ", PPC
},
2584 static bool __init
intel_pstate_platform_pwr_mgmt_exists(void)
2586 struct acpi_table_header hdr
;
2587 struct hw_vendor_info
*v_info
;
2588 const struct x86_cpu_id
*id
;
2591 id
= x86_match_cpu(intel_pstate_cpu_oob_ids
);
2593 rdmsrl(MSR_MISC_PWR_MGMT
, misc_pwr
);
2594 if ( misc_pwr
& (1 << 8))
2598 if (acpi_disabled
||
2599 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT
, 0, &hdr
)))
2602 for (v_info
= vendor_info
; v_info
->valid
; v_info
++) {
2603 if (!strncmp(hdr
.oem_id
, v_info
->oem_id
, ACPI_OEM_ID_SIZE
) &&
2604 !strncmp(hdr
.oem_table_id
, v_info
->oem_table_id
,
2605 ACPI_OEM_TABLE_ID_SIZE
))
2606 switch (v_info
->oem_pwr_table
) {
2608 return intel_pstate_no_acpi_pss();
2610 return intel_pstate_has_acpi_ppc() &&
2618 static void intel_pstate_request_control_from_smm(void)
2621 * It may be unsafe to request P-states control from SMM if _PPC support
2622 * has not been enabled.
2625 acpi_processor_pstate_control();
2627 #else /* CONFIG_ACPI not enabled */
2628 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2629 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2630 static inline void intel_pstate_request_control_from_smm(void) {}
2631 #endif /* CONFIG_ACPI */
2633 static const struct x86_cpu_id hwp_support_ids
[] __initconst
= {
2634 { X86_VENDOR_INTEL
, 6, X86_MODEL_ANY
, X86_FEATURE_HWP
},
2638 static int __init
intel_pstate_init(void)
2640 const struct x86_cpu_id
*id
;
2641 struct cpu_defaults
*cpu_def
;
2647 if (x86_match_cpu(hwp_support_ids
) && !no_hwp
) {
2648 copy_cpu_funcs(&core_params
.funcs
);
2650 intel_pstate
.attr
= hwp_cpufreq_attrs
;
2651 goto hwp_cpu_matched
;
2654 id
= x86_match_cpu(intel_pstate_cpu_ids
);
2658 cpu_def
= (struct cpu_defaults
*)id
->driver_data
;
2660 copy_pid_params(&cpu_def
->pid_policy
);
2661 copy_cpu_funcs(&cpu_def
->funcs
);
2663 if (intel_pstate_msrs_not_valid())
2668 * The Intel pstate driver will be ignored if the platform
2669 * firmware has its own power management modes.
2671 if (intel_pstate_platform_pwr_mgmt_exists())
2674 if (!hwp_active
&& hwp_only
)
2677 pr_info("Intel P-state driver initializing\n");
2679 all_cpu_data
= vzalloc(sizeof(void *) * num_possible_cpus());
2683 intel_pstate_request_control_from_smm();
2685 intel_pstate_sysfs_expose_params();
2687 mutex_lock(&intel_pstate_driver_lock
);
2688 rc
= intel_pstate_register_driver();
2689 mutex_unlock(&intel_pstate_driver_lock
);
2694 pr_info("HWP enabled\n");
2698 device_initcall(intel_pstate_init
);
2700 static int __init
intel_pstate_setup(char *str
)
2705 if (!strcmp(str
, "disable")) {
2707 } else if (!strcmp(str
, "passive")) {
2708 pr_info("Passive mode enabled\n");
2709 intel_pstate_driver
= &intel_cpufreq
;
2712 if (!strcmp(str
, "no_hwp")) {
2713 pr_info("HWP disabled\n");
2716 if (!strcmp(str
, "force"))
2718 if (!strcmp(str
, "hwp_only"))
2720 if (!strcmp(str
, "per_cpu_perf_limits"))
2721 per_cpu_limits
= true;
2724 if (!strcmp(str
, "support_acpi_ppc"))
2730 early_param("intel_pstate", intel_pstate_setup
);
2732 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2733 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2734 MODULE_LICENSE("GPL");