2 * intel_pstate.c: Native P state management for Intel processors
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/kernel.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/ktime.h>
19 #include <linux/hrtimer.h>
20 #include <linux/tick.h>
21 #include <linux/slab.h>
22 #include <linux/sched/cpufreq.h>
23 #include <linux/list.h>
24 #include <linux/cpu.h>
25 #include <linux/cpufreq.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
29 #include <linux/debugfs.h>
30 #include <linux/acpi.h>
31 #include <linux/vmalloc.h>
32 #include <trace/events/power.h>
34 #include <asm/div64.h>
36 #include <asm/cpu_device_id.h>
37 #include <asm/cpufeature.h>
38 #include <asm/intel-family.h>
40 #define INTEL_PSTATE_DEFAULT_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
41 #define INTEL_PSTATE_HWP_SAMPLING_INTERVAL (50 * NSEC_PER_MSEC)
43 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
44 #define INTEL_CPUFREQ_TRANSITION_DELAY 500
47 #include <acpi/processor.h>
48 #include <acpi/cppc_acpi.h>
52 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
53 #define fp_toint(X) ((X) >> FRAC_BITS)
56 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
57 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
58 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
60 static inline int32_t mul_fp(int32_t x
, int32_t y
)
62 return ((int64_t)x
* (int64_t)y
) >> FRAC_BITS
;
65 static inline int32_t div_fp(s64 x
, s64 y
)
67 return div64_s64((int64_t)x
<< FRAC_BITS
, y
);
70 static inline int ceiling_fp(int32_t x
)
75 mask
= (1 << FRAC_BITS
) - 1;
81 static inline int32_t percent_fp(int percent
)
83 return div_fp(percent
, 100);
86 static inline u64
mul_ext_fp(u64 x
, u64 y
)
88 return (x
* y
) >> EXT_FRAC_BITS
;
91 static inline u64
div_ext_fp(u64 x
, u64 y
)
93 return div64_u64(x
<< EXT_FRAC_BITS
, y
);
96 static inline int32_t percent_ext_fp(int percent
)
98 return div_ext_fp(percent
, 100);
102 * struct sample - Store performance sample
103 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
104 * performance during last sample period
105 * @busy_scaled: Scaled busy value which is used to calculate next
106 * P state. This can be different than core_avg_perf
107 * to account for cpu idle period
108 * @aperf: Difference of actual performance frequency clock count
109 * read from APERF MSR between last and current sample
110 * @mperf: Difference of maximum performance frequency clock count
111 * read from MPERF MSR between last and current sample
112 * @tsc: Difference of time stamp counter between last and
114 * @time: Current time from scheduler
116 * This structure is used in the cpudata structure to store performance sample
117 * data for choosing next P State.
120 int32_t core_avg_perf
;
129 * struct pstate_data - Store P state data
130 * @current_pstate: Current requested P state
131 * @min_pstate: Min P state possible for this platform
132 * @max_pstate: Max P state possible for this platform
133 * @max_pstate_physical:This is physical Max P state for a processor
134 * This can be higher than the max_pstate which can
135 * be limited by platform thermal design power limits
136 * @scaling: Scaling factor to convert frequency to cpufreq
138 * @turbo_pstate: Max Turbo P state possible for this platform
139 * @max_freq: @max_pstate frequency in cpufreq units
140 * @turbo_freq: @turbo_pstate frequency in cpufreq units
142 * Stores the per cpu model P state limits and current P state.
148 int max_pstate_physical
;
151 unsigned int max_freq
;
152 unsigned int turbo_freq
;
156 * struct vid_data - Stores voltage information data
157 * @min: VID data for this platform corresponding to
159 * @max: VID data corresponding to the highest P State.
160 * @turbo: VID data for turbo P state
161 * @ratio: Ratio of (vid max - vid min) /
162 * (max P state - Min P State)
164 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
165 * This data is used in Atom platforms, where in addition to target P state,
166 * the voltage data needs to be specified to select next P State.
176 * struct _pid - Stores PID data
177 * @setpoint: Target set point for busyness or performance
178 * @integral: Storage for accumulated error values
179 * @p_gain: PID proportional gain
180 * @i_gain: PID integral gain
181 * @d_gain: PID derivative gain
182 * @deadband: PID deadband
183 * @last_err: Last error storage for integral part of PID calculation
185 * Stores PID coefficients and last error for PID controller.
198 * struct global_params - Global parameters, mostly tunable via sysfs.
199 * @no_turbo: Whether or not to use turbo P-states.
200 * @turbo_disabled: Whethet or not turbo P-states are available at all,
201 * based on the MSR_IA32_MISC_ENABLE value and whether or
202 * not the maximum reported turbo P-state is different from
203 * the maximum reported non-turbo one.
204 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
206 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
209 struct global_params
{
217 * struct cpudata - Per CPU instance data storage
218 * @cpu: CPU number for this instance data
219 * @policy: CPUFreq policy value
220 * @update_util: CPUFreq utility callback information
221 * @update_util_set: CPUFreq utility callback is set
222 * @iowait_boost: iowait-related boost fraction
223 * @last_update: Time of the last update.
224 * @pstate: Stores P state limits for this CPU
225 * @vid: Stores VID limits for this CPU
226 * @pid: Stores PID parameters for this CPU
227 * @last_sample_time: Last Sample time
228 * @aperf_mperf_shift: Number of clock cycles after aperf, merf is incremented
229 * This shift is a multiplier to mperf delta to
230 * calculate CPU busy.
231 * @prev_aperf: Last APERF value read from APERF MSR
232 * @prev_mperf: Last MPERF value read from MPERF MSR
233 * @prev_tsc: Last timestamp counter (TSC) value
234 * @prev_cummulative_iowait: IO Wait time difference from last and
236 * @sample: Storage for storing last Sample data
237 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
238 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
239 * @acpi_perf_data: Stores ACPI perf information read from _PSS
240 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
241 * @epp_powersave: Last saved HWP energy performance preference
242 * (EPP) or energy performance bias (EPB),
243 * when policy switched to performance
244 * @epp_policy: Last saved policy used to set EPP/EPB
245 * @epp_default: Power on default HWP energy performance
247 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
250 * This structure stores per CPU instance data for all CPUs.
256 struct update_util_data update_util
;
257 bool update_util_set
;
259 struct pstate_data pstate
;
264 u64 last_sample_time
;
265 u64 aperf_mperf_shift
;
269 u64 prev_cummulative_iowait
;
270 struct sample sample
;
271 int32_t min_perf_ratio
;
272 int32_t max_perf_ratio
;
274 struct acpi_processor_performance acpi_perf_data
;
275 bool valid_pss_table
;
277 unsigned int iowait_boost
;
284 static struct cpudata
**all_cpu_data
;
287 * struct pstate_adjust_policy - Stores static PID configuration data
288 * @sample_rate_ms: PID calculation sample rate in ms
289 * @sample_rate_ns: Sample rate calculation in ns
290 * @deadband: PID deadband
291 * @setpoint: PID Setpoint
292 * @p_gain_pct: PID proportional gain
293 * @i_gain_pct: PID integral gain
294 * @d_gain_pct: PID derivative gain
296 * Stores per CPU model static PID configuration data.
298 struct pstate_adjust_policy
{
309 * struct pstate_funcs - Per CPU model specific callbacks
310 * @get_max: Callback to get maximum non turbo effective P state
311 * @get_max_physical: Callback to get maximum non turbo physical P state
312 * @get_min: Callback to get minimum P state
313 * @get_turbo: Callback to get turbo P state
314 * @get_scaling: Callback to get frequency scaling factor
315 * @get_val: Callback to convert P state to actual MSR write value
316 * @get_vid: Callback to get VID data for Atom platforms
317 * @update_util: Active mode utilization update callback.
319 * Core and Atom CPU models have different way to get P State limits. This
320 * structure is used to store those callbacks.
322 struct pstate_funcs
{
323 int (*get_max
)(void);
324 int (*get_max_physical
)(void);
325 int (*get_min
)(void);
326 int (*get_turbo
)(void);
327 int (*get_scaling
)(void);
328 int (*get_aperf_mperf_shift
)(void);
329 u64 (*get_val
)(struct cpudata
*, int pstate
);
330 void (*get_vid
)(struct cpudata
*);
331 void (*update_util
)(struct update_util_data
*data
, u64 time
,
335 static struct pstate_funcs pstate_funcs __read_mostly
;
336 static struct pstate_adjust_policy pid_params __read_mostly
= {
337 .sample_rate_ms
= 10,
338 .sample_rate_ns
= 10 * NSEC_PER_MSEC
,
346 static int hwp_active __read_mostly
;
347 static bool per_cpu_limits __read_mostly
;
349 static struct cpufreq_driver
*intel_pstate_driver __read_mostly
;
352 static bool acpi_ppc
;
355 static struct global_params global
;
357 static DEFINE_MUTEX(intel_pstate_driver_lock
);
358 static DEFINE_MUTEX(intel_pstate_limits_lock
);
362 static bool intel_pstate_get_ppc_enable_status(void)
364 if (acpi_gbl_FADT
.preferred_profile
== PM_ENTERPRISE_SERVER
||
365 acpi_gbl_FADT
.preferred_profile
== PM_PERFORMANCE_SERVER
)
371 #ifdef CONFIG_ACPI_CPPC_LIB
373 /* The work item is needed to avoid CPU hotplug locking issues */
374 static void intel_pstste_sched_itmt_work_fn(struct work_struct
*work
)
376 sched_set_itmt_support();
379 static DECLARE_WORK(sched_itmt_work
, intel_pstste_sched_itmt_work_fn
);
381 static void intel_pstate_set_itmt_prio(int cpu
)
383 struct cppc_perf_caps cppc_perf
;
384 static u32 max_highest_perf
= 0, min_highest_perf
= U32_MAX
;
387 ret
= cppc_get_perf_caps(cpu
, &cppc_perf
);
392 * The priorities can be set regardless of whether or not
393 * sched_set_itmt_support(true) has been called and it is valid to
394 * update them at any time after it has been called.
396 sched_set_itmt_core_prio(cppc_perf
.highest_perf
, cpu
);
398 if (max_highest_perf
<= min_highest_perf
) {
399 if (cppc_perf
.highest_perf
> max_highest_perf
)
400 max_highest_perf
= cppc_perf
.highest_perf
;
402 if (cppc_perf
.highest_perf
< min_highest_perf
)
403 min_highest_perf
= cppc_perf
.highest_perf
;
405 if (max_highest_perf
> min_highest_perf
) {
407 * This code can be run during CPU online under the
408 * CPU hotplug locks, so sched_set_itmt_support()
409 * cannot be called from here. Queue up a work item
412 schedule_work(&sched_itmt_work
);
417 static void intel_pstate_set_itmt_prio(int cpu
)
422 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy
*policy
)
429 intel_pstate_set_itmt_prio(policy
->cpu
);
433 if (!intel_pstate_get_ppc_enable_status())
436 cpu
= all_cpu_data
[policy
->cpu
];
438 ret
= acpi_processor_register_performance(&cpu
->acpi_perf_data
,
444 * Check if the control value in _PSS is for PERF_CTL MSR, which should
445 * guarantee that the states returned by it map to the states in our
448 if (cpu
->acpi_perf_data
.control_register
.space_id
!=
449 ACPI_ADR_SPACE_FIXED_HARDWARE
)
453 * If there is only one entry _PSS, simply ignore _PSS and continue as
454 * usual without taking _PSS into account
456 if (cpu
->acpi_perf_data
.state_count
< 2)
459 pr_debug("CPU%u - ACPI _PSS perf data\n", policy
->cpu
);
460 for (i
= 0; i
< cpu
->acpi_perf_data
.state_count
; i
++) {
461 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
462 (i
== cpu
->acpi_perf_data
.state
? '*' : ' '), i
,
463 (u32
) cpu
->acpi_perf_data
.states
[i
].core_frequency
,
464 (u32
) cpu
->acpi_perf_data
.states
[i
].power
,
465 (u32
) cpu
->acpi_perf_data
.states
[i
].control
);
469 * The _PSS table doesn't contain whole turbo frequency range.
470 * This just contains +1 MHZ above the max non turbo frequency,
471 * with control value corresponding to max turbo ratio. But
472 * when cpufreq set policy is called, it will call with this
473 * max frequency, which will cause a reduced performance as
474 * this driver uses real max turbo frequency as the max
475 * frequency. So correct this frequency in _PSS table to
476 * correct max turbo frequency based on the turbo state.
477 * Also need to convert to MHz as _PSS freq is in MHz.
479 if (!global
.turbo_disabled
)
480 cpu
->acpi_perf_data
.states
[0].core_frequency
=
481 policy
->cpuinfo
.max_freq
/ 1000;
482 cpu
->valid_pss_table
= true;
483 pr_debug("_PPC limits will be enforced\n");
488 cpu
->valid_pss_table
= false;
489 acpi_processor_unregister_performance(policy
->cpu
);
492 static void intel_pstate_exit_perf_limits(struct cpufreq_policy
*policy
)
496 cpu
= all_cpu_data
[policy
->cpu
];
497 if (!cpu
->valid_pss_table
)
500 acpi_processor_unregister_performance(policy
->cpu
);
503 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy
*policy
)
507 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy
*policy
)
512 static signed int pid_calc(struct _pid
*pid
, int32_t busy
)
515 int32_t pterm
, dterm
, fp_error
;
516 int32_t integral_limit
;
518 fp_error
= pid
->setpoint
- busy
;
520 if (abs(fp_error
) <= pid
->deadband
)
523 pterm
= mul_fp(pid
->p_gain
, fp_error
);
525 pid
->integral
+= fp_error
;
528 * We limit the integral here so that it will never
529 * get higher than 30. This prevents it from becoming
530 * too large an input over long periods of time and allows
531 * it to get factored out sooner.
533 * The value of 30 was chosen through experimentation.
535 integral_limit
= int_tofp(30);
536 if (pid
->integral
> integral_limit
)
537 pid
->integral
= integral_limit
;
538 if (pid
->integral
< -integral_limit
)
539 pid
->integral
= -integral_limit
;
541 dterm
= mul_fp(pid
->d_gain
, fp_error
- pid
->last_err
);
542 pid
->last_err
= fp_error
;
544 result
= pterm
+ mul_fp(pid
->integral
, pid
->i_gain
) + dterm
;
545 result
= result
+ (1 << (FRAC_BITS
-1));
546 return (signed int)fp_toint(result
);
549 static inline void intel_pstate_pid_reset(struct cpudata
*cpu
)
551 struct _pid
*pid
= &cpu
->pid
;
553 pid
->p_gain
= percent_fp(pid_params
.p_gain_pct
);
554 pid
->d_gain
= percent_fp(pid_params
.d_gain_pct
);
555 pid
->i_gain
= percent_fp(pid_params
.i_gain_pct
);
556 pid
->setpoint
= int_tofp(pid_params
.setpoint
);
557 pid
->last_err
= pid
->setpoint
- int_tofp(100);
558 pid
->deadband
= int_tofp(pid_params
.deadband
);
562 static inline void update_turbo_state(void)
567 cpu
= all_cpu_data
[0];
568 rdmsrl(MSR_IA32_MISC_ENABLE
, misc_en
);
569 global
.turbo_disabled
=
570 (misc_en
& MSR_IA32_MISC_ENABLE_TURBO_DISABLE
||
571 cpu
->pstate
.max_pstate
== cpu
->pstate
.turbo_pstate
);
574 static int min_perf_pct_min(void)
576 struct cpudata
*cpu
= all_cpu_data
[0];
577 int turbo_pstate
= cpu
->pstate
.turbo_pstate
;
579 return turbo_pstate
?
580 (cpu
->pstate
.min_pstate
* 100 / turbo_pstate
) : 0;
583 static s16
intel_pstate_get_epb(struct cpudata
*cpu_data
)
588 if (!static_cpu_has(X86_FEATURE_EPB
))
591 ret
= rdmsrl_on_cpu(cpu_data
->cpu
, MSR_IA32_ENERGY_PERF_BIAS
, &epb
);
595 return (s16
)(epb
& 0x0f);
598 static s16
intel_pstate_get_epp(struct cpudata
*cpu_data
, u64 hwp_req_data
)
602 if (static_cpu_has(X86_FEATURE_HWP_EPP
)) {
604 * When hwp_req_data is 0, means that caller didn't read
605 * MSR_HWP_REQUEST, so need to read and get EPP.
608 epp
= rdmsrl_on_cpu(cpu_data
->cpu
, MSR_HWP_REQUEST
,
613 epp
= (hwp_req_data
>> 24) & 0xff;
615 /* When there is no EPP present, HWP uses EPB settings */
616 epp
= intel_pstate_get_epb(cpu_data
);
622 static int intel_pstate_set_epb(int cpu
, s16 pref
)
627 if (!static_cpu_has(X86_FEATURE_EPB
))
630 ret
= rdmsrl_on_cpu(cpu
, MSR_IA32_ENERGY_PERF_BIAS
, &epb
);
634 epb
= (epb
& ~0x0f) | pref
;
635 wrmsrl_on_cpu(cpu
, MSR_IA32_ENERGY_PERF_BIAS
, epb
);
641 * EPP/EPB display strings corresponding to EPP index in the
642 * energy_perf_strings[]
644 *-------------------------------------
647 * 2 balance_performance
651 static const char * const energy_perf_strings
[] = {
654 "balance_performance",
659 static const unsigned int epp_values
[] = {
661 HWP_EPP_BALANCE_PERFORMANCE
,
662 HWP_EPP_BALANCE_POWERSAVE
,
666 static int intel_pstate_get_energy_pref_index(struct cpudata
*cpu_data
)
671 epp
= intel_pstate_get_epp(cpu_data
, 0);
675 if (static_cpu_has(X86_FEATURE_HWP_EPP
)) {
676 if (epp
== HWP_EPP_PERFORMANCE
)
678 if (epp
<= HWP_EPP_BALANCE_PERFORMANCE
)
680 if (epp
<= HWP_EPP_BALANCE_POWERSAVE
)
684 } else if (static_cpu_has(X86_FEATURE_EPB
)) {
687 * 0x00-0x03 : Performance
688 * 0x04-0x07 : Balance performance
689 * 0x08-0x0B : Balance power
691 * The EPB is a 4 bit value, but our ranges restrict the
692 * value which can be set. Here only using top two bits
695 index
= (epp
>> 2) + 1;
701 static int intel_pstate_set_energy_pref_index(struct cpudata
*cpu_data
,
708 epp
= cpu_data
->epp_default
;
710 mutex_lock(&intel_pstate_limits_lock
);
712 if (static_cpu_has(X86_FEATURE_HWP_EPP
)) {
715 ret
= rdmsrl_on_cpu(cpu_data
->cpu
, MSR_HWP_REQUEST
, &value
);
719 value
&= ~GENMASK_ULL(31, 24);
722 epp
= epp_values
[pref_index
- 1];
724 value
|= (u64
)epp
<< 24;
725 ret
= wrmsrl_on_cpu(cpu_data
->cpu
, MSR_HWP_REQUEST
, value
);
728 epp
= (pref_index
- 1) << 2;
729 ret
= intel_pstate_set_epb(cpu_data
->cpu
, epp
);
732 mutex_unlock(&intel_pstate_limits_lock
);
737 static ssize_t
show_energy_performance_available_preferences(
738 struct cpufreq_policy
*policy
, char *buf
)
743 while (energy_perf_strings
[i
] != NULL
)
744 ret
+= sprintf(&buf
[ret
], "%s ", energy_perf_strings
[i
++]);
746 ret
+= sprintf(&buf
[ret
], "\n");
751 cpufreq_freq_attr_ro(energy_performance_available_preferences
);
753 static ssize_t
store_energy_performance_preference(
754 struct cpufreq_policy
*policy
, const char *buf
, size_t count
)
756 struct cpudata
*cpu_data
= all_cpu_data
[policy
->cpu
];
757 char str_preference
[21];
760 ret
= sscanf(buf
, "%20s", str_preference
);
764 while (energy_perf_strings
[i
] != NULL
) {
765 if (!strcmp(str_preference
, energy_perf_strings
[i
])) {
766 intel_pstate_set_energy_pref_index(cpu_data
, i
);
775 static ssize_t
show_energy_performance_preference(
776 struct cpufreq_policy
*policy
, char *buf
)
778 struct cpudata
*cpu_data
= all_cpu_data
[policy
->cpu
];
781 preference
= intel_pstate_get_energy_pref_index(cpu_data
);
785 return sprintf(buf
, "%s\n", energy_perf_strings
[preference
]);
788 cpufreq_freq_attr_rw(energy_performance_preference
);
790 static struct freq_attr
*hwp_cpufreq_attrs
[] = {
791 &energy_performance_preference
,
792 &energy_performance_available_preferences
,
796 static void intel_pstate_get_hwp_max(unsigned int cpu
, int *phy_max
,
801 rdmsrl_on_cpu(cpu
, MSR_HWP_CAPABILITIES
, &cap
);
803 *current_max
= HWP_GUARANTEED_PERF(cap
);
805 *current_max
= HWP_HIGHEST_PERF(cap
);
807 *phy_max
= HWP_HIGHEST_PERF(cap
);
810 static void intel_pstate_hwp_set(unsigned int cpu
)
812 struct cpudata
*cpu_data
= all_cpu_data
[cpu
];
817 max
= cpu_data
->max_perf_ratio
;
818 min
= cpu_data
->min_perf_ratio
;
820 if (cpu_data
->policy
== CPUFREQ_POLICY_PERFORMANCE
)
823 rdmsrl_on_cpu(cpu
, MSR_HWP_REQUEST
, &value
);
825 value
&= ~HWP_MIN_PERF(~0L);
826 value
|= HWP_MIN_PERF(min
);
828 value
&= ~HWP_MAX_PERF(~0L);
829 value
|= HWP_MAX_PERF(max
);
831 if (cpu_data
->epp_policy
== cpu_data
->policy
)
834 cpu_data
->epp_policy
= cpu_data
->policy
;
836 if (cpu_data
->epp_saved
>= 0) {
837 epp
= cpu_data
->epp_saved
;
838 cpu_data
->epp_saved
= -EINVAL
;
842 if (cpu_data
->policy
== CPUFREQ_POLICY_PERFORMANCE
) {
843 epp
= intel_pstate_get_epp(cpu_data
, value
);
844 cpu_data
->epp_powersave
= epp
;
845 /* If EPP read was failed, then don't try to write */
851 /* skip setting EPP, when saved value is invalid */
852 if (cpu_data
->epp_powersave
< 0)
856 * No need to restore EPP when it is not zero. This
858 * - Policy is not changed
859 * - user has manually changed
860 * - Error reading EPB
862 epp
= intel_pstate_get_epp(cpu_data
, value
);
866 epp
= cpu_data
->epp_powersave
;
869 if (static_cpu_has(X86_FEATURE_HWP_EPP
)) {
870 value
&= ~GENMASK_ULL(31, 24);
871 value
|= (u64
)epp
<< 24;
873 intel_pstate_set_epb(cpu
, epp
);
876 wrmsrl_on_cpu(cpu
, MSR_HWP_REQUEST
, value
);
879 static int intel_pstate_hwp_save_state(struct cpufreq_policy
*policy
)
881 struct cpudata
*cpu_data
= all_cpu_data
[policy
->cpu
];
886 cpu_data
->epp_saved
= intel_pstate_get_epp(cpu_data
, 0);
891 static int intel_pstate_resume(struct cpufreq_policy
*policy
)
896 mutex_lock(&intel_pstate_limits_lock
);
898 all_cpu_data
[policy
->cpu
]->epp_policy
= 0;
899 intel_pstate_hwp_set(policy
->cpu
);
901 mutex_unlock(&intel_pstate_limits_lock
);
906 static void intel_pstate_update_policies(void)
910 for_each_possible_cpu(cpu
)
911 cpufreq_update_policy(cpu
);
914 /************************** debugfs begin ************************/
915 static int pid_param_set(void *data
, u64 val
)
920 pid_params
.sample_rate_ns
= pid_params
.sample_rate_ms
* NSEC_PER_MSEC
;
921 for_each_possible_cpu(cpu
)
922 if (all_cpu_data
[cpu
])
923 intel_pstate_pid_reset(all_cpu_data
[cpu
]);
928 static int pid_param_get(void *data
, u64
*val
)
933 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param
, pid_param_get
, pid_param_set
, "%llu\n");
935 static struct dentry
*debugfs_parent
;
940 struct dentry
*dentry
;
943 static struct pid_param pid_files
[] = {
944 {"sample_rate_ms", &pid_params
.sample_rate_ms
, },
945 {"d_gain_pct", &pid_params
.d_gain_pct
, },
946 {"i_gain_pct", &pid_params
.i_gain_pct
, },
947 {"deadband", &pid_params
.deadband
, },
948 {"setpoint", &pid_params
.setpoint
, },
949 {"p_gain_pct", &pid_params
.p_gain_pct
, },
953 static void intel_pstate_debug_expose_params(void)
957 debugfs_parent
= debugfs_create_dir("pstate_snb", NULL
);
958 if (IS_ERR_OR_NULL(debugfs_parent
))
961 for (i
= 0; pid_files
[i
].name
; i
++) {
962 struct dentry
*dentry
;
964 dentry
= debugfs_create_file(pid_files
[i
].name
, 0660,
965 debugfs_parent
, pid_files
[i
].value
,
968 pid_files
[i
].dentry
= dentry
;
972 static void intel_pstate_debug_hide_params(void)
976 if (IS_ERR_OR_NULL(debugfs_parent
))
979 for (i
= 0; pid_files
[i
].name
; i
++) {
980 debugfs_remove(pid_files
[i
].dentry
);
981 pid_files
[i
].dentry
= NULL
;
984 debugfs_remove(debugfs_parent
);
985 debugfs_parent
= NULL
;
988 /************************** debugfs end ************************/
990 /************************** sysfs begin ************************/
991 #define show_one(file_name, object) \
992 static ssize_t show_##file_name \
993 (struct kobject *kobj, struct attribute *attr, char *buf) \
995 return sprintf(buf, "%u\n", global.object); \
998 static ssize_t
intel_pstate_show_status(char *buf
);
999 static int intel_pstate_update_status(const char *buf
, size_t size
);
1001 static ssize_t
show_status(struct kobject
*kobj
,
1002 struct attribute
*attr
, char *buf
)
1006 mutex_lock(&intel_pstate_driver_lock
);
1007 ret
= intel_pstate_show_status(buf
);
1008 mutex_unlock(&intel_pstate_driver_lock
);
1013 static ssize_t
store_status(struct kobject
*a
, struct attribute
*b
,
1014 const char *buf
, size_t count
)
1016 char *p
= memchr(buf
, '\n', count
);
1019 mutex_lock(&intel_pstate_driver_lock
);
1020 ret
= intel_pstate_update_status(buf
, p
? p
- buf
: count
);
1021 mutex_unlock(&intel_pstate_driver_lock
);
1023 return ret
< 0 ? ret
: count
;
1026 static ssize_t
show_turbo_pct(struct kobject
*kobj
,
1027 struct attribute
*attr
, char *buf
)
1029 struct cpudata
*cpu
;
1030 int total
, no_turbo
, turbo_pct
;
1033 mutex_lock(&intel_pstate_driver_lock
);
1035 if (!intel_pstate_driver
) {
1036 mutex_unlock(&intel_pstate_driver_lock
);
1040 cpu
= all_cpu_data
[0];
1042 total
= cpu
->pstate
.turbo_pstate
- cpu
->pstate
.min_pstate
+ 1;
1043 no_turbo
= cpu
->pstate
.max_pstate
- cpu
->pstate
.min_pstate
+ 1;
1044 turbo_fp
= div_fp(no_turbo
, total
);
1045 turbo_pct
= 100 - fp_toint(mul_fp(turbo_fp
, int_tofp(100)));
1047 mutex_unlock(&intel_pstate_driver_lock
);
1049 return sprintf(buf
, "%u\n", turbo_pct
);
1052 static ssize_t
show_num_pstates(struct kobject
*kobj
,
1053 struct attribute
*attr
, char *buf
)
1055 struct cpudata
*cpu
;
1058 mutex_lock(&intel_pstate_driver_lock
);
1060 if (!intel_pstate_driver
) {
1061 mutex_unlock(&intel_pstate_driver_lock
);
1065 cpu
= all_cpu_data
[0];
1066 total
= cpu
->pstate
.turbo_pstate
- cpu
->pstate
.min_pstate
+ 1;
1068 mutex_unlock(&intel_pstate_driver_lock
);
1070 return sprintf(buf
, "%u\n", total
);
1073 static ssize_t
show_no_turbo(struct kobject
*kobj
,
1074 struct attribute
*attr
, char *buf
)
1078 mutex_lock(&intel_pstate_driver_lock
);
1080 if (!intel_pstate_driver
) {
1081 mutex_unlock(&intel_pstate_driver_lock
);
1085 update_turbo_state();
1086 if (global
.turbo_disabled
)
1087 ret
= sprintf(buf
, "%u\n", global
.turbo_disabled
);
1089 ret
= sprintf(buf
, "%u\n", global
.no_turbo
);
1091 mutex_unlock(&intel_pstate_driver_lock
);
1096 static ssize_t
store_no_turbo(struct kobject
*a
, struct attribute
*b
,
1097 const char *buf
, size_t count
)
1102 ret
= sscanf(buf
, "%u", &input
);
1106 mutex_lock(&intel_pstate_driver_lock
);
1108 if (!intel_pstate_driver
) {
1109 mutex_unlock(&intel_pstate_driver_lock
);
1113 mutex_lock(&intel_pstate_limits_lock
);
1115 update_turbo_state();
1116 if (global
.turbo_disabled
) {
1117 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1118 mutex_unlock(&intel_pstate_limits_lock
);
1119 mutex_unlock(&intel_pstate_driver_lock
);
1123 global
.no_turbo
= clamp_t(int, input
, 0, 1);
1125 if (global
.no_turbo
) {
1126 struct cpudata
*cpu
= all_cpu_data
[0];
1127 int pct
= cpu
->pstate
.max_pstate
* 100 / cpu
->pstate
.turbo_pstate
;
1129 /* Squash the global minimum into the permitted range. */
1130 if (global
.min_perf_pct
> pct
)
1131 global
.min_perf_pct
= pct
;
1134 mutex_unlock(&intel_pstate_limits_lock
);
1136 intel_pstate_update_policies();
1138 mutex_unlock(&intel_pstate_driver_lock
);
1143 static ssize_t
store_max_perf_pct(struct kobject
*a
, struct attribute
*b
,
1144 const char *buf
, size_t count
)
1149 ret
= sscanf(buf
, "%u", &input
);
1153 mutex_lock(&intel_pstate_driver_lock
);
1155 if (!intel_pstate_driver
) {
1156 mutex_unlock(&intel_pstate_driver_lock
);
1160 mutex_lock(&intel_pstate_limits_lock
);
1162 global
.max_perf_pct
= clamp_t(int, input
, global
.min_perf_pct
, 100);
1164 mutex_unlock(&intel_pstate_limits_lock
);
1166 intel_pstate_update_policies();
1168 mutex_unlock(&intel_pstate_driver_lock
);
1173 static ssize_t
store_min_perf_pct(struct kobject
*a
, struct attribute
*b
,
1174 const char *buf
, size_t count
)
1179 ret
= sscanf(buf
, "%u", &input
);
1183 mutex_lock(&intel_pstate_driver_lock
);
1185 if (!intel_pstate_driver
) {
1186 mutex_unlock(&intel_pstate_driver_lock
);
1190 mutex_lock(&intel_pstate_limits_lock
);
1192 global
.min_perf_pct
= clamp_t(int, input
,
1193 min_perf_pct_min(), global
.max_perf_pct
);
1195 mutex_unlock(&intel_pstate_limits_lock
);
1197 intel_pstate_update_policies();
1199 mutex_unlock(&intel_pstate_driver_lock
);
1204 show_one(max_perf_pct
, max_perf_pct
);
1205 show_one(min_perf_pct
, min_perf_pct
);
1207 define_one_global_rw(status
);
1208 define_one_global_rw(no_turbo
);
1209 define_one_global_rw(max_perf_pct
);
1210 define_one_global_rw(min_perf_pct
);
1211 define_one_global_ro(turbo_pct
);
1212 define_one_global_ro(num_pstates
);
1214 static struct attribute
*intel_pstate_attributes
[] = {
1222 static const struct attribute_group intel_pstate_attr_group
= {
1223 .attrs
= intel_pstate_attributes
,
1226 static void __init
intel_pstate_sysfs_expose_params(void)
1228 struct kobject
*intel_pstate_kobject
;
1231 intel_pstate_kobject
= kobject_create_and_add("intel_pstate",
1232 &cpu_subsys
.dev_root
->kobj
);
1233 if (WARN_ON(!intel_pstate_kobject
))
1236 rc
= sysfs_create_group(intel_pstate_kobject
, &intel_pstate_attr_group
);
1241 * If per cpu limits are enforced there are no global limits, so
1242 * return without creating max/min_perf_pct attributes
1247 rc
= sysfs_create_file(intel_pstate_kobject
, &max_perf_pct
.attr
);
1250 rc
= sysfs_create_file(intel_pstate_kobject
, &min_perf_pct
.attr
);
1254 /************************** sysfs end ************************/
1256 static void intel_pstate_hwp_enable(struct cpudata
*cpudata
)
1258 /* First disable HWP notification interrupt as we don't process them */
1259 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY
))
1260 wrmsrl_on_cpu(cpudata
->cpu
, MSR_HWP_INTERRUPT
, 0x00);
1262 wrmsrl_on_cpu(cpudata
->cpu
, MSR_PM_ENABLE
, 0x1);
1263 cpudata
->epp_policy
= 0;
1264 if (cpudata
->epp_default
== -EINVAL
)
1265 cpudata
->epp_default
= intel_pstate_get_epp(cpudata
, 0);
1268 #define MSR_IA32_POWER_CTL_BIT_EE 19
1270 /* Disable energy efficiency optimization */
1271 static void intel_pstate_disable_ee(int cpu
)
1276 ret
= rdmsrl_on_cpu(cpu
, MSR_IA32_POWER_CTL
, &power_ctl
);
1280 if (!(power_ctl
& BIT(MSR_IA32_POWER_CTL_BIT_EE
))) {
1281 pr_info("Disabling energy efficiency optimization\n");
1282 power_ctl
|= BIT(MSR_IA32_POWER_CTL_BIT_EE
);
1283 wrmsrl_on_cpu(cpu
, MSR_IA32_POWER_CTL
, power_ctl
);
1287 static int atom_get_min_pstate(void)
1291 rdmsrl(MSR_ATOM_CORE_RATIOS
, value
);
1292 return (value
>> 8) & 0x7F;
1295 static int atom_get_max_pstate(void)
1299 rdmsrl(MSR_ATOM_CORE_RATIOS
, value
);
1300 return (value
>> 16) & 0x7F;
1303 static int atom_get_turbo_pstate(void)
1307 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS
, value
);
1308 return value
& 0x7F;
1311 static u64
atom_get_val(struct cpudata
*cpudata
, int pstate
)
1317 val
= (u64
)pstate
<< 8;
1318 if (global
.no_turbo
&& !global
.turbo_disabled
)
1319 val
|= (u64
)1 << 32;
1321 vid_fp
= cpudata
->vid
.min
+ mul_fp(
1322 int_tofp(pstate
- cpudata
->pstate
.min_pstate
),
1323 cpudata
->vid
.ratio
);
1325 vid_fp
= clamp_t(int32_t, vid_fp
, cpudata
->vid
.min
, cpudata
->vid
.max
);
1326 vid
= ceiling_fp(vid_fp
);
1328 if (pstate
> cpudata
->pstate
.max_pstate
)
1329 vid
= cpudata
->vid
.turbo
;
1334 static int silvermont_get_scaling(void)
1338 /* Defined in Table 35-6 from SDM (Sept 2015) */
1339 static int silvermont_freq_table
[] = {
1340 83300, 100000, 133300, 116700, 80000};
1342 rdmsrl(MSR_FSB_FREQ
, value
);
1346 return silvermont_freq_table
[i
];
1349 static int airmont_get_scaling(void)
1353 /* Defined in Table 35-10 from SDM (Sept 2015) */
1354 static int airmont_freq_table
[] = {
1355 83300, 100000, 133300, 116700, 80000,
1356 93300, 90000, 88900, 87500};
1358 rdmsrl(MSR_FSB_FREQ
, value
);
1362 return airmont_freq_table
[i
];
1365 static void atom_get_vid(struct cpudata
*cpudata
)
1369 rdmsrl(MSR_ATOM_CORE_VIDS
, value
);
1370 cpudata
->vid
.min
= int_tofp((value
>> 8) & 0x7f);
1371 cpudata
->vid
.max
= int_tofp((value
>> 16) & 0x7f);
1372 cpudata
->vid
.ratio
= div_fp(
1373 cpudata
->vid
.max
- cpudata
->vid
.min
,
1374 int_tofp(cpudata
->pstate
.max_pstate
-
1375 cpudata
->pstate
.min_pstate
));
1377 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS
, value
);
1378 cpudata
->vid
.turbo
= value
& 0x7f;
1381 static int core_get_min_pstate(void)
1385 rdmsrl(MSR_PLATFORM_INFO
, value
);
1386 return (value
>> 40) & 0xFF;
1389 static int core_get_max_pstate_physical(void)
1393 rdmsrl(MSR_PLATFORM_INFO
, value
);
1394 return (value
>> 8) & 0xFF;
1397 static int core_get_tdp_ratio(u64 plat_info
)
1399 /* Check how many TDP levels present */
1400 if (plat_info
& 0x600000000) {
1406 /* Get the TDP level (0, 1, 2) to get ratios */
1407 err
= rdmsrl_safe(MSR_CONFIG_TDP_CONTROL
, &tdp_ctrl
);
1411 /* TDP MSR are continuous starting at 0x648 */
1412 tdp_msr
= MSR_CONFIG_TDP_NOMINAL
+ (tdp_ctrl
& 0x03);
1413 err
= rdmsrl_safe(tdp_msr
, &tdp_ratio
);
1417 /* For level 1 and 2, bits[23:16] contain the ratio */
1418 if (tdp_ctrl
& 0x03)
1421 tdp_ratio
&= 0xff; /* ratios are only 8 bits long */
1422 pr_debug("tdp_ratio %x\n", (int)tdp_ratio
);
1424 return (int)tdp_ratio
;
1430 static int core_get_max_pstate(void)
1438 rdmsrl(MSR_PLATFORM_INFO
, plat_info
);
1439 max_pstate
= (plat_info
>> 8) & 0xFF;
1441 tdp_ratio
= core_get_tdp_ratio(plat_info
);
1446 /* Turbo activation ratio is not used on HWP platforms */
1450 err
= rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO
, &tar
);
1454 /* Do some sanity checking for safety */
1455 tar_levels
= tar
& 0xff;
1456 if (tdp_ratio
- 1 == tar_levels
) {
1457 max_pstate
= tar_levels
;
1458 pr_debug("max_pstate=TAC %x\n", max_pstate
);
1465 static int core_get_turbo_pstate(void)
1470 rdmsrl(MSR_TURBO_RATIO_LIMIT
, value
);
1471 nont
= core_get_max_pstate();
1472 ret
= (value
) & 255;
1478 static inline int core_get_scaling(void)
1483 static u64
core_get_val(struct cpudata
*cpudata
, int pstate
)
1487 val
= (u64
)pstate
<< 8;
1488 if (global
.no_turbo
&& !global
.turbo_disabled
)
1489 val
|= (u64
)1 << 32;
1494 static int knl_get_aperf_mperf_shift(void)
1499 static int knl_get_turbo_pstate(void)
1504 rdmsrl(MSR_TURBO_RATIO_LIMIT
, value
);
1505 nont
= core_get_max_pstate();
1506 ret
= (((value
) >> 8) & 0xFF);
1512 static int intel_pstate_get_base_pstate(struct cpudata
*cpu
)
1514 return global
.no_turbo
|| global
.turbo_disabled
?
1515 cpu
->pstate
.max_pstate
: cpu
->pstate
.turbo_pstate
;
1518 static void intel_pstate_set_pstate(struct cpudata
*cpu
, int pstate
)
1520 trace_cpu_frequency(pstate
* cpu
->pstate
.scaling
, cpu
->cpu
);
1521 cpu
->pstate
.current_pstate
= pstate
;
1523 * Generally, there is no guarantee that this code will always run on
1524 * the CPU being updated, so force the register update to run on the
1527 wrmsrl_on_cpu(cpu
->cpu
, MSR_IA32_PERF_CTL
,
1528 pstate_funcs
.get_val(cpu
, pstate
));
1531 static void intel_pstate_set_min_pstate(struct cpudata
*cpu
)
1533 intel_pstate_set_pstate(cpu
, cpu
->pstate
.min_pstate
);
1536 static void intel_pstate_max_within_limits(struct cpudata
*cpu
)
1540 update_turbo_state();
1541 pstate
= intel_pstate_get_base_pstate(cpu
);
1542 pstate
= max(cpu
->pstate
.min_pstate
, cpu
->max_perf_ratio
);
1543 intel_pstate_set_pstate(cpu
, pstate
);
1546 static void intel_pstate_get_cpu_pstates(struct cpudata
*cpu
)
1548 cpu
->pstate
.min_pstate
= pstate_funcs
.get_min();
1549 cpu
->pstate
.max_pstate
= pstate_funcs
.get_max();
1550 cpu
->pstate
.max_pstate_physical
= pstate_funcs
.get_max_physical();
1551 cpu
->pstate
.turbo_pstate
= pstate_funcs
.get_turbo();
1552 cpu
->pstate
.scaling
= pstate_funcs
.get_scaling();
1553 cpu
->pstate
.max_freq
= cpu
->pstate
.max_pstate
* cpu
->pstate
.scaling
;
1554 cpu
->pstate
.turbo_freq
= cpu
->pstate
.turbo_pstate
* cpu
->pstate
.scaling
;
1556 if (pstate_funcs
.get_aperf_mperf_shift
)
1557 cpu
->aperf_mperf_shift
= pstate_funcs
.get_aperf_mperf_shift();
1559 if (pstate_funcs
.get_vid
)
1560 pstate_funcs
.get_vid(cpu
);
1562 intel_pstate_set_min_pstate(cpu
);
1565 static inline void intel_pstate_calc_avg_perf(struct cpudata
*cpu
)
1567 struct sample
*sample
= &cpu
->sample
;
1569 sample
->core_avg_perf
= div_ext_fp(sample
->aperf
, sample
->mperf
);
1572 static inline bool intel_pstate_sample(struct cpudata
*cpu
, u64 time
)
1575 unsigned long flags
;
1578 local_irq_save(flags
);
1579 rdmsrl(MSR_IA32_APERF
, aperf
);
1580 rdmsrl(MSR_IA32_MPERF
, mperf
);
1582 if (cpu
->prev_mperf
== mperf
|| cpu
->prev_tsc
== tsc
) {
1583 local_irq_restore(flags
);
1586 local_irq_restore(flags
);
1588 cpu
->last_sample_time
= cpu
->sample
.time
;
1589 cpu
->sample
.time
= time
;
1590 cpu
->sample
.aperf
= aperf
;
1591 cpu
->sample
.mperf
= mperf
;
1592 cpu
->sample
.tsc
= tsc
;
1593 cpu
->sample
.aperf
-= cpu
->prev_aperf
;
1594 cpu
->sample
.mperf
-= cpu
->prev_mperf
;
1595 cpu
->sample
.tsc
-= cpu
->prev_tsc
;
1597 cpu
->prev_aperf
= aperf
;
1598 cpu
->prev_mperf
= mperf
;
1599 cpu
->prev_tsc
= tsc
;
1601 * First time this function is invoked in a given cycle, all of the
1602 * previous sample data fields are equal to zero or stale and they must
1603 * be populated with meaningful numbers for things to work, so assume
1604 * that sample.time will always be reset before setting the utilization
1605 * update hook and make the caller skip the sample then.
1607 if (cpu
->last_sample_time
) {
1608 intel_pstate_calc_avg_perf(cpu
);
1614 static inline int32_t get_avg_frequency(struct cpudata
*cpu
)
1616 return mul_ext_fp(cpu
->sample
.core_avg_perf
,
1617 cpu
->pstate
.max_pstate_physical
* cpu
->pstate
.scaling
);
1620 static inline int32_t get_avg_pstate(struct cpudata
*cpu
)
1622 return mul_ext_fp(cpu
->pstate
.max_pstate_physical
,
1623 cpu
->sample
.core_avg_perf
);
1626 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata
*cpu
)
1628 struct sample
*sample
= &cpu
->sample
;
1629 int32_t busy_frac
, boost
;
1630 int target
, avg_pstate
;
1632 busy_frac
= div_fp(sample
->mperf
<< cpu
->aperf_mperf_shift
,
1635 boost
= cpu
->iowait_boost
;
1636 cpu
->iowait_boost
>>= 1;
1638 if (busy_frac
< boost
)
1641 sample
->busy_scaled
= busy_frac
* 100;
1643 target
= global
.no_turbo
|| global
.turbo_disabled
?
1644 cpu
->pstate
.max_pstate
: cpu
->pstate
.turbo_pstate
;
1645 target
+= target
>> 2;
1646 target
= mul_fp(target
, busy_frac
);
1647 if (target
< cpu
->pstate
.min_pstate
)
1648 target
= cpu
->pstate
.min_pstate
;
1651 * If the average P-state during the previous cycle was higher than the
1652 * current target, add 50% of the difference to the target to reduce
1653 * possible performance oscillations and offset possible performance
1654 * loss related to moving the workload from one CPU to another within
1657 avg_pstate
= get_avg_pstate(cpu
);
1658 if (avg_pstate
> target
)
1659 target
+= (avg_pstate
- target
) >> 1;
1664 static inline int32_t get_target_pstate_use_performance(struct cpudata
*cpu
)
1666 int32_t perf_scaled
, max_pstate
, current_pstate
, sample_ratio
;
1670 * perf_scaled is the ratio of the average P-state during the last
1671 * sampling period to the P-state requested last time (in percent).
1673 * That measures the system's response to the previous P-state
1676 max_pstate
= cpu
->pstate
.max_pstate_physical
;
1677 current_pstate
= cpu
->pstate
.current_pstate
;
1678 perf_scaled
= mul_ext_fp(cpu
->sample
.core_avg_perf
,
1679 div_fp(100 * max_pstate
, current_pstate
));
1682 * Since our utilization update callback will not run unless we are
1683 * in C0, check if the actual elapsed time is significantly greater (3x)
1684 * than our sample interval. If it is, then we were idle for a long
1685 * enough period of time to adjust our performance metric.
1687 duration_ns
= cpu
->sample
.time
- cpu
->last_sample_time
;
1688 if ((s64
)duration_ns
> pid_params
.sample_rate_ns
* 3) {
1689 sample_ratio
= div_fp(pid_params
.sample_rate_ns
, duration_ns
);
1690 perf_scaled
= mul_fp(perf_scaled
, sample_ratio
);
1692 sample_ratio
= div_fp(100 * (cpu
->sample
.mperf
<< cpu
->aperf_mperf_shift
),
1694 if (sample_ratio
< int_tofp(1))
1698 cpu
->sample
.busy_scaled
= perf_scaled
;
1699 return cpu
->pstate
.current_pstate
- pid_calc(&cpu
->pid
, perf_scaled
);
1702 static int intel_pstate_prepare_request(struct cpudata
*cpu
, int pstate
)
1704 int max_pstate
= intel_pstate_get_base_pstate(cpu
);
1707 min_pstate
= max(cpu
->pstate
.min_pstate
, cpu
->min_perf_ratio
);
1708 max_pstate
= max(min_pstate
, cpu
->max_perf_ratio
);
1709 return clamp_t(int, pstate
, min_pstate
, max_pstate
);
1712 static void intel_pstate_update_pstate(struct cpudata
*cpu
, int pstate
)
1714 if (pstate
== cpu
->pstate
.current_pstate
)
1717 cpu
->pstate
.current_pstate
= pstate
;
1718 wrmsrl(MSR_IA32_PERF_CTL
, pstate_funcs
.get_val(cpu
, pstate
));
1721 static void intel_pstate_adjust_pstate(struct cpudata
*cpu
, int target_pstate
)
1723 int from
= cpu
->pstate
.current_pstate
;
1724 struct sample
*sample
;
1726 update_turbo_state();
1728 target_pstate
= intel_pstate_prepare_request(cpu
, target_pstate
);
1729 trace_cpu_frequency(target_pstate
* cpu
->pstate
.scaling
, cpu
->cpu
);
1730 intel_pstate_update_pstate(cpu
, target_pstate
);
1732 sample
= &cpu
->sample
;
1733 trace_pstate_sample(mul_ext_fp(100, sample
->core_avg_perf
),
1734 fp_toint(sample
->busy_scaled
),
1736 cpu
->pstate
.current_pstate
,
1740 get_avg_frequency(cpu
),
1741 fp_toint(cpu
->iowait_boost
* 100));
1744 static void intel_pstate_update_util_pid(struct update_util_data
*data
,
1745 u64 time
, unsigned int flags
)
1747 struct cpudata
*cpu
= container_of(data
, struct cpudata
, update_util
);
1748 u64 delta_ns
= time
- cpu
->sample
.time
;
1750 if ((s64
)delta_ns
< pid_params
.sample_rate_ns
)
1753 if (intel_pstate_sample(cpu
, time
)) {
1756 target_pstate
= get_target_pstate_use_performance(cpu
);
1757 intel_pstate_adjust_pstate(cpu
, target_pstate
);
1761 static void intel_pstate_update_util(struct update_util_data
*data
, u64 time
,
1764 struct cpudata
*cpu
= container_of(data
, struct cpudata
, update_util
);
1767 if (flags
& SCHED_CPUFREQ_IOWAIT
) {
1768 cpu
->iowait_boost
= int_tofp(1);
1769 } else if (cpu
->iowait_boost
) {
1770 /* Clear iowait_boost if the CPU may have been idle. */
1771 delta_ns
= time
- cpu
->last_update
;
1772 if (delta_ns
> TICK_NSEC
)
1773 cpu
->iowait_boost
= 0;
1775 cpu
->last_update
= time
;
1776 delta_ns
= time
- cpu
->sample
.time
;
1777 if ((s64
)delta_ns
< INTEL_PSTATE_DEFAULT_SAMPLING_INTERVAL
)
1780 if (intel_pstate_sample(cpu
, time
)) {
1783 target_pstate
= get_target_pstate_use_cpu_load(cpu
);
1784 intel_pstate_adjust_pstate(cpu
, target_pstate
);
1788 static struct pstate_funcs core_funcs
= {
1789 .get_max
= core_get_max_pstate
,
1790 .get_max_physical
= core_get_max_pstate_physical
,
1791 .get_min
= core_get_min_pstate
,
1792 .get_turbo
= core_get_turbo_pstate
,
1793 .get_scaling
= core_get_scaling
,
1794 .get_val
= core_get_val
,
1795 .update_util
= intel_pstate_update_util_pid
,
1798 static const struct pstate_funcs silvermont_funcs
= {
1799 .get_max
= atom_get_max_pstate
,
1800 .get_max_physical
= atom_get_max_pstate
,
1801 .get_min
= atom_get_min_pstate
,
1802 .get_turbo
= atom_get_turbo_pstate
,
1803 .get_val
= atom_get_val
,
1804 .get_scaling
= silvermont_get_scaling
,
1805 .get_vid
= atom_get_vid
,
1806 .update_util
= intel_pstate_update_util
,
1809 static const struct pstate_funcs airmont_funcs
= {
1810 .get_max
= atom_get_max_pstate
,
1811 .get_max_physical
= atom_get_max_pstate
,
1812 .get_min
= atom_get_min_pstate
,
1813 .get_turbo
= atom_get_turbo_pstate
,
1814 .get_val
= atom_get_val
,
1815 .get_scaling
= airmont_get_scaling
,
1816 .get_vid
= atom_get_vid
,
1817 .update_util
= intel_pstate_update_util
,
1820 static const struct pstate_funcs knl_funcs
= {
1821 .get_max
= core_get_max_pstate
,
1822 .get_max_physical
= core_get_max_pstate_physical
,
1823 .get_min
= core_get_min_pstate
,
1824 .get_turbo
= knl_get_turbo_pstate
,
1825 .get_aperf_mperf_shift
= knl_get_aperf_mperf_shift
,
1826 .get_scaling
= core_get_scaling
,
1827 .get_val
= core_get_val
,
1828 .update_util
= intel_pstate_update_util_pid
,
1831 static const struct pstate_funcs bxt_funcs
= {
1832 .get_max
= core_get_max_pstate
,
1833 .get_max_physical
= core_get_max_pstate_physical
,
1834 .get_min
= core_get_min_pstate
,
1835 .get_turbo
= core_get_turbo_pstate
,
1836 .get_scaling
= core_get_scaling
,
1837 .get_val
= core_get_val
,
1838 .update_util
= intel_pstate_update_util
,
1841 #define ICPU(model, policy) \
1842 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1843 (unsigned long)&policy }
1845 static const struct x86_cpu_id intel_pstate_cpu_ids
[] = {
1846 ICPU(INTEL_FAM6_SANDYBRIDGE
, core_funcs
),
1847 ICPU(INTEL_FAM6_SANDYBRIDGE_X
, core_funcs
),
1848 ICPU(INTEL_FAM6_ATOM_SILVERMONT1
, silvermont_funcs
),
1849 ICPU(INTEL_FAM6_IVYBRIDGE
, core_funcs
),
1850 ICPU(INTEL_FAM6_HASWELL_CORE
, core_funcs
),
1851 ICPU(INTEL_FAM6_BROADWELL_CORE
, core_funcs
),
1852 ICPU(INTEL_FAM6_IVYBRIDGE_X
, core_funcs
),
1853 ICPU(INTEL_FAM6_HASWELL_X
, core_funcs
),
1854 ICPU(INTEL_FAM6_HASWELL_ULT
, core_funcs
),
1855 ICPU(INTEL_FAM6_HASWELL_GT3E
, core_funcs
),
1856 ICPU(INTEL_FAM6_BROADWELL_GT3E
, core_funcs
),
1857 ICPU(INTEL_FAM6_ATOM_AIRMONT
, airmont_funcs
),
1858 ICPU(INTEL_FAM6_SKYLAKE_MOBILE
, core_funcs
),
1859 ICPU(INTEL_FAM6_BROADWELL_X
, core_funcs
),
1860 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP
, core_funcs
),
1861 ICPU(INTEL_FAM6_BROADWELL_XEON_D
, core_funcs
),
1862 ICPU(INTEL_FAM6_XEON_PHI_KNL
, knl_funcs
),
1863 ICPU(INTEL_FAM6_XEON_PHI_KNM
, knl_funcs
),
1864 ICPU(INTEL_FAM6_ATOM_GOLDMONT
, bxt_funcs
),
1865 ICPU(INTEL_FAM6_ATOM_GEMINI_LAKE
, bxt_funcs
),
1868 MODULE_DEVICE_TABLE(x86cpu
, intel_pstate_cpu_ids
);
1870 static const struct x86_cpu_id intel_pstate_cpu_oob_ids
[] __initconst
= {
1871 ICPU(INTEL_FAM6_BROADWELL_XEON_D
, core_funcs
),
1872 ICPU(INTEL_FAM6_BROADWELL_X
, core_funcs
),
1873 ICPU(INTEL_FAM6_SKYLAKE_X
, core_funcs
),
1877 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids
[] = {
1878 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP
, core_funcs
),
1882 static bool pid_in_use(void);
1884 static int intel_pstate_init_cpu(unsigned int cpunum
)
1886 struct cpudata
*cpu
;
1888 cpu
= all_cpu_data
[cpunum
];
1891 cpu
= kzalloc(sizeof(*cpu
), GFP_KERNEL
);
1895 all_cpu_data
[cpunum
] = cpu
;
1897 cpu
->epp_default
= -EINVAL
;
1898 cpu
->epp_powersave
= -EINVAL
;
1899 cpu
->epp_saved
= -EINVAL
;
1902 cpu
= all_cpu_data
[cpunum
];
1907 const struct x86_cpu_id
*id
;
1909 id
= x86_match_cpu(intel_pstate_cpu_ee_disable_ids
);
1911 intel_pstate_disable_ee(cpunum
);
1913 intel_pstate_hwp_enable(cpu
);
1914 } else if (pid_in_use()) {
1915 intel_pstate_pid_reset(cpu
);
1918 intel_pstate_get_cpu_pstates(cpu
);
1920 pr_debug("controlling: cpu %d\n", cpunum
);
1925 static void intel_pstate_set_update_util_hook(unsigned int cpu_num
)
1927 struct cpudata
*cpu
= all_cpu_data
[cpu_num
];
1932 if (cpu
->update_util_set
)
1935 /* Prevent intel_pstate_update_util() from using stale data. */
1936 cpu
->sample
.time
= 0;
1937 cpufreq_add_update_util_hook(cpu_num
, &cpu
->update_util
,
1938 pstate_funcs
.update_util
);
1939 cpu
->update_util_set
= true;
1942 static void intel_pstate_clear_update_util_hook(unsigned int cpu
)
1944 struct cpudata
*cpu_data
= all_cpu_data
[cpu
];
1946 if (!cpu_data
->update_util_set
)
1949 cpufreq_remove_update_util_hook(cpu
);
1950 cpu_data
->update_util_set
= false;
1951 synchronize_sched();
1954 static int intel_pstate_get_max_freq(struct cpudata
*cpu
)
1956 return global
.turbo_disabled
|| global
.no_turbo
?
1957 cpu
->pstate
.max_freq
: cpu
->pstate
.turbo_freq
;
1960 static void intel_pstate_update_perf_limits(struct cpufreq_policy
*policy
,
1961 struct cpudata
*cpu
)
1963 int max_freq
= intel_pstate_get_max_freq(cpu
);
1964 int32_t max_policy_perf
, min_policy_perf
;
1965 int max_state
, turbo_max
;
1968 * HWP needs some special consideration, because on BDX the
1969 * HWP_REQUEST uses abstract value to represent performance
1970 * rather than pure ratios.
1973 intel_pstate_get_hwp_max(cpu
->cpu
, &turbo_max
, &max_state
);
1975 max_state
= intel_pstate_get_base_pstate(cpu
);
1976 turbo_max
= cpu
->pstate
.turbo_pstate
;
1979 max_policy_perf
= max_state
* policy
->max
/ max_freq
;
1980 if (policy
->max
== policy
->min
) {
1981 min_policy_perf
= max_policy_perf
;
1983 min_policy_perf
= max_state
* policy
->min
/ max_freq
;
1984 min_policy_perf
= clamp_t(int32_t, min_policy_perf
,
1985 0, max_policy_perf
);
1988 pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n",
1989 policy
->cpu
, max_state
,
1990 min_policy_perf
, max_policy_perf
);
1992 /* Normalize user input to [min_perf, max_perf] */
1993 if (per_cpu_limits
) {
1994 cpu
->min_perf_ratio
= min_policy_perf
;
1995 cpu
->max_perf_ratio
= max_policy_perf
;
1997 int32_t global_min
, global_max
;
1999 /* Global limits are in percent of the maximum turbo P-state. */
2000 global_max
= DIV_ROUND_UP(turbo_max
* global
.max_perf_pct
, 100);
2001 global_min
= DIV_ROUND_UP(turbo_max
* global
.min_perf_pct
, 100);
2002 global_min
= clamp_t(int32_t, global_min
, 0, global_max
);
2004 pr_debug("cpu:%d global_min:%d global_max:%d\n", policy
->cpu
,
2005 global_min
, global_max
);
2007 cpu
->min_perf_ratio
= max(min_policy_perf
, global_min
);
2008 cpu
->min_perf_ratio
= min(cpu
->min_perf_ratio
, max_policy_perf
);
2009 cpu
->max_perf_ratio
= min(max_policy_perf
, global_max
);
2010 cpu
->max_perf_ratio
= max(min_policy_perf
, cpu
->max_perf_ratio
);
2012 /* Make sure min_perf <= max_perf */
2013 cpu
->min_perf_ratio
= min(cpu
->min_perf_ratio
,
2014 cpu
->max_perf_ratio
);
2017 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", policy
->cpu
,
2018 cpu
->max_perf_ratio
,
2019 cpu
->min_perf_ratio
);
2022 static int intel_pstate_set_policy(struct cpufreq_policy
*policy
)
2024 struct cpudata
*cpu
;
2026 if (!policy
->cpuinfo
.max_freq
)
2029 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2030 policy
->cpuinfo
.max_freq
, policy
->max
);
2032 cpu
= all_cpu_data
[policy
->cpu
];
2033 cpu
->policy
= policy
->policy
;
2035 mutex_lock(&intel_pstate_limits_lock
);
2037 intel_pstate_update_perf_limits(policy
, cpu
);
2039 if (cpu
->policy
== CPUFREQ_POLICY_PERFORMANCE
) {
2041 * NOHZ_FULL CPUs need this as the governor callback may not
2042 * be invoked on them.
2044 intel_pstate_clear_update_util_hook(policy
->cpu
);
2045 intel_pstate_max_within_limits(cpu
);
2047 intel_pstate_set_update_util_hook(policy
->cpu
);
2051 intel_pstate_hwp_set(policy
->cpu
);
2053 mutex_unlock(&intel_pstate_limits_lock
);
2058 static void intel_pstate_adjust_policy_max(struct cpufreq_policy
*policy
,
2059 struct cpudata
*cpu
)
2061 if (cpu
->pstate
.max_pstate_physical
> cpu
->pstate
.max_pstate
&&
2062 policy
->max
< policy
->cpuinfo
.max_freq
&&
2063 policy
->max
> cpu
->pstate
.max_freq
) {
2064 pr_debug("policy->max > max non turbo frequency\n");
2065 policy
->max
= policy
->cpuinfo
.max_freq
;
2069 static int intel_pstate_verify_policy(struct cpufreq_policy
*policy
)
2071 struct cpudata
*cpu
= all_cpu_data
[policy
->cpu
];
2073 update_turbo_state();
2074 cpufreq_verify_within_limits(policy
, policy
->cpuinfo
.min_freq
,
2075 intel_pstate_get_max_freq(cpu
));
2077 if (policy
->policy
!= CPUFREQ_POLICY_POWERSAVE
&&
2078 policy
->policy
!= CPUFREQ_POLICY_PERFORMANCE
)
2081 intel_pstate_adjust_policy_max(policy
, cpu
);
2086 static void intel_cpufreq_stop_cpu(struct cpufreq_policy
*policy
)
2088 intel_pstate_set_min_pstate(all_cpu_data
[policy
->cpu
]);
2091 static void intel_pstate_stop_cpu(struct cpufreq_policy
*policy
)
2093 pr_debug("CPU %d exiting\n", policy
->cpu
);
2095 intel_pstate_clear_update_util_hook(policy
->cpu
);
2097 intel_pstate_hwp_save_state(policy
);
2099 intel_cpufreq_stop_cpu(policy
);
2102 static int intel_pstate_cpu_exit(struct cpufreq_policy
*policy
)
2104 intel_pstate_exit_perf_limits(policy
);
2106 policy
->fast_switch_possible
= false;
2111 static int __intel_pstate_cpu_init(struct cpufreq_policy
*policy
)
2113 struct cpudata
*cpu
;
2116 rc
= intel_pstate_init_cpu(policy
->cpu
);
2120 cpu
= all_cpu_data
[policy
->cpu
];
2122 cpu
->max_perf_ratio
= 0xFF;
2123 cpu
->min_perf_ratio
= 0;
2125 policy
->min
= cpu
->pstate
.min_pstate
* cpu
->pstate
.scaling
;
2126 policy
->max
= cpu
->pstate
.turbo_pstate
* cpu
->pstate
.scaling
;
2128 /* cpuinfo and default policy values */
2129 policy
->cpuinfo
.min_freq
= cpu
->pstate
.min_pstate
* cpu
->pstate
.scaling
;
2130 update_turbo_state();
2131 policy
->cpuinfo
.max_freq
= global
.turbo_disabled
?
2132 cpu
->pstate
.max_pstate
: cpu
->pstate
.turbo_pstate
;
2133 policy
->cpuinfo
.max_freq
*= cpu
->pstate
.scaling
;
2135 intel_pstate_init_acpi_perf_limits(policy
);
2136 cpumask_set_cpu(policy
->cpu
, policy
->cpus
);
2138 policy
->fast_switch_possible
= true;
2143 static int intel_pstate_cpu_init(struct cpufreq_policy
*policy
)
2145 int ret
= __intel_pstate_cpu_init(policy
);
2150 policy
->cpuinfo
.transition_latency
= CPUFREQ_ETERNAL
;
2151 if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE
))
2152 policy
->policy
= CPUFREQ_POLICY_PERFORMANCE
;
2154 policy
->policy
= CPUFREQ_POLICY_POWERSAVE
;
2159 static struct cpufreq_driver intel_pstate
= {
2160 .flags
= CPUFREQ_CONST_LOOPS
,
2161 .verify
= intel_pstate_verify_policy
,
2162 .setpolicy
= intel_pstate_set_policy
,
2163 .suspend
= intel_pstate_hwp_save_state
,
2164 .resume
= intel_pstate_resume
,
2165 .init
= intel_pstate_cpu_init
,
2166 .exit
= intel_pstate_cpu_exit
,
2167 .stop_cpu
= intel_pstate_stop_cpu
,
2168 .name
= "intel_pstate",
2171 static int intel_cpufreq_verify_policy(struct cpufreq_policy
*policy
)
2173 struct cpudata
*cpu
= all_cpu_data
[policy
->cpu
];
2175 update_turbo_state();
2176 cpufreq_verify_within_limits(policy
, policy
->cpuinfo
.min_freq
,
2177 intel_pstate_get_max_freq(cpu
));
2179 intel_pstate_adjust_policy_max(policy
, cpu
);
2181 intel_pstate_update_perf_limits(policy
, cpu
);
2186 static int intel_cpufreq_target(struct cpufreq_policy
*policy
,
2187 unsigned int target_freq
,
2188 unsigned int relation
)
2190 struct cpudata
*cpu
= all_cpu_data
[policy
->cpu
];
2191 struct cpufreq_freqs freqs
;
2194 update_turbo_state();
2196 freqs
.old
= policy
->cur
;
2197 freqs
.new = target_freq
;
2199 cpufreq_freq_transition_begin(policy
, &freqs
);
2201 case CPUFREQ_RELATION_L
:
2202 target_pstate
= DIV_ROUND_UP(freqs
.new, cpu
->pstate
.scaling
);
2204 case CPUFREQ_RELATION_H
:
2205 target_pstate
= freqs
.new / cpu
->pstate
.scaling
;
2208 target_pstate
= DIV_ROUND_CLOSEST(freqs
.new, cpu
->pstate
.scaling
);
2211 target_pstate
= intel_pstate_prepare_request(cpu
, target_pstate
);
2212 if (target_pstate
!= cpu
->pstate
.current_pstate
) {
2213 cpu
->pstate
.current_pstate
= target_pstate
;
2214 wrmsrl_on_cpu(policy
->cpu
, MSR_IA32_PERF_CTL
,
2215 pstate_funcs
.get_val(cpu
, target_pstate
));
2217 freqs
.new = target_pstate
* cpu
->pstate
.scaling
;
2218 cpufreq_freq_transition_end(policy
, &freqs
, false);
2223 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy
*policy
,
2224 unsigned int target_freq
)
2226 struct cpudata
*cpu
= all_cpu_data
[policy
->cpu
];
2229 update_turbo_state();
2231 target_pstate
= DIV_ROUND_UP(target_freq
, cpu
->pstate
.scaling
);
2232 target_pstate
= intel_pstate_prepare_request(cpu
, target_pstate
);
2233 intel_pstate_update_pstate(cpu
, target_pstate
);
2234 return target_pstate
* cpu
->pstate
.scaling
;
2237 static int intel_cpufreq_cpu_init(struct cpufreq_policy
*policy
)
2239 int ret
= __intel_pstate_cpu_init(policy
);
2244 policy
->cpuinfo
.transition_latency
= INTEL_CPUFREQ_TRANSITION_LATENCY
;
2245 policy
->transition_delay_us
= INTEL_CPUFREQ_TRANSITION_DELAY
;
2246 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2247 policy
->cur
= policy
->cpuinfo
.min_freq
;
2252 static struct cpufreq_driver intel_cpufreq
= {
2253 .flags
= CPUFREQ_CONST_LOOPS
,
2254 .verify
= intel_cpufreq_verify_policy
,
2255 .target
= intel_cpufreq_target
,
2256 .fast_switch
= intel_cpufreq_fast_switch
,
2257 .init
= intel_cpufreq_cpu_init
,
2258 .exit
= intel_pstate_cpu_exit
,
2259 .stop_cpu
= intel_cpufreq_stop_cpu
,
2260 .name
= "intel_cpufreq",
2263 static struct cpufreq_driver
*default_driver
= &intel_pstate
;
2265 static bool pid_in_use(void)
2267 return intel_pstate_driver
== &intel_pstate
&&
2268 pstate_funcs
.update_util
== intel_pstate_update_util_pid
;
2271 static void intel_pstate_driver_cleanup(void)
2276 for_each_online_cpu(cpu
) {
2277 if (all_cpu_data
[cpu
]) {
2278 if (intel_pstate_driver
== &intel_pstate
)
2279 intel_pstate_clear_update_util_hook(cpu
);
2281 kfree(all_cpu_data
[cpu
]);
2282 all_cpu_data
[cpu
] = NULL
;
2286 intel_pstate_driver
= NULL
;
2289 static int intel_pstate_register_driver(struct cpufreq_driver
*driver
)
2293 memset(&global
, 0, sizeof(global
));
2294 global
.max_perf_pct
= 100;
2296 intel_pstate_driver
= driver
;
2297 ret
= cpufreq_register_driver(intel_pstate_driver
);
2299 intel_pstate_driver_cleanup();
2303 global
.min_perf_pct
= min_perf_pct_min();
2306 intel_pstate_debug_expose_params();
2311 static int intel_pstate_unregister_driver(void)
2317 intel_pstate_debug_hide_params();
2319 cpufreq_unregister_driver(intel_pstate_driver
);
2320 intel_pstate_driver_cleanup();
2325 static ssize_t
intel_pstate_show_status(char *buf
)
2327 if (!intel_pstate_driver
)
2328 return sprintf(buf
, "off\n");
2330 return sprintf(buf
, "%s\n", intel_pstate_driver
== &intel_pstate
?
2331 "active" : "passive");
2334 static int intel_pstate_update_status(const char *buf
, size_t size
)
2338 if (size
== 3 && !strncmp(buf
, "off", size
))
2339 return intel_pstate_driver
?
2340 intel_pstate_unregister_driver() : -EINVAL
;
2342 if (size
== 6 && !strncmp(buf
, "active", size
)) {
2343 if (intel_pstate_driver
) {
2344 if (intel_pstate_driver
== &intel_pstate
)
2347 ret
= intel_pstate_unregister_driver();
2352 return intel_pstate_register_driver(&intel_pstate
);
2355 if (size
== 7 && !strncmp(buf
, "passive", size
)) {
2356 if (intel_pstate_driver
) {
2357 if (intel_pstate_driver
== &intel_cpufreq
)
2360 ret
= intel_pstate_unregister_driver();
2365 return intel_pstate_register_driver(&intel_cpufreq
);
2371 static int no_load __initdata
;
2372 static int no_hwp __initdata
;
2373 static int hwp_only __initdata
;
2374 static unsigned int force_load __initdata
;
2376 static int __init
intel_pstate_msrs_not_valid(void)
2378 if (!pstate_funcs
.get_max() ||
2379 !pstate_funcs
.get_min() ||
2380 !pstate_funcs
.get_turbo())
2387 static void intel_pstate_use_acpi_profile(void)
2389 switch (acpi_gbl_FADT
.preferred_profile
) {
2392 case PM_APPLIANCE_PC
:
2394 case PM_WORKSTATION
:
2395 pstate_funcs
.update_util
= intel_pstate_update_util
;
2399 static void intel_pstate_use_acpi_profile(void)
2404 static void __init
copy_cpu_funcs(struct pstate_funcs
*funcs
)
2406 pstate_funcs
.get_max
= funcs
->get_max
;
2407 pstate_funcs
.get_max_physical
= funcs
->get_max_physical
;
2408 pstate_funcs
.get_min
= funcs
->get_min
;
2409 pstate_funcs
.get_turbo
= funcs
->get_turbo
;
2410 pstate_funcs
.get_scaling
= funcs
->get_scaling
;
2411 pstate_funcs
.get_val
= funcs
->get_val
;
2412 pstate_funcs
.get_vid
= funcs
->get_vid
;
2413 pstate_funcs
.update_util
= funcs
->update_util
;
2414 pstate_funcs
.get_aperf_mperf_shift
= funcs
->get_aperf_mperf_shift
;
2416 intel_pstate_use_acpi_profile();
2421 static bool __init
intel_pstate_no_acpi_pss(void)
2425 for_each_possible_cpu(i
) {
2427 union acpi_object
*pss
;
2428 struct acpi_buffer buffer
= { ACPI_ALLOCATE_BUFFER
, NULL
};
2429 struct acpi_processor
*pr
= per_cpu(processors
, i
);
2434 status
= acpi_evaluate_object(pr
->handle
, "_PSS", NULL
, &buffer
);
2435 if (ACPI_FAILURE(status
))
2438 pss
= buffer
.pointer
;
2439 if (pss
&& pss
->type
== ACPI_TYPE_PACKAGE
) {
2450 static bool __init
intel_pstate_has_acpi_ppc(void)
2454 for_each_possible_cpu(i
) {
2455 struct acpi_processor
*pr
= per_cpu(processors
, i
);
2459 if (acpi_has_method(pr
->handle
, "_PPC"))
2470 struct hw_vendor_info
{
2472 char oem_id
[ACPI_OEM_ID_SIZE
];
2473 char oem_table_id
[ACPI_OEM_TABLE_ID_SIZE
];
2477 /* Hardware vendor-specific info that has its own power management modes */
2478 static struct hw_vendor_info vendor_info
[] __initdata
= {
2479 {1, "HP ", "ProLiant", PSS
},
2480 {1, "ORACLE", "X4-2 ", PPC
},
2481 {1, "ORACLE", "X4-2L ", PPC
},
2482 {1, "ORACLE", "X4-2B ", PPC
},
2483 {1, "ORACLE", "X3-2 ", PPC
},
2484 {1, "ORACLE", "X3-2L ", PPC
},
2485 {1, "ORACLE", "X3-2B ", PPC
},
2486 {1, "ORACLE", "X4470M2 ", PPC
},
2487 {1, "ORACLE", "X4270M3 ", PPC
},
2488 {1, "ORACLE", "X4270M2 ", PPC
},
2489 {1, "ORACLE", "X4170M2 ", PPC
},
2490 {1, "ORACLE", "X4170 M3", PPC
},
2491 {1, "ORACLE", "X4275 M3", PPC
},
2492 {1, "ORACLE", "X6-2 ", PPC
},
2493 {1, "ORACLE", "Sudbury ", PPC
},
2497 static bool __init
intel_pstate_platform_pwr_mgmt_exists(void)
2499 struct acpi_table_header hdr
;
2500 struct hw_vendor_info
*v_info
;
2501 const struct x86_cpu_id
*id
;
2504 id
= x86_match_cpu(intel_pstate_cpu_oob_ids
);
2506 rdmsrl(MSR_MISC_PWR_MGMT
, misc_pwr
);
2507 if ( misc_pwr
& (1 << 8))
2511 if (acpi_disabled
||
2512 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT
, 0, &hdr
)))
2515 for (v_info
= vendor_info
; v_info
->valid
; v_info
++) {
2516 if (!strncmp(hdr
.oem_id
, v_info
->oem_id
, ACPI_OEM_ID_SIZE
) &&
2517 !strncmp(hdr
.oem_table_id
, v_info
->oem_table_id
,
2518 ACPI_OEM_TABLE_ID_SIZE
))
2519 switch (v_info
->oem_pwr_table
) {
2521 return intel_pstate_no_acpi_pss();
2523 return intel_pstate_has_acpi_ppc() &&
2531 static void intel_pstate_request_control_from_smm(void)
2534 * It may be unsafe to request P-states control from SMM if _PPC support
2535 * has not been enabled.
2538 acpi_processor_pstate_control();
2540 #else /* CONFIG_ACPI not enabled */
2541 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2542 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2543 static inline void intel_pstate_request_control_from_smm(void) {}
2544 #endif /* CONFIG_ACPI */
2546 static const struct x86_cpu_id hwp_support_ids
[] __initconst
= {
2547 { X86_VENDOR_INTEL
, 6, X86_MODEL_ANY
, X86_FEATURE_HWP
},
2551 static int __init
intel_pstate_init(void)
2558 if (x86_match_cpu(hwp_support_ids
)) {
2559 copy_cpu_funcs(&core_funcs
);
2561 pstate_funcs
.update_util
= intel_pstate_update_util
;
2564 intel_pstate
.attr
= hwp_cpufreq_attrs
;
2565 goto hwp_cpu_matched
;
2568 const struct x86_cpu_id
*id
;
2570 id
= x86_match_cpu(intel_pstate_cpu_ids
);
2574 copy_cpu_funcs((struct pstate_funcs
*)id
->driver_data
);
2577 if (intel_pstate_msrs_not_valid())
2582 * The Intel pstate driver will be ignored if the platform
2583 * firmware has its own power management modes.
2585 if (intel_pstate_platform_pwr_mgmt_exists())
2588 if (!hwp_active
&& hwp_only
)
2591 pr_info("Intel P-state driver initializing\n");
2593 all_cpu_data
= vzalloc(sizeof(void *) * num_possible_cpus());
2597 intel_pstate_request_control_from_smm();
2599 intel_pstate_sysfs_expose_params();
2601 mutex_lock(&intel_pstate_driver_lock
);
2602 rc
= intel_pstate_register_driver(default_driver
);
2603 mutex_unlock(&intel_pstate_driver_lock
);
2608 pr_info("HWP enabled\n");
2612 device_initcall(intel_pstate_init
);
2614 static int __init
intel_pstate_setup(char *str
)
2619 if (!strcmp(str
, "disable")) {
2621 } else if (!strcmp(str
, "passive")) {
2622 pr_info("Passive mode enabled\n");
2623 default_driver
= &intel_cpufreq
;
2626 if (!strcmp(str
, "no_hwp")) {
2627 pr_info("HWP disabled\n");
2630 if (!strcmp(str
, "force"))
2632 if (!strcmp(str
, "hwp_only"))
2634 if (!strcmp(str
, "per_cpu_perf_limits"))
2635 per_cpu_limits
= true;
2638 if (!strcmp(str
, "support_acpi_ppc"))
2644 early_param("intel_pstate", intel_pstate_setup
);
2646 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2647 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2648 MODULE_LICENSE("GPL");