2 * intel_pstate.c: Native P state management for Intel processors
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 #include <linux/kernel.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/module.h>
16 #include <linux/ktime.h>
17 #include <linux/hrtimer.h>
18 #include <linux/tick.h>
19 #include <linux/slab.h>
20 #include <linux/sched.h>
21 #include <linux/list.h>
22 #include <linux/cpu.h>
23 #include <linux/cpufreq.h>
24 #include <linux/sysfs.h>
25 #include <linux/types.h>
27 #include <linux/debugfs.h>
28 #include <linux/acpi.h>
29 #include <linux/vmalloc.h>
30 #include <trace/events/power.h>
32 #include <asm/div64.h>
34 #include <asm/cpu_device_id.h>
35 #include <asm/cpufeature.h>
37 #define ATOM_RATIOS 0x66a
38 #define ATOM_VIDS 0x66b
39 #define ATOM_TURBO_RATIOS 0x66c
40 #define ATOM_TURBO_VIDS 0x66d
43 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
44 #define fp_toint(X) ((X) >> FRAC_BITS)
46 static inline int32_t mul_fp(int32_t x
, int32_t y
)
48 return ((int64_t)x
* (int64_t)y
) >> FRAC_BITS
;
51 static inline int32_t div_fp(s64 x
, s64 y
)
53 return div64_s64((int64_t)x
<< FRAC_BITS
, y
);
56 static inline int ceiling_fp(int32_t x
)
61 mask
= (1 << FRAC_BITS
) - 1;
68 int32_t core_pct_busy
;
81 int max_pstate_physical
;
106 struct timer_list timer
;
108 struct pstate_data pstate
;
112 ktime_t last_sample_time
;
116 u64 prev_cummulative_iowait
;
117 struct sample sample
;
120 static struct cpudata
**all_cpu_data
;
121 struct pstate_adjust_policy
{
130 struct pstate_funcs
{
131 int (*get_max
)(void);
132 int (*get_max_physical
)(void);
133 int (*get_min
)(void);
134 int (*get_turbo
)(void);
135 int (*get_scaling
)(void);
136 void (*set
)(struct cpudata
*, int pstate
);
137 void (*get_vid
)(struct cpudata
*);
138 int32_t (*get_target_pstate
)(struct cpudata
*);
141 struct cpu_defaults
{
142 struct pstate_adjust_policy pid_policy
;
143 struct pstate_funcs funcs
;
146 static inline int32_t get_target_pstate_use_performance(struct cpudata
*cpu
);
147 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata
*cpu
);
149 static struct pstate_adjust_policy pid_params
;
150 static struct pstate_funcs pstate_funcs
;
151 static int hwp_active
;
166 static struct perf_limits performance_limits
= {
170 .max_perf
= int_tofp(1),
172 .min_perf
= int_tofp(1),
173 .max_policy_pct
= 100,
174 .max_sysfs_pct
= 100,
179 static struct perf_limits powersave_limits
= {
183 .max_perf
= int_tofp(1),
186 .max_policy_pct
= 100,
187 .max_sysfs_pct
= 100,
192 #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE
193 static struct perf_limits
*limits
= &performance_limits
;
195 static struct perf_limits
*limits
= &powersave_limits
;
198 static inline void pid_reset(struct _pid
*pid
, int setpoint
, int busy
,
199 int deadband
, int integral
) {
200 pid
->setpoint
= setpoint
;
201 pid
->deadband
= deadband
;
202 pid
->integral
= int_tofp(integral
);
203 pid
->last_err
= int_tofp(setpoint
) - int_tofp(busy
);
206 static inline void pid_p_gain_set(struct _pid
*pid
, int percent
)
208 pid
->p_gain
= div_fp(int_tofp(percent
), int_tofp(100));
211 static inline void pid_i_gain_set(struct _pid
*pid
, int percent
)
213 pid
->i_gain
= div_fp(int_tofp(percent
), int_tofp(100));
216 static inline void pid_d_gain_set(struct _pid
*pid
, int percent
)
218 pid
->d_gain
= div_fp(int_tofp(percent
), int_tofp(100));
221 static signed int pid_calc(struct _pid
*pid
, int32_t busy
)
224 int32_t pterm
, dterm
, fp_error
;
225 int32_t integral_limit
;
227 fp_error
= int_tofp(pid
->setpoint
) - busy
;
229 if (abs(fp_error
) <= int_tofp(pid
->deadband
))
232 pterm
= mul_fp(pid
->p_gain
, fp_error
);
234 pid
->integral
+= fp_error
;
237 * We limit the integral here so that it will never
238 * get higher than 30. This prevents it from becoming
239 * too large an input over long periods of time and allows
240 * it to get factored out sooner.
242 * The value of 30 was chosen through experimentation.
244 integral_limit
= int_tofp(30);
245 if (pid
->integral
> integral_limit
)
246 pid
->integral
= integral_limit
;
247 if (pid
->integral
< -integral_limit
)
248 pid
->integral
= -integral_limit
;
250 dterm
= mul_fp(pid
->d_gain
, fp_error
- pid
->last_err
);
251 pid
->last_err
= fp_error
;
253 result
= pterm
+ mul_fp(pid
->integral
, pid
->i_gain
) + dterm
;
254 result
= result
+ (1 << (FRAC_BITS
-1));
255 return (signed int)fp_toint(result
);
258 static inline void intel_pstate_busy_pid_reset(struct cpudata
*cpu
)
260 pid_p_gain_set(&cpu
->pid
, pid_params
.p_gain_pct
);
261 pid_d_gain_set(&cpu
->pid
, pid_params
.d_gain_pct
);
262 pid_i_gain_set(&cpu
->pid
, pid_params
.i_gain_pct
);
264 pid_reset(&cpu
->pid
, pid_params
.setpoint
, 100, pid_params
.deadband
, 0);
267 static inline void intel_pstate_reset_all_pid(void)
271 for_each_online_cpu(cpu
) {
272 if (all_cpu_data
[cpu
])
273 intel_pstate_busy_pid_reset(all_cpu_data
[cpu
]);
277 static inline void update_turbo_state(void)
282 cpu
= all_cpu_data
[0];
283 rdmsrl(MSR_IA32_MISC_ENABLE
, misc_en
);
284 limits
->turbo_disabled
=
285 (misc_en
& MSR_IA32_MISC_ENABLE_TURBO_DISABLE
||
286 cpu
->pstate
.max_pstate
== cpu
->pstate
.turbo_pstate
);
289 static void intel_pstate_hwp_set(const struct cpumask
*cpumask
)
291 int min
, hw_min
, max
, hw_max
, cpu
, range
, adj_range
;
294 rdmsrl(MSR_HWP_CAPABILITIES
, cap
);
295 hw_min
= HWP_LOWEST_PERF(cap
);
296 hw_max
= HWP_HIGHEST_PERF(cap
);
297 range
= hw_max
- hw_min
;
299 for_each_cpu(cpu
, cpumask
) {
300 rdmsrl_on_cpu(cpu
, MSR_HWP_REQUEST
, &value
);
301 adj_range
= limits
->min_perf_pct
* range
/ 100;
302 min
= hw_min
+ adj_range
;
303 value
&= ~HWP_MIN_PERF(~0L);
304 value
|= HWP_MIN_PERF(min
);
306 adj_range
= limits
->max_perf_pct
* range
/ 100;
307 max
= hw_min
+ adj_range
;
308 if (limits
->no_turbo
) {
309 hw_max
= HWP_GUARANTEED_PERF(cap
);
314 value
&= ~HWP_MAX_PERF(~0L);
315 value
|= HWP_MAX_PERF(max
);
316 wrmsrl_on_cpu(cpu
, MSR_HWP_REQUEST
, value
);
320 static void intel_pstate_hwp_set_online_cpus(void)
323 intel_pstate_hwp_set(cpu_online_mask
);
327 /************************** debugfs begin ************************/
328 static int pid_param_set(void *data
, u64 val
)
331 intel_pstate_reset_all_pid();
335 static int pid_param_get(void *data
, u64
*val
)
340 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param
, pid_param_get
, pid_param_set
, "%llu\n");
347 static struct pid_param pid_files
[] = {
348 {"sample_rate_ms", &pid_params
.sample_rate_ms
},
349 {"d_gain_pct", &pid_params
.d_gain_pct
},
350 {"i_gain_pct", &pid_params
.i_gain_pct
},
351 {"deadband", &pid_params
.deadband
},
352 {"setpoint", &pid_params
.setpoint
},
353 {"p_gain_pct", &pid_params
.p_gain_pct
},
357 static void __init
intel_pstate_debug_expose_params(void)
359 struct dentry
*debugfs_parent
;
364 debugfs_parent
= debugfs_create_dir("pstate_snb", NULL
);
365 if (IS_ERR_OR_NULL(debugfs_parent
))
367 while (pid_files
[i
].name
) {
368 debugfs_create_file(pid_files
[i
].name
, 0660,
369 debugfs_parent
, pid_files
[i
].value
,
375 /************************** debugfs end ************************/
377 /************************** sysfs begin ************************/
378 #define show_one(file_name, object) \
379 static ssize_t show_##file_name \
380 (struct kobject *kobj, struct attribute *attr, char *buf) \
382 return sprintf(buf, "%u\n", limits->object); \
385 static ssize_t
show_turbo_pct(struct kobject
*kobj
,
386 struct attribute
*attr
, char *buf
)
389 int total
, no_turbo
, turbo_pct
;
392 cpu
= all_cpu_data
[0];
394 total
= cpu
->pstate
.turbo_pstate
- cpu
->pstate
.min_pstate
+ 1;
395 no_turbo
= cpu
->pstate
.max_pstate
- cpu
->pstate
.min_pstate
+ 1;
396 turbo_fp
= div_fp(int_tofp(no_turbo
), int_tofp(total
));
397 turbo_pct
= 100 - fp_toint(mul_fp(turbo_fp
, int_tofp(100)));
398 return sprintf(buf
, "%u\n", turbo_pct
);
401 static ssize_t
show_num_pstates(struct kobject
*kobj
,
402 struct attribute
*attr
, char *buf
)
407 cpu
= all_cpu_data
[0];
408 total
= cpu
->pstate
.turbo_pstate
- cpu
->pstate
.min_pstate
+ 1;
409 return sprintf(buf
, "%u\n", total
);
412 static ssize_t
show_no_turbo(struct kobject
*kobj
,
413 struct attribute
*attr
, char *buf
)
417 update_turbo_state();
418 if (limits
->turbo_disabled
)
419 ret
= sprintf(buf
, "%u\n", limits
->turbo_disabled
);
421 ret
= sprintf(buf
, "%u\n", limits
->no_turbo
);
426 static ssize_t
store_no_turbo(struct kobject
*a
, struct attribute
*b
,
427 const char *buf
, size_t count
)
432 ret
= sscanf(buf
, "%u", &input
);
436 update_turbo_state();
437 if (limits
->turbo_disabled
) {
438 pr_warn("intel_pstate: Turbo disabled by BIOS or unavailable on processor\n");
442 limits
->no_turbo
= clamp_t(int, input
, 0, 1);
445 intel_pstate_hwp_set_online_cpus();
450 static ssize_t
store_max_perf_pct(struct kobject
*a
, struct attribute
*b
,
451 const char *buf
, size_t count
)
456 ret
= sscanf(buf
, "%u", &input
);
460 limits
->max_sysfs_pct
= clamp_t(int, input
, 0 , 100);
461 limits
->max_perf_pct
= min(limits
->max_policy_pct
,
462 limits
->max_sysfs_pct
);
463 limits
->max_perf_pct
= max(limits
->min_policy_pct
,
464 limits
->max_perf_pct
);
465 limits
->max_perf_pct
= max(limits
->min_perf_pct
,
466 limits
->max_perf_pct
);
467 limits
->max_perf
= div_fp(int_tofp(limits
->max_perf_pct
),
471 intel_pstate_hwp_set_online_cpus();
475 static ssize_t
store_min_perf_pct(struct kobject
*a
, struct attribute
*b
,
476 const char *buf
, size_t count
)
481 ret
= sscanf(buf
, "%u", &input
);
485 limits
->min_sysfs_pct
= clamp_t(int, input
, 0 , 100);
486 limits
->min_perf_pct
= max(limits
->min_policy_pct
,
487 limits
->min_sysfs_pct
);
488 limits
->min_perf_pct
= min(limits
->max_policy_pct
,
489 limits
->min_perf_pct
);
490 limits
->min_perf_pct
= min(limits
->max_perf_pct
,
491 limits
->min_perf_pct
);
492 limits
->min_perf
= div_fp(int_tofp(limits
->min_perf_pct
),
496 intel_pstate_hwp_set_online_cpus();
500 show_one(max_perf_pct
, max_perf_pct
);
501 show_one(min_perf_pct
, min_perf_pct
);
503 define_one_global_rw(no_turbo
);
504 define_one_global_rw(max_perf_pct
);
505 define_one_global_rw(min_perf_pct
);
506 define_one_global_ro(turbo_pct
);
507 define_one_global_ro(num_pstates
);
509 static struct attribute
*intel_pstate_attributes
[] = {
518 static struct attribute_group intel_pstate_attr_group
= {
519 .attrs
= intel_pstate_attributes
,
522 static void __init
intel_pstate_sysfs_expose_params(void)
524 struct kobject
*intel_pstate_kobject
;
527 intel_pstate_kobject
= kobject_create_and_add("intel_pstate",
528 &cpu_subsys
.dev_root
->kobj
);
529 BUG_ON(!intel_pstate_kobject
);
530 rc
= sysfs_create_group(intel_pstate_kobject
, &intel_pstate_attr_group
);
533 /************************** sysfs end ************************/
535 static void intel_pstate_hwp_enable(struct cpudata
*cpudata
)
537 wrmsrl_on_cpu(cpudata
->cpu
, MSR_PM_ENABLE
, 0x1);
540 static int atom_get_min_pstate(void)
544 rdmsrl(ATOM_RATIOS
, value
);
545 return (value
>> 8) & 0x7F;
548 static int atom_get_max_pstate(void)
552 rdmsrl(ATOM_RATIOS
, value
);
553 return (value
>> 16) & 0x7F;
556 static int atom_get_turbo_pstate(void)
560 rdmsrl(ATOM_TURBO_RATIOS
, value
);
564 static void atom_set_pstate(struct cpudata
*cpudata
, int pstate
)
570 val
= (u64
)pstate
<< 8;
571 if (limits
->no_turbo
&& !limits
->turbo_disabled
)
574 vid_fp
= cpudata
->vid
.min
+ mul_fp(
575 int_tofp(pstate
- cpudata
->pstate
.min_pstate
),
578 vid_fp
= clamp_t(int32_t, vid_fp
, cpudata
->vid
.min
, cpudata
->vid
.max
);
579 vid
= ceiling_fp(vid_fp
);
581 if (pstate
> cpudata
->pstate
.max_pstate
)
582 vid
= cpudata
->vid
.turbo
;
586 wrmsrl_on_cpu(cpudata
->cpu
, MSR_IA32_PERF_CTL
, val
);
589 static int silvermont_get_scaling(void)
593 /* Defined in Table 35-6 from SDM (Sept 2015) */
594 static int silvermont_freq_table
[] = {
595 83300, 100000, 133300, 116700, 80000};
597 rdmsrl(MSR_FSB_FREQ
, value
);
601 return silvermont_freq_table
[i
];
604 static int airmont_get_scaling(void)
608 /* Defined in Table 35-10 from SDM (Sept 2015) */
609 static int airmont_freq_table
[] = {
610 83300, 100000, 133300, 116700, 80000,
611 93300, 90000, 88900, 87500};
613 rdmsrl(MSR_FSB_FREQ
, value
);
617 return airmont_freq_table
[i
];
620 static void atom_get_vid(struct cpudata
*cpudata
)
624 rdmsrl(ATOM_VIDS
, value
);
625 cpudata
->vid
.min
= int_tofp((value
>> 8) & 0x7f);
626 cpudata
->vid
.max
= int_tofp((value
>> 16) & 0x7f);
627 cpudata
->vid
.ratio
= div_fp(
628 cpudata
->vid
.max
- cpudata
->vid
.min
,
629 int_tofp(cpudata
->pstate
.max_pstate
-
630 cpudata
->pstate
.min_pstate
));
632 rdmsrl(ATOM_TURBO_VIDS
, value
);
633 cpudata
->vid
.turbo
= value
& 0x7f;
636 static int core_get_min_pstate(void)
640 rdmsrl(MSR_PLATFORM_INFO
, value
);
641 return (value
>> 40) & 0xFF;
644 static int core_get_max_pstate_physical(void)
648 rdmsrl(MSR_PLATFORM_INFO
, value
);
649 return (value
>> 8) & 0xFF;
652 static int core_get_max_pstate(void)
659 rdmsrl(MSR_PLATFORM_INFO
, plat_info
);
660 max_pstate
= (plat_info
>> 8) & 0xFF;
662 err
= rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO
, &tar
);
664 /* Do some sanity checking for safety */
665 if (plat_info
& 0x600000000) {
670 err
= rdmsrl_safe(MSR_CONFIG_TDP_CONTROL
, &tdp_ctrl
);
674 tdp_msr
= MSR_CONFIG_TDP_NOMINAL
+ tdp_ctrl
;
675 err
= rdmsrl_safe(tdp_msr
, &tdp_ratio
);
679 if (tdp_ratio
- 1 == tar
) {
681 pr_debug("max_pstate=TAC %x\n", max_pstate
);
692 static int core_get_turbo_pstate(void)
697 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT
, value
);
698 nont
= core_get_max_pstate();
705 static inline int core_get_scaling(void)
710 static void core_set_pstate(struct cpudata
*cpudata
, int pstate
)
714 val
= (u64
)pstate
<< 8;
715 if (limits
->no_turbo
&& !limits
->turbo_disabled
)
718 wrmsrl_on_cpu(cpudata
->cpu
, MSR_IA32_PERF_CTL
, val
);
721 static int knl_get_turbo_pstate(void)
726 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT
, value
);
727 nont
= core_get_max_pstate();
728 ret
= (((value
) >> 8) & 0xFF);
734 static struct cpu_defaults core_params
= {
736 .sample_rate_ms
= 10,
744 .get_max
= core_get_max_pstate
,
745 .get_max_physical
= core_get_max_pstate_physical
,
746 .get_min
= core_get_min_pstate
,
747 .get_turbo
= core_get_turbo_pstate
,
748 .get_scaling
= core_get_scaling
,
749 .set
= core_set_pstate
,
750 .get_target_pstate
= get_target_pstate_use_performance
,
754 static struct cpu_defaults silvermont_params
= {
756 .sample_rate_ms
= 10,
764 .get_max
= atom_get_max_pstate
,
765 .get_max_physical
= atom_get_max_pstate
,
766 .get_min
= atom_get_min_pstate
,
767 .get_turbo
= atom_get_turbo_pstate
,
768 .set
= atom_set_pstate
,
769 .get_scaling
= silvermont_get_scaling
,
770 .get_vid
= atom_get_vid
,
771 .get_target_pstate
= get_target_pstate_use_cpu_load
,
775 static struct cpu_defaults airmont_params
= {
777 .sample_rate_ms
= 10,
785 .get_max
= atom_get_max_pstate
,
786 .get_max_physical
= atom_get_max_pstate
,
787 .get_min
= atom_get_min_pstate
,
788 .get_turbo
= atom_get_turbo_pstate
,
789 .set
= atom_set_pstate
,
790 .get_scaling
= airmont_get_scaling
,
791 .get_vid
= atom_get_vid
,
792 .get_target_pstate
= get_target_pstate_use_cpu_load
,
796 static struct cpu_defaults knl_params
= {
798 .sample_rate_ms
= 10,
806 .get_max
= core_get_max_pstate
,
807 .get_max_physical
= core_get_max_pstate_physical
,
808 .get_min
= core_get_min_pstate
,
809 .get_turbo
= knl_get_turbo_pstate
,
810 .get_scaling
= core_get_scaling
,
811 .set
= core_set_pstate
,
812 .get_target_pstate
= get_target_pstate_use_performance
,
816 static void intel_pstate_get_min_max(struct cpudata
*cpu
, int *min
, int *max
)
818 int max_perf
= cpu
->pstate
.turbo_pstate
;
822 if (limits
->no_turbo
|| limits
->turbo_disabled
)
823 max_perf
= cpu
->pstate
.max_pstate
;
826 * performance can be limited by user through sysfs, by cpufreq
827 * policy, or by cpu specific default values determined through
830 max_perf_adj
= fp_toint(mul_fp(int_tofp(max_perf
), limits
->max_perf
));
831 *max
= clamp_t(int, max_perf_adj
,
832 cpu
->pstate
.min_pstate
, cpu
->pstate
.turbo_pstate
);
834 min_perf
= fp_toint(mul_fp(int_tofp(max_perf
), limits
->min_perf
));
835 *min
= clamp_t(int, min_perf
, cpu
->pstate
.min_pstate
, max_perf
);
838 static void intel_pstate_set_pstate(struct cpudata
*cpu
, int pstate
, bool force
)
840 int max_perf
, min_perf
;
843 update_turbo_state();
845 intel_pstate_get_min_max(cpu
, &min_perf
, &max_perf
);
847 pstate
= clamp_t(int, pstate
, min_perf
, max_perf
);
849 if (pstate
== cpu
->pstate
.current_pstate
)
852 trace_cpu_frequency(pstate
* cpu
->pstate
.scaling
, cpu
->cpu
);
854 cpu
->pstate
.current_pstate
= pstate
;
856 pstate_funcs
.set(cpu
, pstate
);
859 static void intel_pstate_get_cpu_pstates(struct cpudata
*cpu
)
861 cpu
->pstate
.min_pstate
= pstate_funcs
.get_min();
862 cpu
->pstate
.max_pstate
= pstate_funcs
.get_max();
863 cpu
->pstate
.max_pstate_physical
= pstate_funcs
.get_max_physical();
864 cpu
->pstate
.turbo_pstate
= pstate_funcs
.get_turbo();
865 cpu
->pstate
.scaling
= pstate_funcs
.get_scaling();
867 if (pstate_funcs
.get_vid
)
868 pstate_funcs
.get_vid(cpu
);
869 intel_pstate_set_pstate(cpu
, cpu
->pstate
.min_pstate
, false);
872 static inline void intel_pstate_calc_busy(struct cpudata
*cpu
)
874 struct sample
*sample
= &cpu
->sample
;
877 core_pct
= int_tofp(sample
->aperf
) * int_tofp(100);
878 core_pct
= div64_u64(core_pct
, int_tofp(sample
->mperf
));
880 sample
->freq
= fp_toint(
882 cpu
->pstate
.max_pstate_physical
*
883 cpu
->pstate
.scaling
/ 100),
886 sample
->core_pct_busy
= (int32_t)core_pct
;
889 static inline void intel_pstate_sample(struct cpudata
*cpu
)
895 local_irq_save(flags
);
896 rdmsrl(MSR_IA32_APERF
, aperf
);
897 rdmsrl(MSR_IA32_MPERF
, mperf
);
899 if ((cpu
->prev_mperf
== mperf
) || (cpu
->prev_tsc
== tsc
)) {
900 local_irq_restore(flags
);
903 local_irq_restore(flags
);
905 cpu
->last_sample_time
= cpu
->sample
.time
;
906 cpu
->sample
.time
= ktime_get();
907 cpu
->sample
.aperf
= aperf
;
908 cpu
->sample
.mperf
= mperf
;
909 cpu
->sample
.tsc
= tsc
;
910 cpu
->sample
.aperf
-= cpu
->prev_aperf
;
911 cpu
->sample
.mperf
-= cpu
->prev_mperf
;
912 cpu
->sample
.tsc
-= cpu
->prev_tsc
;
914 intel_pstate_calc_busy(cpu
);
916 cpu
->prev_aperf
= aperf
;
917 cpu
->prev_mperf
= mperf
;
921 static inline void intel_hwp_set_sample_time(struct cpudata
*cpu
)
925 delay
= msecs_to_jiffies(50);
926 mod_timer_pinned(&cpu
->timer
, jiffies
+ delay
);
929 static inline void intel_pstate_set_sample_time(struct cpudata
*cpu
)
933 delay
= msecs_to_jiffies(pid_params
.sample_rate_ms
);
934 mod_timer_pinned(&cpu
->timer
, jiffies
+ delay
);
937 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata
*cpu
)
939 struct sample
*sample
= &cpu
->sample
;
940 u64 cummulative_iowait
, delta_iowait_us
;
941 u64 delta_iowait_mperf
;
945 cummulative_iowait
= get_cpu_iowait_time_us(cpu
->cpu
, &now
);
948 * Convert iowait time into number of IO cycles spent at max_freq.
949 * IO is considered as busy only for the cpu_load algorithm. For
950 * performance this is not needed since we always try to reach the
951 * maximum P-State, so we are already boosting the IOs.
953 delta_iowait_us
= cummulative_iowait
- cpu
->prev_cummulative_iowait
;
954 delta_iowait_mperf
= div64_u64(delta_iowait_us
* cpu
->pstate
.scaling
*
955 cpu
->pstate
.max_pstate
, MSEC_PER_SEC
);
957 mperf
= cpu
->sample
.mperf
+ delta_iowait_mperf
;
958 cpu
->prev_cummulative_iowait
= cummulative_iowait
;
962 * The load can be estimated as the ratio of the mperf counter
963 * running at a constant frequency during active periods
964 * (C0) and the time stamp counter running at the same frequency
965 * also during C-states.
967 cpu_load
= div64_u64(int_tofp(100) * mperf
, sample
->tsc
);
968 cpu
->sample
.busy_scaled
= cpu_load
;
970 return cpu
->pstate
.current_pstate
- pid_calc(&cpu
->pid
, cpu_load
);
973 static inline int32_t get_target_pstate_use_performance(struct cpudata
*cpu
)
975 int32_t core_busy
, max_pstate
, current_pstate
, sample_ratio
;
980 * core_busy is the ratio of actual performance to max
981 * max_pstate is the max non turbo pstate available
982 * current_pstate was the pstate that was requested during
983 * the last sample period.
985 * We normalize core_busy, which was our actual percent
986 * performance to what we requested during the last sample
987 * period. The result will be a percentage of busy at a
990 core_busy
= cpu
->sample
.core_pct_busy
;
991 max_pstate
= int_tofp(cpu
->pstate
.max_pstate_physical
);
992 current_pstate
= int_tofp(cpu
->pstate
.current_pstate
);
993 core_busy
= mul_fp(core_busy
, div_fp(max_pstate
, current_pstate
));
996 * Since we have a deferred timer, it will not fire unless
997 * we are in C0. So, determine if the actual elapsed time
998 * is significantly greater (3x) than our sample interval. If it
999 * is, then we were idle for a long enough period of time
1000 * to adjust our busyness.
1002 sample_time
= pid_params
.sample_rate_ms
* USEC_PER_MSEC
;
1003 duration_us
= ktime_us_delta(cpu
->sample
.time
,
1004 cpu
->last_sample_time
);
1005 if (duration_us
> sample_time
* 3) {
1006 sample_ratio
= div_fp(int_tofp(sample_time
),
1007 int_tofp(duration_us
));
1008 core_busy
= mul_fp(core_busy
, sample_ratio
);
1011 cpu
->sample
.busy_scaled
= core_busy
;
1012 return cpu
->pstate
.current_pstate
- pid_calc(&cpu
->pid
, core_busy
);
1015 static inline void intel_pstate_adjust_busy_pstate(struct cpudata
*cpu
)
1017 int from
, target_pstate
;
1018 struct sample
*sample
;
1020 from
= cpu
->pstate
.current_pstate
;
1022 target_pstate
= pstate_funcs
.get_target_pstate(cpu
);
1024 intel_pstate_set_pstate(cpu
, target_pstate
, true);
1026 sample
= &cpu
->sample
;
1027 trace_pstate_sample(fp_toint(sample
->core_pct_busy
),
1028 fp_toint(sample
->busy_scaled
),
1030 cpu
->pstate
.current_pstate
,
1037 static void intel_hwp_timer_func(unsigned long __data
)
1039 struct cpudata
*cpu
= (struct cpudata
*) __data
;
1041 intel_pstate_sample(cpu
);
1042 intel_hwp_set_sample_time(cpu
);
1045 static void intel_pstate_timer_func(unsigned long __data
)
1047 struct cpudata
*cpu
= (struct cpudata
*) __data
;
1049 intel_pstate_sample(cpu
);
1051 intel_pstate_adjust_busy_pstate(cpu
);
1053 intel_pstate_set_sample_time(cpu
);
1056 #define ICPU(model, policy) \
1057 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1058 (unsigned long)&policy }
1060 static const struct x86_cpu_id intel_pstate_cpu_ids
[] = {
1061 ICPU(0x2a, core_params
),
1062 ICPU(0x2d, core_params
),
1063 ICPU(0x37, silvermont_params
),
1064 ICPU(0x3a, core_params
),
1065 ICPU(0x3c, core_params
),
1066 ICPU(0x3d, core_params
),
1067 ICPU(0x3e, core_params
),
1068 ICPU(0x3f, core_params
),
1069 ICPU(0x45, core_params
),
1070 ICPU(0x46, core_params
),
1071 ICPU(0x47, core_params
),
1072 ICPU(0x4c, airmont_params
),
1073 ICPU(0x4e, core_params
),
1074 ICPU(0x4f, core_params
),
1075 ICPU(0x5e, core_params
),
1076 ICPU(0x56, core_params
),
1077 ICPU(0x57, knl_params
),
1080 MODULE_DEVICE_TABLE(x86cpu
, intel_pstate_cpu_ids
);
1082 static const struct x86_cpu_id intel_pstate_cpu_oob_ids
[] = {
1083 ICPU(0x56, core_params
),
1087 static int intel_pstate_init_cpu(unsigned int cpunum
)
1089 struct cpudata
*cpu
;
1091 if (!all_cpu_data
[cpunum
])
1092 all_cpu_data
[cpunum
] = kzalloc(sizeof(struct cpudata
),
1094 if (!all_cpu_data
[cpunum
])
1097 cpu
= all_cpu_data
[cpunum
];
1102 intel_pstate_hwp_enable(cpu
);
1104 intel_pstate_get_cpu_pstates(cpu
);
1106 init_timer_deferrable(&cpu
->timer
);
1107 cpu
->timer
.data
= (unsigned long)cpu
;
1108 cpu
->timer
.expires
= jiffies
+ HZ
/100;
1111 cpu
->timer
.function
= intel_pstate_timer_func
;
1113 cpu
->timer
.function
= intel_hwp_timer_func
;
1115 intel_pstate_busy_pid_reset(cpu
);
1116 intel_pstate_sample(cpu
);
1118 add_timer_on(&cpu
->timer
, cpunum
);
1120 pr_debug("intel_pstate: controlling: cpu %d\n", cpunum
);
1125 static unsigned int intel_pstate_get(unsigned int cpu_num
)
1127 struct sample
*sample
;
1128 struct cpudata
*cpu
;
1130 cpu
= all_cpu_data
[cpu_num
];
1133 sample
= &cpu
->sample
;
1134 return sample
->freq
;
1137 static int intel_pstate_set_policy(struct cpufreq_policy
*policy
)
1139 if (!policy
->cpuinfo
.max_freq
)
1142 if (policy
->policy
== CPUFREQ_POLICY_PERFORMANCE
&&
1143 policy
->max
>= policy
->cpuinfo
.max_freq
) {
1144 pr_debug("intel_pstate: set performance\n");
1145 limits
= &performance_limits
;
1147 intel_pstate_hwp_set(policy
->cpus
);
1151 pr_debug("intel_pstate: set powersave\n");
1152 limits
= &powersave_limits
;
1153 limits
->min_policy_pct
= (policy
->min
* 100) / policy
->cpuinfo
.max_freq
;
1154 limits
->min_policy_pct
= clamp_t(int, limits
->min_policy_pct
, 0 , 100);
1155 limits
->max_policy_pct
= DIV_ROUND_UP(policy
->max
* 100,
1156 policy
->cpuinfo
.max_freq
);
1157 limits
->max_policy_pct
= clamp_t(int, limits
->max_policy_pct
, 0 , 100);
1159 /* Normalize user input to [min_policy_pct, max_policy_pct] */
1160 limits
->min_perf_pct
= max(limits
->min_policy_pct
,
1161 limits
->min_sysfs_pct
);
1162 limits
->min_perf_pct
= min(limits
->max_policy_pct
,
1163 limits
->min_perf_pct
);
1164 limits
->max_perf_pct
= min(limits
->max_policy_pct
,
1165 limits
->max_sysfs_pct
);
1166 limits
->max_perf_pct
= max(limits
->min_policy_pct
,
1167 limits
->max_perf_pct
);
1168 limits
->max_perf
= round_up(limits
->max_perf
, FRAC_BITS
);
1170 /* Make sure min_perf_pct <= max_perf_pct */
1171 limits
->min_perf_pct
= min(limits
->max_perf_pct
, limits
->min_perf_pct
);
1173 limits
->min_perf
= div_fp(int_tofp(limits
->min_perf_pct
),
1175 limits
->max_perf
= div_fp(int_tofp(limits
->max_perf_pct
),
1179 intel_pstate_hwp_set(policy
->cpus
);
1184 static int intel_pstate_verify_policy(struct cpufreq_policy
*policy
)
1186 cpufreq_verify_within_cpu_limits(policy
);
1188 if (policy
->policy
!= CPUFREQ_POLICY_POWERSAVE
&&
1189 policy
->policy
!= CPUFREQ_POLICY_PERFORMANCE
)
1195 static void intel_pstate_stop_cpu(struct cpufreq_policy
*policy
)
1197 int cpu_num
= policy
->cpu
;
1198 struct cpudata
*cpu
= all_cpu_data
[cpu_num
];
1200 pr_debug("intel_pstate: CPU %d exiting\n", cpu_num
);
1202 del_timer_sync(&all_cpu_data
[cpu_num
]->timer
);
1206 intel_pstate_set_pstate(cpu
, cpu
->pstate
.min_pstate
, false);
1209 static int intel_pstate_cpu_init(struct cpufreq_policy
*policy
)
1211 struct cpudata
*cpu
;
1214 rc
= intel_pstate_init_cpu(policy
->cpu
);
1218 cpu
= all_cpu_data
[policy
->cpu
];
1220 if (limits
->min_perf_pct
== 100 && limits
->max_perf_pct
== 100)
1221 policy
->policy
= CPUFREQ_POLICY_PERFORMANCE
;
1223 policy
->policy
= CPUFREQ_POLICY_POWERSAVE
;
1225 policy
->min
= cpu
->pstate
.min_pstate
* cpu
->pstate
.scaling
;
1226 policy
->max
= cpu
->pstate
.turbo_pstate
* cpu
->pstate
.scaling
;
1228 /* cpuinfo and default policy values */
1229 policy
->cpuinfo
.min_freq
= cpu
->pstate
.min_pstate
* cpu
->pstate
.scaling
;
1230 policy
->cpuinfo
.max_freq
=
1231 cpu
->pstate
.turbo_pstate
* cpu
->pstate
.scaling
;
1232 policy
->cpuinfo
.transition_latency
= CPUFREQ_ETERNAL
;
1233 cpumask_set_cpu(policy
->cpu
, policy
->cpus
);
1238 static struct cpufreq_driver intel_pstate_driver
= {
1239 .flags
= CPUFREQ_CONST_LOOPS
,
1240 .verify
= intel_pstate_verify_policy
,
1241 .setpolicy
= intel_pstate_set_policy
,
1242 .get
= intel_pstate_get
,
1243 .init
= intel_pstate_cpu_init
,
1244 .stop_cpu
= intel_pstate_stop_cpu
,
1245 .name
= "intel_pstate",
1248 static int __initdata no_load
;
1249 static int __initdata no_hwp
;
1250 static int __initdata hwp_only
;
1251 static unsigned int force_load
;
1253 static int intel_pstate_msrs_not_valid(void)
1255 if (!pstate_funcs
.get_max() ||
1256 !pstate_funcs
.get_min() ||
1257 !pstate_funcs
.get_turbo())
1263 static void copy_pid_params(struct pstate_adjust_policy
*policy
)
1265 pid_params
.sample_rate_ms
= policy
->sample_rate_ms
;
1266 pid_params
.p_gain_pct
= policy
->p_gain_pct
;
1267 pid_params
.i_gain_pct
= policy
->i_gain_pct
;
1268 pid_params
.d_gain_pct
= policy
->d_gain_pct
;
1269 pid_params
.deadband
= policy
->deadband
;
1270 pid_params
.setpoint
= policy
->setpoint
;
1273 static void copy_cpu_funcs(struct pstate_funcs
*funcs
)
1275 pstate_funcs
.get_max
= funcs
->get_max
;
1276 pstate_funcs
.get_max_physical
= funcs
->get_max_physical
;
1277 pstate_funcs
.get_min
= funcs
->get_min
;
1278 pstate_funcs
.get_turbo
= funcs
->get_turbo
;
1279 pstate_funcs
.get_scaling
= funcs
->get_scaling
;
1280 pstate_funcs
.set
= funcs
->set
;
1281 pstate_funcs
.get_vid
= funcs
->get_vid
;
1282 pstate_funcs
.get_target_pstate
= funcs
->get_target_pstate
;
1286 #if IS_ENABLED(CONFIG_ACPI)
1287 #include <acpi/processor.h>
1289 static bool intel_pstate_no_acpi_pss(void)
1293 for_each_possible_cpu(i
) {
1295 union acpi_object
*pss
;
1296 struct acpi_buffer buffer
= { ACPI_ALLOCATE_BUFFER
, NULL
};
1297 struct acpi_processor
*pr
= per_cpu(processors
, i
);
1302 status
= acpi_evaluate_object(pr
->handle
, "_PSS", NULL
, &buffer
);
1303 if (ACPI_FAILURE(status
))
1306 pss
= buffer
.pointer
;
1307 if (pss
&& pss
->type
== ACPI_TYPE_PACKAGE
) {
1318 static bool intel_pstate_has_acpi_ppc(void)
1322 for_each_possible_cpu(i
) {
1323 struct acpi_processor
*pr
= per_cpu(processors
, i
);
1327 if (acpi_has_method(pr
->handle
, "_PPC"))
1338 struct hw_vendor_info
{
1340 char oem_id
[ACPI_OEM_ID_SIZE
];
1341 char oem_table_id
[ACPI_OEM_TABLE_ID_SIZE
];
1345 /* Hardware vendor-specific info that has its own power management modes */
1346 static struct hw_vendor_info vendor_info
[] = {
1347 {1, "HP ", "ProLiant", PSS
},
1348 {1, "ORACLE", "X4-2 ", PPC
},
1349 {1, "ORACLE", "X4-2L ", PPC
},
1350 {1, "ORACLE", "X4-2B ", PPC
},
1351 {1, "ORACLE", "X3-2 ", PPC
},
1352 {1, "ORACLE", "X3-2L ", PPC
},
1353 {1, "ORACLE", "X3-2B ", PPC
},
1354 {1, "ORACLE", "X4470M2 ", PPC
},
1355 {1, "ORACLE", "X4270M3 ", PPC
},
1356 {1, "ORACLE", "X4270M2 ", PPC
},
1357 {1, "ORACLE", "X4170M2 ", PPC
},
1358 {1, "ORACLE", "X4170 M3", PPC
},
1359 {1, "ORACLE", "X4275 M3", PPC
},
1360 {1, "ORACLE", "X6-2 ", PPC
},
1361 {1, "ORACLE", "Sudbury ", PPC
},
1365 static bool intel_pstate_platform_pwr_mgmt_exists(void)
1367 struct acpi_table_header hdr
;
1368 struct hw_vendor_info
*v_info
;
1369 const struct x86_cpu_id
*id
;
1372 id
= x86_match_cpu(intel_pstate_cpu_oob_ids
);
1374 rdmsrl(MSR_MISC_PWR_MGMT
, misc_pwr
);
1375 if ( misc_pwr
& (1 << 8))
1379 if (acpi_disabled
||
1380 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT
, 0, &hdr
)))
1383 for (v_info
= vendor_info
; v_info
->valid
; v_info
++) {
1384 if (!strncmp(hdr
.oem_id
, v_info
->oem_id
, ACPI_OEM_ID_SIZE
) &&
1385 !strncmp(hdr
.oem_table_id
, v_info
->oem_table_id
,
1386 ACPI_OEM_TABLE_ID_SIZE
))
1387 switch (v_info
->oem_pwr_table
) {
1389 return intel_pstate_no_acpi_pss();
1391 return intel_pstate_has_acpi_ppc() &&
1398 #else /* CONFIG_ACPI not enabled */
1399 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
1400 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
1401 #endif /* CONFIG_ACPI */
1403 static const struct x86_cpu_id hwp_support_ids
[] __initconst
= {
1404 { X86_VENDOR_INTEL
, 6, X86_MODEL_ANY
, X86_FEATURE_HWP
},
1408 static int __init
intel_pstate_init(void)
1411 const struct x86_cpu_id
*id
;
1412 struct cpu_defaults
*cpu_def
;
1417 if (x86_match_cpu(hwp_support_ids
) && !no_hwp
) {
1418 copy_cpu_funcs(&core_params
.funcs
);
1420 goto hwp_cpu_matched
;
1423 id
= x86_match_cpu(intel_pstate_cpu_ids
);
1427 cpu_def
= (struct cpu_defaults
*)id
->driver_data
;
1429 copy_pid_params(&cpu_def
->pid_policy
);
1430 copy_cpu_funcs(&cpu_def
->funcs
);
1432 if (intel_pstate_msrs_not_valid())
1437 * The Intel pstate driver will be ignored if the platform
1438 * firmware has its own power management modes.
1440 if (intel_pstate_platform_pwr_mgmt_exists())
1443 pr_info("Intel P-state driver initializing.\n");
1445 all_cpu_data
= vzalloc(sizeof(void *) * num_possible_cpus());
1449 if (!hwp_active
&& hwp_only
)
1452 rc
= cpufreq_register_driver(&intel_pstate_driver
);
1456 intel_pstate_debug_expose_params();
1457 intel_pstate_sysfs_expose_params();
1460 pr_info("intel_pstate: HWP enabled\n");
1465 for_each_online_cpu(cpu
) {
1466 if (all_cpu_data
[cpu
]) {
1467 del_timer_sync(&all_cpu_data
[cpu
]->timer
);
1468 kfree(all_cpu_data
[cpu
]);
1473 vfree(all_cpu_data
);
1476 device_initcall(intel_pstate_init
);
1478 static int __init
intel_pstate_setup(char *str
)
1483 if (!strcmp(str
, "disable"))
1485 if (!strcmp(str
, "no_hwp")) {
1486 pr_info("intel_pstate: HWP disabled\n");
1489 if (!strcmp(str
, "force"))
1491 if (!strcmp(str
, "hwp_only"))
1495 early_param("intel_pstate", intel_pstate_setup
);
1497 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
1498 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
1499 MODULE_LICENSE("GPL");